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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
FEATURES
* One 3.3V LVPECL output pair and one LVCMOS/LVTTL REF_OUT output * Selectable crystal oscillator interfaces or LVCMOS/LVTTL single-ended input * Crystal and CLK range: 17.5MHz - 29.54MHz * Able to generate GbE/10GbE/12GbE, Fibre Channel (1Gb/4Gb/10Gb), PCI-E and SATA from a 25MHz crystal * VCO range: 1.12GHz - 1.3GHz * Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV * RMS phase jitter @ 622.08MHz (12kHz - 20MHz): <1ps (typical) design target * Supply modes: VCC/VCCO 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
GENERAL DESCRIPTION
The ICS843001I-23 is a highly versatile, low IC S phase noise LVPECL/LVCMOS Synthesizer HiPerClockSTM which can generate low jitter reference clocks for a variety of communication applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. The dual crystal interface allows the synthesizer to support up to three communication standards in a given application (i.e. SONET with a 19.44MHz crystal, 1Gb/10Gb Ethernet and Fibre Channel using a 25MHz crystal). The rms phase jitter performance is typically less than 1ps, thus www..com making the device acceptable for use in demanding applications such as OC48 SONET, GbE/10Gb Ethernet and SAN applications. The ICS843001I-23 is packaged in a small 24-pin TSSOP package.
BLOCK DIAGRAM
3 N2:N0 SEL0
Pulldown
PIN ASSIGNMENT
SEL1 Pulldown N XTAL_IN0 000 001 010 011 100 101 110 111 /2 /4 /5 /6 /8 (default) /10 /12 /16
OSC
XTAL_OUT0 XTAL_IN1
00
11
OSC
XTAL_OUT1 CLK
Pulldown
01
Phase Detector
VCO
10 01 00
VCCO_LVCMOS N0 N1 N2 VCCO_LVPECL Q nQ Q VEE VCCA nQ VCC XTAL_OUT1 XTAL_IN1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
REF_OUT VEE OE_REF M2 M1 M0 MR SEL1 SEL0 CLK XTAL_IN0 XTAL_OUT0
10 11
000 001 010 011 100 111
M /44 /45 /48 /50 /51 /64 (default)
ICS843001I-23
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
MR Pulldown M2:M0 Pullup 3
REF_OUT OE_REF Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843001AGI-23
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1
REV. B JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Type Description Output supply pin for LVCMOS/LVTTL REF_OUT output. Pulldown Output divider select pins. See Table 3C. LVCMOS/LVTTL interface levels. Pullup Output supply pin for LVPECL output. Differential output pair. LVPECL interface levels. Negative supply pin. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown LVCMOS/LVTTL clock input. Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q to go low and the inver ted output nQ to Pulldown go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Feedback divider select pins. See Table 3B. Pullup LVCMOS/LVTTL interface levels. Reference clock output enable. Default Low. See Table 3E. Pulldown LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5 6, 7 8, 23
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Name VCCO_CMOS N0, N1 N2 VCCO_LVPECL Q, nQ VEE VCCA VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 CLK SEL0, SEL1 MR Input Input
Power
Power Ouput Power Power Power Input Input Input Input Input
9
10 11 12 13 14 15
16, 17 18
19, 20 , 21 22 24
M0, M1, M2 OE_REF REF_OUT
Input Input Output
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Rout Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Output Impedance REF_OUT 5 Test Conditions Minimum Typical 4 51 51 7 12 Maximum Units pF k k
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REV. B JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Output Frequency (MHz) 74.25 74.25 155.52 622.08 311.04 125 156.25 25 0 312.5 625 187.5 100 150 75 106.25 159.375 212.5
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input XTAL Input (MHz) 27 24.75 19.44 19.44 19.44
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Feedback Divider 44 48 64 64 64 50 50 50 50 50 45 48 48 48 51 51 51
VCO (MHz) 1188 1188 1244.16 1244.16 1244.16 1250 1250 1250 1250 1250 1125 1200 1200 1200 1275 1275 1275
N Divider Value 16 16 8 2 4 10 8 5 4 2 6 12 8 16 12 8 6
Application HDTV HDTV SONET SONET SONET GigE 10 GigE GigE XGMII 10 GigE 12 GigE PCI Express SATA SATA Fibre Channel 10 Gig Fibre Channel 4 Gig Fibre Channel
25
25
25 25 25 25 25 25 25 25 25 25
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER FUNCTION TABLE
Inputs M2 0 0 0 0 1 1 M1 0 0 1 1 0 1 M0 0 1 0 1 0 1 64 M Divider Value 44 45 48 50 51
(default)
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER FUNCTION TABLE
Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divide Value 2 4 5 6 8 (default) 10 12 16
Input Frequency Minimum 25.5 24.9 23.3 22.4 22.0 17.5 Maximum 29.54 28.88 27.08 26.0 25.49 20.31
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Reference Input XTAL0 XTAL1 CLK CLK PLL Mode Active Active Active Bypass
TABLE 3E. OE_REF OUTPUT FUNCTION TABLE
Inputs OE_REF 0 1 Output REF_OUT Hi-Z Active
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REV. B JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA -0.5V to VCCO + 0.5V 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) Package Thermal Impedance, JA Storage Temperature, TSTG www..com
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 3.3V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO_LVPECL VCCO_LVCMOS IEE ICCA ICCO_LVPECL ICCO_LVCMOS Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Output Supply Current OE_REF = 0 OE_REF = 1, REF_OUT = 29.54MHz OE_REF = 0 OE_REF = 1, REF_OUT = 29.54MHz Test Conditions Minimum 3.135 3.135 3.135 3.135 Typical 3.3 3.3 3.3 3.3 TBD TBD 5 TBD TBD Maximum 3.465 3.465 3.465 3.465 Units V V V V mA mA mA mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V5%,
TA = -40C TO 85C
Symbol VCC VCCA VCCO_LVPECL VCCO_LVCMOS IEE ICCA ICCO_LVPECL ICCO_LVCMOS
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Output Supply Current
Test Conditions
Minimum 3.135 3.135 2.625 2.625
Typical 3.3 3.3 2.5 2.5 TBD TBD TBD TBD TBD
Maximum 3.465 3.465 2.625 2.625
Units V V V V mA mA mA mA mA
OE_REF = 0 OE_REF = 1, REF_OUT = 29.54MHz OE_REF = 0 OE_REF = 1, REF_OUT = 29.54MHz
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REV. B JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Test Conditions Minimum 2.625 2.625 2.625 2.625 OE_REF = 0 OE_REF = 1, REF_OUT = 29.54MHz OE_REF = 0 OE_REF = 1, REF_OUT = 29.54MHz Typical 2.5 2.5 2.5 2.5 TBD TBD 5 TBD TBD Maximum 2.625 2.625 2.625 2.625 Units V V V V mA mA mA mA mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO_LVPECL VCCO_LVCMOS IEE Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Output Supply Voltage Power Supply Current
An ICCA www..comalog Supply Current ICCO_LVPECL ICCO_LVCMOS Output Supply Current Output Supply Current
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V5% OR 2.5V5%, OR
VCC = VCCA = 3.3V5%, VCCO_LVCMOS = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage CLK, SEL0, SEL1, OE_REF, MR, N0, N1 N2, M0:M2 CLK, SEL0, SEL1, OE_REF, MR, N0, N1 N2, M0:M2 REF_OUT REF_OUT Test Conditions VCC = 3.3V VCC = 2.5V VCC = 3.3V VCC = 2.5V VCC = VIN = 3.465V or 2.625V VCC = VIN = 3.465V or 2.625V VCC = 3.465V or 2.625V, VIN = 0V VCC = 3.465V or 2.625V, VIN = 0V VCCO_LVCMOS = 3.465V VCCO_LVCMOS = 2.625V VCCO_LVCMOS = 3.465V Minimum Typical 2 1.7 -0.3 -0.3 Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 150 5 -5 -150 2.6 1.8 0.5 TB D Units V V V V A A A A V V V V/ns
IIH
Input High Current
IIL
Input Low Current
VOH VOL
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
or 2.625V Input Edge Rate CLK 20% - 80% V/T NOTE 1: Output terminated with 50 to VCCO _LVCMOS/2. See Parameter Measurement Information Section, "Output Load Test Circuit Diagram" diagrams.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V5% OR 2.5V5%, OR
VCC = VCCA = 3.3V5%, VCCO_LVPECL = 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO_LVPECL - 1.4 VCCO_LVPECL - 2.0 0.6 Typical Maximum VCCO_LVPECL - 0.9 VCCO_LVPECL - 1.7 1.0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO_LVPECL - 2V.
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REV. B JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Test Conditions Minimum 17.5 Typical Maximum 29.54 50 7 1 Units MHz MHz pF mW
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal.
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Fundamental
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 3.3V5%, TA = -40C TO 85C
Symbol fOUT tPD tjit(O) fVCO tL_SEL tL_M tR / tF Parameter Output Frequency Propagation CLK to Delay, NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range Select Time PLL Lock Time Output Rise/Fall Time Q/nQ REF_OUT 20% to 80% 20% to 80% Test Conditions Minimum 56 TBD 622.08MHz (12kHz - 20MHz) 1.12 TBD TBD 500 500 50 50 TBD 1.3 Typical Maximum 650 Units MH z ns ps GHz ms ms ps ps % %
Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO_LVPECL, VCCO_LVCMOS = 2.5V5%,
TA = -40C TO 85C
Symbol fOUT tPD tjit(O) fVCO tL_SEL tL_M tR / tF
Parameter Output Frequency Propagation CLK to Delay, NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range Select Time PLL Lock Time Output Rise/Fall Time Q/nQ REF_OUT
Test Conditions
Minimum 56
Typical
Maximum 650
Units MH z ns ps
TBD 622.08MHz (12kHz - 20MHz) 1.12 TBD TBD 20% to 80% 20% to 80% 500 500 50 50 TBD 1.3
GHz ms ms ps ps % %
Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
843001AGI-23
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REV. B JANUARY 6, 2006
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Test Conditions Minimum 56 TBD 622.08MHz (12kHz - 20MHz) 1.12 TBD TBD Q/nQ REF_OUT 20% to 80% 20% to 80% 500 500 50 50 TBD 1.3 Typical Maximum 650 Units MHz ns ps GHz ms ms ps ps % %
TABLE 6C. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL, VCCO_LVCMOS = 2.5V5%, TA = -40C TO 85C
Symbol fOUT tPD tjit(O) fVCO tL_SEL Parameter Output Frequency Propagation CLK to Delay, NOTE 1 REF_OUT RMS Phase Jitter, (Random); NOTE 2, 3 PLL VCO Lock Range Select Time Output Rise/Fall Time
PLL L tL_M www..com ock Time tR / tF
Q/nQ odc Output Duty Cycle REF_OUT NOTE 1: Measured from the VCC/2 of the input to VCCO_LVCMOS/2 of the output. NOTE 2: Phase jitter measured using a 19.44MHz quar tz crystal. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
1.655%
V CC , VCCA, VCCO_LVPECL
Qx
SCOPE
VCC , VCCA, VCCO_LVCMOS
Qx
SCOPE
LVPECL www..com
nQx
LVCMOS
VEE
VEE
-1.3V0.165V
-1.65V5%
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2.8V0.04V 2V V CC , VCCA VCCO_LVPECL
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2.055% 1.255%
Qx
SCOPE
VCC , VCCA VCCO_LVCMOS
Qx
SCOPE
LVPECL
VEE
nQx
LVCMOS
VEE
VDDO 2
-0.5V0.125V
-1.25V5%
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
2V
1.255%
VCC , VCCA, VCCO_LVPECL
Qx
SCOPE
V CC , VCCA, VCCO_LVCMOS
Qx
SCOPE
LVPECL
nQx
LVCMOS
VEE
VEE
-0.5V0.125V
-1.25V5%
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
843001AGI-23
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
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Integrated Circuit Systems, Inc.
ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Phase Noise Plot
Noise Power
nQ
Phase Noise Mask
Q
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t PW
t
PERIOD
f1
Offset Frequency
f2
odc =
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
V
CCO_LVCMOS
REF_OUT t PW
t
PERIOD
2
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
odc =
t PW t PERIOD
x 100%
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
CLK
VCC 2
VCCO_LVCMOS
REF_OUT
t
PD
2
PROPAGATION DELAY
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ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843001I-23 provides separate power supplies to isolate any high switching www..com noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V or 2.5V VCC .01F VCCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. CLK INPUT: For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground. CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
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ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error.
CRYSTAL INPUT INTERFACE
The ICS843001I-23 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p
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ICS843001I-23 ICS84332
Figure 2. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V 125
FOUT FIN
Zo = 50
125
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 3A. LVPECL OUTPUT TERMINATION
843001AGI-23
FIGURE 3B. LVPECL OUTPUT TERMINATION
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FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm R3 250 + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
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R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7.
JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0 1
65C/W
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2.5
62C/W
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
TRANSISTOR COUNT
The transistor count for ICS843001I-23 is: 4165
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ICS843001I-23
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
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TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
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FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL/LVCMOS FREQUENCY SYNTHESIZER
Marking Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843001AGI-23 ICS843001AGI-23T ICS843001AGI-23LF ICS843001AGI-23LFT ICS843001AI23 ICS843001AI23 TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
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The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843001AGI-23
www.icst.com/products/hiperclocks.html
15
REV. B JANUARY 6, 2006

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