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| 256k x 16-Bit Dynamic RAM HYB 514171BJ-50/-60 Advanced Information * * * * 262 144 words by 16-bit organization 0 to 70 C operating temperature Fast access and cycle time RAS access time: 50 ns (-50 version) 60 ns (-60 version) CAS access time: 15ns (-50, -60 version) Cycle time: 95 ns (-50 version) 110 ns (-60 version) Fast page mode cycle time 35 ns (-50 version) 40 ns (-60 version) Single + 5.0 V ( 10 %) supply with a built-in VBB generator Low Power dissipation max. 1045 mW active (-50 version) max. 935 mW active (-60 version) * Standby power dissipation 11 mW standby (TTL) 5.5 mW max. standby (CMOS) * Output unlatched at cycle end allows two-dimensional chip selection * Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability * 2 CAS / 1 WE control * All inputs and outputs TTL-compatible * 512 refresh cycles / 16 ms * Plastic Packages: P-SOJ-40-1 400 mil width * * * * * The HYB 514171BJ is a 4 MBit dynamic RAM organized as 262 144 words by 16-bit. The HYB 514171BJ utilizes CMOS silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514171BJ to be packed in a standard plastic 400 mil wide P-SOJ-40-1 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V ( 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Semiconductor Group 1 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM Ordering Information Type HYB 514171BJ-50 HYB 514171BJ-60 Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1 - I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9 - I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write - Ordering Code Q67100-Q2021 Q67100-Q727 Package P-SOJ-40-1 400 mil P-SOJ-40-1 400 mil Description 50 ns 256k x 16 DRAM 60 ns 256k x 16 DRAM Pin Names A0 - A8 RAS UCAS, LCAS WE OE I/O1 - I/O16 Address Inputs Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply (+ 5 V) Ground (0 V) No Connection VCC VSS N.C. Semiconductor Group 2 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM P-SOJ-40-1 V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. A0 A1 A2 A3 V CC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 V SS 39 I/O16 38 I/O15 37 I/O14 36 I/O13 35 V SS 34 I/O12 33 I/O11 32 I/O10 31 I/O9 30 N.C. 29 LCAS 28 UCAS 27 OE 26 A8 25 A7 24 A6 23 A5 22 A4 21 V SS SPP02811 Pin Configuration (top view) Semiconductor Group 3 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM I/O1 I/O2 . . . I/O16 . . .. Data In Buffer WE UCAS LCAS & 16 Data Out Buffer 16 OE No.2 Clock Generator 9 Column Address Buffers (9) 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 9 Refresh Counter (9) 9 Row Address Buffers (9) 9 Row Decoder . . . 512 . . . Refresh Controller Column Decoder Sense Amplifier I/O Gating 512 x 16 16 Memory Array 512 x 512 x 16 . . . . . . RAS No.1 Clock Generator Substrate Bias Generator V CC V SS SPB02827 Block Diagram Semiconductor Group 4 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM Absolute Maximum Ratings Operating temperature range ....................................................................................... 0 to + 70 C Storage temperature range.................................................................................... - 55 to + 150 C Input/output voltage ......................................................................................................... - 1 to 6 V Power supply voltage........................................................................................................ - 1 to 6 V Data out current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 5 ns Parameter Input high voltage Input low voltage TTL Output high voltage (IOUT = - 5.0 mA) TTL Output low voltage (IOUT = 4.2 mA) Symbol Limit Values min. max. 2.4 - 1.0 2.4 - - 10 - 10 - - - Unit Notes 1 1 1 1 1 VIH VIL VOH VOL VCC + 0.5 V 0.8 - 0.4 10 10 190 170 2 V V V A A mA mA Input leakage current, any input II(L) (0 V < VIN < VCC + 0.3 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC ) Average VCC supply current -50 version -60 version IO(L) ICC1 ICC2 1 2, 3, 4 Standby VCC supply current (RAS = LCAS = UCAS = WE = VIH) Average VCC supply current during RAS-only refresh cycles -50 version -60 version Average VCC supply current during fast page mode operation -50 version -60 version Standby VCC supply current (RAS = LCAS = UCAS = WE = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode -50 version -60 version 2, 4 ICC3 - 190 170 160 150 - - 1 mA 2, 3, 4 ICC4 ICC5 mA mA 1 2, 4 ICC6 190 170 mA Semiconductor Group 5 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM Capacitance TA = 0 to 70 C; VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A8) Input capacitance (RAS, UCAS, LCAS, WE, OE) Output capacitance (l/O1 to l/O16) Symbol Limit Values min. max. 6 7 7 pF pF pF - - - Unit CI1 CI2 CIO AC Characteristics 5, 6 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 5 ns Parameter Symbol min. Common Parameters Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Read Cycle Access time from RAS Access time from CAS Access time from column address OE access time Limit Values -50 max. min. -60 max. Unit Note tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 95 35 50 15 0 10 0 10 20 15 15 50 5 3 - - - 10k 10k - - - - 35 25 - - - 50 16 110 40 60 15 0 10 0 15 20 15 15 60 5 3 - - - 10k 10k - - - - 45 30 - - - 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 tRAC tCAC tAA tOEA 6 - - - - 50 15 25 15 - - - - 60 15 30 15 ns ns ns ns 8, 9 8, 9 8, 10 Semiconductor Group 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 5 ns Parameter Symbol min. Column address to RAS lead time Read command setup time Read command hold time Read command hold time ref. to RAS CAS to output in low-Z Output buffer turn-off delay from CAS Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay Write Cycle Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Data to CAS low delay Read-Modify-Write Cycle Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time Fast Page Mode Cycle Fast page mode cycle time Limit Values -50 max. min. - - - - - 15 15 - - 30 0 0 0 0 0 0 0 20 20 -60 max. - - - - - 20 20 - - - ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 13 14 14 Unit Note tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZO tCDD tODD 25 0 0 0 0 0 0 0 15 15 tWCH tWP tWCS tRWL tCWL tDS tDH tDZC 10 10 0 15 15 0 10 0 - - - - - - - - 10 10 0 15 15 0 15 0 - - - - - - - - ns ns ns ns ns ns ns ns 16 16 13 15 tRWC tRWD tCWD tAWD tOEH 140 75 40 50 15 - - - - - 160 90 45 60 20 - - - - - ns ns ns ns ns 15 15 15 tPC 35 - 40 - ns Semiconductor Group 7 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM AC Characteristics (cont'd) 5, 6 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 %, tT = 5 ns Parameter Symbol min. CAS precharge time Access time from CAS precharge RAS pulse width RAS hold time from CAS precharge Fast Page Mode Read-Modify-Write Cycle Fast page mode read/write cycle time CAS precharge to WE delay time CAS-before-RAS Refresh Cycle CAS setup time CAS hold tim RAS to CAS precharge time Write to RAS precharge time Write to RAS hold time CAS-before-RAS Counter Test Cycle CAS precharge time Limit Values -50 max. min. - 30 200k - 10 - 60 35 -60 max. - 35 200k - ns ns ns ns 7 Unit Note tCP tCPA tRASP tRHCP 10 - 50 30 tPRWC tCPWD 80 55 - - 90 60 - - ns ns tCSR tCHR tRPC tWRP tWRH 5 10 0 10 10 - - - - - 5 10 0 10 10 - - - - - ns ns ns ns ns tCPT 25 - 30 - ns Semiconductor Group 8 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM Notes All voltages are referenced to VSS. ICC, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a page mode cycle 5. An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 2 TTL loads and 100 pF. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only. If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only. If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.), tOEZ (MAX.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. 13.Either tDZC or tDZO must be satisfied. 14.Either tCDD or tODD must be satisfied. 15.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.) and tAWD > tAWD (MIN.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 9 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD UCAS LCAS t RSH t CAS t CRP VIH VIL t RAD t ASR VIH t ASC t CAH t RAL t ASR Column Row Address Row VIL t RAH t RCS t RRH t AA t OEA t RCH VIH WE VIL VIH OE VIL t DZC t DZO t ODD t CDD I/O (Inputs) VIH VIL t CAC t CLZ t OEZ Valid Data OUT Hi Z t OFF VOH I/O (Outputs) V OL Hi Z t RAC "H" or "L" SPT03043 Read Cycle Semiconductor Group 10 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD UCAS LCAS t RSH t CAS t CRP VIH VIL t RAD t ASR VIH t ASC t CAH t RAL t ASR Column Row Address Row VIL t RAH t WCS t CWL t WP t WCH t RWL VIH WE VIL VIH OE VIL t DS I/O (Inputs) t DH VIH Valid Data IN VIL Hi Z VOH I/O (Outputs) V OL "H" or "L" SPT03044 Write Cycle (Early Write) Semiconductor Group 11 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RAS VIH RAS t RP VIL t CSH t RCD UCAS LCAS t RSH t CAS t CRP VIH VIL t RAD t ASR VIH t ASC t CAH t RAL t ASR Column Row Address Row VIL t RAH t CWL t RWL t WP VIH WE VIL t OEH VIH OE VIL t DZO t DZC I/O (Inputs) t ODD t DS t DH VIH Valid Data VIL t CLZ t OEA VOH t OEZ I/O (Outputs) V OL Hi Z Hi Z "H" or "L" SPT03045 Write Cycle (OE Controlled Write) Semiconductor Group 12 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RWC t RAS VIH RAS VIL t CSH t RCD UCAS LCAS t RP t RSH t CAS t CRP VIH VIL t ASR VIH t RAH t ASC Column t CAH t ASR Row Address Row VIL t RAD t AWD t CWD t RWD VIH WE t CWL t RWL t WP VIL t RCS t AA t OEA t OEH VIH OE VIL t DZC t DZO t DS t DH Valid Data IN I/O (Inputs) VIH VIL t CAC t CLZ t ODD t OEZ Data OUT VOH I/O (Outputs) V OL t RAC "H" or "L" SPT03046 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 13 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RASP VIH RAS VIL t RP t PC t RCD UCAS LCAS t RHCP t CAS t CP t RSH t CAS t CRP t CAS VIH VIL t RAH t ASR VIH t ASC Row t CSH t CAH t ASC t CAH t ASC t CAH t ASR Row Address Column Column Column VIL t RAD t RCS VIH WE t RCH t RCS t RCS t RRH t RCH VIL t RAC t AA t OEA VIH OE t CPA t AA t OEA t CPA t AA t OEA VIL t DZC t DZO t DZC t DZO t ODD t DZC t DZO t ODD t ODD t CDD I/O (Inputs) VIH VIL t OFF t OEZ t CAC t CLZ t CAC t CLZ Valid Data OUT "H" or "L" SPT03047 t OFF t OEZ t CAC t CLZ Valid Data OUT t OFF t OEZ I/O (Outputs) V OL VOH Valid Data OUT Fast Page Mode Read Cycle Semiconductor Group 14 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RASP VIH RAS VIL t PC t CAS t RCD UCAS LCAS t RP t CAS t CP t RSH t CAS t CRP VIH VIL t RAH t ASR VIH t ASC Row t RAL t CAH t ASC t CAH t ASC Column t CAH t ASR Row Address Column Column VIL t RAD t WCS t CWL t WCH t WP VIH WE t WCS t CWL t WCH t WP t WCS t RWL t CWL t WCH t WP VIL VIH OE VIL t DS I/O (Inputs) t DH Valid Data IN t DS t DH Valid Data IN Hi Z t DS t DH Valid Data IN VIH VIL VOH I/O (Outputs) V OL "H" or "L" SPT03048 Fast Page Mode Early Write Cycle Semiconductor Group 15 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RAS VIH RAS VIL t CSH t CP t RCD UCAS LCAS t RP t PRWC t CAS t CAS t RSH t CRP t CAS VIH VIL t ASR VIH t RAD t RAH t ASC Row t CAH t CAH t ASC Column t RAL t CAH t ASC Column t ASR Row Address Column VIL t RWD t CWD t RCS VIH WE t CWL t CPWD t CWD t CWL t CPWD t CWD t RWL t CWL VIL t AA t AWD t OEA t OEH t WP t AWD t OEA t OEH t WP t AWD t OEA t WP t OEH VIH OE VIL t DZC t DZO VIH I/O (Inputs) V IL t CAC t RAC VOH I/O (Outputs) V OL t CLZ t CLZ t ODD t DZC Data IN t CLZ t CPA t CPA t ODD Data IN t DZC t ODD Data IN t DH t DS t OEZ Data OUT t DH t AA t DS t CAC t AA t OEZ Data OUT t DH t DS t OEZ Data OUT "H" or "L" SPT03049 Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 16 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RAS VIH RAS t RP VIL t CRP t RPC UCAS LCAS VIH VIL VIH t ASR t RAH t ASR Row Row Address VIL VOH I/O (Outputs) V OL Hi Z "H" or "L" SPT03050 RAS-Only Refresh Cycle Semiconductor Group 17 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RP VIH RAS t RAS t RP VIL t RPC t CP t CSR UCAS LCAS t CHR t RPC t CRP VIH VIL t WRH t WRP VIH WE VIL VIH OE VIL t ODD I/O (Inputs) VIH VIL t CDD t OEZ VOH I/O (Outputs) V OL t OFF Hi Z "H" or "L" SPT03051 CAS-Before-RAS Refresh Cycle Semiconductor Group 18 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RP VIH RAS t RASS ~ ~ t RPS VIL t RPC t CP t CSR UCAS LCAS t CHS ~ ~ t CRP VIH VIL t WRP VIH t WRH ~ ~ WE VIL VIH OE ~ ~ ~ ~ VIL t ODD I/O (Inputs) ~ ~ VIH VIL t CDD t OEZ ~ ~ ~ ~ VOH I/O (Outputs) V OL t OFF Hi Z ~ ~ "H" or "L" SPT03052 CAS-Before-RAS Self Refresh Cycle Semiconductor Group 19 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RP t RAS t RAS t RC t RP VIH RAS VIL t RCD t RSH t CHR t CRP VIH VIL t RAD t ASC t RAH t ASR VIH t CAH Row Column UCAS LCAS t WRP t WRH t ASR Row Address VIL VIH WE t RCS t RRH VIL t AA t OEA VIH OE VIL t DZC t DZO t CDD t ODD I/O (Inputs) VIH VIL t CLZ t RAC t CAC t OEZ Valid Data OUT Hi Z t OFF VOH I/O (Outputs) V OL "H" or "L" SPT03053 Hidden Refresh Cycle (Read) Semiconductor Group 20 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM t RC t RAS VIH RAS t RC t RP t RAS t RP VIL t RCD UCAS LCAS t RSH t CHR t CRP VIH VIL t RAD t ASC t RAH t ASR VIH t CAH Row Column t ASR Row Address VIL t WCS t WCH t WP t WRP t WRH VIH WE VIL t DS t DH I/O (Input) VIN Valid Data VIL Hi Z VOH I/O (Output) V OL "H" or "L" SPT03054 Hidden Refresh Cycle (Early Write) Semiconductor Group 21 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM Read Cycle VIH RAS t RAS t RP VIL t CHR t CSR UCAS LCAS t RSH t CP t CAS t RAL t CAH t ASC t ASR Row VIH VIL VIH Address Column VIL VIH t WRP t AA t CAC t OEA t RRH WE VIL VIH OE t WRH t RCS t RCH VIL t DZC I/O (Inputs) t CDD t ODD t DZO t CLZ t OFF t OEZ Data OUT VIH VIL VOH I/O (Outputs) V OL t WCS t WRP t RWL t CWL t WCH t WRH t DH Write Cycle VIH WE VIL VIH OE VIL t DS I/O (Inputs) VIH Data IN VIL Hi Z VOH I/O (Outputs) V OL "H" or "L" SPT03055 CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 22 1998-10-01 HYB 514171BJ-50/-60 256k x 16 DRAM Package Outlines Plastic Package, P-SOJ- 40-1 (SMD) (Plastic small outline J-leaded) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 23 Dimensions in mm 1998-10-01 GPJ09018 |
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