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| (R) OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD DESCRIPTION The S3040 evaluation board provides a flexible platform for verifying the operation of AMCC OC-48 clock recovery units. This document provides information on the board contents and layout. It should be used in conjuction with the S3040 data sheet, which contains full technical details on the chips operation. The S3040 evaluation board is factory configured with the S3040 device, and includes a test point to monitor the LOCKDET output. The board can be configured with either the on-board ECL crystal oscillator or with an external oscillator connected via the REFCLKP/N connectors. EV3040 EV3040 ELECTRICAL CONNECTIONS Power Connections Terminal posts are provided at the top edge of the board allowing separate control of voltage levels for the S3040 itself. The serial input is terminated on the chip, and capacitive bypass to ground is provided on the board. For operation with standard test equipment, the board should be operated below ground, with the VEE supply at -5V DC. Figure 1. Evaluation Board Top View GND GND S3040 VEE (-5V) SERDATIP 0.01 SERCLKOP S3040 0.01 SERCLKON SERDATOP SERDATIN GND SERDATON ECL CRYSTAL OSCILLATOR (option) (on back) REFCLKN REFCLKP LCKREFN SDN BYPASS NC 1 2 3 4 1.0K GND LOCKDET OFF August 13, 1999 1 EV3040 OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD SET-UP FOR JITTER MEASUREMENT Figure 2 depicts how the S3040 evaluation board can be connected for jitter measurements, and shows all of the DIP switch settings and power supply requirements. The connection from A to B will be used for the PK-PK jitter generation measurement on the Digital Sampling Oscilloscope (DSO). The connection from A to C will be used for the jitter transfer, jitter tolerance and jitter generation measurement on the transition analyzer. Figure 2. Jitter Test Setup POWER VCC=GND :0V VEE : -5.0V HP 70820A Transition Analyzer INPUT : 2 INPUT : 1 Tek CSA 803 D.S.O. CONNECTION MEASUREMENT A B : PK-PK JITTER HP 3325 MAIN SIGNAL B HP pn# 0955-0731 HP pn# 0955-0731 Bandpass filter 2.488 GHz C Bandpass filter 2.488 GHz A A C : JITTER TRANSFER JITTER TOLERANCE JITTER GENERATION MODULATION INPUT HP 70841B SERDATIP SERDATIN SERCLKOP SERCLKON HP 70842B B.E.R.T. Tx (2.488 GHz) S3040 CLK P CLK N SERDATOP SERDATON B.E.R.T. Rx (2.488 GHz) DIP SWITCH DIP SETTINGS HI (0V) LO (-5.0V) LCKREFN SDN HI LO LO N/A LCK/DATA DATA OUT/OFF VCO/OFF N/A LCK/REF DATA OUT/ON VCO/ON N/A HP 8624B REFCLK 155.52 MHz BUFFER REFCLKP REFCLKN BYPASS NOT USED 2 August 13, 1999 OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD Table 1. Power Connections for DUT and Test Equipment Interface Power Supply DUT VCC DUT VEE Nominal Input Voltage 0V -5.0V Type of Signal CML Output Termination 50 to GND EV3040 ECL SMA Connectors SMA connectors are provided for the differential serial data input/output signals and output clock. Serial Data In [SERDATIP/N] - PECL Differential inputs. Clock is recovered from the transition on these inputs. Reference Clock [REFCLKP/N] - PECL Differential inputs. These inputs are used to establish the initial operating frequency of the clock recovery PLL and are also used as a standby clock in the absence of data. These inputs must be provided with a differential clock of 155.52 MHz. Serial Data Out [SERDATOP/N] - CML outputs. This signal is the delayed version of the incoming data stream (SERDATI) updated on the falling edge of Serial Clock Out (SERCLKOP). Serial Clock Output [SERCLKP/N] - CML outputs. This signal is phase aligned with Serial Data Out (SERDATOP). Lock Detect [LOCKDET] - TTL output. Indicates that the Clock Recovery Unit (CRU) has locked onto the incoming data stream. DIP Switches The evaluation board is equipped with a DIP switch to control the static control functions of the on-board device. For both arrays the OFF (open = "0") condition of the DIP switch asserts a logic low on the assigned signal, and the ON (closed = "1") condition asserts a logic high. Figure 2 shows the particular DIP switch settings that are needed for a particular test case. Lock to Reference [LCKREFN] - Active Low. When active, the serial clock output will be forced to lock to the local reference clock input [REFCLK]. Signal Detect [SDN] - Active Low. Used to indicate a loss of received optical power. Bypass Enable [BYPASS] - Active High. Used to bypass the VCO in the PLL. August 13, 1999 3 EV3040 Figure 3. EV3040 Evaluation Board Schematic OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD VEE J1 C25 J2 J3 C1 .1uf C2 .1uf 10UF 1UF 100PF PWRX2 2 1 C6 .1uf J4 C7 .1uf GND C3 C4 C5 GND OSCECL Y1 R1 100 3 4 VCC OUTN 1 2 OUTP VEE U2 VCC .1UF VEE L2 FB VCC VCC VEE L1 FB 1 2 3 4 BYPASS VEE .1UF C23 1 2 3 4 5 6 7 8 100PF nc avcc avee avee serdatiP serdatiN nc refclkP 1k 1k 1k R3 R4 R5 1UF C20 C21 .1UF C22 100PF L4 FB S3040 CAP1 CAP2 C24 9 10 11 12 13 14 15 16 nc nc avee avcc cap1 cap2 vee vcc refclkN lockrefN sdn vcc vee vcc vee lockdet 32 31 30 29 28 27 26 25 8 7 6 5 U3 dip4 GND 1N4001 D(MELF) .1uf nc serclkoP serclkoN avee bypass serdatoP serdatoN nc 24 23 22 21 20 19 18 17 U1 C18 100pf C19 JP1 1uf C15 .1uf C16 100pf C17 R2 1k VEE D1 D2 D3 BYPASS VEE 1N4001 D(MELF) L3 FB 1UF C8 .1UF C9 C10 1UF C11 100PF .1UF C12 100PF C13 VEE VEE CAP2 CAP1 R6 R7 GND J8 J7 GND J9 J10 FILTER 1uf C14 82 82 4 August 13, 1999 OC-48 CLOCK RECOVERY UNIT EVALUATION BOARD Ordering Information PREFIX DEVICE PACKAGE EV3040 EV - Evaluation Board 3040 A - 32 TQFP XX Prefix XXXX Device X Package IS O 90 0 D 1 IFI Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation E CE RT August 13, 1999 5 |
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