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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 1:8 RECEIVER BiCMOS LVPECL OC-48 TRANSMITTER CLOCK GENERATOR SONET/SDH/ATM OC-12 1:8 RECEIVER AND RECEIVER GENERAL DESCRIPTION
S3042 S3042 S3042
FEATURES
* Micro-power Bipolar technology * Complies with Bellcore and ITU-T specifications * Supports 2.488 Gbps (OC-48) * 8-bit LVDS data path * Compact 100 TQFP/TEP package * Diagnostic loopback mode * Line loopback * LVPECL Signal detect input * Low jitter serial interface * Single 3.3V supply
The S3042 SONET/SDH receiver chip is a fully integrated deserialization SONET OC-48 (2.488 Gbps) interface device. The chip performs all necessary serial-to-parallel and framing functions in conformance with SONET/SDH transmission standards. The device is suitable for SONETbased ATM applications. Figure 1 shows a typical network application. The low jitter serial interface guarantees compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3042 is packaged in a 100 TQFP/TEP, offering designers a small package outline.
APPLICATIONS
* * * * * * * * * SONET/SDH-based transmission systems SONET/SDH modules SONET/SDH test equipment ATM over SONET/SDH Section repeaters Add drop multiplexers Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
Figure 1. System Block Diagram
8 8 8 8
Network Interface Processor
8
S3045
S3041 8 S3042
OTX
8 8 8 8 8
S3045
ORX
S3040
S3042
8
8 8 8 8 8 8 8
8 S3040 ORX OTX S3041
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Network Interface Processor
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S3042 S3042 OVERVIEW
The S3042 receiver implements SONET/SDH deserialization and frame detection functions. The block diagram in Figure 2 shows basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip includes serial-to-parallel conversion and system timing. The system timing circuitry consists of management of the datastream, framing, and clock distribution throughout the front end.
SONET/SDH/ATM OC-48 1:8 RECEIVER
The sequence of operations of the S3042 is as follows: Receiver Operations: 1. Serial input 2. Frame detection 3. Serial-to-parallel conversion 4. 8-bit parallel output Internal clocking and control functions are transparent to the user. Details of data timing can be seen in Figures 7 through 9.
Suggested Interface Devices
AMCC AMCC AMCC S3040 S3045 S3041 Clock Recovery Device OC-48 to OC-12 Mux/Demux OC-48 Mux
Figure 2. S3042 Functional Block Diagram
SDLVPECL
1:8 SERIAL TO PARALLEL
16
POUTP/N[7:0]
2
OOF FRAMEN DLEB RSDP/N LSDP/N
2 2 D
TIMING FRAME GEN BYTE DETECT
RX311MCKP/N POCLKP/N FPP/N SEARCH KILLRXCLK LLDP/N
2 2
M U X
2
D
2 2
RSCLKP/N LSCLKP/N
M U X
2
LLCLKP/N
LLEB RSTB
2
June 24, 1999 / Revision E
SONET/SDH/ATM OC-48 1:8 RECEIVER SONET OVERVIEW
Synchronous Optical Network (SONET) is a standard for connecting one fiber system to another at the optical level. SONET, together with the Synchronous Digital Hierarchy (SDH) administered by the ITU-T, forms a single international standard for fiber interconnect between telephone networks of different countries. SONET is capable of accommodating a variety of transmission rates and applications. The SONET standard is a layered protocol with four separate layers defined. These are: * Photonic * Section * Line * Path Figure 3 shows the layers and their functions. Each of the layers has overhead bandwidth dedicated to administration and maintenance. The photonic layer simply handles the conversion from electrical to optical and back with no overhead. It is responsible for transmitting the electrical signals in optical form over the physical media. The section layer handles the transport of the framed electrical signals across the optical cable from one end to the next. Key functions of this layer are framing, scrambling, and error monitoring. The line layer is responsible for the reliable transmission of the path layer information stream carrying voice, data, and video signals. Its main functions are synchronization, multiplexing, and reliable transport. The path layer is responsible for the actual transport of services at the appropriate signaling rates. Data Rates and Signal Hierarchy Table 1 contains the data rates and signal designations of the SONET hierarchy. The lowest level is the basic SONET signal referred to as the synchronous transport signal level-1 (STS-1). An STS-N signal is made up of N byte-interleaved STS-1 signals. The optical counter-
S3042
part of each STS-N signal is an optical carrier level-N signal (OC-N). The S3042 chip supports OC-48 rate (2.488 Gbps). Frame and Byte Boundary Detection The SONET/SDH fundamental frame format for STS-48 consists of 144 transport overhead bytes followed by Synchronous Payload Envelope (SPE) bytes. This pattern of 144 overhead and 4176 SPE bytes is repeated nine times in each frame. Frame and byte boundaries are detected using the A1 and A2 bytes found in the transport overhead. (See Figure 4.) For more details on SONET operations, refer to the Bellcore SONET standard document.
Figure 3. SONET Structure
Functions
Payload to SPE mapping Maintenance, protection, switching Scrambling, framing Optical transmission
Layer Overhead (Embedded Ops Channel) Path layer Line layer Section layer Path layer Line layer Section layer
576 Kbps
192 Kbps
Photonic layer
Photonic layer 0 bps
End Equipment
Fiber Cable End Equipment
Table 1. SONET Signal Hierarchy
Elec.
STS-1 STS-3 STS-12 STS-24 STS-48
CCITT
STM-1 STM-4 STM-8 STM-16
Optical Data Rate (Mbps)
OC-1 OC-3 OC-12 OC-24 OC-48 51.84 155.52 622.08 1244.16 2488.32
Figure 4. STS-48/OC-48 Frame Format
A1 A1
9 Rows
A1 A1 48 A1 Bytes
A2 A2
A2 A2 48 A2 Bytes
Transport Overhead 144 Columns 144 x 9 = 1296 bytes
Synchronous Payload Envelope 4176 Columns 4176 x 9 = 37,584 bytes
s
125 sec
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s
3
S3042
RECEIVER OPERATION
The S3042 receiver chip provides the first stage of digital processing of a receive SONET STS-48 bitserial stream. It converts the bit-serial 2.488 Gbps data stream into a 311 Mbyte/sec byte-serial data format. A loopback mode is provided for diagnostic loopback (transmitter to receiver). A Line Loopback (receiver to transmitter) is also provided. Both line and local loopback modes can be active at the same time. Frame and Byte Boundary Detection The Frame and Byte Boundary Detection circuitry searches the incoming data for three consecutive A1 bytes followed immediately by one A2 byte. Framing pattern detection is enabled by the Out-of-Frame (OOF) input. Detection is enabled by a rising edge on OOF when FRAMEN is active. It is disabled when a framing pattern is detected. When framing pattern detection is enabled, the framing pattern is used to locate byte and frame boundaries in the incoming data stream (RSD or looped transmitter data). During this time, the parallel data bus (POUT [7:0]) will not contain valid data. The timing generator block takes the located byte boundary and uses it to block the incoming data stream into bytes for output on the parallel output data bus (POUT[7:0]). The frame boundary is reported on the Frame Pulse (FP) output when any 32-bit pattern matching the framing pattern is detected on the incoming data stream. When framing pattern detection is disabled, the byte boundary is frozen to the location found when detection was previously enabled. Only framing patterns aligned to the fixed byte boundary are indicated on the FP output. Frame detection can be immediately disabled by bringing FRAMEN inactive. The probability that random data in an STS-48 stream will generate the 32-bit framing pattern is extremely small. It is highly improbable that a mimic pattern would occur within one frame of data. Therefore, the time to match the first frame pattern and to verify it with down-stream circuitry, at the next occurrence of the pattern, is expected to be less than the required 250 s, even for extremely high bit error rates.
SONET/SDH/ATM OC-48 1:8 RECEIVER
Serial-to-Parallel Converter The Serial-to-Parallel Converter consists of three 8-bit registers. The first is a serial-in, parallel-out shift register, which performs serial to parallel conversion clocked by the clock recovery block. The second is an 8-bit internal holding register, which transfers data from the serial to parallel register on byte boundaries as determined by the frame and byte boundary detection block. On the falling edge of the POCLK, the data in the holding register is transferred to an output holding register which drives POUT[7:0].
OTHER OPERATING MODES
Diagnostic Loopback When the Diagnostic Loopback Enable (DLEB) input is low, a loopback from the transmitter (S3041) to the receiver (S3042) at the serial data rate can be set up for diagnostic purposes. The differential serial output data and clock from the transmitter (S3041) (LSD/LSCLK) is routed to the receiver (S3042) (LSD/ LSCLK) in place of the normal data stream. Line Loopback The line loopback circuitry consists of alternate clock and data output drivers. For the S3042, enabling line loopback enables the LLD/LLCLK outputs. When the line loopback enable input (LLEB) is inactive, the LLD/ LLCLK outputs are disabled. When LLEB is active, data and clock from the primary inputs (RSD/RSCLK) are transmitted on LLD/LLCLK, allowing a receive-totransmit loopback to be established at the serial data rate. The S3042 LLD/LLCLK outputs should be connected to the S3041 LLD/LLCLK inputs.
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SONET/SDH/ATM OC-48 1:8 RECEIVER
Table 2 . Input Pin Assignment and Descriptions
Pin Name RSDP RSDN Level Internally Biased Diff. LVPECL Internally Biased Diff. LVPECL LVTTL I/O I Pin # 71 70 Description
S3042
Receive Serial Data. Serial data streams normally connected to an optical receiver module. These inputs are clocked by the rising RSCLK inputs. The RSD will be frame aligned and demultiplexed to an 8-bit parallel output <7:0>. Receive Serial Clock. Recovered clock signal that is synchronous with the RSD inputs. This clock is used by the receive section as the master clock to perform framing and deserialization functions. Out of Frame. Indicator used to enable framing pattern detection logic in the S3042. The framing pattern detection logic is enabled by a rising edge on OOF, and remains enabled until frame boundary is detected. OOF is an asynchronous signal with a minimum pulse width of one POCLK period. (See Figure 10.) LVPECL Signal Detect. Active high. A single-ended 10K LVPECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDLVPECL is inactive, the data on the Serial Data In (RSDP/N) pins will be internally forced to a constant zero. When SDLVPECL is active, data on the RSDP/N pins will be processed normally. Diagnostic Loopback Enable. Active Low. Selects diagnostic loopback. When DLEB is inactive, the S3042 device uses the primary data (RSD) and clock (RSCLK) inputs. When active, the S3042 device uses the diagnostic loopback data (LSD) and clock (LSCLK) from the transmitter. Master Reset. Reset input for the device. Active Low. During reset, POCLK and RX311MCK do not toggle. Line Loopback Enable. Active Low. Selects Line Loopback. When LLEB is active, the S3042 will enable the data on the LLD/LLCLK outputs. Loopback Serial Data. Inputs normally provided from a companion S3041 device. Used to implement a diagnostic loopback.
RSCLKP RSCLKN
I
66 65
OOF
I
55
SDLVPECL
LVPECL
I
52
DLEB
LVTTL
I
46
RSTB LLEB
LVTTL LVTTL
I I
45 47
LSDP LSDN
Externally Biased Diff. LVPECL Externally Biased Diff. LVPECL LVTTL
I
85 86
LSCLKP LSCLKN
I
76 77
Loopback Serial Clock. Inputs normally provided from a companion S3041 device. Used to implement a diagnostic loopback.
KILLRXCLK
I
53
Kill Receive Clock Input. For normal operation set KILLRXCLK "High." When this input is low, it will force RX311MCK and POCLK outputs to a logic "0" state. Frame Enable Input. For normal operation set FRAMEN High. This enables the frame detector circuit to detect A1 A2 alignment and lock to word boundary. When this input is Low, it will disable the frame detector circuit and it will lock on the last byte alignment state.
FRAMEN
LVTTL
I
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S3042
Table 3. Output Pin Assignment and Descriptions
Pin Name POUTN7 POUTP7 POUTN6 POUTP6 POUTN5 POUTP5 POUTN4 POUTP4 POUTN3 POUTP3 POUTN2 POUTP2 POUTN1 POUTP1 POUTN0 POUTP0 LLDP LLDN LLCLKP LLCLKN FPP FPN Level LVDS I/O O Pin # 14 15 16 17 18 19 20 21 28 29 30 31 32 33 34 35 99 100 90 91 37 36
SONET/SDH/ATM OC-48 1:8 RECEIVER
Description Parallel Output. Parallel data bus, a 311 Mbps word, aligned to the parallel output clock (POCLK). POUT<7> is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). POUT<0> is the least significant bit (corresponding to bit 8 of each PCM word, the last bit received). POUT<7:0> is updated on the falling edge of POCLK.
Diff. LSCML Diff. LSCML LVDS
O O O
Line Loopback Data. A retimed version of the incoming data stream [RSD]. Enabled by LLEB. Line Loopback Clock. A buffered version of the RSCLK input. Enabled by LLEB. Frame Pulse. Indicates frame boundaries in the incoming data stream (RSD). If framing pattern detection is enabled, as controlled by the OOF input, FP pulses high for one POCLK cycle during the third A2 byte when a 32-bit sequence matching the framing pattern is detected on the RSD inputs. When framing pattern detection is disabled, FP pulses high during the third A2 byte when the incoming data stream, after byte alignment, matches the framing pattern. FP is updated on the falling edge of POCLK. Parallel Output Clock. A 311MHz nominally 50% duty cycle, byte rate output clock that is aligned to POUT<7:0> byte serial output data. POUT<7:0> and FP are updated on the falling edge of POCLK. Receive Free Running 311MHz clock output. This clock is generated by dividing the RSCLK signal by eight. A1 A2 Frame Search Output. A High on this output pin indicates the frame detection circuit is activated and it is searching for a new A1 A2 byte alignment. This output will be High during the entire period of A1 A2 frame search. Once a new alignment is found, this signal will remain High for a minimum of one 311MHz clock period beyond the third A2 byte before it will be set to Low.
POCLKP POCLKN
LVDS
O
13 12
RX311MCKP RX311MCKN SEARCH
LVDS LVTTL
O O
39 38 44
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Table 4. Common Pin Assignment and Description
Pin Name COREGND Level GND I/O Pin # Description
S3042
6, 7, 58, Core Ground 59, 61, 63, 88, 89 4, 5, 60, Core VCC 62, 64, 87 69, 74, PECL VCC 75, 78, 79, 82, 92, 95, 96 67, 68, 72, 73, 80, 81, 83, 84, 93, 94, 97, 98 56 57 49 50 10, 11, 24, 25, 26, 27, 40, 41 PECL Ground
COREVCC PECLVCC
+3.3V +3.3V
PECLGND
GND
TTLVCC TTLGND LVDSGND
+3.3V GND GND
TTL VCC TTL Ground LVDS Ground
LVDSVCC NC
+3.3V
8, 9, 22, LVDS VCC 23, 42, 43 1, 2, 3, 48, 51 Not Connected
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S3042
Figure 5. S3042 Pinout
SONET/SDH/ATM OC-48 1:8 RECEIVER
LVDSGND LVDSGND POUTN3 POUTP3 POUTN2 POUTP2 POUTN1 POUTP1 POUTN0 POUTP0 FPN FPP RX311MCKN RX311MCKP LVDSGND LVDSGND LVDSVCC LVDSVCC SEARCH RSTB DLEB LLEB NC TTLGND TTLGND
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC NC COREVCC COREVCC COREGND COREGND LVDSVCC LVDSVCC LVDSGND LVDSGND POCLKN POCLKP POUTN7 POUTP7 POUTN6 POUTP6 POUTN5 POUTP5 POUTN4 POUTP4 LVDSVCC LVDSVCC LVDSGND LVDSGND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
LLDN LLDP PECLGND PECLGND PECLVCC PECLVCC PECLGND PECLGND PECLVCC LLCLKN LLCLKP COREGND COREGND COREVCC LSDN LSDP PECLGND PECLGND PECLVCC PECLGND PECLGND PECLVCC PECLVCC LSCLKN LSCLKP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
S3042 Pinout Top View
100 TQFP/TEP
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PECLVCC PECLVCC PECLGND PECLGND RSDP RSDN PECLVCC PECLGND PECLGND RSCLKP RSCLKN COREVCC COREGND COREVCC COREGND COREVCC COREGND COREGND TTLVCC TTLVCC OOF FRAMEN KILLRXCLK SDLVPECL NC
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SONET/SDH/ATM OC-48 1:8 RECEIVER
Figure 6. 100 TQFP/TEP Package
S3042
TOP VIEW
Thermal Management
Device
S3042
Max Power
1.11 W
ja
33 C/W
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S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
Table 5. Differential Low Swing CML Output DC Characteristics
Parameters VOL VOH VOUTDIFF VOUTSINGLE Description Low Swing CML Output LOW Voltage Low Swing CML Output HIGH Voltage Low Swing CML Serial Output Differential Voltage Swing Low Swing CML Serial Output Single-ended Voltage Swing Mi n VCC -0.50 VCC -0.20 360 180 Typ Ma x VCC -0.25 VCC -0.05 800 400 Units V V mV mV Conditions 100 line-to-line. 100 line-to-line. 100 line-to-line. See Figure 13. 100 line-to-line. See Figure 13.
Table 6. Internally Biased LVPECL Input DC Characteristics
Parameters VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min 300 15 0 80 100 Typ Max 1200 600 120 Units mV mV Conditions See Figure 13. See Figure 13.
Table 7. Externally Biased LVPECL Input DC Characteristics
Parameters VBIAS VIL VIH VINDIFF VINSINGLE RDIFF Description LVPECL DC Bias Voltage LVPECL Input LOW Voltage LVPECL Input HIGH Voltage Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance Min VCC -1.2 VCC -2.000 VCC -1.20 300 150 80 100 Typ Max VCC -0.8 VCC -0.35 VCC -0.05 1200 600 120 Units V V V mV mV See Figure 13. See Figure 13. Conditions Inputs open.
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SONET/SDH/ATM OC-48 1:8 RECEIVER
Table 8. Absolute Maximum Ratings
Parameter Storage Temperature Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin ESD Sensitivity1
1. Human body model.
S3042
Min -65 -0.5 0
Typ
Max 150 +4.0 VCC
Units C V V V
Under 500
Table 9 Recommended Operating Conditions
Parameter Ambient Temperature Under Bias Voltage on VCC with Respect to GND Voltage on any LVPECL Input Pin Min -40 3.13 VCC -2 3.3 Typ Max 85 3.47 VCC Units C V V
Table 10. Power Consumption
Parameter ICC1
1. Add 60 mA for line loopback active.
Min
Typ 200
Max 260
Units mA
Table 11. LVTTL Input/Output DC Characteristics
Symbol VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage -500 2.2 Min 2.0 0.0 Typ Max TTL VCC 0.8 50 Unit V V A A V Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min. VIL = Max. IOH = -100 A VIH = Min. VIL = Max. IoL = 4 mA
VOL
Output Low Voltage
0.5
V
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S3042
Table 12. LVDS Input/Output Characteristics1
Symbol VKH VKL VOH VOL VOUTDIFF 2 VOUTSINGLE Description High I/O Clamp Voltage Low I/O Clamp Voltage Output High Voltage Output Low Voltage Output Differential Voltage Output Single-ended Voltage
SONET/SDH/ATM OC-48 1:8 RECEIVER
Min 0.15 -1.5 1.00 0.700 460 230
Typ
Max 1.5 -0.15 1.80 1.40
Unit V V V V mV mV
Conditions II = Io = +100A VLVDSVCC = 0V II = Io = -100A VLVDSVCC = 0V VIH = Min VIL = Max VIH = Min VIL = Max VIH = Max VIL = Min VIH = Max VIL = Min
740 370
900 450
1. Output loading is 275 to GND and 100 line-to-line. 2. See Figure 13.
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SONET/SDH/ATM OC-48 1:8 RECEIVER
Table 13. AC Receiver Timing Characteristics
S3042
Symbol
tPPOUT tSPOUT tHPOUT tSRSD tHRSD
Description
POCLK Duty Cycle POCLK Low to POUT [7:0] Valid Prop. Delay POUT[7:0] and FP Set-up Time w.r.t. POCLK POUT[7:0] and FP Hold Time w.r.t. POCLK RSD/LSD Set-up Time w.r.t. RSCLK/LSCLK RSD/LSD Hold Time w.r.t. RSCLK/LSCLK LLCLK Duty Cycle
Min
40 -500 1 1 75 75 40 -100 45
Max
60 +500
Units
% ps ns ns ps ps
60 100 55 150
% ps % ps ps ps
tPLLD
LLCLK Low to LLD Valid Propagation Delay RSCLK/LSCLK Duty Cycle Low Swing CML Output Rise/Fall Time 20 to 80% 50 to VCC Load
tSLLD tHLLD
LLD Setup Time w.r.t. LLCLK LLD Hold Time w.r.t. LLCLK
100 100
Figure 7. Output Timing Diagram
POCLK tPPOUT POUT[7:0], FP
Notes on LVDS Output Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
tS POUT
tH POUT
Figure 8. Receiver Input Timing Diagram
RSCLKP/LSCLKP tSRSD RSD/LSD tHRSD
Notes on High-Speed LVPECL Input Timing: 1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input.
Figure 9. LLD Output Timing
LLCLKP tPLLD LLD tSLLD tHLLD
1. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output.
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S3042 RECEIVER FRAMING
Figure 10 shows a typical reframe sequence in which a byte realignment is made. The frame and byte boundary detection is enabled by the rising edge of OOF. The byte alignment is made during the A1 data sequence, resulting in correct byte alignment on the outgoing data bus (POUT[7:0]). Frame boundary is recognized upon receipt of the first A2 byte, and is reported via the frame pulse being set high for one POCLK cycle concurrent with the third A2 byte.
SONET/SDH/ATM OC-48 1:8 RECEIVER
The frame and byte boundary detection block is activated by the rising edge of OOF, and stays active until the first FP pulse. Figure 11 shows the frame and byte boundary detection activation by a rising edge of OOF, and deactivated by the first FP pulse. Figure 12 shows the frame and byte boundary detection activation by a rising edge of FRAMEN, and deactivated by the FRAMEN input. Figure 12 also shows the frame and byte boundary detection activation by a rising edge on FRAMEN, and deactivation by the first FP pulse.
Figure 10. Frame and Byte Detection
A1 Invalid Data
A1
A1
A1 Valid Data
A2
A2
A2 (28H)
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Figure 11. OOF Timing (FRAMEN = 1)
BOUNDARY DETECTION ENABLED
S3042
OOF
FP
SEARCH
Figure 12. FRAMEN Timing (OOF = 1)
BOUNDARY DETECTION ENABLED
BOUNDARY DETECTION ENABLED
FRAMEN
FP
SEARCH
Figure 13. Differential Voltage Measurement
Single-ended swing
V SINGLE
V DIFF = 2X Single-ended swing
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S3042
SONET/SDH/ATM OC-48 1:8 RECEIVER
Figure 14. +5V Differential PECL Driver to S3042 Input AC Coupled Termination
+5V .01F 330
Vcc -.65V
+3.3V
100
330
.01F
Vcc -.65V S3042/44 RSDP/N RSCLKP/N
Figure 15. S3040 to S3042/S3044 Terminations
+5V .01F Vcc -.65V
+3.3V
100
.01F S3040 SERDATOP/N SERCLKOP/N Vcc -.65V S3042/44 RSDP/N RSCLKP/N
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Figure 16. S3041 to S3042 for Diagnostic Loopback
S3042
+3.3V
+3.3V
100
S3041 LSDP/N LSCLKP/N
S3042 LSDP/N LSCLKP/N
Figure 17. S3042 LVDS Driver to S3045 LVDS Driver
+3.3V
+3.3V
100 275 275
S3042 POCLK POUT
S3045 311 DATIN 311CLKIN
Figure 18. S3040/48/50 +5V PECL Output to CML Input AC Coupled Termination
+5V .01F
Vcc -.65V (DC AVG)
+5V
100
.01F S3040/48/50 SERDATO SERCLKO
Vcc -.65V (DC AVG)
S3042/44 RSD RSCLK
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S3042
Ordering Information
PREFIX DEVICE
SONET/SDH/ATM OC-48 1:8 RECEIVER
PACKAGE
S - Integrated Circuit
3042
A - 100 TQFP/TEP
X Prefix
XXXX Device
X Package
IS
O 90 0
RT
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
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