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DEVICE SPECIFICATION
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR BiCMOS LVPECL OC-48 TRANSMITTER AND RECEIVER CLOCK GENERATOR SONET/SDH/ATM OC-12 16 BIT TRANSCEIVER WITH CDR
* * * * * Section repeaters Add Drop Multiplexers (ADM) Broad-band cross-connects Fiber optic terminators Fiber optic test equipment
S3055 S3055 S3055
FEATURES
* CMOS 0.18 micron technology * Complies with Bellcore and ITU-T specifications * On-chip high-frequency PLL for clock generation and clock recovery * Supports OC-48 (2488.32 Mbps) * Reference frequency of 155.52 MHz * Interface to LVPECL and LVTTL logic * 16-bit differential LVPECL data path * 324 FC-PBGA * Diagnostic loopback mode * Supports line timing * Lock detect * Signal detect input * Low jitter LVPECL interface * Internal FIFO to decouple transmit clocks * Dual 1.8 V/ 3.3 V supply * Typical power 1.25 Watts * Available in die form
GENERAL DESCRIPTION
The S3055 SONET/SDH transceiver chip is a fully integrated serialization/deserialization SONET OC-48 (2488.32 Mbps) interface device. The S3055 receives an OC-48 scrambled Non-Return to Zero (NRZ) signal and recovers the clock from the data. The chip performs all necessary serial-to-parallel and parallelto-serial functions in conformance with SONET/SDH transmission standards. The device is suitable for SONET-based WDM applications. Figure 1 shows a typical network application. On-chip clock synthesis is performed by the highfrequency Phase-Locked Loop (PLL) on the S3055 transceiver chip allowing the use of a slower external transmit clock reference. The chip can be used with a 155.52 MHz reference clock in support of existing system clocking schemes. The low jitter LVPECL interface is compliant with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3055 is packaged in a 324 FC-PBGA, offering designers a small package outline. The S3055 is also available in die form.
APPLICATIONS
* Wavelength Division Multiplexing (WDM) equipment * SONET/SDH-based transmission systems * SONET/SDH modules * SONET/SDH test equipment * ATM over SONET/SDH
Figure 1. System Block Diagram
16 AMCC AMAZON S4801 AMCC S3055
OTX
ORX AMCC S3055
16 AMCC AMAZON S4801
16
16
ORX
OTX
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S3055 S3055 OVERVIEW
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
The S3055 is divided into a transmitter section and a receiver section. The sequence of operations is as follows: Transmitter Operations: 1. 16-bit parallel input 2. Parallel-to-serial conversion 3. Serial output Receiver Operations: 1. Clock and data recovery from serial input 2. Serial-to-parallel conversion 3. 16-bit parallel output Internal clocking and control functions are transparent to the user.
The S3055 transceiver implements SONET/SDH serialization/deserialization, and transmission functions. The block diagram in Figure 2 shows the basic operation of the chip. This chip can be used to implement the front end of SONET equipment, which consists primarily of the serial transmit interface and the serial receive interface. The chip handles all the functions of these two elements, including parallel-to-serial and serial-to-parallel conversion, clock generation, and system timing. The system timing circuitry consists of management of the data stream and clock distribution throughout the front end. Table 1 shows the suggested interface devices for the S3055.
Table 1. Sugggested Interface Devices STS-48C POS/ATM SONET AMCC S4801 Mapper SONET/SDH STS-48/STM-16 AMCC S4802 Framer/Pointer Processor STS-48 POS/ATM SONET AMCC S4804 Mapper SONET/SDH STS-48/STM-16 AMCC S4805 Framer/Pointer Processor STS-192 SONET/SDM AMCC S19201 Interleaver/Disinterleaver
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Figure 2. S3055 Transceiver Functional Block Diagram
S3055
TX
PHINITP/N TXCLK_SEL TXLOCKDET CLOCK SYNTHESIZER CLOCKS 155/77 MCKP/N
REFCLKP/N POCLKP/N (Internal) RLPTIME BYPASSCLKP/N TXCAP1 TXCAP2 BYPASS TESTEN PINP/N[15:0] PICLKP/N SLPTIME LLEB
TIME GEN
PCLKP/N PHERRP/N
16
16:1 Parallel to Serial
TXDP/N D TSDP/N
TXCLKP/N KILLRXCLKB TSCLKP/N
BACKUP REFERENCE GENERATOR
RX
TIME GEN
POCLKP/N
TXDP/N (Internal) RSDP/N CDR R RXCAP1 RXCAP2 1:16 SERIAL TO PARALLEL 16 POUTP/N[15:0] D
DLEB
LCKREFN
LOCKDET
RXLOCKDET
SDLVTTL SDLVPECL RSTB
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S3055 S3055 TRANSCEIVER FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
output and the REFCLKP/N input, a loop filter which converts the phase detector output into a smooth DC voltage, and a VCO, whose frequency is varied by this voltage. The loop filter generates a VCO control voltage based on the average DC level of the phase discriminator output pulses. A single external clean-up capacitor is utilized as part of the loop filter. The loop filter's corner frequency is optimized to minimize output phase jitter.
The S3055 transceiver chip performs the serialization stage in the processing of a transmit SONET STS-48 data stream. It converts 16-bit parallel data to bit serial format at 2488.32 Mbps. A high-frequency bit clock can be generated from a 155.52 MHz frequency reference by using an integral frequency synthesizer consisting of a Phase-Locked Loop (PLL) circuit with a divider in the loop. Diagnostic loopback (transmitter to receiver) and line loopback (receiver to transmitter) is provided. See Other Operating Modes.
Timing Generator
The timing generation function, seen in Figure 2, provides a divide-by-16 rate version of the transmit serial clock. This circuitry also provides an internally generated load signal, which transfers the PINP/N[15:0] data from the FIFO to the serial shift register. The PCLK output is a divide-by-16 rate version of the transmit serial clock. PCLK is intended for use as a divide-by-16 clock for upstream multiplexing and overhead processing circuits. Using PCLK for upstream circuits will ensure a stable frequency and phase relationship between the data coming into and leaving the S3055 device. The timing generator also produces a feedback reference clock to the clock synthesizer. A counter divides the synthesized clock down to the same frequency as the REFCLK. The PLL in the clock synthesizer maintains the stability of the synthesized clock by comparing the phase of the internal clock with that of the REFCLK.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in Figure 2, is a monolithic PLL that generates the serial output clock frequency locked to the input Reference Clock (REFCLKP/N). The REFCLKP/N input must be generated from a crystal oscillator which has a frequency accuracy that meets the value stated in Table 7, the frequency spectrum in Figure 11. In order for the Transmit Serial Clock (TSCLK) frequency to have the same accuracy required for operation in a SONET system. The REFCLK must meet the phase noise requirements shown in Figure 11 to meet the jitter generation specifications given in Table 7. Lower accuracy crystal oscillators may be used in applications less demanding than SONET/SDH. The on-chip PLL consists of a phase detector, which compares the phase relationship between the VCO
Table 2. Reference Jitter Limits
Operating Mode STS-48 Band Width 12 kHz to 20 MHz RMS Jitter 5 ps
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Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 2 is comprised of a FIFO and a parallel-to-serial register. The FIFO input latches the data from the PINP/N[15:0] bus on the rising edge of PICLK. The parallel-to-serial register is a loadable shift register which takes its parallel input from the FIFO output. An internally generated divide-by-16 clock, which is phase aligned to the transmit serial clock as described in the Timing Generator description, activates the parallel data transfer between registers. The serial data is shifted out of the parallel-to-serial register at the TSCLK rate.
S3055
FIFO
A FIFO is added to decouple the internal and external (PICLK) clocks. The internally generated divideby-16 clock is used to clock out data from the FIFO. Phase Initialization (PHINIT) and Lock Detect (LOCKDET) are used to center or reset the FIFO. The PHINIT and LOCKDET signals will center the FIFO after the third PICLK pulse. This is in order to insure that PICLK is stable. This scheme allows the user to have an infinite PCLK to PICLK delay through the ASIC. Once the FIFO is centered, the PCLK to PICLK delay can have a maximum drift as specified by Table 17.
clock are the same, their phase relationship is arbitrary. To prevent errors caused by short setup or hold times between the two timing domains, the timing generator circuitry monitors the phase relationship between PICLK and the internally generated clock. When a potential setup or hold time violation is detected, the phase error becomes active. When Phase Error (PHERR) conditions occur, PHINIT should be activated to recenter the FIFO (at least 2 PCLK periods). This can be done by connecting PHERR to PHINIT. When realignment occurs, up to ten bytes of data will be lost. The user can also take in the PHERR signal, process it and send an output to PHINIT in such a way that idle bytes are lost during the realignment process. PHERR will go inactive when the realignment is complete.
RECEIVER OPERATION
The S3055 transceiver chip provides the first stage of the digital processing of a receive SONET STS-48 bit-serial stream. It converts the bit-serial 2.488 Gbps data stream into a 16-bit parallel data format. A loopback mode is provided for diagnostic loopback (transmitter to receiver). A line loopback (receiver to transmitter) is also provided.
Clock Recovery
The S3055 clock recovery device performs the clock recovery function for SONET OC-48 serial data links. The chip extracts the clock from the serial data inputs and provides retimed clock and data outputs. A 155.52 MHz reference clock is used for phase locked loop start up and proper operation under loss of signal conditions. An integral prescaler and phase locked loop circuit is used to multiply this reference to the nominal bit rate. The clock recovery generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. Output pulses from the discriminator indicate the required direction of phase corrections. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock.
FIFO Initialization
The FIFO can be initialized in one of the following three ways: 1. During power up, once the PLL has locked to the reference clock provided on the REFCLK pins, the LOCKDET will go active and initialize the FIFO. 2. When RSTB goes active, the entire chip is reset. This causes the PLL to go out of lock and thus the LOCKDET goes inactive. When the PLL reacquires the lock, the LOCKDET goes active and initializes the FIFO. Note: PCLK is held in reset when RSTB is active. 3. The user can also initialize the FIFO by raising PHINIT. During normal operation, the incoming data is passed from the PICLK timing domain to the internally generated divide-by-16 clock domain. Although the frequency of PICLK and the internally generated
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is active, a loopback from the transmitter to the receiver at the serial data rate can be set up for diagnostic purposes. The differential serial output data from the transmitter is routed to the serial-toparallel block in place of the Receiver Serial Data (RSD). Transmit Serial Data/Transmit Serial Clock (TSD/TSCLK) outputs are active. DLEB takes precedence over SDLVPECL and SDLVTTL.
Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the frequency of the incoming signal varies by a value greater than that stated in Table 7, with respect to REFCLKP/N, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The assertion of LVTTL Signal Detect (SDLVTTL) or LVPECL Signal Detect (SDLVPECL) will also cause an out of lock condition. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for SONET equipment by the Bellcore TA-NWT-000253 standard, shown in Figure 3.
Line Loopback
The line loopback circuitry selects the source of the data and clock which is output on TSD and TSCLK. When the Line Loopback Enable (LLEB) input is inactive, it selects the data and clock from the parallel to serial converter block. When LLEB is active, it forces the output data multiplexer to select the data and clock from the RSD and Receive Serial Clock (RSCLK) inputs, and a receive-to-transmit loopback can be established at the serial data rate.
Lock Detect
The S3055 contains a lock detect circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by a value greater than that stated in Table 7, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within the values stated in Table 7, the PLL will be declared in lock and the lock detect output will go active. When SDLVTTL XOR SDLVPECL = 0, it causes an out of lock condition.
Loop Timing
In Serial Loop Timing (SLPTIME) mode, the clock synthesizer PLL of the S3055 is bypassed, and the timing of the entire transmitter section is controlled by the Receive Serial Clock, RSCLKP/N. This mode is entered by setting the SLPTIME input to a TTL high level. In this mode, the REFCLKP/N input is not used to generate TSCLKP/N. It should be carefully noted that the internal PLL and CDR PLL continue to operate in this mode, and continue as the source for the 155/77MCK and RSD/RSCLK, and if these signals are being used, the REFCLKP/N input must be properly driven. In Reference Loop Timing (RLPTIME) mode, the Parallel Output Clock (POCLK) from the receiver is used as the reference clock to the transmitter. The 155/77MCK are generated from the POCLK in this operating mode.
Serial-to-Parallel Converter
The serial-to-parallel converter consists of two 16-bit registers. The first is a serial-in, parallel-out shift register, which performs the serial-to-parallel conversion clocked by the clock recovery block. On the falling edge of the Parallel Output Clock (POCLK), the data in the parallel register is transferred to an output parallel register which drives POUTP/N[15:0].
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR CDR CHARACTERISTICS
Performance The S3055 CDR PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used as specified. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB optical/electrical power penalty. SONET input jitter tolerance requirements are shown in Figure 3. Jitter Transfer The jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 4. The measurement condition is that input sinusoidal jitter up to the mask level in Figure 3 be applied. Jitter Generation The jitter generation of the serial clock and serial data outputs shall not exceed the value specified in Table 7 when a serial data input with no jitter is presented to the serial data inputs. The REFCLK input must meet the phase noise requirements shown in Figure 11 to meet the jitter generation value specified in Table 7.
Jitter Transfer Acceptable
S3055
Figure 3. Input Jitter Tolerance Specification
Sinusodal Input Jitter Amplitude (UI p-p)
15
1.5
0.15 f0 f1 f2 f3 ft
Frequency
OC/STS Level 48 f0 (Hz) 10 f1 (Hz) 600 f2 (Hz) 6000 f3 (kHz) 100 ft (kHz) 1000
Figure 4. Jitter Transfer Specification
P
slope = -20 dB/decade
Range
fc
Frequency
OC/STS Level1,2 48
fc (kHz) 2000
P (dB) 0.1
1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995. 2. ITU-T Recommendations: G.958.
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 3. S3055 Transmitter Pin Assignment and Descriptions
Pin Name PINP0 PINN0 PINP1 PINN1 PINP2 PINN2 PINP3 PINN3 PINP4 PINN4 PINP5 PINN5 PINP6 PINN6 PINP7 PINN7 PINP8 PINN8 PINP9 PINN9 PINP10 PINN10 PINP11 PINN11 PINP12 PINN12 PINP13 PINN13 PINP14 PINN14 PINP15 PINN15 PICLKP PICLKN Level Internally Biased Diff. LVPECL I/O I Pin # V12 U12 P13 N13 U13 T13 R14 P14 V14 U14 U15 T15 V16 U16 T18 T17 R17 R16 P18 P17 N17 N16 M15 M14 M18 M17 L17 L16 K18 K17 K15 K14 R12 P12 Description Parallel Input Data, aligned to the PICLK parallel input clock. PINP/N[15] is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). PINP/N[0] is the least significant bit (corresponding to bit 16 of each PCM word, the last bit transmitted). PINP/N[15:0] is sampled on the rising edge of PICLK.
Internally Biased Diff. LVPECL Analog Internally Biased Diff. LVPECL LVTTL
I
Parallel Input Clock. A divide-by-16, nominally 50% duty cycle input clock, to which PINP/N[15:0] is aligned. PICLK is used to transfer the data on the PINP/N inputs into a holding register in the parallel-to-serial converter. The rising edge of PICLK samples PINP/N[15:0]. Transmit Loop Filter Capacitor. The external loop filter capacitor and resistors are connected to these pins. See Figure 21. Phase Initialization. Rising edge will realign internal timing.
TXCAP1 TXCAP2 PHINITP PHINITN
I I
E18 F18 U11 T11
TXCLK_SEL
I
E12
Transmit Clock Select. Used to select between the 155.52 MHz and the 77.76 MHz clock on the 155/77 MCKP/N output. A low on TXCLK_SEL selects 155.52 output clock, and a high on TXCLK_SEL selects 77.76 MHz output clock.
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 3. S3055 Transmitter Pin Assignment and Descriptions (Continued)
Pin Name TSDP TSDN TSCLKP TSCLKN PCLKP PCLKN PHERRP PHERRN TXLOCKDET Level Diff. CML Diff. CML Diff. LVPECL Diff. LVPECL LVTTL I/O O Pin # A11 A10 A15 A14 V9 U9 T10 R10 H2 Description
S3055
Transmit Serial Data. Differential CML serial data stream signals, normally connected to an optical transmitter module. Transmit Serial Clock that can be used to retime the TSD signal.
O
O
Parallel Clock. A reference clock generated by dividing the internal bit clock by 16. It is normally used to coordinate 16-bit wide transfers between upstream logic and the S3055 device. Phase Error. Active high. Pulses high during each PCLK cycle for which there is a potential setup/hold timing violation between the internal byte clock and PICLK timing domains. Transmit PLL Lock Detect. Goes High after the PLL has locked to the clock provided on the REFCLK pins. TXLOCKDET is an asynchronous output.
O
O
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 4. S3055 Receiver Pin Assignment and Descriptions
Pin Name RSDP RSDN Level Internally biased and terminated Diff. CML Single Ended LVPECL I/O I Pin # A4 A5 Description Receive Serial Data stream signals normally connected to an optical receiver module.
SDLVPECL
I
A7
LVPECL Signal Detect. LVPECL with internal pull-down. Active high when SDLVTTL is held at a logic 0. A single-ended 10K LVPECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDLVPECL is inactive, the data on the Receive Serial Data In (RSDP/N) pins will be internally forced to a constant state (one or zero), and any transition on RSDP/N will be squelched. When SDLVPECL is active, data on the RSDP/N pins will be processed normally. When SDLVTTL is to be connected to the optical receiver module instead of SDLVPECL, then SDLVPECL should be tied high to implement an active low signal detect, or left unconnected to implement an active high signal detect. LVTTL Signal Detect. Active high when SDLVPECL is unconnected (logic 0). Active low when SDLVPECL is held at a logic 1. A single-ended LVTTL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDLVTTL is inactive, the data on the Receive Serial Data In (RSDP/N) pins will be internally forced to a constant state (one or zero), and any transition on RSDP/N will be squelched. When SDLVTTL is active, data on the RSDP/N pins will be processed normally. Receive Loop FIlter Capacitor. The external loop filter capacitor and resistors are connected to these pins. See Figure 22. Lock to Reference. Active low. When active, the serial clock output will be forced to lock to the local reference clock input [REFCLK].
SDLVTTL
LVTTL
I
B6
RXCAP1 RXCAP2 LCKREFN
Analog
I
D1 E1 B7
LVTTL
I
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 4. S3055 Receiver Pin Assignment and Descriptions (Continued)
Pin Name POUTP0 POUTN0 POUTP1 POUTN1 POUTP2 POUTN2 POUTP3 POUTN3 POUTP4 POUTN4 POUTP5 POUTN5 POUTP6 POUTN6 POUTP7 POUTN7 POUTP8 POUTN8 POUTP9 POUTN9 POUTP10 POUTN10 POUTP11 POUTN11 POUTP12 POUTN12 POUTP13 POUTN13 POUTP14 POUTN14 POUTP15 POUTN15 POCLKP POCLKN Level Diff. LVPECL I/O O Pin # K1 K2 L2 L3 M1 M2 N2 N3 P1 P2 R2 R3 T1 T2 V3 U3 U4 T4 R5 P5 V5 U5 P6 N6 U6 T6 R7 P7 V7 U7 U8 T8 P8 N8 Description
S3055
Parallel Data Output bus, aligned to the Parallel Output Clock (POCLK). POUTP/N[15] is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). POUTP/N[0] is the least significant bit. POUTP/N[15:0] is updated on the falling edge of POCLK.
Diff. LVPECL
O
Parallel Output Clock. A divide-by-16, nominally 50% duty cycle, parallel output clock that is aligned to POUTP/N[15:0] 16-bit parallel output data. POUTP/N[15:0] is updated on the falling edge of POCLK. Receive PLL Lock Detect. Clock recovery indicator that is set high when the internal clock recovery has locked onto the incoming data stream. RXLOCKDET is an asynchronous output.
RXLOCKDET
LVTTL
O
H1
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Table 5. S3055 Common Pin Assignment and Descriptions
Pin Name REFCLKP REFCLKN Level Internally Biased Diff. LVPECL LVTTL I/ O I Pin # H18 H17 Description Reference Clock. Used as the reference for the internal bit clock frequency synthesizer. Internally biased. Diagnostic Loopback Enable. Active low. Selects diagnostic loopback. When DLEB is inactive, the S3055 device uses the primary data (RSD) input. When active, the S3055 device uses the diagnostic loopback data from the transmitter. TSD/TSCLK is active in DLEB. Line Loopback Enable. Active low. Selects line loopback. When LLEB is active, the S3055 will route the data from the RSD/RSCLK inputs to the TSD/TSCLK outputs. Kill Receive Clock Input. Active low. For normal operation, KILLRXCLKB is high. When this input is low, it will force the POCLK output to a logic "0" state. Serial Clock Loop Time Select input. Active high. When active, SLPTIME enables the recovered clock from the receive section to be used in place of the synthesized transmit clock. Reference Clock Loop Time Select input. Active high. When active, RLPTIME enables POCLK from the receiver to be used as the reference clock input to the transmitter. Master Reset. Reset input for the device. Active low for a duration of 5 REFCLK cycles. During reset, all clocks are disabled. Test Enable. Used for production testing. Low for normal operation. 155.52/77.76 MHz clock output from the clock synthesizer. Bypass Clock. Provides an alternative serial clock bypassing the internal VCO.
DLEB
I
C8
LLEB
LVTTL
I
C5
KILLRXCLKB
LVTTL
I
D5
SLPTIME
LVTTL
I
B8
RLPTIME
LVTTL
I
A8
RSTB
LVTTL
I
C9
TESTEN 155/77MCKP 155/77MCKN BYPASSCLKP BYPASSCLKN
LVTTL Diff. LVPECL Internally biased and terminated Diff. CML LVTTL
I O I
C10 H3 H4 B18 C18
BYPASS
I
C14
Active high. Selects between BYPASS clock and the VCO clock.
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 5. S3055 Common Pin Assignment and Descriptions (Continued)
Pin Name AVSS Level GND I/O Pin # Description
S3055
C1, C2, C3, D2, D4, E2, E4, Analog Ground (0 V). E17, F1, F2, G1, C15, D15, D17, D18, F15, F17, G14, G16, G17, G18, H16 A3, B4, B3 A1, B2 B10, B11, B12 B14, B15, B16 B17, C17 RSD Ground (0 V). TTL Ground (0 V). TSD Ground (0 V). TSCLK Ground (0 V). BYPASS Ground (0 V).
VSS_RSD VSS_TTL VSS_TSD VSS_TSCLK VSS_BYPASS VSS_LVPECL
GND GND GND GND GND GND
J1, L1, M4, N1, K4, N4, N9, LVPECL Ground (0 V). P10, R1, R4, R6, R8, T3, T9, U2, V1, V4, V6, V8 C6, C11, D7, D8, D14, E5, E8, H14, J14, V10 Ground (0 V).
VSS VSS_RX
GND GND
F7, F8, F9, G7, G8, G9, H6, Receive Core Ground (0 V). H7, H8, H9, J6, J7, J8, J9, K7, K8, K9, L7, L8, L9, M6 F10, F11, F12, G10,G11, G12, H10, H11, H12, J10, J11, J12, K10, K11, K12, L10, L11, L12, M11 J17 K16, L15, L18, M13, N12, N18, P11, P15, P16, R18, T12, T14, T16, U17, V11, V13, V15, V18 C7, D6, D10, E6, E7, M16, N14, R11, R15, U18 A2, B1, E14, F14 K3, L4, M3, M8, N5, N7, N10, P3, P4, P9, R9, T5, T7, U1, U10, V2 Transmit Core Ground (0 V).
VSS_TX
GND
VSS_REF VSS_CMOS
GND GND
Reference clock Ground (0 V). CMOS Ground (0 V).
VDD_3V VDD_TTL VDD_LVPECL
3.3 V 3.3 V 3.3 V
Power Supply. TTL Power Supply LVPECL Power Supply.
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SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 5. S3055 Common Pin Assignment and Descriptions (Continued)
Pin Name AVDD_RX VDD_RSD VDD_RX_ CORE VDD_TSD VDD_TX_ CORE VDD_1V VDD_TSCLK VDD_1V_REF AVDD_TX VDD_BYPASS VDD_3V_REF NC Level 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V I/O Pin # Description
C4, D3, E3, F3, F4, G2, G3, Receive Analog Power Supply. G4 A6, B5 RSD Power Supply.
E9, F5, F6, G5, G6, H5, J5, Receive Core Power Supply. K6, L5, L6, M5, M7, M9 A9, B9, A12 E13, F13, G13, H13, J13, K13, L13, M12, M10, E10, E11 N11, R13, L14, V17, N15 D9, D11 A13, B13, A16 J1 6 C16, D16, E15, E16, F16, G15, H15, J15 A17, A18 J18 J4, D12, D13, J2, J3, C12, C13, K5 TSD Power Supply. Transmit Core Power Supply.
1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 3.3 V
Power Supply. TSCLK Power Supply. Reference Clock Power Supply. Transmit Analog Power Supply. Bypass Power Supply. Reference Clock Power Supply. No Connect. Do not connect these pins to power or ground.
14
May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Figure 5. S3055 Pinout BottomView
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
S3055
1
A
VDD_ BYPASS
VDD_ BYPASS
VDD_TSCLK
TSCLKP
TSCLKN
VDD_TSCLK
VDD_TSD
TSDP
TSDN
VDD_TSD
RLPTIME
SDLVPECL
VDD_RSD
RSDN
RSDP
VSS_RSD
VDD_TTL
VSS_TTL
B
BYPASSCLKP VSS_BYPASS VSS_TSCLK
VSS_TSCLK
VSS_TSCLK
VDD_TSCLK
VSS_TSD
VSS_TSD
VSS_TSD
VDD_TSD
SLPTIME
LCKREFN
SDLVTTL
VDD_RSD
VSS_RSD
VSS_RSD
VSS_TTL
VDD_TTL
C
BYPASSCLKN VSS_BYPASS
AVDD_TX
AVSS
BYPASS
NC
NC
VS S
TESTEN
RSTB
DLEB
VDD_3V
VS S
LLE B
AVDD_RX
AVSS
AVSS
AVSS
D
AVSS
AVSS
AVDD_TX
AVSS
VSS
NC
NC
VDD_1V
VDD_3V
VDD_1V
VS S
VSS
VDD_3V
KILLRXCLKB
AVSS
AVDD_RX
AVSS
RXCAP1
E
TXCAP1
AVSS
AVDD_TX
AVDD_TX
VDD_TLL
VDD_TX_ CORE
TXCLK_SEL
VDD_TX_ CORE
VDD_TX_ CORE
VDD_RX_ CORE
VSS
VDD_3V
VDD_3V
VS S
AVSS
AVDD_RX
AVSS
RXCAP2
F
TXCAP2
AVSS
AVDD_TX
AVSS
VDD_TLL
VDD_TX_ CORE
VSS_TX
VSS_TX
VSS_TX
VSS_RX
VSS_RX
VSS_RX
VDD_RX_ CORE
VDD_RX_ CORE
AVDD_RX
AVDD_RX
AVSS
AVSS
G
AVSS
AVSS
AVSS
AVDD_TX
AVSS
VDD_TX_ CORE
VSS_TX
VSS_TX
VSS_TX
VSS_RX
VSS_RX
VSS_RX
VDD_RX_ CORE
VDD_RX_ CORE
AVDD_RX
AVDD_RX
AVDD_RX
AVSS
H
REFCLKP
REFCLKN
AVSS
AVDD_TX
VSS
VDD_TX_ CORE
VSS_TX
VSS_TX
VSS_TX
VSS_RX
VSS_RX
VSS_RX
VSS_RX
VDD_RX_ CORE
155/77MCKN 155/77MCKP TXLOCKDET RXLOCKDET
J
VDD_3V_REF
VSS_REF
V DD_ 1 V _ RE F
AVDD_TX
VSS
VDD_TX_ CORE
VSS_TX
VSS_TX
VSS_TX
VSS_RX
VSS_RX
VSS_RX
VSS_RX
VDD_RX_ CORE
NC
NC
NC
VSS_LVPECL
K
PINP14
PINN14
VSS_CMOS
PINP15
PINN15
VDD_TX_ CORE
VSS_TX
VSS_TX
VSS_TX
VSS_RX
VSS_RX
VSS_RX
VDD_RX_ CORE
NC
VSS_LVPECL VDD_LVPECL
POUTN0
POUTP0
L
VSS_CMOS
PINP13
PINN13
VSS_CMOS
VDD_1V
VDD_TX_ CORE
VSS_TX
VSS_TX
VSS_TX
VSS_RX
VSS_RX
VSS_RX
VDD_RX_ CORE
VDD_RX_ CORE
VDD_LVPECL
POUTN1
POUTP1
VSS_LVPECL
M
PINP12
PINN12
VDD_3V
PINP11
PINN11
VSS_CMOS
VDD_TX_ CORE
VSS_TX
VDD_TX_ CORE
VDD_RX_ CORE
VDD_LVPECL
VDD_RX_CORE
VSS_RX
VDD_RX_ CORE
VSS_LVPECL VDD_LVPECL
POUTN2
POUTP2
N
VSS_CMOS
PINP10
PINN10
V DD_ 1 V
VDD_3V
PINN1
VSS_CMOS
VDD_1V
VDD_LVPECL VSS-LVPECL
POCLKN
VDD_LVPECL
POUTN11
VDD_LVPECL VSS_LVPECL
POUTN3
POUTP3
VSS_LVPECL
P
PINP9
PINN9
VSS_CMOS
VSS_CMOS
PINN3
PINP1
PICLKN
VSS_CMOS
VSS_LVPECL VDD_LVPECL
POCLKP
POUTN13
POUTP11
POUTN9
VDD_LVPECL VDD_LVPECL
POUTN4
POUTP4
R
VSS_CMOS
PINP8
PINN8
VDD_3V
PINP3
VDD-1V
PICLKP
VDD_3V
PHERRN
VDD-LVPECL VSS_LVPECL
POUTP13
VSS_LVPECL
POUTP9
VSS_LVPECL
POUTN5
POUTP5
VSS_LVPECL
T
PINP7
PINN7
VSS_CMOS
PINN5
VSS_CMOS
PINN2
VSS_CMOS
PHINITN
PHERRP
VSS-LVPECL
POUTN15
VDD_LVPECL
POUTN12
VDD_LVPECL
POUTN8
VSS_LVPECL
POUTN6
POUTP6
U
VDD_3V
VSS_CMOS
PINN6
PINP5
PINN4
PINP2
PINN0
PHINITP
VDD_LVPECL
PCLKN
POUTP15
POUTN14
POUTP12
POUTN10
POUTP8
POUTN7
VSS_LVPECL VDD_LVPECL
V
VSS_CMOS
VDD_1V
PINP6
VSS_CMOS
PINP4
VSS_CMOS
PINP0
VSS_CMOS
VSS
PCLKP
VSS_LVPECL
POUTP14
VSS_LVPECL
POUTP10
VSS_LVPECL
POUTP7
VDD-LVPECL VSS_LVPECL
May 25, 2001 / Revision A
15
S3055
Figure 6. S3055 Pinout Top View
1 2 3 4 5
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
6
7
8
9
10
11
12
13
14
15
16
17
18
A
VSS_TTL
VDD_TTL
VSS_RSD
RSDP
RS D N
V DD_ RS D
SDLVPECL
RLPTIME
VDD_TSD
TSDN
TSDP
VDD_TSD
VDD_TSCLK
TSCLKN
TSCLKP
VDD_TSCLK
VDD_ BYPASS
VDD_ BYPASS
B
VDD_TTL
VSS_TTL
VSS_RSD
VSS_RSD
VDD_RSD
SDLVTTL
LCKREFN
SLPTIME
VDD_TSD
VSS_TSD
VSS_TSD
VSS_TSD
VDD_TSCLK
VSS_TSCLK
VSS_TSCLK
VSS_TSCLK VSS_BYPASS BYPASSCLKP
C
AVSS
AVSS
AVSS
AVDD_RX
LLEB
VS S
VDD_3V
DLEB
RSTB
TESTEN
VSS
NC
NC
BYPASS
AVSS
AVDD_TX
VSS_BYPASS BYPASSCLKN
D
RXCAP1
AVSS
AVDD_RX
AVSS
KILLRXCLKB
VDD_3V
VS S
VSS
VDD_1V
VDD_3V
VDD_1V
NC
NC
VS S
AVSS
AVDD_TX
AVSS
AVSS
E
RXCAP2
AVSS
AVDD_RX
AVSS
V SS
VDD_3V
VDD_3V
VS S
VDD_RX_ CORE
VDD_TX_ CORE
VDD_TX_ CORE
TXCLK_SEL
VDD_TX_ CORE
VDD_TTL
AVDD_TX
AVDD_TX
AVSS
TXCAP1
F
AVSS
AVSS
AVDD_RX
AVDD_RX
VDD_RX_ CORE
VDD_RX_ CORE
VSS_RX
VSS_RX
VSS_RX
VSS_TX
VSS_TX
VSS_TX
VDD_TX_ CORE
VDD_TTL
AVSS
AVDD_TX
AVSS
TXCAP2
G
AVSS
AVDD_RX
AVDD_RX
AVDD_RX
VDD_RX_ CORE
VDD_RX_ CORE
VSS_RX
VSS_RX
VSS_RX
VSS_TX
VSS_TX
VSS_TX
VDD_TX_ CORE
AVSS
AVDD_TX
AVSS
AVSS
AVSS
H
RXLOCKDET TXLOCKDET 155/77MCKP 155/77MCKN
VDD_RX_ CORE
V S S _ RX
VSS_RX
VSS_RX
VSS_RX
VSS_TX
VSS_TX
VSS_TX
VDD_TX_ CORE
VSS
AVDD_TX
AVSS
REFCLKN
REFCLKP
J
VSS_LVPECL
NC
NC
NC
VDD_RX_ CORE
V S S _ RX
VSS_RX
VSS_RX
VSS_RX
VSS_TX
VSS_TX
VSS_TX
VDD_TX_ CORE
VSS
AVDD_TX
VDD_1V_REF
VSS_REF
VDD_3V_REF
K
POUTP0
POUTN0
VDD_LVPECL VSS_LVPECL
NC
V DD_ RX _ CORE
VSS_RX
VSS_RX
VSS_RX
VSS_TX
VSS_TX
VSS_TX
VDD_TX_ CORE
PINN15
PINP15
VSS_CMOS
PINN14
PINP14
L
VSS_LVPECL
POUTP1
POUTN1
VDD_LVPECL
VDD_RX_ CORE
VDD_RX_ CORE
VSS_RX
VSS_RX
VSS_RX
VSS_TX
VSS_TX
VSS_TX
VDD_TX_ CORE
VDD_1V
VSS_CMOS
PINN13
PINP13
VSS_CMOS
M
POUTP2
POUTN2
VDD_LVPECL VSS_LVPECL
VDD_RX_ CORE
VSS_RX
VDD_RX_COVDD_LVPECL RE
VDD_RX_ CORE
VDD_TX_ CORE
VSS_TX
VDD_TX_ CORE
VSS_CMOS
PINN11
PINP11
VDD_3V
PINN12
PINP12
N
VSS_LVPECL
POUTP3
POUTN3
VSS_LVPECL VDD_LVPECL
POUTN11
VDD_LVPECL
POCLKN
VSS-LVPECL VDD_LVPECL
VDD_1V
VSS_CMOS
PINN1
VDD_3V
VDD_1V
PINN10
PINP10
VSS_CMOS
P
POUTP4
POUTN4
VDD_LVPECL VDD_LVPECL
POUTN9
POUTP11
POUTN13
POCLKP
VDD_LVPECL VSS_LVPECL
VSS_CMOS
PICLKN
PINP1
PINN3
VSS_CMOS
VSS_CMOS
PINN9
PINP9
R
VSS_LVPECL
POUTP5
POUTN5
VSS_LVPECL
POUTP9
VSS_LVPECL
POUTP13
VSS_LVPECL VDD-LVPECL
PHERRN
VDD_3V
PICLKP
VDD-1V
PINP3
VDD_3V
PINN8
PINP8
VSS_CMOS
T
POUTP6
POUTN6
VSS_LVPECL
POUTN8
VDD_LVPECL
POUTN12
VDD_LVPECL
POUTN15
VSS-LVPECL
PHERRP
PHINITN
VSS_CMOS
PINN2
VSS_CMOS
PINN5
VSS_CMOS
PINN7
PINP7
U
VDD_LVPECL VSS_LVPECL
POUTN7
POUTP8
POUTN10
POUTP12
POUTN14
POUTP15
PCLKN
VDD_LVPECL
PHINITP
PINN0
PINP2
PINN4
PINP5
PINN6
VSS_CMOS
VDD_3V
V
VSS_LVPECL VDD-LVPECL
POUTP7
VSS_LVPECL
POUTP10
VSS_LVPECL
POUTP14
VSS_LVPECL
PCLKP
VSS
VSS_CMOS
PINP0
VSS_CMOS
PINP4
VSS_CMOS
PINP6
VDD_1V
VSS_CMOS
16
May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Figure 7. Package Drawing 324 PBGA
S3055
Table 6. Thermal Management
Device
S3055
Max Package Power
1.9 W
ja (Still Air)
27.4 C/W
jc
1.9 C/W
Note: S3055 requires an airflow of 300 LFPM for industrial operating range.
May 25, 2001 / Revision A
17
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 7. Performance Specifications
Parameter Nominal VCO Center Frequency CSU and CDR Jitter Generation (CSU) Min Typ 2.488 Max Units GHz Conditions
0.007
Reference Clock Frequency Tolerance Reference Clock Input Duty Cycle Reference Clock Rise and Fall Times Acquisition Time (CDR) 155.52 MHz REFCLK
-100 45
+100 55 1.5 250
UI (rms) Note: Output jitter measured at SONET operating rate using appropriate filter, rms jitter, in lock. ppm 20 is required to meet SONET output frequency specification. % ns sec 10% to 90% of amplitude. Minimum transition density of 20%. Guaranteed but not tested. With device already powered up and valid ref. clk. Guaranteed but not tested.
Frequency difference at which the PLL goes out of lock (REFCLK compared to the divided down VCO clock)-CDR Frequency difference at which the receive PLL goes into lock (REFCLK compared to the divided down VCO clock) CDR Jitter Generation (CDR) with VCO locked to SERDATIP/N REFCLK to PCLK Delay RSTB to TXLOCKDET Delay Bit Latency - Number of clock cycles after PINP/N[X] appears at TSDP/N
450
600
770
ppm
220
30 0
390
ppm
Guaranteed but not tested.
0.01
0
6.43 500 20
UI (rms) Note: This mode is valid in the SLPTIME, RLPTIME, and LLEB mode only. ns Guaranteed but not tested. s Guaranteed but not tested.
REFCLK Guaranteed but not tested. Cycles
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May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 8. Jitter Tolerance Specifications
Parameter Jitter Tolerance STS-48 Min 0.4 Typ 0.5 Max Units UI Conditions 1 MHz < f < 20 MHz Data Pattern = 27-1 PRBS
S3055
Table 9. Absolute Maximum Ratings
The following are the absolute maximum stress ratings for S3055 device. Stresses beyond those listed may cause permanent damage to the device. Absolute maximum ratings are stress ratings only and operation of the device at the maximums stated or any other conditions beyond those indicated in the "Recomended Operating Conditions" of the document are not inferred.
Parameter Storage Temperature Voltage on 3.3 Volts Power pins with respect to GND Voltage on 1.8 Volts Power pins with respect to GND Voltage on any LVPECL Input Pin
Mi n -6 5 -0.5 -0.2 0
Typ
Max 150 +3.6 +1.98 VDD_LVPECL
Units
o
C
V V V
ESD Ratings The S3055 is rated to the following voltages based on the human body model: 1. All pins are rated at 500 volts except TXCAP1, TXCAP2 and TSDP. TXCAP1, TXCAP2 and TSDP are rated at 100 volts.
Table 10. Recommended Operating Conditions
Parameter Ambient Temperature Under Bias1 Voltage on 1.8 Volts Power Planes with respect to GND Voltage on 3.3 Volts Power Planes with respect to GND Voltage on any LVPECL Input Pin Voltage on any LVTTL Input Pin 1.8 Volts Supply Current2 3.3 Volts Supply Current2
1. 300 LFPM of airflow is required for a upper temperature range of 85 C. 2. Outputs unloaded.
Min 0 1.71 3.135 0 0
Typ
Max 70
Units
o
C
1.8 3.3
1.89 3.465 VDD_LVPECL VDD_TTL 550 150
V V V V mA mA
May 25, 2001 / Revision A
19
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 11. LVTTL Input/Output DC Characteristics
Parameter VIH VIL IIH IIL VOH VOL Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage Output Low Voltage -500 2.4 0.5 Min 2.0 0.0 Typ Max VDD_TTL 0.8 50 Units V V A A V V Conditions VDD_TTL = Max VDD_TTL = Max VIN = 2.4 V VIN = 0.5 V VCC = min IOH = -100 A VCC = min IOL = 1 mA
Table 12. Internally Biased Differential LVPECL Input DC Characteristics
Parameter VIL VIH VINSINGLE VINDIFF VBIAS Description LVPECL Input Low LVPECL Input High Single Ended Input Voltage Swing Diff. Input Voltage Swing Input DC Bias Min VDD_LVPECL -2.0 VDD_LVPECL -1.25 200 40 0 VDD_LVPECL -0.65 VCC -0.5 Typ Max VDD_LVPECL -1.4 VDD_LVPECL -0.55 1200 2400 VDD_LVPECL -0.35 Units V V mV mV V Conditions Funtional Test Only. Funtional Test Only. See Figure 12. See Figure 12.
20
May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 13. Differential LVPECL Output DC Characteristics
Parameter Description Single Ended Output Voltage Swing Min Typ Max Units
S3055
Conditions 270 to GND. 100 Line to Line. See Figure 12. 270 to GND. 100 Line to Line. See Figure 12. 270 to GND. 100 Line to Line. 270 to GND. 100 Line to Line.
VOUTSINGLE
500
90 0
mV
VOUTDIFF
Diff. Output Voltage Swing
1000
1800
mV
VOH
Output High Voltage
VDD_ LVPECL -1.09 VDD_ LVPECL -1.93
VDD_ LVPECL -0.83 VDD_ LVPECL -1.44
V
VOL
Output Low Voltage
V
May 25, 2001 / Revision A
21
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 14. Single-Ended LVPECL Input DC Characteristics
Parameter VIL VIH Description PECL Input Low Voltage PECL Input High Voltage Min VDD_LVPECL -2.0 VDD_LVPECL -1.25 Typ Max VDD_LVPECL -1.40 VDD_LVPECL -0.55 Units V V Conditions Functional test only. Functional test only.
Table 15. Differential CML Output DC Characteristics
Parameter VOH (CLOCK) VOL (CLOCK) VOUTDIFF (CLOCK) VOUTSINGLE (CLOCK) VOH (DATA) VOL (DATA) VOUTDIFF (DATA) VOUTSINGLE (DATA) Description CML Output High Voltage. CML Output Low Voltage. CML Serial Output Differential Voltage Swing CML Serial Output SingleEnded Voltage Swing CML Output High Voltage. CML Output Low Voltage. CML Serial Output Differential Voltage Swing CML Serial Output SingleEnded Voltage Swing Min VDD_TSCLK -0.42 VDD_TSCLK -1.01 800 Typ Max VDD_TSCLK -0.25 VDD_TSCLK -0.71 1400 Units V V mV 100 line-toline. See Figure 12. 100 line-toline. See Figure 12. Conditions
400 VDD_TSD -0.45 VDD_TSD -1.15 800 400
700 VDD_TSD -0.25 VDD_TSD -0.73 1400 700
mV V V mV mV
Table 16. CML Input DC Characteristics
Parameter VINDIFF VINSINGLE RDIFF Description Differential Input Voltage Swing Single-Ended Input Voltage Swing Differential Input Resistance Min 300 150 80 100 Typ Max 1600 800 120 Units mV mV Conditions See Figure 12. See Figure 12.
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May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 17. Transmitter AC Timing Characteristics
Parameter TSCLK Frequency TSCLK Duty Cycle TSCLK Duty Cycle Distortion w.r.t. RSCLK (internal) or BYPASSCLK (In SLPTIME, LLEB or BYPASS modes) PICLK Duty Cycle tSPIN tHPIN tSTSD tHTSD PINP/N[15:0] Setup Time w.r.t. PICLK PINP/N[15:0] Hold Time w.r.t. PICLK TSD Setup Time w.r.t. TSCLK Rising TSD Hold Time w.r.t. TSCLK Rising PCLK to PICLK drift after FIFO is centered PCLK Duty Cycle TSCLK Rise and Fall Time TSD Rise and Fall Time 45 35 1.5 0.5 120 120 5.2 55 120 150 45 Description Min Max 2.488 55 5.0 65
S3055
Units GHz % % % ns ns ps ps ns % ps ps
Figure 8. Transmitter Input Timing1
PICLKP tSPIN tHPIN
Figure 9. Transmitter Output Timing1
TSCLKP tSTSD TSD tHTSD
PINP/N[15:0]
Notes on Timing: 1. Timing is measured from the crossover point of the clock to the crossover point of the data.
May 25, 2001 / Revision A
23
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Table 18. AC Receiver Timing Characteristics
Parameter Description POCLK Duty Cycle tSPOUT tHPOUT POUTP/N[15:0] Setup Time w.r.t. POCLK POUTP/N[15:0] Hold Time w.r.t. POCLK Min 45 2.25 2 Max 55 Units % ns ns
Figure 10. Receiver Output Timing Diagram1
POCLKP tS POUT POUTP/N[15:0] tHPOUT
Notes on Timing: 1. Timing is measured from the crossover point of the clock to the crossover point of the data.
Figure 11. S3055 155.52 MHz REFCLK Phase Noise Limit
-60
-80
Phase Noise (dBc)
155 Limit 1 (100mUI jitter)
-100
155 Limit 2 (100mUI jitter)
-120
-140
-160
100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000
Freq (Hz)
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May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Figure 12. Differential Voltage Measurement
V(+) VSINGLE V(-)
S3055
V(+) - V(-) VDIFF = 2 X VSINGLE 0.0V
Note: V(+) - V(-) is the algebraic difference of the input signals.
Figure 13. Phase Adjust Timing1
4-10 BYTE CLOCKS
2 BYTE CLOCKS
PHERR PHINIT
PCLKP
PICLKP
TRANSFER CLK (Internal)
1. The byte clock = 155.52 MHz.
May 25, 2001 / Revision A
25
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Figure 14. Differential CML Output to +5V/+3.3V PECL Input AC Coupled Termination
+1.8 V
0.01 F
Zo=50
+5 V/+3.3 V 100
0.01 F S3055 TSDP/N TSCLKP/N
Zo=50
Figure 15. Differential LVPECL Driver to LVPECL Input Termination
+3.3 V
Zo=50
130 82 130 82
+3.3 V
Zo=50 S3055 POUTP/N[15:0] / POCLKP/N PCLKP/N / PHERRP/N 155/77 MCKP/N
Figure 16. Differential LVPECL Driver to Differential LVPECL Input Termination
+3.3 V 270 270 S3055 POUTP/N[15:0] / POCLKP/N PCLKP/N / PHERRP/N 155/77MCKP/N
Zo=50 100 Zo=50
+3.3 V
26
May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Figure 17. +5V Differential PECL Driver to S3055 Differential CML Input AC Coupled Termination
S3055
+3.3/5 V 0.01 F 330 330 0.01 F Zo=50 Vcc1.8 - 0.5 V S3055 RSDP/N BYPASSCLKP/N Zo=50 Vcc1.8 - 0.5 V +1.8 V
100
Figure 18. +5V Differential PECL Driver to S3055 Differential LVPECL Reference Clock Input AC Coupled Termination
+5 V 0.01 F 330 330 0.01 F Zo=50 Zo=50 100
Vcc3.3 -0.5 V +3.3 V
Vcc3.3 -0.5 V S3055 REFCLKP/N
155 MHZ OSCILLATOR
Figure 19. +3V Differential LVPECL Driver to S3055 Differential LVPECL Reference Clock Input DC Coupled Termination
+3.3 V Zo=50 330 330 Zo=50 100
Vcc3.3 -0.5 V
+3.3 V
Vcc3.3 -0.5 V S3055 REFCLKP/N
155 MHz OSCILLATOR
May 25, 2001 / Revision A
27
S3055
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Figure 20. Differential LVPECL Driver to S3055 Internally Biased Differential LVPECL Inputs
+3.3 V Zo=50 100 Zo=50
Vcc3.3 -0.5 V
+3.3 V
Vcc3.3 -0.5 V S3055 PINP/N[15:0] PICLKP/N PHINITP/N
Figure 21. External Loop Filter Components
20 F 51 RXCAP1 51 RXCAP2 150
10 F 150 TXCAP2
TXCAP1
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May 25, 2001 / Revision A
SONET/SDH/ATM OC-48 16 BIT TRANSCEIVER WITH CDR
Ordering Information
PREFIX DEVICE PACKAGE
S3055
S - Integrated Circuit
3055
PB-324PBGA
X Prefix
XXXX Part No.
XX Package (S3055 PB)
IS
O 90 0
RT
IFI
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 2001 Applied Micro Circuits Corporation D147/R710
May 25, 2001 / Revision A
E
D
1
CE
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