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| ADVANCE INFORMATION MICRONAS INTERMETALL VDP 3108 Single-Chip Video Processor MICRONAS Edition Oct. 12, 1994 6251-352-3AI VDP 3108 Contents Page 4 4 5 5 5 5 5 5 5 5 8 8 8 8 8 9 9 9 10 11 11 12 12 12 12 13 13 13 13 16 16 16 16 17 17 17 17 18 19 20 21 22 22 22 24 24 24 2 Section 1. 1.1. 2. 2.1. 2.1.1. 2.1.2. 2.1.3. 2.1.4. 2.1.5. 2.1.6. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.2.6. 2.2.7. 2.2.8. 2.2.9. 2.2.10. 2.3. 2.3.1. 2.3.2. 2.3.3. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.4.4. 2.4.5. 2.4.6. 2.4.7. 2.4.8. 2.4.9. 2.4.10. 2.5. 2.5.1. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.4. 2.7 3. 3.1. 3.2. Title Introduction System Architecture Functional Description Analog Front End Input Selector Clamping Automatic Gain Control Analog-to-Digital Converters ADC Range Digitally Controlled Clock Oscillator Color Decoder IF-Compensation Demodulator Chrominance Filter Frequency Demodulator Burst Detection Color Killer Operation Delay Line/Comb Filter Luminance Notch filter Skew Filter Picture Bus Color Space Digital Video Interfaces Picture Bus Interface Digital RGB Interface Priority Codec Display Processor Contrast Adjustment Black Level Expander Dynamic Peaking Brightness Adjustment Soft Limiter Chroma Interpolation Chroma Transient Improvement Dematrix RGB Processing FIFO Display Buffer Analog Back End CRT Measurement and Control Synchronization and Deflection Video Sync Processing Deflection Processing Vertical, East-West Deflection Protection Circuitry Reset and Standby Functions Serial Interface I2C Bus Interface Control and Status Registers ADVANCE INFORMATION MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 35 35 35 38 40 42 44 44 44 44 44 54 60 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.3. 4.6.4. 4.7. 5. Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions (pin numbers for 68-PLCC) Pin Configuration Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Crystal Characteristics Application Circuit Data Sheet History MICRONAS INTERMETALL 3 VDP 3108 Single-Chip Video Processor 1. Introduction The entire video processing and controlling for a color TV has been developed on a single chip in 0.8 CMOS technology. Modular design and submicron technology allow the economic integration of features in all classes of TV sets. Open architecture is the key word to the new DSP generation. Flexible standard building blocks have been defined that offer continuity and transparency of the entire system. One IC contains the entire video and deflection processing and builds the heart of a modern color TV. Its performance and complexity allow the user to standardize his product development. Hardware and software applications can profit from the modularity as well as manufacturing, system support or maintenance. The main features are: - low cost, high performance - all digital video processing - multi-standard color decoder PAL/NTSC/SECAM - 3 composite, 1 S-VHS input - integrated high-quality AD/DA converters ADVANCE INFORMATION - sync and deflection processing - luminance and chrominance features, e.g. peaking, color transient improvement - programmable RGB matrix - various digital interfaces - embedded RISC controller (80 MIPS) - one crystal, few external components - single power supply 5 V - 0.8 CMOS Technology - 68-pin PLCC or 64-pin Shrink DIL Package 1.1. System Architecture Two main modules have been defined: Video Processor and Display Processor. They are designed as silicon building blocks. Their partitioning permits a variety of IC configurations with the aim to satisfy the particular requirements of different applications. Both, analog and digital interfaces, support state of the art TV receivers as well as other environments. Fig. 1-1 shows the block diagram of the singlechip Video Processor which consists of both modules. feature interface Frontend Color Decoder Display Processor Backend Fast Blank Analog RGB V1 V2/Y C V3 2*ADC, 8 bit NTSC/PAL/SECAM YCrCb -> RGB 3*DAC, 10 bit R G B Hor. Flyback Clock Gen. DCO 20.25 MHz I2C Sync and Deflection 3 PLLs, horizontal output, vertical outputs H/V Drive Fig. 1-1: VDP block diagram 4 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 2.1.3. Automatic Gain Control A digitally working automatic gain control adjusts the magnitude of the selected baseband by +6/-4.5 dB in 64 logarithmic steps to the optimal range of the ADC . The gain of the video input stage including the ADC is 213 steps/V for all three standards (PAL/NTSC/SECAM/ Y/C), with the AGC set to 0 dB. 2. Functional Description 2.1. Analog Front End This block provides the analog interfaces to all video inputs and mainly carries out analog-to digital conversion for the following digital video processing. A block diagram is given in figure 2-1. Most of the functional blocks in the front end are digitally controlled (clamping, AGC and clock-DCO). The control loops are closed by the Fast Processor (`FP') embedded in the decoder. 2.1.1. Input Selector Up to four analog inputs can be connected. Three inputs are for input of composite video or S-VHS luma signal. These inputs are clamped to the sync back porch and are amplified by a variable gain amplifier. One input is for connection of S-VHS carrier-chrominance signal. This input is internally biased and has a fixed gain amplifier. 2.1.2. Clamping The composite video input signals are AC coupled to the IC. The clamping voltage is stored on the coupling capacitors and is generated by digitally controlled current sources. The clamping level is the back porch of the video signal. S-VHS chroma is also AC coupled. The input pin is internally biased to the center of the ADC input range. CVBS/Y 2.1.4. Analog-to-Digital Converters Two ADCs are provided to digitize the input signals. Each converter runs with 20.25 MHz and has 8 bit resolution. An integrated bandgap circuit generates the required reference voltages for the converters. The two ADCs are of a 2-stage subranging type. 2.1.5. ADC Range The ADC input range for the various input signals and the digital representation is given in table 2-1 and figure 2-2. 2.1.6. Digitally Controlled Clock Oscillator The clock generation is also a part of the analog front end. The crystal oscillator is controlled digitally by the control processor; the clock frequency can be adjusted within 150 ppm. reference generation VIN3 AGC +6/-4.5dB VIN2 input mux clamp DAC level gain CVBS/Y ADC 8 digital CVBS or Y to color decoder CVBS/ Y/C VIN1 C CIN output mux 8 bias/ clamp ADC digital chroma select level DAC freq. DVC O 150 ppm frequ. doubler frequ. divider 20.25 MHz Fig. 2-1: Analog front end system clocks MICRONAS INTERMETALL 5 VDP 3108 Table 2-1: ADC input range for PAL input Signal Signal ADC Range [steps] -6 dB CVBS 100% CVBS 75% CVBS video (luma) sync clamp level Chroma burst 100% Chroma 75% Chroma bias level 252 (clipped at 125 IRE) 213 149 64 (AGC reference) 68 64 190 143 128 300 890 670 667 500 350 150 ADVANCE INFORMATION Input Level [mVpp] 0 dB 1333 1000 700 300 +4.5 dB 2238 1679 1175 504 CVBS/Y upper headroom = 38 steps = 1.4 dB = 25 IRE 255 217 192 Chroma headroom = 56 steps = 2.1 dB 228 192 white video = 100 IRE 128 128 black = clamp level 68 32 0 80 32 lower headroom = 4 steps = 0.2 dB Fig. 2-2: ADC ranges for CVBS/Luma and Chroma, PAL input signal 6 IIIIIIIII IIIIIIIII MICRONAS INTERMETALL sync = 41 IRE IIIIIIIII IIIIIIIII 100% Chroma 75% Chroma burst IIIIIIIIII IIIIIIIIII IIIIIIIIII IIIIIIIIII MUX 1H Delay EEEE EEEE E EEEE EEEE E EEEE EEEE E EEEE EEEE E MUX Chroma 8 IF- compens. 8 Lowpass & Multiplex Limit detect SIN/COS gener. phase frequ. EEEE E EEEE E EEEE E EEEE E EEE EEE EEE EEE EEE EEE EEE EEE EEE EEE EEEE EEE EEE EEE EEEE EEE EEE EEEE EEE EEEE EEEE EEEE E E EEEE EEEE E E EEEE EEEE E E ECCC E ECCC E ECCC E 8 EEE EEE EEE EEE EEE EEE EEE MICRONAS INTERMETALL 7 ADVANCE INFORMATION CVBS or Y 8 Fig. 2-3: Color decoder Notch- filter to Sync- separation ROM Cross- switch Comb Skew- filter AAAA AAAA AAAA BUS arbiter Delay- match FIFO 8 Delay- match FIFO 8 dig. Y PRIO DCS Skew MUX Skew- filter dig. Cr C b Phase Bellfilter Lowpass Phase- demod. CORDIC Diff. Freq. Deemph. Clamp Lowpass Magn. Burst Key to ACC to APC to IDENT Deemph. Adjust Dr, Db scaling ACC Lowpass Adjust VDP 3108 SECAM processing PAL/NTSC processing VDP 3108 2.2. Color Decoder In this block the entire luma/chroma separation and multi standard color demodulation is carried out. The color demodulation uses an asynchronous clock, thus allowing a unified architecture for all color standards. Both luma and chroma are processed to an orthogonal sampling raster. Luma and Chroma delays are matched. The total delay of the decoder is adjustable by a FIFO memory. Thus, including the delay of the display processing, exactly 64 sec processing delay can be obtained. The output of color decoder is YCrCb in a 4:2:2 format. ADVANCE INFORMATION such as PAL 3.58 or NTSC 4.43 can also be demodulated. 2.2.3. Chrominance Filter The demodulation is followed by a lowpass filter for the color difference signals for PAL/NTSC. SECAM requires a modified lowpass function with bell-filter characteristic. At the output of the lowpass filter all luma information is eliminated. The lowpass filters are calculated in time multiplex for the two color signals. Three bandwidth settings (narrow, normal, broad) are available for each standard. The filter passband can be shaped with an extra peaking term at 1.25 MHz. 2.2.1. IF-Compensation With off-air or mistuned reception any attenuation at higher frequencies or asymmetry around the color subcarrier is compensated. Three different settings of the IF-compensation are possible: flat (no compensation) 6 dB /octave 12 dB /octave dB 0 -10 PAL/ NTSC -20 normal -30 narrow -40 broad -50 0 1 2 3 4 5 MHz 0 dB SECAM -10 -20 -30 -40 -50 MHz 0 1 2 3 4 5 Fig. 2-4: Frequency response of chroma IF-compensation Fig. 2-5: Frequency response of chroma filters 2.2.2. Demodulator The entire signal (which might still contain luma) is now quadrature-mixed to the baseband. The mixing frequency is equal to the subcarrier for PAL and NTSC, thus achieving the chroma demodulation. For SECAM, the mixing frequency is 4.286 MHz giving the quadrature baseband components of the FM modulated chroma. After the mixer, a lowpass filter selects the chroma components; a downsampling stage converts the color difference signals to a multiplexed half rate data stream. The subcarrier frequency in the demodulator is generated by direct digital synthesis; therefore substandards 8 2.2.4. Frequency Demodulator The frequency demodulator for demodulating the SECAM signal is implemented as a CORDIC-structure. It calculates the phase and magnitude of the quadrature components by coordinate rotation. The phase output of the CORDIC processor is differentiated to obtain the demodulated frequency. After a programmable deemphasis filter the Dr and Db signals are scaled to standard CrCb amplitudes and fed to the crossover-switch. MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 color distortion and chroma noise is reduced. In the NTSC combfilter mode, Fig. 2-7 d), the delay line is in the composite signal path, thus allowing reduction of cross-color components as well as cross-luminance. The loss of vertical resolution in the luminance channel is compensated by adding the vertical detail signal with removed color information. CVBS MHz 8 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 dB Notch filter Chroma Process. Y CrC b Luma 8 Y Chroma Process. 0.01 0.1 1.0 chroma 8 CrC b Fig. 2-6: Frequency response of SECAM deemphasis a) conventional CVBS 8 Notch- filter b) S-VHS Y 2.2.5. Burst Detection In the PAL/NTSC-system the burst is the reference for the color signal. The phase and magnitude outputs of the CORDIC are gated with the color key and used for controlling the phase-lock-loop (APC) of the demodulator and the automatic color control (ACC) in PAL/NTSC. The ACC has a control range of +30 ... -6 dB. For SECAM decoding, the frequency of the burst is measured. Thus, the current chroma carrier frequency can be identified and is used to control the SECAM processing. The burst measurements also control the color killer operation; they can be used for automatic standard detection as well. 2.2.6. Color Killer Operation The color killer uses the burst-phase, -frequency measurement to identify a PAL/NTSC or SECAM color signal. For PAL/NTSC the color is switched off (killed) as long as the color subcarrier PLL is not locked. For SECAM the killer is controlled by the toggle of the burst frequency. The burst amplitude measurement is used to switch-off the color if the burst amplitude is below a programmable threshold. Thus color will be killed for very noisy signals. The color amplitude killer has a programmable hysteresis. 2.2.7. Delay Line / Comb Filter The color decoder uses one fully integrated delay line. Only active video is stored. The delay line application depends on the color standard: NTSC: combfilter or color compensation PAL: color compensation SECAM: crossover-switch In the NTSC compensated mode, Fig. 2-7 c), the color signal is averaged for two adjacent lines. Thus cross- MICRONAS INTERMETALL Chroma Process. 1H Delay CrC b c) compensated CVBS 8 1H Delay Notch- filter Y Chroma Process. CrC b d) Comb Filter Fig. 2-7: NTSC color decoding options CVBS 8 Notch- filter Y Chroma Process. 1H Delay CrC b a) conventional Luma 8 Y Chroma 8 Chroma Process. 1H Delay CrC b b) S-VHS Fig. 2-8: PAL color decoding options CVBS 8 Notch- filter Y Chroma Process. 1H Delay MUX CrC b Fig. 2-9: SECAM color decoding 9 VDP 3108 2.2.8. Luminance Notch Filter If a composite video signal is applied, the color information is suppressed by a programmable notch filter. The position of the filter center frequency depends on the ADVANCE INFORMATION subcarrier frequency for PAL/NTSC. For SECAM, the notch is directly controlled by the chroma carrier frequency. This considerably reduces the cross-luminance. The frequency responses and the delay characteristics of all three systems are shown below. 10 dB 100 90 nsec 0 80 70 -10 60 50 -20 40 30 -30 20 10 -40 0 2 4 6 8 10 MHz 0 0 2 4 6 8 10 MHz PAL notch filter dB 10 0 100 90 80 70 -10 60 50 -20 40 30 -30 20 10 -40 0 2 4 6 8 10 MHz 0 nsec MHz 0 2 4 6 8 10 SECAM notch filter 10 dB 100 90 nsec 0 80 70 -10 60 50 -20 40 30 -30 20 10 -40 0 2 4 6 8 10 MHz 0 0 2 4 6 8 10 MHz NTSC notch filter Fig. 2-10: Frequency Responses and Time Delay Characteristics for PAL, SECAM, NTSC 10 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 allow to apply a group delay to the input signals without introducing waveform of frequency response distortion. The amount of phase shift of this filter is controlled by the horizontal PLL1. The accuracy of the filters is 1/32 clocks for luminance and 1/4 clocks for chroma. Thus the output of the color decoder is in an orthogonal pixel format even in the case of nonstandard input signals such as VCR. 2.5 clocks 2.2.9. Skew Filter The system clock is free running and not locked to the TV line frequency. Therefore, the ADC sampling pattern is not orthogonal. The decoded YCrCb signals are converted to an orthogonal sampling raster by skew filter block at the output of the color decoder. The skew filters are controlled by a skew parameter and 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 0 2 4 6 8 10 MHz 0.5 0.4, 0.6 0.3, 0.7 0.2, 0.8 0.1, 0.9 dB parameter: , 32 steps 0, 1.0 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 0 parameter: , 32 steps 1.0 0.9 0.8 0.7 0.6 0.5 0.2 0.3 0.4 0 0.1 MHz 2 4 6 8 10 Fig. 2-11: Luminance, Chrominance skew filter magnitude frequency response Fig. 2-12: Luminance, chrominance skew filter group delay characteristics 2.2.10. Picture Bus Color Space Output of the color decoder block is YCrCb with 20.25 Msamples/s. Only active video is transferred. The number of active samples is 1068 per line for all standards (525 lines and 625 lines). The following equations explain the data formats. The R,G,B source signals are already gamma-weighted. The transform matrix from R,G,B to color difference signals is given by: Y R*Y B*Y 0.299 0.587 0.114 0.701 * 0.587 * 0.114 * 0.299 * 0.587 0.886 R G B Studio Cr = 0.713*(R-Y) (CCIR 601) Cb = 0.564*(B-Y) In the color decoder the weighting for both color difference signals is adjusted individually. The default format will have the following specification: Y Cr Cb = 224*Y + 16 (pure binary), = 224*(0.713*(R-Y)) + 128 (offset binary), = 224*(0.564*(B-Y)) + 128 (offset binary). + In each TV broadcast standard different weighting factors for (R-Y) and (B-Y) are used: PAL: NTSC: SECAM: MAC V U I Q = 0.877*(R-Y) = 0.493*(B-Y) = V*cos33 - U*sin33 = V*sin33 + U*cos33 Optionally the picture bus format of the chrominance components Cr, Cb can be switched to two's complement format. The YCrCb FIFO memories allow an adjustable delay for the video processing e.g. one TV line. The memories are controlled by the horizontal sync information available in the front end and the display processor. Using the front end sync, a window for the active video is generated. Only active video data are written to the FIFO memories. The display processor generates the main sync signal from the display timing and data is read from the FIFOs using the main sync signal. This allows an adjustable delay as well as a variable delay, e.g. for VCR timebase correction. Dr = -1.9*(R-Y) Db = 1.5*(B-Y) Vm = 0.927*(R-Y) Um = 0.733*(B-Y) MICRONAS INTERMETALL 11 VDP 3108 2.3. Digital Video Interfaces The digital video interface allows insertion of digital data in YCrCb format on the internal YCrCb data bus. The orthogonal data structure of this bus is the ideal interface point to external data sources and sinks. On top of this, a host of formats are supported, e.g. support of level-2 teletext or the priority pixel bus concept. Figure 2-13 shows all available digital interfaces: YCrCb 16 bit 4:2:2 RBG 5 bit 4:4:4 PRIO 3 bit, source selection The YCrCb bus is used for video insertion. The RGB interface is used for insertion of a Teletext or OSD picture. The priority bus allows to mix up to 8 sources on the YCrCb / RGB bus. VDP Video Display Processor ADVANCE INFORMATION Via the MSY line, serial data is transferred which contains information about the main picture such as current line number, odd/even field etc.). It is generated by the deflection circuitry and represents the orthogonal timebase for the entire system. Feature ICs (e.g. PIP) will be synchronized to the main YCrCb bus. Digital insertion (boxing) is controlled by a priority system. 2.3.2. Digital RGB Interface Digital RGB from text or on-screen-display is connected via the Picture bus. The RGB signal is 5 bits wide. The RGB signals are not subject to any post-filtering. The RGB signal provides 3-bit RGB (one bit per color), the 4th bit allows to display half contrast colors. Bit 5 enables a programmable color-look-up table with 16 entries and 4 bit resolution per color. This allows the support of a World System Teletext level-2 color display. Display contrast for RGB data can be adjusted separately by three contrast multipliers. 2.3.3. Priority Codec PIP Fig. 2-13: VDP video interfaces 2.3.1. Picture Bus Interface The picture bus format between all DIGIT3000 ICs is YCrCb with 20.25 Msamples/s. Only active video is transferred, synchronized by the system main sync signal (MSY) which indicates the start of valid data for each scan line. The number of active samples per line is 1068 for all standards (525 and 625). 12 EE EEEEEEE E E EE EE EEEEEEE EEE EE EE E E EE EEEE EEE E EEEE EE EE YCrCb PRIO RGB CCU/ OSD Up to eight digital YCrCb or RGB sources (main decoder, PIP, OSD, Text, etc.) may be selected in real-time by means of a 3-bit priority bus. Thus a pixelwise bus arbitration and source switching is possible. It is essential that all YCrCb-sources are synchronous and orthogonal. In general each source (= master) has its own YCrCb bus request. This bus request may either be software or hardware-controlled, i.e. a fast blank signal. Data collision is avoided by a bus arbiter that provides the individual bus acknowledge in accordance to a user defined priority. Each master sends a bus request with his individual priority ID onto the PRIO-bus and immediately reads back the bus status. Only in case of positive arbitration (send-PRIO-ID = read-PRIO-ID) the bus acknowledge becomes active and the data is sent. This treatment has many features that have impact on the appearance of a TV picture: real-time bus arbitration (PIP, OSD, ...) priorities are software configurable different coefficients for different sources TPU MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 black level expander are shown in Fig. 2-14 and Fig. 2-15. The tilt point Lt is a function of the dynamic range of the video signal. Thus, the black level expansion is only performed when the video signal has a large dynamic range. Otherwise, the expansion to black is zero. This allows the correction of the characteristics of the picture tube. Lmax Ltr Lt BAM BTLT 2.4. Display Processor In the display processor the conversion from digital YCrCb to analog RGB is carried out. A block diagram is shown in figure 2-18. In the luminance processing path contrast and brightness adjustments and variety of features such as black level expansion, dynamic peaking and soft limiting are provided. In the chrominance path, the CrCb signals are converted to 20.25 MHz sampling rate and filtered by a color transient improvement circuit. The YCrCb signals are converted by a programmable matrix to RGB color space. The signals inserted via the YCrCb bus are identified by their respective priority. The display processor provides separate control settings for two pictures, i.e. different coefficients for a `main' and a `side' picture. The digital RGB insertion circuit allows the insertion of a 5 bit RGB signal. The color space for this signal is controlled by a programmable color look up table (CLUT) and contrast adjustment. The RGB signals and the display clock are synchronized to the horizontal flyback. For the display clock a gate delay phase shifter is used. The RGB signals are synchronized by a FIFO. In the analog back-end, three 10bit digital-to-analog converters provide the analog output signals. 2.4.1. Contrast Adjustment Lout Lmin Ltr BTHR Lin Fig. 2-14: Characteristics of the black level expander a) Lmax Lt Lmin The 8 bit luminance input is multiplied by a factor of 0 ... 2 in 64 steps. A 2-bit noise shaping on the result is used to increase the resolution of the luma signal. Contrast adjustment is separate for main and side picture. b) 2.4.2. Black Level Expander The black level expander enhances the contrast of the picture. Therefore the luminance signal is modified with an adjustable, nonlinear function. Dark areas of the picture are changed to black, while bright areas remain unchanged. The advantage of this black level expander is that the black expansion is performed only if there is a large dynamic range in the video signal and when it will be most noticeable to the viewer. The black level expander works adaptively. Depending on the measured amplitudes `Lmin' and `Lmax' of the lowpass-filtered luminance and an adjustable coefficient BTLT, a tilt point `Lt' is being established by Lt = Lmin + BTLT ( Lmax - Lmin). Above this value there is no expansion, while all luminance values below this point are expanded according to: Lout = Lin + BAM (Lin - Lt) A second threshold, Ltr, can be programmed, above which there is no expansion. The characteristics of the MICRONAS INTERMETALL Lt Fig. 2-15: Black-level-expansion a) luminance input b) luminance output 2.4.3. Dynamic Peaking Especially with composite input signals and notch filter luminance separation, it is necessary to improve the luminance frequency characteristics. In DIGIT3000 the luma response is improved by `dynamic' peaking. The algorithm has been optimized regarding step and frequency response. It adapts to the amplitude of the high frequency part. Small amplitudes are enhanced while large amplitudes stay nearly unmodified. 13 VDP 3108 The dynamic range can be adjusted to 0 ... +14 dB for small high frequency signals. Adjustment is separate for signal overshoot and for signal undershoot. For large signals the dynamic range is limited by a nonlinear function that does not create any visible alias components. The center frequency of the peaking filter is switchable from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter color decoding, the total system frequency responses for PAL and NTSC are shown in figure 2-17. Transients, produced by the dynamic peaking when switching video source signals, can be suppressed via the priority bus. dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz 20 ADVANCE INFORMATION dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz Fig. 2-16: Dynamic peaking frequency response dB CF= 3.2 MHz 15 10 5 CF= 2.5 MHz S-VHS 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz 20 dB CF= 3.2 MHz 15 10 5 CF= 2.5 MHz PAL/SECAM 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz dB 20 15 10 5 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz 20 dB CF= 3.2 MHz 15 10 5 CF= 2.5 MHz NTSC 0 -5 -10 -15 -20 0 2 4 6 8 10 MHz Fig. 2-17: Total frequency response for peaking filter and S-VHS, PAL, NTSC 14 MICRONAS INTERMETALL MICRONAS INTERMETALL 15 ADVANCE INFORMATION Fig. 2-18: Display processor contrast brightness + offset whitedrive measurement dynamic peaking clock dig. Y in softlimiter 8 MSY luma insert for CRTmeasurement 5 CLUT, CONTRAST whitedrive R* beamcurr.limiter display & clock control hor. flyback dig. RGB black level expander 8 blanking for CRTmeasurement Y Matrix R' FIFO 8 clocks R whitedrive G* beamcurr.limiter dig. Rout 10 Cr dig. CrCb in DTI (Cr) Interpol 4:4:4 Matrix G' DTI (Cb) FIFO 8 clocks G whitedrive B* beamcurr.limiter dig. Gout Cb dig. Bout Matrix B' FIFO 8 clocks B PRIO 3 side picture PRIO decoder select coefficients main picture VDP 3108 Matrix saturation VDP 3108 2.4.4. Brightness Adjustment ADVANCE INFORMATION LPF LIM1 LIM2 The DC-level of the luminance signal can be adjusted by -30 ... +100 % with 8 bit resolution. It is desirable to keep a small offset with the signal to prevent undershoots from the peaking from being cut. The brightness adjustment is separate for main and side picture. IN HPF var. notch OUT Loop Filter 2.4.5. Soft Limiter Fig. 2-19: Block diagram of the soft limiter The dynamic range of the processed luma signal must be limited to prevent the CRT from overload. An appropriate headroom for contrast, peaking and brightness can be adjusted by the manufacturer according to the CRT-characteristic. All signals higher than above this limit will be `soft'-clipped. The soft limiter can support or even replace an analog beam current limiter. Aliasing due to signal limitation is avoided by using a filterbank with individual limiter circuits. 2.4.6. Chroma Interpolation A linear phase interpolator is used to convert the chroma sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz (4:4:4). The frequency response of the interpolator is shown in fig. 2-20. All further processing is carried out at the full sampling rate. dB 0 A block diagram of the soft limiter is shown in figure 2-19. The signal is split into high and low frequency bands. The low frequency part represents the average picture level; if the average level is too high the picture tube will overheat and produce coloration. The high frequency part represents the peak picture level which can be considerably higher than the average picture level. Due to this characteristic of the picture tube, both components are treated individually and are later recombined. For the low frequency band a limiter with adjustable threshold is used. The high frequency components produced in the limiter are below the nyquist frequency, therefore no disturbing alias frequencies are generated. For the high frequency band, the limiting is done by a variable gain notch filter, effectively bounding the peak to peak amplitude of the signal. In this way the signal is limited without generating unwanted aliasing. -10 -20 -30 -40 -50 0 2 4 6 8 10 MHz Fig. 2-20: Frequency response of the chroma interpolation filter 2.4.7. Chroma Transient Improvement The intention of this block is to enhance the chroma resolution. A correction signal is calculated by differentiation of the color difference signals. The differentiation can be adjusted according to the signal bandwidth, e.g. for PAL/NTSC/SECAM or digital component signals respectively. The amplitude of the correction signal is adjustable independently for the Cr/Cb signals. Small When the high and low frequency bands are added together again a second limiter sets the exact signal amplitude range. The state of this limiter is used to control the attenuation of the variable notch filter. 16 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 noise amplitudes in the correction signal are suppressed by an adjustable coring circuit. To eliminate `wrong colors' , which are caused by over and undershoots at the chroma transition, the sharpened chroma signals are limited to a proper value automatically. a) R G+ B 1 0 1.402 1 * 0.345 * 0.713 1 1.773 0 Y Cb Cr For a contrast setting of CTM=32 the matrix values are scaled by a factor of 64, see also table 3-1. 2.4.9. RGB Processing After adding the post processed luma, the digital RGBs are limited to 10 bits. Three multipliers are used to digitally adjust the whitedrive. Using the same multipliers an average beam current limiter is implemented. See also paragraph `CRT control'. 2.4.10. FIFO Display Buffer A FIFO is used to buffer the phase differences between the video source and the flyback signal. By using the described clock system, this `phase-buffer` is working with sub-pixel accuracy. It has a range of 8 clocks which is equivalent to +/- 200 ns @ 20.25 MHz. 2.5. Analog Back End The digital RGB signals are converted to analog RGBs using three video digital to analog converters (DAC) with 10 bit resolution. An analog brightness value is provided by three additional DACs. The adjustment range is 40% of the full RGB range. t Cr in Cb in t b) Ampl. t c) Cr out Cb out a) Cr Cb input of DTI b) Cr Cb input + Correction signal c) sharpened and limited Cr Cb Fig. 2-21: Digital Color Transient Improvement 2.4.8. Dematrix A 6-multiplier matrix transcodes the Cr and Cb signals to R-Y, B-Y and G-Y. The multipliers are also used to adjust color saturation in the range of 0 ... 2. The coefficients are signed and have a resolution of 9 bits. The matrix coefficients are separate for main and side picture. The matrix computes: R-Y = G-Y = B-Y = MR1*Cb + MR2*Cr MG1*Cb + MG2*Cr MB1*Cb + MB2*Cr The back end allows insertion of an external analog RGB signal. The RGB signal is key-clamped and inserted into the main RGB by the fast blank switch. The external RGB signals are virtually handled as priority bus signals. Thus they can be overlaid or underlaid to the digital picture. The external RGB signals can be independently adjusted in DC-level (brightness) and magnitude (contrast). The controls for the whitedrive / analog brightness and also for the external contrast and brightness adjustments are via the Fast Processor. The controls for the cutoff DACs are via I2C bus registers. Finally cutoff and blanking values are added to the RGB signals. Cutoff (dark current) is provided by three 9-bit DACs. The adjustment range is 60% of full scale RGB range. The analog RGB-outputs are current outputs with current-sink characteristics. The maximum current drawn by the output stage is obtained with peak white RGB. The initialization values for the matrix are computed from the standard ITUR matrix: MICRONAS INTERMETALL 17 VDP 3108 ADVANCE INFORMATION int. brightness * white drive R cutoff R 9 bit DAC 1.5 mA digital R in 10 10 bit DAC Video 3.8 mA int. brightness * white drive G 9 bit DAC 2.2 mA blanking 750 uA analog R out cutoff G 9 bit DAC 1.5 mA digital G in 10 bit DAC Video 3.8 mA int. brightness * white drive B 9 bit DAC 2.2 mA blanking 750 uA analog G out cutoff B 9 bit DAC 1.5 mA digital B in 10 bit DAC Video 3.8 mA 9 bit DAC 2.2 mA blanking 750 uA analog B out H V FP Interface ext. brightness * white drive R white drive R white drive G 8 bit ADC measurm. ext. contrast * white drive R * beam current lim. ext. contrast * white drive G * beam current lim. white drive B int . brightness ext. contrast ext. brightness 9 bit U/I-DAC 3.8 mA clamp 9 bit U/I-DAC 3.8 mA clamp ext. contrast * white drive B * beam current lim. 9 bit U/I-DAC 3.8 mA clamp key analog R in analog G in analog B in fast blank in Sense Input I/O Fig. 2-22: Analog back end 2.5.1. CRT Measurement and Control The display processor is equipped with an 8 bit PDMADC for all measuring purposes. The ADC is connected to the Sense input pin, the input range is 0...1.5V. The bandwidth of the PDM filter can be selected; the measurement window is 19/9.5 s for small/large bandwidth setting. The input impedance is more than 1 M. Cutoff and white drive current measurement is carried out during the vertical blanking interval. It is always using the small bandwidth setting. The current range for the cutoff measurement is set by connecting a sense resistor to then MADC input. For the whitedrive measure18 ment, the range is set by using a sense resistor and the range select switch 2 output pin. During the active picture the minimum and maximum beam current is measured. The measurement range can be set by using the range select switch pin. The timing window of this measurement is programmable. The intention is to automatically detect letterbox transmission or to measure the actual beam current. All control loops are closed via the external control microprocessor. In each field two sets of measurements can be taken: a) The picture tube measurement returns results for MICRONAS INTERMETALL measurement buffer 9 bit DAC 1.5 mA ext. brightness * white drive G 9 bit DAC 1.5 mA ext. brightness * white drive B blank & measurem. timing 9 bit DAC 1.5 mA ADVANCE INFORMATION VDP 3108 2.5.2. Average Beam Current Limiter The average beam current limiter (BCL) uses the sense input for the beam current measurement. The BCL uses a different filter to average the beam current during the active picture. The filter bandwidth is approximately 2 kHz. The beam current limiter has an automatic offset adjust that is active two lines before the first cutoff measurement line. The beam current limiter allows to set a threshold current. If the beam current is above the threshold, the excess current is low pass filtered and used to attenuate the RGB outputs by adjusting the white drive multipliers for the internal (digital) RGB signals and the analog contrast multipliers for the analog RGB inputs respectively. The lower limit of the attenuator is programmable, thus a minimum contrast can always be set. During the tube measurement the ABL attenuation is switched off. After the whitedrive measurement line it takes 3 lines to switch back to BCL limited drives and brightness. Typical characteristics of the ABL for different loop gains are shown in Fig. 2-24; for this example the tube has been assumed to have a square law characteristic. cutoff R cutoff G cutoff B white drive R or G or B (sequentially). b) The picture measurement returns active picture maximum current active picture minimum current. The tube measurement is automatically started when the cutoff blue result register is read. Cutoff control for RGB requires one field only while a complete white-drive control requires three fields. If the measurement mode is set to 'offset check' a measurement cycle is run with the cutoff / whitedrive signals set to zero. This allows to compensate the MADC offset as well as input the leakage currents. During cutoff and whitedrive measurements, the average beam current limiter function (ref. 2.5.2.) is switched of and a programmable value is used for the brightness setting. The start line of the tube measurement can be programmed via I2C bus, the first line used for the measurement, i.e. measurement of cutoff red, is 2 lines after the programmed start line. The picture measurement must be enabled by the control microprocessor after reading the min./max. result registers. The measurement is always started at the beginning of active video. The vertical timing for the picture measurement is programmable, and may even be a single line. Also the signal bandwidth is switchable for the picture measurement. Two horizontal windows are available for the picture measurement. The large window is active for the entire active line. Tube measurement is always carried out with the small window. Measurement windows for picture and tube measurement are shown in figure 2-23. beam current drive Fig. 2-24: Beam current limiter characteristics: beam current output vs. drive BCL threshold: 1 tube measurement picture meas. start 2.6. Synchronization and Deflection active video field 1/ 2 picture meas. end small window for active picture window for cutoff, white drive The synchronization and deflection processing is distributed over front end and back end. The video clamping, horizontal and vertical sync separation and all video related timing information are processed in the front end. Most of the processing that runs at the horizontal frequency is programmed on the internal Fast Processor (FP). Also the values for vertical & East-West deflection are calculated by the FP software. The display related synchronization, i.e. generation of horizontal and vertical drive and synchronization of horizontal and vertical drive to the video timing extracted in the front end, are implemented in hardware. 19 Fig. 2-23: Windows for tube and picture measurement MICRONAS INTERMETALL IIIIIIIII II II large window for active picture VDP 3108 2.6.1. Video Sync Processing Fig. 2-25 shows a block diagram of the front end sync processing. To extract the sync information from the video signal, a linear phase lowpass filter eliminates all noise and video contents above one MHz. The sync is separated by a slicer, the sync phase is measured. A variable window can be selected to improve the noise immunity of the slicer. The phase comparator measures the falling edge of sync as well as the integrated sync pulse. The sync phase error is filtered by a phase locked loop that is computed by the FP. All timing in the front end is derived from a counter that is part of this PLL and it thus counts synchronously to the video signal. A separate hardware block measures the signal back porch and also allows to gather maximum/minimum of . ADVANCE INFORMATION the video signal. This information is processed by the FP and used for of gain control and clamping. For vertical sync separation the sliced video signal is integrated. The FP uses the integrator value to derive vertical sync and field information. The information extracted by the video sync processing is multiplexed onto the hardware front sync signal (FSY) and is distributed to the rest of the video processing system. The format of the front sync signal is given in fig. 2-26. The data for the vertical deflection, the sawtooth and the East-West correction signal is calculated by the FP. The data is buffered in a FIFO and transferred to the back end by a single wire interface. PLL1 lowpass 1 MHz & syncslicer video input frontend timing clamp & signal meas. horizontal sync separation phase comparator counter & lowpass front sync generator FSY skew v blank even field clamping, colorkey, FIFO_write vertical sync separation Sawtooth Parabola Calculation FIFO vertical serial data VDATA E/W sawtooth Fig. 2-25: Sync separation block diagram F1 input analog video skew MSB skew not LSB used V: F V Parity F: Vert. blanking 0 = off 1 = on Field # 0 = field 1 1 = field 2 (not in scale) F0 F1 F2 F3 F4 F5 F0, F2..F5 reserved FSY Fig. 2-26: Front sync format 20 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 - PLL3 adjusts the phase of the horizontal drive pulse and compensates for the delay of the horizontal output stage. The horizontal drive circuitry uses a digital sine wave generator to produce the exact (subclock) timing for the drive pulse. The generator runs at 1 MHz; in the output stage the frequency is divided down to give drive-pulse period and width. In standby mode, the output stage is driven from an internal 1 MHz clock that is derived from the 20 MHz main clock oscillator and a fixed drive pulse width is used. When the circuit is switched out of standby operation the drive pulse width is programmable. The horizontal drive uses a high voltage (8V) open drain output transistor. H flyback 2.6.2. Deflection Processing The deflection processing generates the signals for the horizontal and vertical drive (fig. 2-27). This block contains two phase-locked loops: - PLL2 generates the horizontal and vertical timing. Phase and frequency are synchronized by the front sync signal. The Main Sync (MSY) signal that is generated from PLL2 is a multiplex of all display related data (fig. 2-28). This signal is intended for use by other processors, e.g. a PIP processor can use this signal to adjust to a certain display position. PLL3 phase comparator & lowpass DCO sinewave DAC & generator LPF 1:64 & output stage Standby clock H drive FSY main sync interface phase comparator & lowpass DCO line counter composite sync generator CSY MSY main sync generator display timing PLL2 clock & control V flyback blanking, clamping, etc. E/W correction VDATA vertical serial data sawtooth PWM 15 bit V output PWM 15 bit E/W ouput Fig. 2-27: Deflection processing block diagram M1 input analog video M1 M2 M2 (not in scale) timing reference for PICTURE bus - chroma multiplex sync - active picture data after xxx clocks line [0] line not not not not not [8] used used used used used F line [7] Parity V Parity V: Vert. blanking 0 = off 1 = on F: Field # 0 = Field 1 1 = Field 2 line: Field line # 1...N MSY Fig. 2-28: Main sync format MICRONAS INTERMETALL 21 VDP 3108 2.6.3. Vertical, East-West Deflection ADVANCE INFORMATION The calculations of the vertical and east-west deflection waveforms are done by the fast processor. The algorithm is using a chain of accumulators to generate the required polynomial waveforms. To produce the deflection waveforms, the accumulators are initialized at the beginning of each field. The initialization values must be computed by the control processor and are written once to the fast processor of the VDP3108. The waveforms are described as polynomials in x, where x varies from 0 to 1 for one field. The initialization values for the accumulators a0..a3 for vertical deflection and a0..a4 for east-west deflection are 12 bit values. The coefficients that should be used to calculate the initialization values for different field frequencies are given is section 3. The vertical waveform can be scaled according the average beam current. This is used to compensate the effects of electric high tension changing due to beam current variations. In order to get a faster vertical retrace timing, the output impedance of the vertical DA converter can be reduced by 50% during the retrace. Fig. 2-29 shows some vertical and east-west deflection waveforms. The polynomial coefficients are given in the figure. P: a + b(x-0.5) + c(x-0.5)2 + d(x-0.5)3 + e(x-0.5)4 Fig. 2-29: Vertical and East-West Deflection Waveforms vertical: a,b,c,d 0,1,0,0 0,1,1,0 0,1,0,1 2.6.4. Protection Circuitry Picture tube and drive stage protection is provided through the following measures: - vertical flyback safety input: this pin looks for a negative edge in every field, otherwise the RGB drive signals are blanked. - drive shutoff during flyback: this feature can be selected by software. - safety input pin: this pin has two thresholds; at the lower threshold the RGB signals are blanked, at the higher threshold the horizontal drive is shut off. - The main oscillator and the horizontal drive circuitry are run from a separate (standby) power supply and are already active while the TV set is powering up. 2.7. Reset and Standby Functions Reset of most functions (exceptions see below) is performed by a reset pin. When this pin becomes active then all the internal registers and counters are set to 22 east-west: a,b,c,d,e 0,0,1,0,0 0,0,0,0,1 0,0,1,1,1 zero. When this pin is released, the internal reset is still active for 4us. After that time all the internal registers are loaded with the values defined in the defaults ROM. All the registers which are updated with the vertical sync get these values with the next vertical sync. During this initialization procedure (approx. 60 s) it is not possible to access the VDP via the serial interface (I2C). Access to other ICs via the serial bus is possible during that time. The same initialization procedure is started when the internal clock supervision detects that there is no clock (in the video processing part). Exceptions for initialization : - CCU clock divider (5MHz), not initialized by reset - standby clock divider (1MHz), not initialized by reset, but clock selector switched to standby clock During standby, only the horizontal drive pulse (see also 2.6.2.) and the 5 MHz clock output for the control microprocessor are active. The standby circuitry is reset when the standby supply voltage is applied. MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 RESETQ POR UPDATE 4 approx. 60 MICRONAS INTERMETALL 23 VDP 3108 3. Serial Interface 3.1. I2C Bus Interface Communication between the VDP and the external controller is done via I2C bus. The VDP has an I2C bus slave interface and uses I2C clock synchronization to slow down the interface if required. The I2C bus interface uses one level of subaddress: one I2C bus address is used to address the IC and a subaddress selects one of the internal registers. The I2C bus chip address is given below: A6 1 A5 0 A4 0 A3 0 A2 1 A1 0 A0 1 R/W 0/1 ADVANCE INFORMATION The registers of the VDP have 8 or 16 bit data size; 16 bit registers are accessed by reading/writing two 8 bit data words. Figure 3-1 shows I2C bus protocols for read and write operations of the interface; the read operation requires an extra start condition and repetition of the chip address with read command set. S 1000 101 W Ack 0111 1100 Ack 1 or 2 byte Data Ack P I2C write access subaddress 7c high byte Data low byte Data Ack Nak P S 1000 101 W Ack 0111 1100 Ack S 1000 101 R Ack I2C read access subaddress 7c SDA S SCL 1 0 P W R Ack Nak S P = = = = = = 0 1 0 1 Start Stop Fig. 3-1: I2C Bus Protocols 3.2. Control and Status Registers Table 3-1 gives definitions of the VDP control and status registers. The number of bits indicated for each register in the table is the number of bits implemented in hardware, i.e. a 9-bit register must always be accessed using two data bytes but the 7 MSB will be don't care on write operations and 0 on read operations. Write registers that can be read back are indicated in the following table. Functions implemented by software in the on-chip control microprocessor (FP) are explained elsewhere. A hardware reset initializes all control registers to 0. The automatic chip initialization loads a selected set of registers with the default values given in Table 3-1. The register modes given in Table 3-1 are: w w/r r v write only register write/read data register read data from VDP register is latched with vertical sync The mnemonics used in the Intermetall VDP demo software are given in the last column. 24 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Table 3-1: Control and status registers I2C Sub address Number of bits Mode Function Default Name FP INTERFACE 26 27 28 29 16 16 16 8 w w w/r r FP read address FP write address FP data FP status bit [0] bit [1] bit [2] write request read request busy FPRD FPWR FPDAT FPSTA FRONTEND 33 8 w/r input selector luma adc: bit [1:0] 00 VIN3 01 VIN2 10 VIN1 11 reserved input selector, chroma adc: bit [2] 0/1 select VIN1/CIN clamping modes: bit [3] 0/1 clamp on/off for chroma ad converter bit [4] 0/1 internal/external clamp enable (luma adc) bit [7:5] reserved VIS CS DCLC DCLY CHROMA PROCESSING 20 8 w/r IF compensation: bit [1:0] 0 2 3 bit [7:2] 12 dB 6 dB/oct 0 dB/oct reserved 3 IFC 22 8 w/r SECAM deemphasis or PAL lowpass peaking filter (1.25 MHz): bit [4:0] 0...31, PAL/NTSC: 8 SECAM: 24 bit [5] reserved chroma bandwidth select: luma delay adjust (LDY) PAL/NTSC SECAM bit [7:6] 00 narrow 0 25 01 normal 3 28 10 broad 6 31 11 reserved 8 DEEM 1 CBW LUMA PROCESSING 30 8 w/r luma notch frequency bit [5:0] 0..63/64 YNF = 128 cos (2 ff/fs) PAL/SECAM: 25 NTSC: 57 bit [6] 0/1 1: disable adaptive notch filter for SECAM must be set to 0 in PAL/NTSC bit [7] reserved luma / chroma matching delay: bit [4:0] 0..31 delay in clocks (+19) bit [7:5] reserved 25 0 YNF YNMD 31 8 w/r 3 LDF MICRONAS INTERMETALL 25 VDP 3108 ADVANCE INFORMATION I2C Sub address Number of bits Mode Function Default Name 34 8 w/r standard select: bit [2:0] 000 100 001 101 010 110 011 111 bit [3] 0/1 bit [7:4] 9 SECAM SECAM-SVHS PAL, NTSC compensated PAL-SVHS, NTSC compensated-SVHS NTSC, simple PAL NTSC-SVHS, simple PAL-SVHS NTSC comb filter mode reserved chroma polarity signed/offset-binary reserved STS PRIORITY BUS - FRONTEND 23 24 8 8 w/r w/r priority bus overwrite register bit [7:0] 8 bit mask, bit[x] = 1 : overwrite priority x priority bus ID register and enable bit [2:0] 0..7 priority ID, 0 highest bit [4:3] 0..3 pad driver strength, number of pull-down transistors 1..4 bit [6:5] reserved bit [7] 0/1 disable/enable priority 64 0 0 1 PIOV PID PIDD PIDE PRIORITY BUS - BACKEND priority mask register, if bit[x] is set to 1 then the function is active for the respective signal priority 75 71 7d 79 53 9 9 9 9 9 wv wv wv wv wv bit [7:0] bit [7:0] bit [7:0] bit [7:0] bit [7:0] bit [x] 0/1: bit [x] 0/1: bit [x] 0/1: bit [x] 0/1: bit [x] 0/1: select main/side picture contrast/brightness/matrix select main/external (via CLUT) RGB disable/enable black level expander disable/enable peaking transient suppression when signal is switched disable/enable analog fast blank input PBCT PBERGB PBBLE PBPK PBFB DISPLAY PROCESSOR - LUMA 61 65 51 55 2a 59 9 9 9 9 16 9 wv wv wv wv w/r wv bit [5:0] bit [5:0] bit [8:0] bit [8:0] bit [10:0] bit [11] 0..63/32 0..63/32 -256..255 -256..255 0/1 main picture contrast side picture contrast main picture brightness side picture brightness reserved disable/enable luma input -16 tilt coefficient (k2) amount (k1) disable expansion, threshold value 1 6 4 120 32 32 0 CTM CTS BRM BRS EY16 BTLT BAM BTHR black level expander: bit [3:0] 0..15 bit [8:4] 0...31 black level expander: bit [8:0] 0..511 5d 9 wv 26 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 I2C Sub address Number of bits Mode Function Default Name 69 9 wv luma peaking filter, the gain at high frequencies and small signal amplitudes is: 1 + (k1+k2)/8 bit [3:0] 0..15 k1: peaking level undershoot bit [7:4] 0..15 k2: peaking level overshoot luma peaking filter, coring bit [5:0] 0..31 coring level bit[7:6] reserved bit[8] 0/1 peaking filter CF 2.5/3.2 MHz luma soft limiter bit[7:0] 0..255 luma soft limiter bit[7:0] 0..255 luma soft limiter bit[4:0] 0..31 bit[5] 0/1 luma soft limiter bit[4:0] 0..31 bit[5] 0/1 maximum limit for low frequency comp. maximum limit for output signal loop filter gain enable/disable noise reduction notch filter gain (for manual notch) automatic/manual notch 4 4 1 0 255 255 PKUN PKOV COR PFS SLDC SLO SFG DNO SFGM SLM 6d 9 wv 4d 49 41 9 9 9 wv wv wv 45 9 wv DISPLAY PROCESSOR - CHROMA 14 8 w/r v luma / chroma matching delay bit [2:0] -2...2 variable chroma delay bit [3] 0/1 chroma polarity signed/offset binary digital transient improvement bit [4:0] 0..31 transient gain Cr bit [8:5] 0..15 coring level for Cr, Cb digital transient improvement bit [4:0] 0..31 transient gain Cb bit [7:5] reserved bit [8] 0/1 filter characteristic broad/narrow 0 1 31 3 31 1 LDB COB CPKV CCOR CPKU CFS 72 9 wv 7a 9 wv DISPLAY PROCESSOR - MATRIX 7c/74 6c/64 5c/54 78/70 68/60 9 9 9 9 9 wv wv wv wv wv main picture matrix coefficient R-Y = MR1M*Cb + MR2M*Cr bit[9:0] -256 ... 255/128 main picture matrix coefficient G-Y = MG1M*Cb + MG2M*Cr bit[9:0] -256 ... 255/128 main picture matrix coefficient B-Y = MB1M*Cb + MB2M*Cr bit[9:0] -256 ... 255 /128 side picture matrix coefficient R-Y = MR1S*Cb + MR2S*Cr bit[9:0] -256 ... 255/128 side picture matrix coefficient G-Y = MG1S*Cb + MG2S*Cr bit[9:0] -256 ... 255/128 0 86 -22 -44 113 0 0 73 -19 -37 MR1M, MR2M MG1M, MG2M MB1M, MB2M MR1S, MR2S MG1S, MG2S DISPLAY PROCESSOR - COLOR LOOK-UP TABLE 58/50 9 wv side picture matrix coefficient B-Y = MB1S*Cb+ MB2S*Cr bit[9:0] -256 ... 255/128 97 0 MB1S, MB2S MICRONAS INTERMETALL 27 VDP 3108 ADVANCE INFORMATION I2C Sub address Number of bits Mode Function Default Name 00-0f 16 wv color look-up table: 16 entries, 12 bit wide, The CLUT registers are initialized at power-up bit [3:0] 0..15 blue amplitude bit [7:4] 0..15 green amplitude bit [11:8] 0..15 red amplitude digital RGB insertion contrast for R/G/B bit [3:0] 0..13 RGB amplitude is CLUT*(4+x), RGB amplitude range is from 0 to 255 14,15 invalid 8 8 8 CLUT0 ... CLUT15 DRCT DGCT DBCT 4c/48/ 44 9 wv DISPLAY PROCESSOR - DISPLAY CONTROLS 6e 6a 66 9 wv cutoff R/G/B CR CG CB DISPLAY PROCESSOR - TUBE AND PICTURE MEASUREMENT 7b 77 7f 25 9 9 9 8 wv wv wv w/r picture measurement start bit [8:0] 0..511 first line of picture measurement picture measurement stop bit [8:0] 0..511 last line of picture measurement tube measurement line bit [8:0] 0..511 line for tube measurement tube and picture measurement control bit [0] 0/1 disable/enable tube measurement bit [1] 0/1 80/40 kHz bandwidth for picture measurement bit [2] 0/1 enable picture measurement start bit [3] 0/1 large/small picture measurement window bit [4] 0/1 measure / offset check for adc bit [7:5] reserved white drive measurement control bit [9:0] 0..1023 white drive value for measurement bit [10] reserved bit [11] 0/1 white drive measurement disabled/enabled measurement result registers minimum maximum white drive cutoff/leakage blue, read pulse starts tube measurement cutoff/leakage green cutoff/leakage red 23 308 15 PMST PMSO TML PMC 13 16 w/r 512 0 - WDRV EWDM MRMIN MRMAX MRWDR MRCB MRCG MRCR 18-1d 18 19 1a 1b 1c 1d 8 r 28 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 I2C Sub address Number of bits Mode Function Default Name 1e 8 r measurement adc status and fast blank input status measurement status register bit [0] 0/1 tube measurement active / complete bit [2:1] white drive measurement cycle 00 red 01 green 10 blue 11 reserved bit [3] 0/1 picture measurement active / complete bit [4] 0/1 fast blank input low / high (static) bit [5] 1 fast blank input negative transition (reset at read) bit [7:6] reserved - PMS 32 8 w fast blank interface mode bit [0] 0 fast blank from FBLIN pin 1 force internal fast blank signal to high bit [1] 0/1 fast blank active high/low bit [2] 0 clmpref 1 bit [7:3] reserved - FBMD DISPLAY PROCESSOR - TIMING 6f 73 6b 9 9 9 wv wv wv vertical blanking start bit [8:0] 0..511 first line of vertical blanking vertical blanking stop bit [8:0] 0..511 last line of vertical blanking start of active video bit [8:0] 0..511 first line of active video 305 25 30 VBST VBSO AVST DISPLAY PROCESSOR - HORIZONTAL DEFLECTION 67 9 wv adjustable delay from front sync to PLL2 adjust analog and digital RGB bit [8:0] -256..+255 +/- 8 sec adjustable delay from fly back to PLL2 adjust horizontal position for analog RGB picture bit [8:0] -256..+255 +/- 8 sec adjustable delay from fly back to main sync adjust horizontal position for digital picture bit [8:0] allowed values ? start of horizontal blanking bit [7:0] 0..255 0..th end of horizontal blanking bit [7:0] 0..255 0..th -141 POFS2 63 9 wv 0 POFS3 7e 9 wv 120 HPOS 17 16 8 8 w/r w/r 1 48 HBST HBSO MICRONAS INTERMETALL 29 VDP 3108 ADVANCE INFORMATION I2C Sub address Number of bits Mode Function Default Name 57 5b 5f 15 9 wv PLL2/3 filter coefficients, refer to section `horizontal deflection' 2 2 2 32 PKP3 PKP2 PKI2 HDRV EHPLL EFLB DUBL EBL DCRGB DVPR CSKEW CSYNC 16 w/r d horizontal drive control register bit [5:0] 0..63 horizontal drive pulse duration in sec bit [6] 0/1 disable/enable horizontal pll loops bit [7] 0/1 1: gate HOUT off during flyback bit [8] 0 bit [9] 0/1 enable/disable ultra black blanking bit [10] 0/1 force/enable blanking after reset bit [11] 0/1 enable/disable analog RGB clamping bit [12] 0/1 disable/enable composite sync(ref.bit[15]) bit [13] 0/1 enable/disable vertical protection bit [14] 0/1 bypass/active display clock skew bit [15,12] function of CSIO pin 00 composite sync signal output 01 25 Hz output (field1/field2 signal) 10 no interlace (field 2), output = 0 11 1 MHz h-drive clock TEST REGISTER 39 3f 3e 3d 2f 2e 2a 2b 2c 3a 3b 2d 3c 8 8 8 8 8 8 16 16 8 8 16 16 8 w/r w/r w/r w/r w/r w/r w/r w/r w/r w/r w/r w/r w/r Main Test Register Front End, Luma1 Front End, Luma2 Front End, Luma3 Front End, Chroma1 Front End, Chroma2 Display 1 Display 2 Display 3 FP Display Processor Control Deflection Analog Backend 30 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Table 3-2: Control Registers of the Fast Processor - default values are initialized at reset - * indicates that register is initialized according to the current standard when SDT register is changed. FP Sub address Function Default Name Standard Selection h'1b Standard select: 0 1 2 3 4 5 6 7 PAL B,G,H,I NTSC M SECAM NTSC44 PAL M PAL N PAL 60 NTSC COMB (50 Hz) (60 Hz) (50 Hz) (60 Hz) (60 Hz) (50 Hz) (60 Hz) (60 Hz) 4.433618 3.579545 4.286 4.433618 3.575611 3.582056 4.433618 3.579545 0 SDT The activated routine will set up several blocks for the selected standard. Option bits: (OR for the new selected standard) h'100 no hpll setup h'200 no vertical setup h'400 no acc setup Note: After FP has switched to a new standard, the MSB of SDT is set to 1 to indicate operation complete. Color Processing h'1c h'a0 NTSC tint angle, $512 = $/4 ACC reference level to adjust Cr, Cb levels on picture bus. (use main matrix) ACCREF = 0: ACC function is disabled, chroma gain can be adjusted via ACCb / ACCr register ACC reference level for increased color saturation. (use side matrix) h'a3 ACC multiplier value for SECAM Dr chroma component to adjust Cr level on picture bus. (use main matrix) b[10:0] eeemmmmmmmm m * 2^-e ACC multiplier value for SECAM Dr chroma component for increased color saturation (use side matrix) h'a4 ACC multiplier value for SECAM Db chroma component to adjust Cb level on picture bus. (use main matrix) b[10:0] eeemmmmmmmm m * 2^-e ACC multiplier value for SECAM Dr chroma component for increased color saturation (use side matrix) h'a8 h'a9 amplitude color killer level (0:killer disabled) amplitude color killer hysteresis P/N: 2070* S: 0* 0 TINT ACCREF P/N: 2263 S: 1496* ACCr S:1532 S: 1155* ACCb S: 1177 30 10 KILVL KILHY MICRONAS INTERMETALL 31 VDP 3108 ADVANCE INFORMATION FP Sub address Function Default Name Vertical Standard Select h'e7 vertical standard select if LSB is set to one, lock to standard signal is enabled AGC - DVCO h'b2 h'be h'20 h'58 h'59 sync amplitude reference (0: AGC disabled). Write 0 to register h'b5 after writing 0 to AGCREF to disable the AGC start value for AGC gain while vertical lock or AGC is inactive AGC gain value ( read only if AGC is enabled ) crystal oscillator center frequency adjust, -2048..2047 crystal oscillator center frequency adjustment value for line lock mode. true adjust value is DVCO - ADJUST. For factory crystal alignment: set DVCO=0, set lock mode, read crystal offset from ADJUST register and use negative value for initial center frequency adjustment via DVCO. line locked mode lock command/status write: 100 enable lock 0 disable lock read: 4095/0 locked / unlocked FP Status Register '53 automatic standard recognition status bit0 1 vertical sync detected bit1 2 horizontally locked bit2 4 reserved bit3 8 color killer active bit5 32 ident killer active number of lines per field, P/S: 312, N: 262 measured sync amplitude value, nominal: 768 measured burst amplitude software version number: software release: 2105 1001 FP Display Control Register h'f0 h'f1 h'f2 h'f9 h'fc h'fa h'fb White Drive Red (0...1023) 700 700 700 256 384 256 350 WDR 1) WDG 1) WDB 1) IBR IBRM ABR ACT - ASR 768 27 read only 0 read only AGCREF SGAIN GAIN DVCO ADJUST 50Hz: 625* 60Hz: 525* VSDT h'26 0 XLG h'eb h'41 h'a5 h'50 h'5f read only read only read only read only read only NLPF SAMPL BAMPL - - White Drive Green (0...1023) White Drive Blue (0...1023) Internal Brightness, Picture (0...511) Internal Brightness, Measurement (0...511) Analog Brightness for external RGB (0...511) Analog Contrast for external RGB (0...511) 32 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 FP Sub address Function Default Name FP Display Control Register, BCL h'd4 h'd2 h'd3 h'd5 h'75 BCL threshold current, 0..2047 (max ADC output ~1152) BCL time constant. 0..15 --> 0.5 .. 100msec BCL loop gain. 0..1023. Bit 11 must be always set to 1. BCL minimum contrast. 0..1023 Test register for BCL/EHT comp. function, register value: 1 stop ADC offset compensation x>1 use x in place of input from Measurement ADC FP Display Control Register, Deflection h'73 h'72 interlace offset, -2048..2047 this value is added to the SAWTOOTH output during one field discharge sample count for deflection retrace, SAWTOOTH DAC output impedance is reduced for DSCC lines after vertical retrace. vertical discharge value, SAWTOOTH output value during discharge operation, typically same as A0 init value for sawtooth EHT (electronic high tension) compensation coefficient. 0..1023 EHT time constant. 0..15 --> 0.5 .. 100msec FP Display Control Register, Vertical Sawtooth h'80 h'8b h'8c h'8d h'8e DC offset of SAWTOOTH output, this offset is independent of EHT compensation. accu0 init value accu1 init value accu2 init value accu3 init value FP Display Control Register, East-West Parabola h'9b h'9c h'9d h'9e h'9f 1) 1000 15 0 307 0 BCLTHR BCLTM BCLG BCLMIN BCLTST 0 7 INTLC DSCC h'8f -1365 DSCV h'7b h'7a 0 15 EHT EHTTM 0 -1365 900 0 0 OFS A0 A1 A2 A3 accu0 init value accu1 init value accu2 init value accu3 init value accu4 init value -1121 219 479 -1416 1052 A0 A1 A2 A3 A4 The white drive values will become active only after writing the blue value WDB, latching of new values is indicated by setting the MSB of WDB. MICRONAS INTERMETALL 33 VDP 3108 ADVANCE INFORMATION Table 3-3: Tables for the Calculation of Initialization values for Vertical Sawtooth and East-West Parabola Vertical Deflection 50 Hz b c -1365.3 +682.7 899.6 -904.3 296.4 Vertical Deflection 60 Hz d -682.7 +1363.4 898.4 585.9 East-West Deflection 50 Hz a a0 a1 a2 a3 a4 1 b -341.3 111.9 c 1365.3 -899.6 586.8 d -85.3 84.8 111.1 72.1 e 341.3 -454.5 898.3 -1171.7 756.5 a0 a1 a2 a3 a4 a 1 a a0 a1 a2 a3 East-West Deflection 60 Hz b -341.3 134.6 c 1365.3 -1083.5 849.3 d -85.3 102.2 -161.2 125.6 e 341.3 -548.5 1305.5 -2046.6 1584.8 1 b -1365.3 1083.5 c 682.7 -1090.2 429.9 d -682.7 1645.5 -1305.8 1023.5 a0 a1 a2 a3 a 1 34 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 4. Specifications 4.1. Outline Dimensions 2.4 1+0.2 x 45 9 10 2 9 25 +0.25 0.711 24.2 0.1 2 1 2 61 60 0.457 2.4 1.27 0.1 15 9 24.2 0.1 0.1 16 x 1.27 0.1 = 20.32 0.1 1.27 0.1 1.2 x 45 26 27 25 +0.25 43 44 1.9 1.5 4.05 4.75 0.15 Fig. 4-1: VDP 3108 in 68-pin PLCC package Weight approx. 4.8 g Dimensions in mm 64 33 1 32 19.3 18 58 0.4 4 3.2 0.25 0 ... 15 1 1.78 1.78 x 31 = 55.14 0.5 Fig. 4-2: VDP 3108 in 64-Pin S-DIL Plastic Package Weight approx. 9.0 g Dimensions in mm 4.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant X = obligatory; connect as described in circuit diagram Pin No. PLCC 68-pin SDIL 64-pin Connection (if not used) Pin Name 0.2 Type Short Description 1 2 3 32 31 30 LV X GNDD MSY RES TEST Main Sync Reset Input Test Pin MICRONAS INTERMETALL 16 x 1.27 0.1 = 20.32 0.1 35 VDP 3108 ADVANCE INFORMATION Pin No. PLCC 68-pin SDIL 64-pin Connection (if not used) Pin Name Type Short Description 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 - 33 29 - - - 28 27 23 - - 21 20 19 18 17 16 15 14 13 12 - - - 10 - - - 4 3 2 1 6 LV GNDD GNDD GNDD X X LV GNDD GNDD GNDD GNDD GNDD X X X X X GNDD GNDD GNDD GNDD GNDD X GNDD GNDD GNDD GNDD GNDD GNDD X LV CSY Y7 Y6 Y5 VSTBY HOUT CLK5 Y4 Y3 Y2 Y1 Y0 GNDD XTAL2 XTAL1 VSUPD SDA C0 C1 C2 C3 C4 SCL C5 C6 C7 PR0 PR1 PR2 VSUB VERT Composite Sync Output Picture Bus Luma (MSB) Picture Bus Luma Picture Bus Luma Stand-By Supply Voltage Horizontal Drive Output 5 MHz Clock Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma Picture Bus Luma (LSB) Ground, Digital Circuitry Crystal (out) Crystal (in) Supply Voltage, Digital Circuitry I2C Bus Data Picture Bus Chroma (LSB) Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma I2C Bus Clock Picture Bus Chroma Picture Bus Chroma Picture Bus Chroma (MSB) Picture Bus Priority (LSB) Picture Bus Priority Picture Bus Priority (MSB) Substrate Vertical Sawtooth Output 36 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Pin No. PLCC 68-pin SDIL 64-pin Connection (if not used) Pin Name Type Short Description 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 - 61 62 63 64 5 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 - - 47 46 45 44 43 42 - 41 40 39 38 GNDO LV GNDO X GNDO X VSUPO X VSUPO GNDO VSUPO GNDD GNDO X GNDO GNDO X GNDD GNDD GNDD X LV X VRT X VRT X X VRT X VRT RIN EW GIN VRD/BCS BIN VSUPO ROUT GNDO GOUT FBLIN BOUT NC SENSE GNDO RSW RSW2 GNDO NC NC NC VSUPB CLK20 VSUPF CIN GNDF VIN1 VSUB/GNDB GNDB VIN2 VRT VIN3 Analog Red Input Vertical Parabola Analog Green Input DAC Reference/Beam Current Safety Analog Blue Input Supply Voltage, Analog Backend Analog Output Red Ground, Analog Backend Analog Output Green Fast Blank Input Analog Output Blue Not connected Sense ADC Input Ground, Analog Backend Range Switch for Measurement ADC Range Switch2 for Measurement ADC Ground, Analog Backend Not connected Not connected Not connected Supply Voltage, CLK20 Buffer 20 MHz System Clock Output Supply Voltage, Analog Frontend Chroma/Video 4 Analog Input Ground, Analog Frontend Video 1 Analog Input Substrate/Ground CLK20 Buffer Ground CLK20 Buffer Video 2 Analog Input Reference Voltage Top Video 3 Analog Input MICRONAS INTERMETALL 37 VDP 3108 ADVANCE INFORMATION Pin No. PLCC 68-pin SDIL 64-pin Connection (if not used) Pin Name Type Short Description 64 65 66 67 68 37 36 35 34 33 GNDF HOUT GNDO GNDO LV ISGND HFLB SAFETY VPROT FSY Signal Ground for Analog Input Horizontal Flyback Input Safety Input Vertical Protection Input Front Sync 4.3. Pin Descriptions (pin numbers for 68-PLCC) Pin 1 - Main Sync Pulse MSY (Fig. 4-8) This pin supplies the main sync information. Pin 2 - Reset Input RES (Fig. 4-5) A low level on this pin resets the VDP3108. Pin 3 - Test Input TEST (Fig. 4-5) This pin enables factory test modes. For normal operation it must be connected to ground. Pin 4 - Composite Sync Output CSY (Fig. 4-6) This output supplies a standard composite sync signal that is compatible to the analog RGB output signals. Pin 5-7, 11-15 Picture Bus Luma L7 - L0 (Fig. 4-8) The Picture Bus Luma lines carry the digital luminance data. The data are sampled at 20.25 MHz. In 5-bit RGB mode the 3 LSB L0,L1,L2 are the 1-bit R,G,B color signals. Pin 8 - Standby Supply Voltage VSTDBY In standby mode, only the clock oscillator and the horizontal drive circuitry are active. Pin 9 - Horizontal Drive HOUT (Fig. 4-9) This open drain output supplies the the drive pulse for the horizontal output stage. The polarity and gating with the flyback pulse are selectable by software. Pin 10 - CCU 5 MHz Clock Output Clk5 (Fig. 4-6) This pin provides a clock frequency for the TV microcontroller, e.g. a CCU3000 controller. Pin 16 - Ground, Digital Circuitry GNDD Pin 17,18 - XTAL1 Crystal Input and XTAL2 Crystal Output (Fig. 4-10) These pins are connected to an 20.25 MHz crystal oscillator is digitally tuned by integrated shunt capacitances. The Clk20 and Clk5 clock signals are derived from this oscillator. An external clock can be fed into XTAL1. In this case clock frequency adjustment must be switched off. 38 Pin 19 - Supply Voltage, Digital Circuitry VSUPD Pin 20 - I2C Data SDA (Fig. 4-18) This pin connects to the I2C bus data line. Pin 21-25, 27-29 - Picture Bus Chroma C0-C7 (Fig. 4-8) The Picture Bus Chroma lines carry the digital UV chrominance data. The data are sampled at 10.125 MHz and multiplexed. The UV multiplex is reset for each TV line. In 5-bit RGB mode the two LSB UV0,UV1 are the C0,C1 bits of the 5-bit RGB signal. If C1 is 0 the RGB signals are displayed in half contrast mode; if C1 is 1 the 4 bits C0, R, G, B address one of the 16 entries of the color map. Pin 26 - I2C Clock SCL (Fig. 4-18) This pin connects to the I2C bus clock line. Pin 30-32 - Picture Bus Priority PR0-PR2 (Fig. 4-8) The Picture Bus Priority lines carry the digital priority selection signals. The priority interface allows digital switching of up to 8 sources to the backend processor. Switching for different sources is prioritized and can be on a per pixel basis. Pin 33 - Vertical Sawtooth Output VERT (Fig. 4-11 ) This pin supplies the drive signal for the vertical output stage. The drive signal is generated with 15-bit precision by the internal Fast Processor. The analog voltage is generated with a 4 bit R-DAC and uses digital noise shaping. Pin 34,36,38 - Analog RGB Input RIN, GIN, BIN (Fig. 4-12) These pins are used to insert an external analog RGB signal, e.g. from a SCART connector, to the analog RGB outputs. The analog backend provides separate brightness and contrast settings for the external analog RGB signals. Pin 35 - East-West Parabola Output EW (Fig. 4-11) This pin supplies the parabola signal for the East-West correction. The drive signal is generated with 15 bit precision by the internal Fast Processor. The analog voltMICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Pin 57 - Chroma Input CIN (Fig. 4-15) This pin is connected to the S-VHS chroma signal. A resistive divider is used to bias the input signal to the middle of the converter input range. CIN can only be connected to the chroma (Video 2) AD converter. The signal must be AC-coupled. Pin 58 - Ground, Analog Frontend GNDF Pin 59,61,63 - Video Input 1-3 VIN1,VIN2,VIN3 (Fig. 4-16) These are the analog video inputs. A CVBS or S-VHS luma signal is converted using the luma (Video 1) AD converter. The VIN1 input can also be switched to the chroma (Video 2) ADC. The input signal must be ACcoupled. Pin 60 - Ground, Clock 20 Buffer, GNDB age is generated by a 4 bit R-DAC and uses digital noise shaping. Pin 37 - DAC Reference Decoupling/Beam Current Safety VRD/BCS (Fig. 4-13) Via this pin the DAC reference voltage is decoupled by an external capacitance. The DAC output currents depend on this voltage, therefore a pulldown transistor can be used to shut off all beam currents. A decoupling capacitor of 3.3F//100nF is required. Pin 39 - Supply Voltage, Analog Backend VSUPO Pin 40, 42, 44 - Analog RGB Output ROUT, GOUT, BOUT (Fig. 4-14) This are the analog Red/Green/Blue outputs of the backend. The outputs sink a current of max. 8mA. Pin 41, 47, 50 - Ground, Analog Backend GNDO Pin 43 - Fast Blank Input FBLIN (Fig. 4-12) This pin is used to switch the RGB outputs to the external analog RGB inputs. Pin 45, 51-53 - not connected Pin 46 - Measurement ADC Input SENSE (Fig. 4-12) This is the input of the analog digital converter for the picture and tube measurement. Pin 48,49 - Range Switch for Meas. ADC, RSW, RSW2 (Fig. 4-9) These pins are open drain pulldown outputs. RSW is switched off during cutoff and whitedrive measurement. RSW2 is switched off during cutoff measurement only. Pin 54, 60 - Supply Voltage, Clk20 Output VSUPB, Ground Clk20 Output GNDB. Pin 55 - Main Clock Output Clk20 (Fig. 4-7) This is the 20.25 main system clock, that is used by all circuits in a high-end VDP system. All external timing is derived from this clock. Pin 56 - Supply Voltage, Analog Frontend VSUPI Pin 62 - Reference Voltage Top VRT (Fig. 4-17) Via this pin, the reference voltage for the AD converters is decoupled. The pin is connected with 10 F//47 nF to the Signal Ground Pin. Pin 64 - Signal Ground for Analog Input ISGND This is the high quality ground reference for the video input signals. Pin 65 - Horizontal Flyback Input HFLB (Fig. 4-12) This pin is connected to the horizontal flyback pulse from the horizontal deflection stage. This flyback pulse is used for synchronization of the display processor and for generation of the display clock. Pin 66 - Safety Input SAFETY (Fig. 4-12) Pin 67 - Vertical Protection Input VPROT (Fig. 4-12) The vertical protection circuitry prevents the picture tube from burn-in in the event of a malfunction of the vertical deflection stage. During vertical blanking, a signal level of 2.5V is sensed. If a negative edge cannot be detected, the RGB output signals are blanked. Pin 68 - Front Sync Pulse FSY (Fig. 4-8) This pin supplies the front sync information. MICRONAS INTERMETALL 39 VDP 3108 4.4. Pin Configuration ADVANCE INFORMATION VSUB PR2 PR1 PR0 EW VERT N.C. N.C. N.C. SCL N.C. C1 C0 SDA VSUPD XTAL1 XTAL2 GNDD Y0 Y1 Y2 N.C. CLK5 N.C. N.C. N.C. HOUT VSTBY CSY TEST RES MSY 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RIN GIN VRD/BCS BIN VSUPO ROUT GNDO GOUT FBLIN BOUT N.C. SENSE GNDO RSW RSW2 GNDO N.C. VSUPB CLK20 VSUPF CIN GNDF VIN1 GNDB VIN2 VRT VIN3 ISGND HFLB SAFETY VPROT FSY Fig. 4-3: VDP 3108 in 64-pin Shrink DIL package 40 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 NC NC VSUPB Clk20 VSUPF CIN GNDF VIN1 VSUB/GNDB 60 VIN2 VRT VIN3 ISGND HFBL SAFETY VPROT FSY MSY RES TEST CSY Y7 Y6 Y5 VSTDBY HOUT 61 NC GNDO RSW2 RSW GNDO SENSE NC BOUT 44 43 FBLIN GOUT GNDO ROUT VSUPO BIN VRD/BCS GIN EW RIN VERT PR2 PR1 PR0 C7 C6 C5 1 9 10 Clk5 Y4 Y3 Y2 Y1 Y0 GNDD XTAL2 XTAL1 C2 C1 C0 SDA VSUPD 26 27 SCL C4 C3 Fig. 4-4: VDP 3108 in 68-pin PLCC package MICRONAS INTERMETALL 41 VDP 3108 4.5. Pin Circuits ADVANCE INFORMATION VSTDBY VSUP P GND N GND Fig. 4-5: Input pins 2, 3 0.5M N Fig. 4-9: Output pin 9, 48, 49 P P VSUP VSUP P N Fig. 4-10: Input pins 17, 18 N GND Fig. 4-6: Output pin 4, 10 VSUP P P N f ECLK GND N VSUP P GND Fig. 4-11: Output pins 33, 35 N GND Fig. 4-7: Output pin 55 P VSUP P N P N GND Fig. 4-12: Input pins 34, 36, 38, 65, 66, 67 BIAS VSUP N N N BIAS To DAC GND Fig. 4-13: Output pins 37 Fig. 4-8: I/O pins 1, 5, 6, 7, 11-15, 21-25, 27-32, 68 42 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 VSUP N BIAS N GND Fig. 4-14: Output pins 40, 42, 44 Fig. 4-18: Pins 20, 26, VSUP To ADC GND Fig. 4-15: Chroma input pin 57 + - ADC Reference GND To ADC Fig. 4-19: Pin 46 i VSUP GND Fig. 4-16: Input pin 59, 61, 63 BIAS - + VSUP P 0.7V GND - + ADC Reference Fig. 4-20: Pin 43 Fig. 4-17: Pin 62 MICRONAS INTERMETALL 43 VDP 3108 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings ADVANCE INFORMATION Symbol TA TS VSUP VI VO Parameter Ambient Operating Temperature Storage Temperature Supply Voltage, all Supply Inputs Input Voltage, all Inputs Output Voltage, all Outputs Pin No. - - Min. 0 -40 -0.3 -0.3 -0.3 Max. 65 125 6 VSUP+0.3 VSUP+0.3 Unit C C V V V 4.6.2. Recommended Operating Conditions Symbol TA VSUP fXTAL Parameter Ambient Operating Temperature Supply Voltages, all Supply Pins Clock Frequency Pin No. - Min. 0 4.75 Typ. - 5.0 20.25 Max. 65 5.25 Unit 5C V MHz XTAL1, XTAL2 4.6.3. Characteristics Symbol IVSUPB IVSUPF IVSUPD IVSUPO IVSTDBY PTOT Parameter Current Consumption Backend Current Consumption Current Consumption Current Consumption Current Consumption Total Power Dissipation Pin No. VSUPB VSUPF VSUPD VSUPO VSTDBY Min. 58 Typ. 70 40 140 5 3 1.3 Max. 85 Unit mA mA mA mA mA W 4.6.4. Recommended Crystal Characteristics Symbol TA fP fP/fP fP/fP C0 Parameter Operating Ambient Temperature Parallel Resonance Frequency with Load Capacitance CL=10pF Accuracy of Adjustment Frequency Temperature Drift Shunt Capacitance Min. 0 - - - 3 Typ. - 20.250000 - - - Max. 65 - +/- 20 +/- 30 6 Unit C MHz ppm ppm pF 44 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Symbol C1 Rr Parameter Motional Capacitance Series Resistance Min. 13 Typ. - Max. 20 40 Unit fF W Characteristics, Priority Bus: Luma, Chroma, Priority, FSync, MSync Symbol Parameter Pin No. Y[7..0] C[7..0] PR[2:0] MSY FSY Min. Typ. Max. Unit Test Conditions VOL Output Low Voltage - 0.25 0.5 V IOL = 8 mA, strength 3 IOL = 6 mA, strength 2 IOL = 4 mA, strength 1 IOL = 2 mA, strength 0 -IOL = 10 A CLOAD = 71pF CLOAD = 71pF IPL = 8.4 mA CLOAD = 71pF IPL = 8.4 mA VOL = 0V VOH tOH tODL IPL VIL VIH tIS tIH Output High Voltage Output Hold Time Output Delay Time Output Pull-up Current Input Low Voltage Input High Voltage Input Setup Time Input Hold Time 1.8 5 - 1.2 - 1.5 10 0 2.0 14 - 1.5 - - - - - TBD 35 1.8 0.8 - - - V ns ns mA V V ns ns 20 MHz Clock tIS Luma/Chroma INPUT tIH VIH VIL tOH PICTURE BUS tOH tODL tODL VOHTRI VOL MICRONAS INTERMETALL 45 VDP 3108 Characteristics, Combined Sync Output, 5 MHz Clock Output Symbol Parameter Pin No. Min. Typ. Max. Unit ADVANCE INFORMATION Test Conditions VOL VOH tOT tOT Output Low Voltage Output High Voltage Output Transition Time Output Transition Time CSY Clk5 Clk5 CSY - 4.0 - - - - 50 10 0.4 VSUP V V ns IOL = 1.6 mA -IOL = 1.6 mA CLOAD = 30pF CLOAD = 30pF 20 ns Characteristics, Horizontal Drive Output Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VOL VOH tOF Output Low Voltage Output High Voltage (Open Drain Stage) Output Fall Time HOUT - - - - - 8 0.4 8 20 V V ns IOL = 10 mA external pull-up resistor CLOAD = 30pF Characteristics, Reset Input, Test Input Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VIL VIH Input Low Voltage Input High Voltage RES TEST - 3.1 - - 2.0 - V V Characteristics, 20 MHz Clock Input/Output, External Clock Input (XTAL1), VR = (spec value/VSUP) x 5V Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VDCAV VPP tOT VIT VI DC Average VOUT Peak to Peak Output Transition Time Input Trigger Level Clock Input Voltage Clk20 VR/2 - 0.3 1.3 - 2.1 VR/2 1.6 - 2.5 - VR/2 + 0.3 - 18 2.9 - V VR ns V VPP CLOAD = 30pF CLOAD = 30pF CLOAD = 30pF only for test purposes capacitive coupling used XTAL2 open XTAL 1 1.3 46 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Characteristics, I2C Bus Interface Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VIL VIH VOL VIH Il tF tR fSCL tLOW tHIGH tSU Data tHD Data Input Low Voltage Input High Voltage Output Low Voltage Input Capacitance Input Leakage Current Signal Fall Time Signal Rise Time Clock Frequency Low Period of SCL High Period of SCL Data Set Up Time to SCL high DATA Hold Time to SCL low SDA, SCL - 3.0 - - -1 - - - - - - - - - - - - 1.5 - 0.4 0.6 TBD 1 300 300 400 - - - - V V V V pF A ns ns kHz ns ns ns ns CL = 400 pF CL = 400 pF Il = 3mA Il = 6mA SCL 0 SDA 0 - - Characteristics, Sense ADC Input Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VI VI255 C0 Input Voltage Range Input Voltage for code 255 output Digital Output for 0 Input SENS E 0 1.4 - 1.54 Vsup 1.7 16 V V LSB read cutoff blue register offset check, read cutoff blue register RI Input Impedance 1 - - M Characteristics, Range Switch Outputs Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions RON IMax ILEAK CIN Output On Resistance Maximum Current Leakage Current Input Capacitance RSW RSW2 - - - - - - - - 50 15 600 W mA nA pF IOL = 10 mA RSW High Impedance MICRONAS INTERMETALL 47 VDP 3108 Characteristics, Horizontal Flyback Input Symbol Parameter Pin No. Min. Typ. Max. Unit ADVANCE INFORMATION Test Conditions VIL VIH VIHST PSRRHF PSRRMF PSRRLF tPID Input Low Voltage Input High Voltage Input Hysteresis Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Power Supply Rejection Ratio of Trigger Level Internal Delay HFLB - 2.6 0.1 0 -20 -40 - - - 1.8 - - V V V dB dB dB F = 20 MHz F < 15 kHz F < 100 Hz slew rate 500mV / ns swing 1VPP 12 ns Characteristics, Vertical Protection Input Symbol Parameter Pin No. VPROT Min. Typ. Max. Unit Test Conditions VIL VIH VIHST Input Low Voltage Input High Voltage Input Hysteresis - 2.6 0.1 - - - 1.8 - - V V V Characteristics, Vertical Safety Input Symbol Parameter Pin No. SAFETY Min. Typ. Max. Unit Test Conditions VILA VIHA VILA VIHA VIHST tPID Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Hysteresis A and B Internal Delay - 2.6 - 3.9 0.1 - - - - - 1.8 - 3.1 - - 100 V V V V V ns 48 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Characteristics, Vertical, East-West Drive Output Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VO PSSR Rdacn Rdacd Output Voltage Range Power Supply Rejection Ratio R-DAC Output Resistance R-DAC Output Resistance discharge EW VERT 0.1 0 1.0 0.47 1.25 0.65 4.9 V dB 1.7 0.8 k k Characteristics, DAC Reference, BEAM Current Safety Output at TA = 0 to 65 C, VSUPO = 4.75 to 5.25 V, f = 20.25 MHz for min./max.-values at TC = 60 C, VSUPO = 5 V, f = 20.25 MHz for typical values Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VDACREF DAC-Ref. Voltage DAC-Ref.-Output resistance VRD/ BCS VRD/ BCS 2.38 18 2.52 25 2.67 32 V k MICRONAS INTERMETALL 49 VDP 3108 ADVANCE INFORMATION Characteristics, R,G,B D/A Converters, External Analog RGB Voltage/Current DA Converters at TA = 0 to 65 C, VSUPO = 4.75 to 5.25 V, f = 20.25 MHz for min./max.-values at TC = 60 C, VSUPO = 5 V, f = 20.25 MHz for typical values Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions RGB-DACs Resolution IOUT IOUT IOUT IOUT Full Scale Output Current Differential Nonlinearity Integral Nonlinearity Glitch Pulse ROUT, GOUT, GOUT BOUT 3.1 10 3.75 4.5 0.5 1 0.5 bits mA LSB LSB pAsec Ramp, line is terminated on both ends with 50Ohms 10% to 90%, 90% to 10% 2/2.5MHz Full Scale Signal: 1MHz Full Scale Bandwidth: 10MHz IOUT IOUT IOUT Rise and Fall Time Intermodulation Signal to Noise +50 3 -50 nsec dB dB IOUT Match R-G, R-B, G-B R/B/G Crosstalk one channel talks two channels talk -2 2 -46 % dB passive channel IOUT =1.88mA Crosstalk-Signal: 1.25MHz 3.75mApp RGB Input Crosstalk from external RGB one channel talks two channels talk three channels talk -50 dB passive channel IOUT =1.88mA Crosstalk-Signal: 1.25MHz 3.75mApp 50 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions Brightness-DACs Resolution IBR IBR IBR IBR IBR IBR Full Scale Output Current Full Scale Output Current typical differential nonlinearity integral nonlinearity Match R-G, R-B, G-B Match to digital RGB R-R, G-G, B-B -2 -2 ROUT, GOUT, GOUT BOUT 39.2 9 40 1.5 0.5 1 2 2 40.8 bits % mApp LSB LSB % % ref to max. digital RGB Cutoff-DACs Resolution ICUT ICUT ICUT ICUT ICUT Full Scale Output Current Full Scale Output Current typical differential nonlinearity integral nonlinearity Match to digital RGB R-R, G-G, B-B -2 ROUT, GOUT, GOUT BOUT 58.8 9 60 2.25 0.5 1 2 61.2 bits % mApp LSB LSB % ref to max. digital RGB Ultrablack-DACs Resolution IUB Full Scale Output Current Full Scale Output Current typical Match to digital RGB R-R, G-G, B-B ROUT, GOUT, GOUT BOUT 19.6 1 20 0.75 -2 2 20.4 bits % mA % ref to max. digital RGB MICRONAS INTERMETALL 51 VDP 3108 ADVANCE INFORMATION Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions Ext. RGB Brightn. DACs Resolution IEXBR Full Scale Output Current of Ex. Brightness DACs Full Scale Output Current of Ex. Brightness DACs typical differential nonlinearity integral nonlinearity Match R-G, R-B, G-B Match to digital RGB R-R, G-G, B-B -2 -2 ROUT, GOUT, BOUT 39.2 9 40 1.5 40.8 bits % mA ref to max. Digital RGB 0.5 1 2 2 LSB LSB % % Ext. RGB V/I-DACs Resolution IEXOUT Full Scale Output Current Full Scale Output Current typical CR Contrast adjust Range Gain Match R-G, R-B, G-B Gain Match to RGB- DACs R-R, G-G, B-B R/B/G Input Crosstalk one channel talks two channels talk RGB Input Crosstalk from internal RGB one channel talks two channels talk tree channels talk ROUT GOUT BOUT ROUT GOUT BOUT -2 -4 ROUT GOUT BOUT 96 9 100 3.75 16:51 1 2 4 104 bits % mA ref to max. Digital RGB VIN=0.7 contrast = 323 same as Digital RGB % % measured at RGB Outputs 0.7 VIN = 0 7 V ConCon trast=323 -46 dB passive channel: VIN = 0.7V contrast =323. Signal: Crosstalk 1.25MHz 3.75mApp -50 dB 52 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions RGB Input Noise & Distortion RGB Input -3dB Bandwidth ROUT GOUT BOUT 10 -50 -40 15 -50 dB VIN=0.7Vpp 1MHz contrast = 323 Bandwidth: 10MHz VIN = 0.7Vpp contrast =323 Input signal 1 MHz Input signal 6 MHz VIN = 0.7Vpp contrast =323 VIN = 0.44V - MHz dB dB RGB Input THD differential nonlinearity of Contrast Adjust integral nonlinearity of Contrast Adjust 1.0 7 LSB LSB VRGBO R,G,B Output Voltage R,G,B Output Load Resistance ROUT GOUT BOUT -1.0 0.3 100 V W V referred to VSUPO to VSUPO ref. to VSUPo Sum of max. Current of RGB-DACs and max. Current of Int.Brightness DACs is 2% degraded VOUTC RGB Output Compliance -1.5 -1.3 -1.2 Ext. RGB Inputs VRGBIN VRGBIN VRGBIN External RGB Inputs Voltage Range nominal RGB Input Voltage peak/peak RGB Inputs Voltage for maximum Output Current RGB Inputs Voltage for maximum Output Current RGB Inputs Voltage for maximum Output Current RIN, GIN, BIN -0.3 0.5 - 0.7 0.44 1.1 1.0 V VPP SCART 3dB Spec: 0.7V contrast setting: 511 0.7 contrast setting: 323 1.1 contrast setting: 204 MICRONAS INTERMETALL 53 VDP 3108 ADVANCE INFORMATION Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions CRGBIN External RGB Input Coupling Capacitor Clamp Pulse Width RIN, GIN, BIN 3.1 - -0.5 15 nF sec CIN IIL VCLIP VCLAMP VINOFF Input Capacitance Input Leakage Current RGB Input Voltage for Clipping Current Clamp Level at Input Offset Level at Input - - 2 13 0.5 pF A V clamping OFF, VIN -0.3..3V 40 -10 60 80 10 mV mV clamping ON extrapolated from VIN= 100mV and 200mV extrapolated from VIN= 100mV and 200mV VINOFF Offset Level Match at Input Clamping On-Resistance -10 10 mV RCLAMP - W 54 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 Characteristics, Fast Blank Input Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VFBLOFF VFBLON VFBLTRIG tPID FBLIN Low Level FBLIN High Level Fast Blanking Trigger Level typical Delay Fast Blanking to RGBOUT from midst of FBLIN-transition to 90% of RGBOUT- transition FBLIN - 0.9 - - 0.7 8 0.5 - V V 15 ns Int. RGB = 3.75mA Full Scale Int. Brightness = 0 ext. Brightness = 1.5mA (Full Scale) RGBin = 0 VFBLOFF=0.4V VFBLON=1.0V rise and fall time = 2ns Difference of Internal Delay to ext. RGBin Delay Switch-over-Glitch -5 0.5 +5 ns pAsec switch from 3.75mA (int) to 1.5mA (ext) Characteristics, Analog Video Inputs Symbol Parameter Pin No. Min. Typ. Max. Unit Test Conditions VVIN CIN CCP Analog Input Voltage Input Capacitance Input Coupling Capacitor Video Inputs Input Coupling Capacitor Chroma Input VIN1 VIN2 VIN3 CIN VIN1 VIN2 VIN3 CIN 0 2.5 13 680 V pF nF VIN = 1.5 V CCP 1 nF MICRONAS INTERMETALL 55 VDP 3108 Characteristics, Analog Frontend and ADCs Symbol Parameter Pin No. Min. Typ. Max. Unit ADVANCE INFORMATION Test Conditions VVIN VVIN VVINCL Full Scale Input Voltage, Video 1 Full Scale Input Voltage, Video 1 Video 1 Input Clamping Level, CVBS VIN1, VIN2, VIN3 1.8 0.5 2.0 0.6 1.0 2.2 0.7 VPP VPP V min. AGC Gain max. AGC Gain Binary Level = 68 LSB min. AGC Gain VCIN VVINCL VCINB RCIN Full Scale Input Voltage, Chroma Video 2 Input Clamping Level, CVBS Video 2 Input Bias Level, SVHS Chroma Video 2 Input Resistance SVHS Chroma Binary Code for Open Chroma Input CIN, VIN1 1.08 1.2 1.2 1.32 VPP V Binary Level = 68 LSB - 1.6 VIN1 CIN VIN1-3, CIN -16 0.7 VRT 2.5 1.5 2 128 - 2.4 V k QCL ICL VVRT Input Clamping Current resolution Input Clamping Current per step Reference Voltage Top Video 1 Bandwidth Video 2 Bandwidth Crosstalk, any Two Video Inputs 15 1 2.6 10 10 -50 -45 -42 1.3 2.8 steps A V MHz MHz dB dB dB 10F//10nF, 1G Probe -3dB for full scale signal -3dB for full scale signal at 1 MHz at 1 MHz, 5th harmonics at 1 MHz Code Density Code Density 300 mVPP, 4.4 MHz on ramp 300 mVPP, 4.4 MHz on ramp THD Distortion Video Signal to Noise & Distortion Video Integral Non-Linearity, static Video Differential Non-Linearity, Video Differential Gain Video Differential Phase VIN1-3, CIN VIN1-3, CIN VIN1-3, CIN VIN1-3, CIN VIN1-3, CIN 41 1 0.5 3 TBD LSB LSB % 5 56 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 680n 680n 680n VSUPF VSUPO SENSE N.C. BOUT FBLIN GOUT GNDO ROUT VDDO BIN VRD/BCL GIN EW RIN VERT PR2 PR1 PR0 UV7 UV6 UV5 UV3 UV4 SCL SUBS VIN1 VSSF VSUPB GNDO RSW2 UV0 UV1 RSW UV2 CIN CLK20 N.C. N.C. VSUPD SDA XTAL1 VIN2 VRT VIN3 ISGND HFLB SAFETY VPROT FSY MSY RESQ TEST CSY Y7 Y6 Y5 VSTDB HOUT CLK5 Y4 XTAL2 GNDD Y3 Y2 Y1 Y0 MICRONAS INTERMETALL N.C. 57 VDP 3108 ADVANCE INFORMATION 58 MICRONAS INTERMETALL ADVANCE INFORMATION VDP 3108 MICRONAS INTERMETALL 59 VDP 3108 5. Data Sheet History 1. Advance Information: "VDP 3108 Single-Chip Video Processor", Edition Feb. 7, 1994, 6251-352-1AI. First release of the Advance Information. 2. Advance Information: "VDP 3108 Single-Chip Video Processor", Edition May 3, 1994, 6251-352-2AI. Second release of the Advance Information. 3. Advance Information: "VDP 3108 Single-Chip Video Processor", Edition Oct. 12, 1994, 6251-352-3AI. Third release of the Advance Information. ADVANCE INFORMATION MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany Order No. 6251-352-3AI All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. 60 MICRONAS INTERMETALL End of Data Sheet Multimedia ICs MICRONAS Back to Summary Back to Data Sheets |
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