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| 700 MHz to 2700 MHz Quadrature Modulator AD8349 FEATURES Output frequency range: 700 MHz to 2700 MHz Modulation bandwidth: dc to 160 MHz (large signal BW) 1 dB output compression: 5.6 dBm @ 2140 MHz Output disable function: output below -50 dBm in < 50 ns Noise floor: -156 dBm/Hz Phase quadrature error: 0.3 degrees @ 2140 MHz Amplitude balance: 0.1 dB Single supply: 4.75 V to 5.5 V Pin compatible with AD8345/AD8346s 16-lead, exposed-paddle TSSOP package FUNCTIONAL BLOCK DIAGRAM AD8349 IBBP 1 16 QBBP IBBN 2 15 QBBN COM1 3 14 COM3 COM1 4 13 COM3 LOIN 5 PHASE SPLITTER 12 VPS2 LOIP 6 11 VOUT APPLICATIONS Cellular/PCS communication systems infrastructure WCDMA/CDMA2000/PCS/GSM/EDGE Wireless LAN/wireless local loop LMDS/broadband wireless access systems VPS1 7 BIAS ENOP 8 10 COM3 03570-0-001 9 COM2 Figure 1. PRODUCT DESCRIPTION The AD8349 is a silicon, monolithic, RF quadrature modulator that is designed for use from 700 MHz to 2700 MHz. Its excellent phase accuracy and amplitude balance enable high performance direct RF modulation for communication systems. The differential LO input signal is buffered, and then split into an in-phase (I) signal and a quadrature-phase (Q) signal using a polyphase phase splitter. These two LO signals are further buffered and then mixed with the corresponding I channel and Q channel baseband signals in two Gilbert cell mixers. The mixers' outputs are then summed together in the output amplifier. The output amplifier is designed to drive 50 loads. The RF output can be switched on and off within 50 ns by applying a control pulse to the ENOP pin. The AD8349 can be used as a direct-to-RF modulator in digital communication systems such as GSM, CDMA, and WCDMA base stations, and QPSK or QAM broadband wireless access transmitters. Its high dynamic range and high modulation accuracy also make it a perfect IF modulator in local multipoint distribution systems (LMDS) using complex modulation formats. The AD8349 is fabricated using Analog Devices' advanced complementary silicon bipolar process, and is available in a 16lead, exposed-paddle TSSOP package. Its performance is specified over a -40C to +85C temperature range. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved. AD8349 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Functional Descriptions.......................... 6 Equivalent Circuits ........................................................................... 7 Typical Performance Characteristics ............................................. 8 Circuit Description......................................................................... 14 Overview...................................................................................... 14 LO Interface................................................................................. 14 V-to-I Converter......................................................................... 14 Mixers .......................................................................................... 14 D-to-S Amplifier......................................................................... 14 Bias Circuit .................................................................................. 14 Output Enable ............................................................................. 14 Basic Connections .......................................................................... 15 Baseband I and Q Inputs ........................................................... 15 Single-Ended Baseband Drive .................................................. 15 LO Input Drive Level ................................................................. 16 Frequency Range ........................................................................ 16 LO Input Impedance Matching ................................................ 16 Single-Ended LO Drive.............................................................. 17 RF Output.................................................................................... 17 Output Enable............................................................................. 17 Baseband DAC Interface ........................................................... 18 AD9777 Interface ....................................................................... 18 Biasing and Filtering .................................................................. 18 Reducing Undesired Sideband Leakage .................................. 19 Reduction of LO Feedthrough ................................................. 19 Sideband Suppression and LO Feedthrough vs. Temperature ....................................................................................................... 20 Applications..................................................................................... 21 3GPP WCDMA Single-Carrier Application ........................... 21 WCDMA MultiCarrier Application ........................................ 21 GSM/EDGE Application ........................................................... 22 Soldering Information ............................................................... 23 LO Generation Using PLLs ....................................................... 23 Transmit DAC Options ............................................................. 23 Evaluation Board ............................................................................ 24 Characterization Setups................................................................. 26 SSB Setup..................................................................................... 26 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 REVISION HISTORY 11/04--Data Sheet Changed from Rev. 0 to Rev. A Changes to Figure 25 through Figure 30 ................................11 Changes to Figure 37 through Figure 39 ................................13 Change to WCDMA MultiCarrier Application section .......21 Change to Figure 60 and Figure 61 .........................................21 11/03--Revision 0: Initial Version Rev. A | Page 2 of 28 AD8349 SPECIFICATIONS VS = 5 V; ambient temperature (TA) = 25C; LO = -6 dBm; I/Q inputs = 1.2 V p-p differential sine waves in quadrature on a 400 mV dc bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 , unless otherwise noted. Table 1. Parameter Operating Frequency LO = 900 MHz Output Power Output P1 dB Carrier Feedthrough Sideband Suppression Third Harmonic1 Output IP3 Quadrature Error I/Q Amplitude Balance Noise Floor GSM Sideband Noise LO = 1900 MHz Output Power Output P1dB Carrier Feedthrough Sideband Suppression Third Harmonic 1 Output IP3 Quadrature Error I/Q Amplitude Balance Noise Floor GSM Sideband Noise LO = 2140 MHz Output Power Output P1dB Carrier Feedthrough Sideband Suppression Third Harmonic 1 Output IP3 Quadrature Error I/Q Amplitude Balance Noise Floor WCDMA Noise Floor LO INPUTS LO Drive Level Nominal Impedance Input Return Loss BASEBAND INPUTS I and Q Input Bias Level Input Bias Current Input Offset Current Bandwidth (0.1 dB) Conditions Min 700 1.5 Typ Max 2700 6 -30 -31 -36 Unit MHz dBm dBm dBm dBc dBc dBm degree dB dBm/Hz dBm/Hz dBc/Hz dBm dBm dBm dBc dBc dBm degree dB dBm/Hz dBm/Hz dBc/Hz dBm dBm dBm dBc dBc dBm degree dB dBm/Hz dBm/Hz dBm/Hz dBm dB mV A A MHz MHz POUT - (FLO + (3 x FBB)), POUT = 4 dBm F1BB = 3 MHz, F2BB = 4 MHz, POUT = -4.2 dBm 20 MHz offset from LO, all BB inputs 400 mV dc bias only 20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc LO = 884.8 MHz, 6 MHz offset from LO, POUT = 2 dBm 0 4 7.6 -45 -35 -39 21 1.9 0.1 -155 -150 -152 3.8 6.8 -38 -40 -37 22 0.7 0.1 -156 -150 -151 2.4 5.6 -42 -43 -37 19 0.3 0.1 -156 -151 -156 -6 50 -8.6 400 11 1.8 10 24 6 POUT - (FLO + (3 x FBB)), POUT = 3.8 dBm F1BB = 3 MHz, F2BB = 4 MHz, POUT = -4.5 dBm -36 -36 20 MHz offset from LO, all BB inputs 400 mV dc bias only 20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc LO = 1960 MHz, 6 MHz offset from LO, POUT = 2 dBm -2 5.1 -30 -36 -36 POUT - (FLO + (3 x FBB)), POUT = 2.4 dBm F1BB = 3 MHz, F2BB = 4 MHz, POUT = -6.5 dBm 20 MHz offset from LO, all BB inputs 400 mV dc bias only 20 MHz offset from LO, BB inputs = 1.2 V p-p differential on 400 mV dc LO = 2140 MHz. 30 MHz offset from LO, PCHAN = -17.3 dBm Pins LOIP and LOIN Characterization performed at typical level Drive via 1:1 balun, LO = 2140 MHz Pins IBBP, IBBN, QBBP, QBBN -10 0 LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc Rev. A | Page 3 of 28 AD8349 Parameter Bandwidth (3 dB) OUTPUT ENABLE Off Isolation Turn-On Settling Time Turn-Off Settling Time ENOP High Level (Logic 1) ENOP Low Level (Logic 0) POWER SUPPLIES Voltage Supply Current Conditions LO = 1500 MHz, baseband input = 600 mV p-p sine wave on 400 mV dc LO = 1500 MHz, baseband input = 60 mV p-p sine wave on 400 mV dc Pin ENOP ENOP Low ENOP Low to High (90% of envelope) ENOP High to Low (10% of envelope) Min Typ 160 340 -78 20 50 2.0 0.8 Pins VPS1 and VPS2 4.75 ENOP = High ENOP = Low 135 130 5.5 150 145 V mA mA Max Unit MHz MHz dBm ns ns V V -50 1 The amplitude of the third harmonic relative to the single sideband power decreases with decreasing baseband drive level (see Figure 19, Figure 20, and Figure 21). Rev. A | Page 4 of 28 AD8349 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPOS IBBP, IBBN, QBBP, QBBN LOIP and LOIN Internal Power Dissipation JA (Exposed Paddle Soldered Down) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 0 V, 2.5 V 10 dBm 800 mW 30C/W 125C -40C to +85C -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 28 AD8349 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS IBBP 1 IBBN 2 COM1 3 AD8349 16 QBBP 15 QBBN 14 COM3 TOP VIEW COM1 4 (Not to Scale) 13 COM3 LOIN 5 12 VPS2 LOIP 6 VPS1 7 ENOP 8 11 VOUT 03570-0-002 10 COM3 9 COM2 Figure 2. Table 3. Pin Function Descriptions Pin No. 1, 2, 15, 16 Mnemonic IBBP, IBBN, QBBN, QBBP Description Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be dc-biased to approximately 400 mV dc, and must be driven from a low impedance source. Nominal characterized ac signal swing is 600 mV p-p on each pin (100 mV to 700 mV). This results in a differential drive of 1.2 V p-p with a 400 mV dc bias. These inputs are not self-biased and must be externally biased. Common Pin for LO Phase Splitter and LO Buffers. COM1, COM2, and COM3 should all be connected to a ground plane via a low impedance path. Differential Local Oscillator Inputs. Internally dc-biased to approximately 1.8 V when VS = 5.0 V. Pins must be ac-coupled. Single-ended drive is possible with degradation in performance. Positive Supply Voltage (4.75 V to 5.5 V) for the LO Bias-Cell and Buffer. VPS1 and VPS2 should be connected to the same supply. To ensure adequate external bypassing, connect 0.1 F and 100 pF capacitors between VPS1 and ground. Output Enable. This pin can be used to enable or disable the RF output. Connect to high logic level for normal operation. Connect to low logic level to disable output. Common Pin for the Output Amplifier. COM1, COM2, and COM3 should all be connected to a ground plane via a low impedance path. Common Pin for Input V-to-I Converters and Mixer Cores. COM1, COM2, and COM3 should all be connected to a ground plane via a low impedance path. Device Output. Single-ended, 50 internally biased RF output. Pin must be ac-coupled to the load. Positive Supply Voltage (4.75 V to 5.5 V) for the Baseband Input V-to-I Converters, Mixer Core, Band Gap Reference, and Output Amplifer. VPS1 and VPS2 should be connected to the same supply. To ensure adequate external bypassing, connect 0.1 F and 100 pF capacitors between VPS2 and ground. Equivalent Circuit Circuit A 3, 4 5, 6 7 COM1 LOIN, LOIP VPS1 Circuit B 8 9 10, 13, 14 11 12 ENOP COM2 COM3 VOUT VPS2 Circuit C Circuit D Rev. A | Page 6 of 28 AD8349 EQUIVALENT CIRCUITS VPS2 VPS2 ENOP IBBP 03570-0-003 COM3 COM3 Figure 3. Circuit A Figure 5. Circuit C VPS1 VPS2 LOIN 40 VOUT 40 COM2 03570-0-004 COM1 Figure 4. Circuit B Figure 6. Circuit D Rev. A | Page 7 of 28 03570-0-006 LOIP 04500-0-005 AD8349 TYPICAL PERFORMANCE CHARACTERISTICS 8 7 6 SSB OUTPUT POWER (dBm) 10 VS = 5.25V 1dB OUTPUT COMPRESSION (dBm) 9 VS = 5V 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 700 T = +85C T = +25C T = -40C 5 4 3 2 1 0 -1 -2 -3 03570-0-007 VS = 4.75V 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (FLO) (I and Q Inputs Driven in Quadrature at Baseband Frequency (FBB) = 1 MHz, I and Q Inputs at 1.2 V p-p Differential, TA = 25C) 1 0 60mV p-p Figure 10. SSB Output 1 dB Compression Point (OP1dB) vs. FLO (FBB = 1 MHz, I and Q Inputs Driven in Quadrature , TA = 25C) -10 -15 CARRIER FEEDTHROUGH (dBm) OUTPUT POWER VARIATION (dB) -1 -2 -3 -4 -5 -6 -7 -8 -9 03570-0-008 -20 -25 -30 -35 -40 -45 -50 -55 VS = 4.75V VS = 5V VS = 5.25V 600mV p-p 1 10 100 1000 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) BASEBAND FREQUENCY (MHz) Figure 8. I and Q Input Bandwidth Normalized to Gain @ 1 MHz (FLO = 1500 MHz, TA = 25C) 4.0 3.5 Figure 11. Carrier Feedthrough vs. FLO (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) -20 -22 -24 CARRIER FEEDTHROUGH (dBm) SSB OUTPUT POWER (dBm) 3.0 2.5 VS = 4.75V 2.0 1.5 1.0 0.5 VS = 5.25V VS = 5V -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 VS = 4.75V VS = 5.25V VS = 5V 03570-0-009 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) TEMPERATURE (C) Figure 9. SSB POUT vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential) Figure 12. Carrier Feedthrough vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) Rev. A | Page 8 of 28 03570-0-012 -48 -50 -40 -30 -20 -10 03570-0-011 -10 -60 700 03570-0-010 -4 700 AD8349 -10 -15 -20 -25 -30 -35 -40 VS = 5V -45 -50 -55 03570-0013 -10 -15 THIRD ORDER DISTORTION (dBc) SIDEBAND SUPPRESSION (dBc) -20 -25 -30 -35 -40 -45 -50 -55 VS = 5.25V VS = 5V VS = 4.75V VS = 5.25V VS = 4.75V 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) Figure 13. Sideband Suppression vs. FLO (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) -10 -15 SIDEBAND SUPPRESSION (dBc) Figure 16. Third Order Distortion vs. FLO (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) -10 VS = 4.75V THIRD ORDER DISTORTION (dBc) -15 -20 -25 -30 -35 -40 -45 -50 -55 03570-0-014 -20 -25 -30 -35 -40 -45 -50 -55 -60 1 10 BASEBAND FREQUENCY (MHz) 100 VS = 5V VS = 5.25V VS = 5V VS = 5.25V VS = 4.75V 1 10 BASEBAND FREQUENCY (MHz) 100 Figure 14. Sideband Suppression vs. FBB (FLO = 2140 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) Figure 17. Third Order Distortion vs. FBB (FLO = 2140 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) -30 -30 VS = 4.75V THIRD ORDER DISTORTION (dBc) VS = 5V SIDEBAND SUPPRESSION (dBc) -35 VS = 5V -35 -40 VS = 4.75V -40 VS = 5.25V -45 VS = 5.25V -50 -45 -50 -55 -55 03570-0-015 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) TEMPERATURE (C) Figure 15. Sideband Suppression vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential) Figure 18. Third Order Distortion vs. Temperature (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential) Rev. A | Page 9 of 28 03570-0-018 -60 -40 -30 -20 -10 -60 -40 -30 -20 -10 03570-0-017 -60 03570-0016 -60 700 -60 700 AD8349 -10 3USB, dBc -15 -20 -25 -30 -35 -40 -45 -50 LO, dBm -55 -60 -65 -8 -10 -12 03570-0-019 10 SSB, dBm 8 6 SUPPLY CURRENT (mA) 160 155 150 145 140 135 130 125 120 115 03570-0-022 03570-0023 4 2 0 USB, dBC -2 -4 -6 VS = 5V VS = 5.25V VS = 4.75V -70 -14 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) 110 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 TEMPERATURE (C) Figure 19. Third Order Distortion (3USB), Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (FLO = 900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25C) -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 USB, dBc 3USB, dBc LO, dBm SSB, dBm 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 03570-0-020 Figure 22. Power Supply Current vs. Temperature 500 200 NO TERMINATION -70 -14 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) Figure 20. Third Order Distortion (3USB), Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (FLO = 1900 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25C) -10 3USB, dBc -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 USB, dBc LO, dBm SSB, dBm 8 10 Figure 23. Smith Chart of LOIP Port S11 (LOIN Pin AC-Coupled to Ground). Curves with Balun and External Termination Resistors Also Shown (TA = 25C) 0 -5 6 4 2 0 -2 -4 -6 -8 -10 -35 -10 -15 -20 -25 -30 VS = 5V -12 03570-0-021 RETURN LOSS (dB) 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 FREQUENCY (MHz) BASEBAND DIFFERENTIAL INPUT VOLTAGE (V p-p) Figure 21. Third Order Distortion (3USB), Carrier Feedthrough, Sideband Suppression, and SSB POUT vs. Baseband Differential Input Level (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25C) Figure 24. Return Loss S22of VOUT Output (TA = 25C) Rev. A | Page 10 of 28 03570-0-024 -14 -70 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -40 700 AD8349 30 28 26 24 22 20 PERCENTAGE PERCENTAGE 20 18 16 14 12 10 8 6 4 2 03570-0-025 03570-0-028 03570-0-030 03570-0-029 18 16 14 12 10 8 6 4 2 0 -157.0 -156.5 -156.0 -155.5 -155.0 -154.5 -154.0 -153.5 -153.0 0 -152.0 -151.5 -151.0 -150.5 -150.0 -149.5 -149.0 -148.5 -148.0 -147.5 -147.0 NOISE FLOOR (dBm/Hz) NOISE FLOOR (dBm/Hz) Figure 25. 20 MHz Offset Noise Floor Distribution at FLO = 900 MHz (BB Inputs at a Bias of 400 mV with no AC signal, TA = 25C) 30 28 26 24 22 PERCENTAGE Figure 28. 20 MHz Offset Noise Floor Distribution at FLO = 940 MHz (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25C) 28 26 24 22 20 PERCENTAGE 03570-0-026 20 18 16 14 12 10 8 6 4 2 0 -158.0 -157.5 -157.0 -156.5 -156.0 -155.5 -155.0 -154.5 -154.0 18 16 14 12 10 8 6 4 2 0 -152.5 -152.0 -151.5 -151.0 -150.5 -150.0 -149.5 -149.0 -148.5 -148.0 NOISE FLOOR (dBm/Hz) NOISE FLOOR (dBm/Hz) Figure 26. 20 MHz Offset Noise Floor Distribution at FLO = 1900 MHz (BB Inputs at a Bias of 400 mV with no AC signal, TA = 25C) 30 28 26 24 22 20 PERCENTAGE Figure 29. 20 MHz Offset Noise Floor Distribution at FLO = 1960 MHz (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25C) 30 28 26 24 22 20 PERCENTAGE 03570-0-027 18 16 14 12 10 8 6 4 2 0 -159.0 -158.5 -158.0 -157.5 -157.0 -156.5 -156.0 -155.5 -155.0 18 16 14 12 10 8 6 4 2 0 -153.0 -152.5 -152.0 -151.5 -151.0 -150.5 -150.0 -149.5 -149.0 NOISE FLOOR (dBm/Hz) NOISE FLOOR (dBm/Hz) Figure 27. 20 MHz Offset Noise Floor Distribution at FLO = 2140 MHz (BB Inputs at a Bias of 400 mV with no AC signal, TA = 25C) Figure 30. 20 MHz Offset Noise Floor Distribution at FLO = 2140 MHz (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25C) Rev. A | Page 11 of 28 AD8349 -140 -142 30 -144 35 NOISE FLOOR (dBm/Hz) -146 -148 -150 -152 -154 WITHOUT AC INPUT -156 25 PERCENTAGE WITH AC INPUT 20 15 10 5 -158 03570-0-031 -8 -6 -4 LO INPUT (dBm) -2 0 2 0 MAGNITUDE IMBALANCE (dB) Figure 31. 20 MHz Offset Noise Floor vs. LO Input Power (FLO = 2140 MHz, TA = 25C) Figure 34. I and Q Inputs Quadrature Phase Imbalance Distribution (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) 35 -10 -15 30 CARRIER FEEDTHROUGH (dBm) -20 -25 -30 -35 -40 -45 FLO = 2140MHz -50 -55 -60 -10 FLO = 900MHz 03570-0032 25 PERCENTAGE FLO = 1900MHz 20 15 10 5 -8 -6 -4 LO INPUT (dBm) -2 0 2 0 0.25 0.50 0.75 1.00 1.25 1.50 PHASE (I-Q) IMBALANCE (Degrees) Figure 32. Carrier Feedthrough vs. LO Input Power (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) Figure 35. I and Q Inputs Amplitude Imbalance Distribution (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) 35 -10 -15 30 SIDEBAND SUPPRESSION (dBc) -20 -25 -30 -35 -40 -45 -50 -55 FLO = 900MHz 25 FLO = 1900MHz PERCENTAGE 20 15 10 FLO = 2140MHz 5 -8 -6 -4 LO INPUT (dBm) -2 0 2 5.0 5.5 OP1dB (dBm) 6.0 6.5 Figure 33. Sideband Suppression vs. LO Input Power (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p Differential, TA = 25C) Figure 36. OP1dB Distribution. (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs Driven in Quadrature, TA = 25C) Rev. A | Page 12 of 28 03570-0-036 03570-0033 -60 -10 0 4.5 03570-0-035 0 03570-0-034 -160 -10 0 -0.200 -0.175 -0.150 -0.125 -0.100 -0.075 -0.050 -0.025 AD8349 20 18 35 T = +85C 30 T = -40C 16 14 25 PERCENTAGE PERCENTAGE 12 10 8 6 4 20 15 10 5 2 03570-0-039 -70 -60 -50 -40 -30 -65 CARRIER FEEDTHROUGH (dBm) -60 -55 -50 CARRIER FEEDTHROUGH (dBm) AFTER NULLING TO < -65dBm AT +25C -45 Figure 37. Carrier Feedthrough Distribution at FLO = 900 MHZ (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25C) Figure 40. Carrier Feedthrough Distribution at Temperature Extremes, After Carrier Feedthrough Nulled to < - 65 dBm at TA = 25C. (FLO = 2140 MHz, I and Q Inputs at a bias of 400 mV) 30 28 T = +85C T = -40C 26 24 22 PERCENTAGE 40 35 30 PERCENTAGE 25 20 15 10 5 03570-0-040 20 18 16 14 12 10 8 6 4 2 0 -75 -55 -50 -45 -40 -35 -30 -25 -70 CARRIER FEEDTHROUGH (dBm) -45 -40 -65 -60 -55 -50 SIDEBAND SUPPRESSION (dBc) AFTER NULLING TO < -50dBc AT +25C -35 Figure 38. Carrier Feedthrough Distribution at FLO = 1900 MHz (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 Vp-p, TA = 25C) Figure 41. Sideband Suppression Distribution at Temperature Extremes, After Sideband Suppression Nulled to < -50 dBc at TA = 25C. (FLO = 2140 MHz, FBB = 1 MHz, I and Q Inputs biased at 0.4 V) 24 22 20 18 PERCENTAGE 16 14 12 10 8 6 4 2 03570-0-041 0 -70 -65 -60 -55 -50 -45 -40 -35 -30 CARRIER FEEDTHROUGH (dBm) Figure 39. Carrier Feedthrough Distribution at FLO = 2140 MHz (FBB = 1 MHz, I and Q Inputs Driven in Quadrature at 1.2 V p-p, TA = 25C) Rev. A | Page 13 of 28 03570-0-038 0 -60 03570-0-037 0 -80 0 -70 AD8349 CIRCUIT DESCRIPTION OVERVIEW The AD8349 can be divided into five sections: the local oscillator (LO) interface, the baseband voltage-to-current (V-to-I) converter, the mixers, the differential-to-single-ended (D-to-S) amplifier, and the bias circuit. A detailed block diagram of the device is shown in Figure 42. V-TO-I CONVERTER The differential baseband input voltages that are applied to the baseband input pins are fed to two op amps that perform a differential voltage-to-current conversion. The differential output currents of these op amps then feed each of their respective mixers. MIXERS LOIP LOIN PHASE SPLITTER IBBP IBBN QBBP QBBN OUT 03570-0-043 The AD8349 has two double-balanced mixers, one for the inphase channel (I channel) and one for the quadrature channel (Q channel). Both mixers are based on the Gilbert cell design of four cross-connected transistors. The output currents from the two mixers sum together in a pair of resistor-inductor (R-L) loads. The signals developed across the R-L loads are sent to the D-to-S amplifier. D-TO-S AMPLIFIER The output D-to-S amplifier consists of two emitter followers driving a totem pole output stage. Output impedance is established by the emitter resistors in the output transistors. The output of this stage connects to the output (VOUT) pin. Figure 42. Block Diagram The LO interface generates two LO signals at 90 degrees of phase difference to drive two mixers in quadrature. Baseband signals are converted into currents by the V-to-I converters, which feed into the two mixers. The outputs of the mixers combine to feed the differential-to-single-ended amplifier, which provides a 50 output interface. Reference currents to each section are generated by the bias circuit. Additionally, the RF output is controlled by an output enable pin (ENOP), which is capable of switching the output on and off within 50 ns. A detailed description of each section follows. BIAS CIRCUIT A band gap reference circuit generates the proportional-toabsolute-temperature (PTAT) reference currents used by different sections. The band gap reference circuit also generates a temperature stable current in the V-to-I converters to produce a temperature independent slew rate. LO INTERFACE The LO interface consists of interleaved stages of buffer amplifiers and polyphase phase splitters. An input buffer provides a 50 termination to the LO signal source driving LOIP and LOIN. The buffer also increases the LO signal amplitude to drive the phase splitter. The phase splitter is formed by an R-C polyphase network that splits the buffered LO signal into two parts in precise quadrature phase relation with each other. Each LO signal then passes through a buffer amplifier to compensate for the signal loss through the phase splitter. The two signals pass through another polyphase network to enhance the quadrature accuracy over the full operating frequency range. The outputs of the second phase splitter are fed into the driver amplifiers for the mixers' LO inputs. OUTPUT ENABLE During normal operation (ENOP = high), the output current from the V-to-I converters feeds into the mixers, where they mix with the two phases of LO signals. When ENOP is pulled low, the V-to-I output currents are steered away from the mixers, thus turning off the RF output. Power to the final stage of LO drivers is also removed to minimize LO feedthrough. Even when the output is disabled, the differential-to-singleended stage is still powered up to maintain constant output impedance. Rev. A | Page 14 of 28 AD8349 BASIC CONNECTIONS The basic connections for operating the AD8349 are shown in Figure 43. A single power supply of between 4.75 V and 5.5 V is applied to pins VPS1 and VPS2. A pair of ESD protection diodes connect internally between VPS1 and VPS2, so these must be tied to the same potential. Both pins should be individually decoupled using 100 pF and 0.1 F capacitors to ground. These capacitors should be located as close as possible to the device. For normal operation, the output enable pin, ENOP, must be pulled high. The turn-on threshold for ENOP is 2 V. Pins COM1, COM2, and COM3 should all be tied to the same ground plane through low impedance paths. power of the output signal is at least a crest factor below the AD8349's output compression point. Refer to the Applications section for drive-level considerations in WCDMA and GSM/EDGE systems. Reducing the baseband drive level also has the benefit of increasing the bandwidth of the baseband input. This would allow the AD8349 to be used in applications requiring a high modulation bandwidth, e.g., as the IF modulator in high datarate microwave radios. SINGLE-ENDED BASEBAND DRIVE Where only single-ended I and Q signals are available, a differential amplifier, such as the AD8132 or AD8138, can be used to generate the required differential drive signal for the AD8349. Figure 44 shows an example of a circuit that converts a groundreferenced, single-ended signal to a differential signal, and adds the required 400 mV bias voltage. The baseband inputs can also be driven with a single-ended signal biased to 400 mV, with the unused inputs biased to 400 mV dc. This mode of operation is not recommended, however, because any dc level difference between the bias level of the drive signal and the dc level on the unused input (including the effect of temperature drift), can result in increased LO feedthrough. Additionally, the maximum low distortion output power will be reduced by 6 dB. BASEBAND I AND Q INPUTS The I and Q inputs should be driven differentially. The typical differential drive level (as used for characterization measurements) for the I and Q baseband signals is 1.2 V p-p, which is equivalent to 600 mV p-p on each baseband input. The baseband inputs have to be externally biased to a level between 400 mV and 500 mV. The optimum level for the best performance is 400 mV. The recommended drive level of 1.2 V p-p does not indicate a maximum drive level. If operation closer to compression is desired, the 1.2 V p-p differential limit can be exceeded. For baseband signals with a high peak-to-average ratio (e.g., CDDA or WCDMA), the peak signal level will have to be below the AD8349's compression level in order to prevent clipping of the signal peaks. Clipping of signal peaks increases distortion. In the case of CDMA and WCDMA inputs, clipping results in an increase of signal leakage into adjacent channels. In general, the baseband drive should be at a level where the peak signal IP 1 2 IBBP IBBN COM1 COM1 QBBP QBBN COM3 COM3 VPS2 VOUT COM3 COM2 16 15 QP IN 3 200 5 1 T1 ETC1-1-13 2 LO 4 3 7 200 8 +VS 0.1F 100pF VPS1 ENOP 10 9 100pF 100pF 5 6 LOIN LOIP 4 14 13 12 11 100pF QN AD8349 +VS 100pF 0.1F VOUT Figure 43. Basic Connections Rev. A | Page 15 of 28 03570-0-044 AD8349 +5V 10k 866 499 0.1F + 10F 0.1F 100pF 100pF 0.1F IIN 499 8 3 5 49.9 499 24.8 0.1F 2 1 AD8132 4 6 VPS1 IBBP + 0.1F IBBN VPS2 10F 499 -5V VOUT LOIP +5V QBBP QBBN + 0.1F 499 10F PHASE SPLITTER LOIN AD8349 COM1 COM2 COM3 QIN 499 8 3 5 49.9 499 24.9 0.1F 2 1 AD8132 4 6 0.1F 499 -5V 10F Figure 44. Single-Ended IQ Drive Circuit LO INPUT DRIVE LEVEL The local oscillator inputs are designed to be driven differentially. The device is specified with an LO drive level of -6 dBm. This level was chosen to provide the best noise performance. Increasing the LO drive level degrades sideband suppression and increases carrier feedthrough, while improving noise performance. Reducing the LO drive level creates the opposite effect: improved sideband suppression and reduced carrier feedthrough. LO INPUT IMPEDANCE MATCHING Single-ended LO sources are transformed into a differential signal via a 1:1 balun (ETC1-1-13). A 200 shunt resistor to GND on each LO input on the device side of the balun reduces the return loss for the LO input port. Because the LO input pins are internally dc-biased, ac coupling capacitors must be used on each LO input pin. FREQUENCY RANGE The LO frequency range is from 700 MHz to 2700 MHz. These limits are defined by the nature of the LO phase splitter circuitry. The phase splitter generates LO drive signals for the internal mixers, which are 90 degrees out of phase from each other. Outside of the specified frequency range (700 MHz to 2700 MHz), this quadrature accuracy degrades, resulting in poor sideband rejection performance. Figure 45 and Figure 46 show the sideband suppression of a typical device operating outside the specified LO frequency range. The level of sideband suppression and degradation is also influenced by manufacturing process variations. Rev. A | Page 16 of 28 03570-0-045 + AD8349 4.0 0 -10 -15 -10 CARRIER FEEDTHROUGH (dBm) SIDEBAND SUPPRESSION (dBc) 3.5 SSB OUTPUT POWER (dBm) -20 -25 -30 -35 -40 -45 -50 03570-0-049 3.0 SSB -20 SINGLE-ENDED LO DRIVE 2.5 -30 USB 2.0 -40 1.5 -50 -55 350 400 450 500 550 600 650 03570-0-046 DIFFERENTIAL LO DRIVE 1.0 300 -60 700 -60 700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700 LO FREQUENCY (MHz) LO FREQUENCY (MHz) Figure 45. Sideband Suppression below 700 MHz 0 -1 -40 Figure 48. LO Feedthrough vs. Frequency, Single-Ended vs. Differential LO Drive (Single-Sideband Modulation) RF OUTPUT -41 USB -42 -43 -44 SSB -45 -46 -47 03570-0-047 -2 -3 -4 -5 -6 -7 -8 2700 The RF output is designed to drive a 50 load, but should be ac-coupled, as shown in Figure 43, because of internal dc biasing. The RF output impedance is close to 50 and provides fairly good return loss over the specified operating frequency range (see Figure 24). As a result, no additional matching circuitry is required if the output is driving a 50 load. The output power of the AD8349 under nominal conditions (1.2 V p-p differential baseband drive, 400 mV dc baseband bias, and a 5 V supply) is shown in Figure 7. SIDEBAND SUPPRESSION (dBc) SSB OUTPUT POWER (dBm) 2750 2800 2850 2900 2950 -48 3000 OUTPUT ENABLE The ENOP pin can be used to turn the RF output on and off. This pin should be held high (greater than 2 V) for normal operation. Taking ENOP low (less than 800 mV) disables the output power and provides an off-isolation level of < -50 dBm at the output. Figure 49 and Figure 50 show the enable and disable time domain responses of the ENOP function at 900 MHz. Typical enable and disable times are approximately 20 ns and 50 ns, respectively. 8 800 600 400 200 0 -200 -400 -600 03570-0-050 LO FREQUENCY (MHz) Figure 46. Sideband Suppression above 2700 MHz SINGLE-ENDED LO DRIVE The LO input can be driven single-ended at the expense of higher LO feedthrough at most frequencies (see Figure 48). LOIN is ac-coupled to ground, and LOIP is driven through a coupling capacitor from a single-ended 50 source (see Figure 47). A 400 shunt resistor on the signal-source side of the ac coupling capacitor was used for the measurement. 6 4 2 100pF 5 LOIN 100pF LO 400 6 LOIP 0 -2 AD8349 03570-0-048 -4 -6 -8 0 20 40 60 TIME (ns) 80 Figure 47. Schematic for Single-Ended LO Drive -800 100 Figure 49. ENOP Enable Time, 900 MHz Rev. A | Page 17 of 28 VVOUT (mV) VENOP (V) AD8349 8 6 4 2 VENOP (V) 800 600 DIFFERENTIAL IQ SWING (V p-p) 1.50 1.35 1.20 1.05 0.90 0.75 0.60 0.45 0.30 03570-0-051 400 200 0 -200 -400 -600 -800 100 0 -2 -4 -6 -8 0 20 40 60 TIME (ns) 80 VVOUT (mV) 10 100 R3 () 1.103 Figure 50. ENOP Disable Time, 900 MHz Figure 52. Relationship Between R3 in Figure 51 and Peak Baseband Input Voltage BASEBAND DAC INTERFACE The recommended baseband input swing and bias levels of the AD8349's differential baseband inputs allow for direct connection to most baseband DACs without the need for any external active components. Typically these DACs have a differential full-scale output current from 0 mA to 20 mA on each differential output. These currents can be easily converted to voltages using ground-referenced shunt resistors. Most baseband DACs for transmit chains are designed with two DACs in a single package. BIASING AND FILTERING A value of 40 on R1 and R2 in Figure 51 will generate the required 400 mV dc bias. Note that this is independent of the value of R3. Figure 52 shows the relationship between the value of R3 and the peak baseband input voltage with the 40 resistors in place. From Figure 52, it can be seen that a value of 240 will provide a peak-to-peak swing of approximately 1.2 V p-p differential into the AD8349's baseband inputs. The closest available resistor values are 40.2 and 240 , and these values were used in the characterization of the AD8349 when the DAC was used as a signal source. When using a DAC, low-pass image reject filters are typically used to eliminate images that are produced by the DAC. They provide the added benefit of eliminating broadband noise that might feed into the modulator from the DAC. Figure 53 shows a single sideband spectrum at 2140 MHz. The baseband sine and cosine signals come from the digital output of a Rohde & Schwarz AMIQ arbitrary waveform generator. These signals drive the AD9777 dual DAC, which in turn drives the AD8349's baseband inputs. Note that the AD9777's complex modulator is not being used. Due to offset voltages, internal device mismatch, and imperfect quadrature over the AD8349's operating range, the SSB spectrum has a number of undesirable components such as LO feedthrough and undesired sideband leakage. When the AD8349 is driven by a modulated baseband signal, (e.g. 8-PSK, GMSK, QPSK, or QAM), these nonidealities will manifest themselves as degraded error vector magnitude (EVM) and degraded spectral purity. 03570-0-052 AD9777 INTERFACE The AD977x family of dual DACs is well suited to driving the baseband inputs of the AD8349. The AD9777 is a dual 16-bit DAC that can generate either a baseband output or a complex IF using the device's complex modulator. The basic interface between the AD9777's IOUT outputs and the AD8349's differential baseband inputs is shown in Figure 51. The Resistors R1 and R2 set the dc bias level, and R3 sets the amplitude of the baseband input voltage swing. AD9777 IOUTA1 73 R1I R2I OPTIONAL LOW-PASS FILTER 1 AD8349 IBBP R3I 2 IBBN IOUTB1 72 IOUTA2 69 R1Q R2Q OPTIONAL LOW-PASS FILTER 16 QBBP R3Q 15 QBBN IOUTB2 68 Figure 51. Basic AD9777 to AD8349 Interface Rev. A | Page 18 of 28 03570-0-053 0.15 AD8349 10 0 -10 SSB = 1.7dBm LO = -44.5dBm USB = -52dBc THIRD HARMONIC = -36.8dBc AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70 03570-0-054 the LO feedthrough is reduced by varying the differential offset voltages on the I and Q inputs (xBBP - xBBN), not by varying the nominal bias level of 400 mV. This is easily accomplished by programming and then storing the appropriate DAC offset code required to minimize the LO feedthrough. This, however, requires a dc-coupled path from the DAC to the I and Q inputs. The procedure for reducing the LO feedthrough is simple. A differential offset voltage is applied from the I DAC until the LO feedthrough reaches a trough. With this offset level held, a differential offset voltage is applied to the Q DAC until a lower trough is reached (This is an iterative process). Figure 54 shows a plot of LO feedthrough vs. I channel offset (in mV) after the Q channel offset has been nulled. This suggests that the compensating offset voltage should have a resolution of at least 100 V to reduce the LO feedthrough to be less than - 65 dBm. Figure 55 shows the single sideband spectrum at 2140 MHz after the nulling of the LO. The reduced LO feedthrough can clearly be seen when compared with the performance shown in Figure 53. Compensated LO feedthrough degrades somewhat as the LO frequency is moved away from the frequency at which the compensation was performed. This variation is very small across a 30 MHz or 60 MHz cellular band, however. This small variation is due to the effects of LO-to-RF output leakage around the package and on the board. -52 -54 -80 -90 CENTER 2.14GHz SPAN 10MHz Figure 53. AD8349 Single Sideband Spectrum at 2140 MHz REDUCING UNDESIRED SIDEBAND LEAKAGE Undesired sideband leakage is the result of phase and amplitude imbalances between the I and Q channel baseband signals. Therefore, to reduce the undesired sideband leakage, the amplitude and phase of the baseband signals have to be matched at the mixer cores. Because of mismatches in the baseband input paths leading to the mixers, perfectly matched baseband signals at the pins of the device may not be perfectly matched when they reach the mixers. Therefore, slight adjustments have to be made to the phase and amplitudes of the baseband signals to compensate for these mismatches. Begin by making one of the inputs, say the I channel, the reference signal. Then adjust the amplitude and phase of the Q channel's signal until the unwanted sideband power reaches a trough. The AD9777 has built-in gain adjust registers that allow this to be performed easily. If an iterative adjustment is performed between the amplitude and the phase, the undesired sideband leakage can be minimized significantly. Note that the compensated sideband rejection performance degrades as the operating baseband frequency is moved away from the frequency at which the compensation was performed. As a result, the frequency of the I and Q sine waves should be approximately half the baseband bandwidth of the modulated carrier. For example, if the modulator is being used to transmit a single WCDMA carrier whose baseband spectrum spans from dc to 3.84/2 MHz, the calibration could be effectively performed with 1 MHz I and Q sine waves. CARRIER FEEDTHROUGH (dBm) -56 -58 -60 -62 -64 -66 -68 03570-0-055 -70 3.0 3.5 4.0 4.5 5.0 5.5 IOPP-IOPN (mV) Figure 54. Plot of LO Feedthrough vs. I Channel Baseband Offset (Q Channel Offset Nulled) REDUCTION OF LO FEEDTHROUGH Because the I and Q signals are being multiplied with the LO, any internal offset voltages on these inputs will result in leakage of the LO to the output. Additionally, any imbalance in the LO to RF in the mixers will also cause the LO signal to leak through the mixer to the RF output. The LO feedthrough is clearly visible in the single sideband spectrum. The nominal LO feedthrough of -42 dBm can be reduced further by applying offset compensation voltages on the I and Q inputs. Note that Rev. A | Page 19 of 28 AD8349 10 0 -10 SSB = 1.7dBm LO = -71.4dBm USB = -52dBc THIRD HARMONIC = -36.8dBc IMPROVING THIRD HARMONIC DISTORTION While sideband suppression can be improved by adjusting the relative baseband amplitudes and phase, the only means available to reduce the third harmonic is to reduce the output power. (See Figure 19, Figure 20, and Figure 21). It is worth noting, however, that as the output power is reduced, the noise floor, in dBc, stays fairly constant at the higher end of the power curve (Figure 56). This indicates that the output power can be reduced to a level that yields an acceptable third harmonic without incurring a signal-to-noise ratio penalty. The constant SNR vs. output power relationship also indicates that baseband voltage variations can be effectively used to control system output power and/or regulate signal chain gain. 6 4 SSB OUTPUT POWER (dBm) -84 -86 -88 940 SSB 1960 SSB 2140 SSB -90 -92 -94 -96 1960 20 MHz NOISE 940 20 MHz NOISE 2140 20 MHz NOISE -98 -100 -102 03570-0-056 AMPLITUDE (dBm) -20 -30 -40 -50 -60 -70 03570-0-077 -80 -90 CENTER 2.14GHz SPAN 10MHz Figure 55. AD8349 Single Sideband Spectrum at 2140 MHz after LO Nulling 2 0 -2 -4 -6 -8 -10 -12 -14 0.2 In practical applications, reduction of LO feedthrough and undesired sideband suppression can be performed as a one time calibration, with the required correction factors being stored in nonvolatile RAM. These compensation schemes hold up well over temperature. Figure 40 and Figure 41 show the variation in LO feedthrough and sideband suppression over temperature after compensation is performed at 25C. SINGLE SIDEBAND PERFORMANCE VS. BASEBAND DRIVE LEVEL Figure 56 shows the SSB output power and noise floor in dBc/100 kHz versus baseband drive level at LO frequencies of 940 MHz, 1960 MHz, and 2140 MHz. 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -104 1.2 DIFFERENTIAL BASEBAND DRIVE (V p-p) Figure 56. SSB POUT and 20 MHz Noise Floor vs. Baseband Drive Level (FLO = 940 MHz, 1960 MHz, and 2140 MHz) Rev. A | Page 20 of 28 20 MHz NOISE FLOOR (dBC/100kHz) SIDEBAND SUPPRESSION AND LO FEEDTHROUGH VS. TEMPERATURE AD8349 APPLICATIONS 3GPP WCDMA SINGLE-CARRIER APPLICATION The interpolation filter used for the measurement of WCDMA performance is shown in Figure 57. This third order Bessel filter has a 3 dB bandwidth of 12 MHz. While the 3GPP single channel bandwidth is only 3.84 MHz, this wide 3 dB bandwidth of 12 MHz was driven by the need for a flat group delay out to at least half the bandwidth of the baseband signal. Figure 58 shows a plot of a WCDMA spectrum at 2140 MHz using the 3 GPP Test Model 1 (64 channels active). At an output power of -17.3 dBm, an adjacent channel power ratio (ACPR) just shy of -69 dBc was measured. Figure 59 shows the variation in ACPR with output power at 1960 MHz and 2140 MHz. It also shows the noise floor measured at an offset of 30 MHz from the center of the modulated WCDMA signal. From the graphs, it can be seen that there is an optimal output power at which to operate that delivers the best ACPR. If the output power is increased beyond that point, the ACPR degrades as the result of increased distortion. Below that optimum, the ACPR degrades due to a reduction in the signal-to-noise ratio of the signal. AD9777 73 IOUTA1 40.2 100pF 72 IOUTB1 40.2 680nH 270pF 240 2 680nH 1 -62 -63 -64 -65 ACPR (dB) -147 -148 NOISE FLOOR (dBm/Hz) 03570-0-062 03570-0-060 1960 ADJ CPR -149 -150 -151 -152 -66 -67 2140 ADJ CPR -68 -69 -70 2140 NOISE -71 -72 -26 -24 -22 -18 -16 -14 -20 CHANNEL POWER (DBM) -153 1960 NOISE -154 -155 -156 -12 -10 -8 -157 Figure 59. Single-Carrier WCDMA ACPR and Noise Floor (dBm/Hz) at 30 MHz Carrier Offset vs. Channel Power at 1960 MHz and 2140 MHz (Test Model 1 with 64 Active Channels) WCDMA MULTICARRIER APPLICATION The high dynamic range of the AD8349 also permits use in multicarrier WCDMA applications. Figure 60 shows a 4-carrier WCDMA spectrum at 1960 MHz. At a per-carrier power of -24.2 dBm, an ACPR of -60.4dB is achieved. Figure 61 shows the variation in ACP and noise floor (dBc/Hz) with output power. -30 CH PWR = -24.2dBm ADJ CPR = -60.4dB ALT CPR = -63.1dB AD8349 IBBP -40 -50 IBBN AMPLITUDE (dBm) 03570-0-058 -60 -70 -80 -90 -100 -110 -120 69 IOUTA2 40.2 100pF 68 IOUTB2 40.2 680nH 16 QBBP 270pF 240 15 QBBN 680nH Figure 57. Single-Carrier WCDMA Application Circuit (DAC-Modulator Interconnect) -33 -40 -50 -60 CH PWR = -17.3dBm ADJ CPR = -68.7dB ALT CPR = -72.7dB -130 CENTER 1.96GHz 4MHz/ SPAN 40MHz Figure 60. 4-Carrier WCDMA Spectral Plot at 1960 MHz, Including Adjacent and Alternate Channel Power Ratio AMPLITUDE (dBm) -70 -80 -90 -100 -110 -120 -130 ALT LO ADJ LO CH ADJ UP ALT UP 03570-0-059 CENTER 2.14GHz SPAN 24.6848MHz Figure 58. Single-Carrier WCDMA Spectral Plot at 2140 MHz, including Adjacent and Alternate Channel Power Ratio Rev. A | Page 21 of 28 AD8349 400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz) 6MHz OFFSET NOISE FLOOR (dBc/100kHz) -54 -55 -144 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -14 -12 -10 -8 AVERAGE NOISE FLOOR PEAK NOISE FLOOR EVM 600kHz 400kHz 4.0 ALT AND ADJ CPR (dB) -57 -58 -59 -60 -61 -62 -63 -64 -65 1960 NOISE 2140 ADJ CPR 1960 ADJ CPR -148 50MHz NOISE FLOOR (dBm/Hz) -56 -146 3.5 3.0 EVM% 03570-0068 -150 2.5 2140 ALT CPR -152 1960 ALT CPR -154 2.0 1.5 03570-0063 -6 -4 -2 0 2 4 CHANNEL POWER (dBm) CHANNEL POWER (dBm) GSM/EDGE APPLICATION Figure 62 and Figure 64 show plots of GMSK error vector magnitude (EVM), spectral performance, and noise floor (dBc/100 kHz at 6 MHz carrier offset) at 885 MHz and 1960 MHz. Based on spectral performance, a maximum output power level of around 2 dBm is appropriate. Note, however, that as the output power decreases below this level, there is only a very slight increase in the dBc noise floor. This indicates that baseband drive variation can be used to control or correct the gain of the signal chain over a range of at least 5 dB, with little or no SNR penalty. Figure 63 and Figure 65 show plots of 8-PSK EVM, spectral performance, and noise floor at 885 MHz and 1960 MHz. 400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz) 6MHz OFFSET NOISE FLOOR (dBc/100kHz) Figure 61. 4-Carrier WCDMA Adjacent and Alternate Channel Power Ratio and 50 MHz Noise Floor (dBm/Hz) vs. Per-Channel Power at 1960 MHz and 2140 MHz Figure 63. 8-PSK EVM, Spectral Performance, and Noise Floor vs. Channel Power (Frequency = 885 MHz) -50 -55 -60 -65 -70 -75 -80 -85 -90 AVERAGE NOISE FLOOR -95 -100 -105 -11 -9 -7 -5 -3 -1 1 3 5 03570-0067 4.0 3.5 400kHz 3.0 EVM% EVM% 600kHz PEAK NOISE FLOOR 2.5 2.0 1.5 EVM -110 -13 1.0 CHANNEL POWER (dBm) 400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz) 6MHz OFFSET NOISE FLOOR (dBc/100kHz) An LO drive level of approximately -6 dBm is recommended for GMSK and 8-PSK. A higher LO drive power will improve the noise floor slightly; however, it also tends to degrade EVM. 400kHz AND 600kHz SPECTRAL MASK (dBc/30kHz) 6MHz OFFSET NOISE FLOOR (dBc/100kHz) Figure 64. GMSK EVM, Spectral Performance, and Noise Floor vs. Channel Power (Frequency = 1960 MHz) -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -14 EVM -12 -10 -8 -6 -4 -2 0 2 1.0 1.5 PEAK NOISE FLOOR AVERAGE NOISE FLOOR 2.0 400kHz 600kHz 2.5 3.0 3.5 4.0 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -10 -8 -6 -4 AVERAGE NOISE FLOOR -2 0 2 4 6 PEAK NOISE FLOOR 600kHz EVM 400kHz 4.0 3.5 3.0 EVM% 2.5 2.0 1.5 CHANNEL POWER (dBm) 03570-0065 1.0 CHANNEL POWER (dBm) Figure 65. 8-PSK EVM, Spectral Performance, and Noise Floor vs. Channel Power (Frequency = 1960 MHz) Figure 62.GMSK EVM, Spectral Performance, and Noise Floor vs. Channel Power (Frequency = 885 MHz) Rev. A | Page 22 of 28 03570-0066 2140 NOISE -156 -66 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 1.0 AD8349 SOLDERING INFORMATION The AD8349 is available in a 16-lead TSSOP package with an exposed paddle. The exposed paddle must be soldered to the exposed metal of a ground plane for a lowered thermal impedance and reduced inductance to ground. This results in a junction-to-air thermal impedance (JA) of 30C/W. If multiple ground planes are present, the area under the exposed paddle should be stitched together with vias. Table 5. ADF4360 Family Operating Frequencies ADI Model ADF4360-1 ADF4360-2 ADF4360-3 ADF4360-4 ADF4360-5 ADF4360-6 ADF4360-7 Output Frequency Range (MHz) 2150/2450 1800/2150 1550/1950 1400/1800 1150/1400 1000/1250 Lower frequencies set by external L LO GENERATION USING PLLS Analog Devices has a line of PLLs that can be used for generating the LO signal. Table 4 lists the PLLs together with their maximum frequency and phase noise performance. Table 4. ADI PLL Selection Table ADI Model ADF4111BRU ADF4111BCP ADF4112BRU ADF4112BCP ADF4117BRU ADF4118BRU Frequency FIN (MHz) 1200 1200 3000 3000 1200 3000 At 1 kHz Phase Noise dBc/Hz, 200 kHz PFD -78 -78 -86 -86 -87 -90 TRANSMIT DAC OPTIONS The AD9777 recommended in the previous sections of this data sheet is by no means the only DAC that can be used to drive the AD8349. There are other DACs that are appropriate, depending on the level of performance required. Table 6 lists the dual Tx-DACs that ADI offers. Table 6. ADI Dual Tx - DAC Selection Table Part AD9709 AD9761 AD9763 AD9765 AD9767 AD9773 AD9775 AD9777 Resolution (Bits) 8 10 10 12 14 12 14 16 Update Rate (MSPS Min) 125 40 125 125 125 160 160 160 Analog Devices also offers the ADF4360 fully integrated synthesizer and VCO on a single chip that offers differential outputs for driving the local oscillator input of the AD8349. This means that the user can eliminate the use of the balun necessary for the single-ended-to-differential conversion. The ADF4360 comes as a family of chips with six operating frequency ranges. One can be chosen depending on the local oscillator frequency required. The user should be aware that while the use of the integrated synthesizer might come at the expense of slightly degraded noise performance from the AD8349, it can be a much cheaper alternative to a separate PLL and VCO solution. Figure 61 shows the options available. Rev. A | Page 23 of 28 AD8349 EVALUATION BOARD A populated AD8349 evaluation board is available. The AD8349 has an exposed paddle underneath the package, which is soldered to the board. The evaluation board is designed without any components on the underside of the board so that heat may be applied under the AD8349 for easy removal and replacement of the DUT. YuPing Toh Mike Chowkwanyun 03570-0-074 Figure 66. Layout of Evaluation Board, Top Layer Figure 67. Evaluation Board Silkscreen Table 7. Evaluation Board Configuration Options Component TP1, TP4, TP3 SW1, ENOP, TP2 Function Power Supply and Ground Vector Pins. Output Enable: Place in the A position to connect the ENOP pin to +VS via pull-up resistor R10. Place in the B position to disable the device by grounding the pin ENOP through a 49.9 pulldown resistor. The device may be enabled via an external voltage applied to the SMA connector ENOP or TP2. Baseband Input Filters: These components can be used to implement a low-pass filter for the baseband signals. Default Condition Not applicable SW1 = A R1, R2, R5, R9, C8-C11 R1, R2, R5, R9 = 0 , C8 - C11 = OPEN Rev. A | Page 24 of 28 03570-0-073 AD8349 R1 IP IN 0 R9 0 C11 OPEN 2 IBBN 3 COM1 4 COM1 C1 100pF C2 100pF T1 ETC-1-1-13 R4 200 7 VPS1 +VS 8 ENOP C4 100pF TP2 ENOP A ENOP B 03570-0-072 C8 OPEN 1 IBBP AD 8349 QBBP 16 QBBN 15 C9 OPEN R2 0 R5 0 TP3 VPOS QP QN C10 OPEN COM3 14 TP4 GND R3 200 R6 OPEN LO COM3 13 VPS2 12 VOUT 11 COM3 10 COM2 9 TP1 GND R11 C5 100pF 0 C6 0.1F 5 LOIN 6 LOIP +VS C7 100pF VOUT C3 0.1F R7 0 R10 10k R8 49.9 Figure 68. Evaluation Board Schematic Rev. A | Page 25 of 28 AD8349 CHARACTERIZATION SETUPS SSB SETUP The primary setup used to characterize the AD8349 is shown in Figure 69. This setup was used to evaluate the product as a single-sideband modulator. The interface board has circuitry that converts the single-ended I and Q inputs from the arbitrary function generator to differential inputs with a dc bias of 400 mV. Additionally, the interface board provides connections for power supply routing. The HP34970A and its associated plug-in 34901 were used to monitor power supply currents and voltages being supplied to the AD8349 characterization board. Two HP34907 plug-ins were used to provide additional miscellaneous dc and control signals to the interface board. The LO input was driven directly by an RF signal generator and the output was measured directly with a spectrum analyzer. With the I channel driven by a sine wave and the Q channel by a cosine wave, the lower sideband is the single sideband (SSB) output. The typical SSB output spectrum is shown in Figure 53. IEEE D1 34901 D1 +15V MAX COM IEEE +25V MAX -25V MAX VN GND VP P1 VPS1 HP34970A D2 34907 D2 D3 34907 D3 TEKAFG2020 INTERFACE BOARD I_IN Q_IN OUTPUT_1 OUTPUT_2 IEEE HP3631 ARB FUNCTION GEN IN IP QP QN IP QP AGILENT E4437B IEEE RFOUT IN AD8349 QN CHARACTERIZATION BOARD LO VOUT ENOP P1 HP8561E RF I/P SPECTRUM ANALYZER IEEE IEEE PC CONTROLLER Figure 69. Characterization Board SSB Test Setup Rev. A | Page 26 of 28 03570-0-076 AD8349 OUTLINE DIMENSIONS 5.10 5.00 4.90 BOTTOM VIEW 9 16 TOP VIEW 1 8 4.50 4.40 4.30 6.40 BSC EXPOSED PAD (Pins Up) 3.00 SQ 1.20 MAX 0.15 0.00 SEATING 0.65 BSC PLANE 1.05 1.00 0.80 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-ABT Figure 70. 16-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP] (RE-16-2) Dimensions shown in millimeters ORDERING GUIDE Model AD8349ARE AD8349ARE-REEL7 AD8349AREZ1 AD8349AREZ-REEL71 AD8349-EVAL Temperature Range (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package Description 16-Lead TSSOP, Tube 16-Lead TSSOP, 7" Tape and Reel 16-Lead TSSOP, Tube 16-Lead TSSOP, 7" Tape and Reel Evaluation Board Package Option RE-16 RE-16 RE-16 RE-16 1 Z = Pb-free part. Rev. A | Page 27 of 28 AD8349 NOTES (c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03570-0-11/04(A) Rev. A | Page 28 of 28 |
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