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D at a S hee t, De c. 2 00 0 C505 C505C C505A C505CA 8-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking. Edition 2000-12 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Da ta She et, De c. 2 00 0 C505 C505C C505A C505CA 8-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking. C505/C505C/C505A/C505CA Data Sheet Revision History : Current Version : 2000-12 Previous Releases : Page Page (in previous (in current version version) 24 24 08.00, 06.00, 07.99, 12.97 Subjects (major changes since last revision) Version register VR2 for C505A-4R/C505CA-4R BB step is updated. Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com 8-Bit Single-Chip Microcontroller C500 Family Advance Information C505/C505C/C505A/ C505CA * Fully compatible to standard 8051 microcontroller * Superset of the 8051 architecture with 8 datapointers * Up to 20 MHz operating frequency * - 375 ns instruction cycle time @16 MHz - 300 ns instruction cycle time @20 MHz (50 % duty cycle) On-chip program memory (with optional memory protection) - C505(C)(A)-2R : 16K byte on-chip ROM - C505A-4R/C505CA-4R: 32K byte on-chip ROM - C505A-4E/C505CA-4E: 32K byte on-chip OTP - alternatively up to 64k byte external program memory 256 byte on-chip RAM On-chip XRAM - C505/C505C : 256 byte - C505A/C505CA : 1K byte (more features on next page) * * On-Chip Emulation Support Module Oscillator Watchdog A/D Converter XRAM RAM C505/C505C: 256 byte C505A/C505CA: 1K byte 256 byte Port 0 Port 1 I/O 8 analog inputs / 8 digit. I/O I/O I/O I/O (2-bit I/O port) Timer C505/C505C : 8-bit 0 C505A/C505CA : 10-bit Timer 2 Full-CAN Controller C505C/C505CA only C500 Core 8 Datapointers 8-bit USART Timer 1 Port 2 Port 3 Program Memory Watchdog Timer C505(C)(A)-2R : 16K ROM C505A-4R/C505CA-4R : 32K ROM Port 4 C505A-4E/C505CA-4E : 32K OTP Figure 1 C505 Functional Units Data Sheet 1 12.00 C505/C505C/C505A/C505CA Features (continued) : * 32 + 2 digital I/O lines - Four 8-bit digital I/O ports - One 2-bit digital I/O port (port 4) - Port 1 with mixed analog/digital I/O capability Three 16-bit timers/counters - Timer 0 / 1 (C501 compatible) - Timer 2 with 4 channels for 16-bit capture/compare operation Full duplex serial interface with programmable baudrate generator (USART) Full CAN Module, version 2.0 B compliant (C505C and C505CA only) - 256 register/data bytes located in external data memory area - 1 MBaud CAN baudrate when operating frequency is equal to or above 8 MHz - internal CAN clock prescaler when input frequency is over 10 MHz On-chip A/D Converter - up to 8 analog inputs - C505/C505C : 8-bit resolution - C505A/C505CA: 10-bit resolution Twelve interrupt sources with four priority levels On-chip emulation support logic (Enhanced Hooks Technology TM) Programmable 15-bit watchdog timer Oscillator watchdog Fast power on reset Power Saving Modes - Slow-down mode - Idle mode (can be combined with slow-down mode) - Software power-down mode with wake up capability through P3.2/INT0 or P4.1/RXDC pin P-MQFP-44 package Pin configuration is compatible to C501, C504, C511/C513-family Temperature ranges: SAB-C505 versions TA = 0 to 70 C SAF-C505 versions TA = -40 to 85C SAH-C505 versions TA = -40 to 110C SAK-C505 versions TA = -40 to 125C * * * * * * * * * * * * * Data Sheet 2 12.00 C505/C505C/C505A/C505CA Table 1 Differences in Functionality of the C505 MCUs Device C505-2R C505-L C505C-2R C505C-L C505A-4R C505A-2R C505A-L C505CA-4R C505CA-2R C505CA-L C505A-4E C505CA-4E Internal Program Memory XRAM Size ROM 16K byte - 16K byte - 32K byte 16K byte - 32K byte 16K byte - - - OTP - - - - - - - - - - 32K byte 32K byte 256 byte 256 byte 256 byte 256 byte 1K byte 1K byte 1K byte 1K byte 1K byte 1K byte 1K byte 1K byte A/D Converter Resolution 8 Bit 8 Bit 8 Bit 8 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit 10 Bit CAN Controller - - - - - - Note: The term C505 refers to all versions described within this document unless otherwise noted. However the term C505 may also be restricted by the context to refer to only CAN-less derivatives with 8-Bit ADC which are C505-2R and C505-L in this document. Note: The term C505(C)(A)-2R, for simplicity, is used to stand for C505 16K byte ROM versions within this document which are C505-2R, C505C-2R, C505A-2R and C505CA-2R. Ordering Information The ordering code for Infineon Technologies' microcontrollers provides an exact reference to the required product. This ordering code identifies: * the derivative itself, i.e. its function set * the specificed temperature rage * the package and the type of delivery For the available ordering codes for the C505 please refer to the "Product information Microcontrollers", which summarizes all available microcontroller variants. Data Sheet 3 12.00 C505/C505C/C505A/C505CA VDD VSS VAREF VAGND XTAL1 XTAL2 RESET EA ALE PSEN Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O / 8-bit Analog Inputs Port 2 8-bit Digital I/O Port 3 8-bit Digital I/O Port 4 2-bit Digital I/O C505 C505C C505A C505CA Figure 2 Logic Symbol Note: The ordering codes for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Data Sheet 4 12.00 C505/C505C/C505A/C505CA P0.3 / AD3 P0.2 / AD2 P0.1 / AD1 P0.0 / AD0 V AREF V AGND P1.0 / AN0 / INT3 / CC0 P1.1 / AN1 / INT4 / CC1 P1.2 / AN2 / INT5 / CC2 P1.3 / AN3 / INT6 / CC3 P1.4 / AN4 33 32 31 30 29 28 27 26 25 24 23 22 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 67 8 21 20 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P4.1 / RXDC ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 C505 C505C C505A C505CA 19 18 17 16 15 14 13 12 9 10 11 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 V DD V SS XTAL1 XTAL2 P3.7 / RD P3.6 / WR This pin functionality is not available in the C505/C505A. Figure 3 C505 Pin Configuration P-MQFP-44 Package (Top View) Data Sheet P1.5 / AN5 / T2EX P1.6 / AN6 / CLKOUT P1.7 / AN7 / T2 RESET P3.0 / RxD P4.0 / TXDC P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 5 12.00 C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions Symbol P1.0-P1.7 Pin Number 40-44,1-3 I/O *) I/O Function Port 1 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 1 pins can be used for digital input/output or as analog inputs of the A/D converter. Port 1 pins that have 1's written to them are pulled high by internal pull-up transistors and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup transistors. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. As secondary digital functions, port 1 contains the interrupt, timer, clock, capture and compare pins. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for compare functions). The secondary functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / INT3 / CC0 Analog input channel 0 interrupt 3 input / capture/compare channel 0 I/O P1.1 / AN1 / INT4 / CC1 Analog input channel 1/ interrupt 4 input / capture/compare channel 1 I/O P1.2 / AN2 / INT5 / CC2 Analog input channel 2 / interrupt 5 input / capture/compare channel 2 I/O P1.3 / AN3 / INT6 / CC3 Analog input channel 3 interrupt 6 input / capture/compare channel 3 I/O P1.4 / AN4 Analog input channel 4 P1.5 / AN5 / T2EX Analog input channel 5 / Timer 2 external reload / trigger input P1.6 / AN6 / CLKOUT Analog input channel 6 / system clock output P1.7 / AN7 / T2 Analog input channel 7 / counter 2 input Port 1 is used for the low-order address byte during program verification of the C505 ROM versions (i.e. C505(C)(A)-2R/ C505A-4R/C505CA-4R). 40 41 42 43 44 1 2 3 *) I = Input O = Output Data Sheet 6 12.00 C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont'd) Symbol RESET Pin Number 4 I/O *) I Function RESET A high level on this pin for two machine cycle while the oscillator is running resets the device. An internal diffused resistor to V SS permits power-on reset using only an external capacitor to VDD. Port 3 is an 8-bit quasi-bidirectional port with internal pull-up arrangement. Port 3 pins that have 1's written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data input/output (synch.) of serial interface P3.1 / TxD Transmitter data output (asynch.) or clock output (synch.) of serial interface External interrupt 0 input / timer 0 gate P3.2 / INT0 control input External interrupt 1 input / timer 1 gate P3.3 / INT1 control input P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input WR control output; latches the data P3.6 / WR byte from port 0 into the external data memory RD control output; enables the external P3.7 / RD data memory P3.0-P3.7 5, 7-13 I/O 5 7 8 9 10 11 12 13 *) I = Input O = Output Data Sheet 7 12.00 C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont'd) Symbol P4.0 P4.1 Pin Number 6 28 I/O *) I/O I/O Function Port 4 is a 2-bit quasi-bidirectional port with internal pull-up arrangement. Port 4 pins that have 1's written to them are pulled high by the internal pull-up transistors and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup transistors. The output latch corresponding to the secondary function RXDC must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows (C505C and C505CA only) : P4.0 / TXDC Transmitter output of CAN controller P4.1 / RXDC Receiver input of CAN controller XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of the etxernal clock signal of 50 % should be maintained. Minimum and maximum high and low times as well as rise/ fall times specified in the AC characteristics must be observed. XTAL2 XTAL1 14 15 O I *) I = Input O = Output Data Sheet 8 12.00 C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont'd) Symbol P2.0-P2.7 Pin Number 18-25 I/O *) I/O Function Port 2 is a an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I IL , in the DC characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup transistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register and uses only the internal pullup resistors. The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every three oscillator periods except during external data memory accesses. Remains high during internal program execution. This pin should not be driven during reset operation. The Address Latch Enable output is used for latching the low-byte of the address into external memory during normal operation. It is activated every three oscillator periods except during an external data memory access. When instructions are executed from internal ROM or OTP (EA=1) the ALE generation can be disabled by bit EALE in SFR SYSCON. ALE should not be driven during reset operation. PSEN 26 O ALE 27 O *) I = Input O = Output Data Sheet 9 12.00 C505/C505C/C505A/C505CA Table 2 Pin Definitions and Functions (cont'd) Symbol EA Pin Number 29 I/O *) I Function External Access Enable When held at high level, instructions are fetched from the internal program memory when the PC is less than 4000H (C505(C)(A)-2R) or 8000H (C505A-4R/C505CA-4R/C505A4E/C505CA-4E). When held at low level, the C505 fetches all instructions from external program memory. For the C505 romless versions (i.e. C505-L, C505C-L, C505A-L and C505CA-L) this pin must be tied low. For the ROM protection version EA pin is latched during reset. Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impendance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup transistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C505 ROM versions. External pullup resistors are required during program verification. Reference voltage for the A/D converter. Reference ground for the A/D converter. Ground (0V) Power Supply (+5V) P0.0-P0.7 37-30 I/O VAREF VAGND VSS VDD *) I = Input O = Output 38 39 16 17 - - - - Data Sheet 10 12.00 C505/C505C/C505A/C505CA VDD Vss XTAL1 XTAL2 Oscillator Watchdog XRAM 1) 256 Byte or 1K Byte RAM 256 Byte ROM/ OTP 1) 16K or 32K Byte OSC & Timing RESET ALE PSEN EA CPU 8 datapointers Programmable Watchdog Timer Timer 0 Port 0 Port 0 8-bit digit. I/O Port 1 8-bit digit. I/O / 8-bit analog In Port 2 8-bit digit. I/O Port 1 Timer 1 Port 2 Timer 2 USART Baudrate generator Port 3 Port 3 8-bit digit. I/O Port 4 2-bit digit. I/O Full-CAN Controller 256 Byte Reg./Data Port 4 Interrupt Unit VAREF VAGND A/D Converter 8-/10-Bit 1) S&H MUX Emulation Support Logic C505C/C505CA only. 1) Please refer to Table 1 for device specific configuration. Figure 4 Block Diagram of the C505/C505C/C505A/C505CA Data Sheet 11 12.00 C505/C505C/C505A/C505CA CPU The C505 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% threebyte instructions. With a 16 MHz crystal, 58% of the instructions are executed in 375 ns (20MHz: 300 ns). Special Function Register PSW (Address D0H) Bit No. MSB D7H D0H CY D6H AC D5H F0 D4H RS1 D3H RS0 D2H OV D1H F1 Reset Value : 00H LSB D0H P PSW Bit CY AC F0 RS1 RS0 Function Carry Flag Used by arithmetic instruction. Auxiliary Carry Flag Used by instructions which execute BCD operations. General Purpose Flag Register Bank Select Control Bits These bits are used to select one of the four register banks. RS1 0 0 1 1 RS0 0 1 0 1 Function Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH OV F1 P Overflow Flag Used by arithmetic instruction. General Purpose Flag Parity Flag Set/cleared by hardware after each instruction to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Data Sheet 12 12.00 C505/C505C/C505A/C505CA Memory Organization The C505 CPU manipulates operands in the following four address spaces: - On-chip program memory :16K byte ROM (C505(C)(A)-2R) or 32K byte ROM (C505A-4R/C505CA-4R) or 32K byte OTP (C505A-4E/C505CA-4E) - Totally up to 64K byte internal/external program memory - up to 64 Kbyte of external data memory - 256 bytes of internal data memory - Internal XRAM data memory :256 byte (C505/C505C) 1K byte (C505A/C505CA) - a 128 byte special function register area Figure 5 illustrates the memory address spaces of the C505 versions. Alternatively FFFF H Internal XRAM Ext. Data Memory Ext. Unused Area Int. CAN Contr. (256 Byte) FFFF H See table below for detailed Data Memory partitioning F6FF H 4000 H / 8000 H 3FFF H / 7FFF H F700 H Indirect Addr. Internal RAM 80 H Internal RAM FF H Direct Addr. Special Function Regs. 7F H FF H Int. (EA = 1) Ext. (EA = 0) Ext. Data Memory 80 H 0000 H "Code Space" "Data Space" 0000 H 00 H "Internal Data Space" MCB03632 "Data Space" F700 H to FFFFH: Device C505 C505C C505A C505CA F700 H F7FFH F700 H F7FFH CAN Area Unused Area F700 H FEFF H F800 H FEFF H F700 H FBFF H F800 H FBFF H XRAM Area FF00 H FFFFH FF00 H FFFFH FC00H FFFFH FC00H FFFFH Figure 5 C505 Memory Map Memory Map Data Sheet 13 12.00 C505/C505C/C505A/C505CA Reset and System Clock The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries. a) VDD + C505 C505C C505A C505CA RESET & b) C505 C505C C505A C505CA RESET c) VDD C505 C505C C505A C505CA RESET VDD + Figure 6 Reset Circuitries Data Sheet 14 12.00 C505/C505C/C505A/C505CA Figure 7 shows the recommended oscillator circuits for crystal and external clock operation. C XTAL2 2-20 MHz C C505 C505C C505A C505CA XTAL1 C = 20pF 10pF for crystal operation C = 20 pF 10pF for crystal operation N.C. VDD XTAL2 C505 C505C C505A C505CA XTAL1 External Clock Signal Figure 7 Recommended Oscillator Circuitries Data Sheet 15 12.00 C505/C505C/C505A/C505CA Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C505 contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function regsiter DPSEL. Figure 8 illustrates the datapointer addressing mechanism. ----DPSEL(92 H) DPSEL .2 0 0 0 0 1 1 1 1 .1 0 0 1 1 0 0 1 1 .0 0 1 0 1 0 1 0 1 .2 .1 .0 DPTR7 Selected Datapointer DPTR 0 DPTR 1 DPTR 2 DPTR 3 DPTR 4 DPTR 5 DPTR 6 DPTR 7 External Data Memory MCD00779 DPTR0 DPH(83 H ) DPL(82 H) Figure 8 External Data Memory Addressing using Multiple Datapointers Data Sheet 16 12.00 C505/C505C/C505A/C505CA Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too. Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical. The Enhanced Hooks TechnologyTM 1), which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break. ICE-System Interface to Emulation Hardware SYSCON PCON TCON RESET EA ALE PSEN RSYSCON RPCON RTCON EH-IC C500 MCU Optional I/O Ports Port 0 Port 2 Enhanced Hooks Interface Circuit Port 3 Port 1 RPort 2 RPort 0 TEA TALE TPSEN Target System Interface MCS02647 Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. 1) "Enhanced Hooks Technology" is a trademark and patent of Metalink Corporation licensed to Infineon Technologies. Data Sheet 17 12.00 C505/C505C/C505A/C505CA Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. Five special function register of the C505 (PCON1,P1ANA, VR0, VR1, VR2) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared ("0"). The registers and data locations of the CAN controller (CAN-SFRs) are located in the external data memory area at addresses F700H to F7FFH.. Special Function Register SYSCON (Address B1H) (C505CA only) Bit No. MSB 7 B1H - Reset Value : XX100X01B Reset Value : XX100001B LSB 0 6 - 5 EALE 2 1 RMAP CMOD CSWO XMAP1 XMAP0 1) 4 3 SYSCON The functions of the shaded bits are not described here. 1) This bit is only available in the C505CA. Bit RMAP Function Special function register map bit RMAP = 0 : The access to the non-mapped (standard) special function register area is enabled. RMAP = 1 : The access to the mapped special function register area is enabled. CAN Controller switch-off bit CSWO = 0 : CAN Controller is enabled (default after reset). CSWO = 1 : CAN Controller is switched off. CSWO As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set respectively by software. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable. The 52 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C505 are listed in Table 3 and Table 4. In Table 3 they are organized in groups which refer to the functional blocks of the C505. The CAN-SFRs (applicable for the C505C and C505CA only) are also included in Table 3. Table 4 illustrates the contents of the SFRs in numeric order of their addresses. Table 5 list the CAN-SFRs in numeric order of their addresses. Data Sheet 18 12.00 C505/C505C/C505A/C505CA Table 3 Special Function Registers - Functional Blocks Block CPU Symbol ACC B DPH DPL DPSEL PSW SP SYSCON2) VR0 4) VR1 4) VR2 4) A/DADCON0 2) Converter ADCON1 ADDAT ADST ADDATH ADDATL P1ANA 2) 4) Interrupt System IEN0 2) IEN1 2) IP0 2) IP1 TCON 2) T2CON 2) SCON 2) IRCON XPAGE SYSCON2) Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer System Control Register Version Register 0 Version Register 1 Version Register 2 A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Reg. (C505/C505C) A/D Converter Start Reg. (C505/C505C) A/D Converter High Byte Data Register (C505A/C505CA) A/D Converter Low Byte Data Register (C505A/C505CA) Port 1 Analog Input Selection Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Timer Control Register Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register Address E0H 1) F0H 1) 83H 82H 92H D0H 1) 81H B1H FCH FDH FEH D8H 1) DCH D9H DAH D9H DAH 90H A8H 1) B8H 1) A9H B9H 88H 1) C8H 1) 98H 1) C0H 1) Contents after Reset 00H 00H 00H 00H XXXXX000B 3) 00H 07H XX100X01B 3) 6) XX100001B 3) 7) C5H 05H 5) 00X00000B 3) 01XXX000B 3) 00H XXH 3) 00H 00XXXXXXB 3) FFH 00H 00H 00H XX000000B 3) 00H 00X00000B 00H 00H 00H XX100X01B 3) 6) XX100001B 3) 7) XRAM Page Address Register for Extended on-chip 91H XRAM and CAN Controller System Control Register B1H 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The content of this SFR varies with the actual step of the C505 (eg. 01H for the first step) 6) C505 / C505A/C505C only 7) C505CA only Data Sheet 19 12.00 C505/C505C/C505A/C505CA Table 3 Special Function Registers - Functional Blocks (cont'd) Block Ports Symbol P0 P1 P1ANA 2) 4) P2 P3 P4 ADCON0 2) PCON 2) SBUF SCON SRELL SRELH TCON TH0 TH1 TL0 TL1 TMOD CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON IEN0 2) IEN1 2) Name Port 0 Port 1 Port 1 Analog Input Selection Register Port 2 Port 3 Port 4 A/D Converter Control Register 0 Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Reload Register High Byte Reload Register Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Interrupt Enable Register 0 Interrupt Enable Register 1 Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Power Control Register Power Control Register 1 Address 80H 1) 90H 1) 90H 1) A0H 1) B0H 1) E8H 1) D8H 1) 87H 99H 98H 1) AAH BAH 88H 1) 8CH 8DH 8AH 8BH 89H C1H C3H C5H C7H C2H C4H C6H CBH CAH CDH CCH C8H 1) A8H 1) B8H 1) 86H A8H 1) B8H 1) A9H 87H 88H 1) Contents after Reset FFH FFH FFH FFH FFH XXXXXX11B 00X00000B 3) 00H XXH 3) 00H D9H XXXXXX11B 3) 00H 00H 00H 00H 00H 00H 00H 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 3) 00H 00H 00H 00H 00H 00H 00H 0XX0XXXXB 3) Serial Channel Timer 0/ Timer 1 Compare/ Capture Unit / Timer 2 Watchdog WDTREL IEN0 2) IEN1 2) IP0 2) Pow. Save PCON 2) Modes PCON1 4) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet 20 12.00 C505/C505C/C505A/C505CA Table 3 Special Function Registers - Functional Blocks (cont'd) Block Symbol Name Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High Message Object Registers : Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7 Address F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH F70CH F70DH F70EH F70FH F7n0H 5) F7n1H 5) F7n2H 5) F7n3H 5) F7n4H 5) F7n5H 5) F7n6H 5) F7n7H 5) F7n8H 5) F7n9H 5) F7nAH 5) F7nBH 5) F7nCH 5) F7nDH 5) F7nEH 5) Contents after Reset 01H XXH 3) XXH 3) UUH 3) CAN CR Controller SR IR (C505C/ BTR0 C505CA BTR1 only) GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 0UUUUUUUB 3) UUH 3) UUU11111B 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUH 3) UUH 3) UUH 3) UUH 3) UUH 3) UUUUU000B 3) UUUUUU00B3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged by a reset operation. "U" values are undefined (as "X") after a power-on reset operation 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 5) The notation "n" (n= 1 to F) in the message object address definition defines the number of the related message object. Data Sheet 21 12.00 C505/C505C/C505A/C505CA Table 4 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Content Bit 7 after Reset1) FFH 07H 00H 00H .7 .7 .7 .7 WDT PSEL TF1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 80H 2) P0 81H SP 82H 83H 86H DPL DPH .6 .6 .6 .6 .6 .5 .5 .5 .5 .5 IDLS TF0 - M1 .5 .5 .5 .5 T2EX EAN5 .5 - SM2 .5 .5 ET2 .5 .4 .4 .4 .4 .4 SD TR0 WS M0 .4 .4 .4 .4 .4 EAN4 .4 - REN .4 .4 ES .4 .4 .3 .3 .3 .3 .3 GF1 IE1 - GATE .3 .3 .3 .3 INT6 EAN3 .3 - TB8 .3 .3 ET1 .3 .3 .2 .2 .2 .2 .2 GF0 IT1 - C/T .2 .2 .2 .2 INT5 EAN2 .2 .2 RB8 .2 .2 EX1 .2 .2 .1 .1 .1 .1 .1 PDE IE0 - M1 .1 .1 .1 .1 INT4 EAN1 .1 .1 TI .1 .1 ET0 .1 .1 .0 .0 .0 .0 .0 IDLE IT0 - M0 .0 .0 .0 .0 .INT3 EAN0 .0 .0 RI .0 .0 EX0 .0 .0 WDTREL 00H 00H 00H 0XX0XXXXB 00H 00H 00H 00H 00H FFH FFH 00H XXXXX000B 00H XXH FFH 00H 00H D9H 87H PCON 88H 2) TCON 88H 3) PCON1 89H 8AH 8BH 8CH TMOD TL0 TL1 TH0 SMOD PDS TR1 EWPD - GATE .7 .7 .7 .7 T2 EAN7 .7 - SM0 .7 .7 EA .7 C/T .6 .6 .6 .6 CLKOUT EAN6 .6 - SM1 .6 .6 WDT .6 8DH TH1 2) 90H P1 90H 3) P1ANA 91H XPAGE 92H DPSEL 98H 2) SCON 99H SBUF A0H2) A8H 2) P2 IEN0 IP0 SRELL A9H AAH OWDS WDTS .5 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Data Sheet 22 12.00 C505/C505C/C505A/C505CA Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) P3 3) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B0H2) B1H B1H FFH RD - - WR - - T1 EALE EALE T0 INT1 INT0 TxD RxD SYSCON XX100X01B RMAP CMOD - XMAP1 XMAP0 SYSCON XX104) 0001B 00H XX000000B XXXXXX11B 00H 00H 00H 00H 00H 00H 00H 00H 00X00000B 00H 00H 00H 00H 00H IP1 SRELH RMAP CMOD CSWO XMAP1 XMAP0 EX5 .4 - IEX5 EX4 .3 - IEX4 EX3 .2 - IEX3 ECAN .1 .1 SWI EADC .0 .0 IADC B8H 2) IEN1 B9H BAH EXEN2 SWDT EX6 - - EXF2 - - TF2 .5 - IEX6 C0H2) IRCON C1H C2H C3H C4H C5H C6H C7H CCEN CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 COCA COCAL COCA H3 3 H2 .7 .7 .7 .7 .7 .7 T2PS .7 .7 .7 .7 CY BD .6 .6 .6 .6 .6 .6 I3FR .6 .6 .6 .6 AC CLK .5 .5 .5 .5 .5 .5 - .5 .5 .5 .5 F0 - COCAL COCA COCAL COCA COCAL 2 H1 1 H0 0 .4 .4 .4 .4 .4 .4 T2R1 .4 .4 .4 .4 RS1 BSY .3 .3 .3 .3 .3 .3 T2R0 .3 .3 .3 .3 RS0 ADM .2 .2 .2 .2 .2 .2 T2CM .2 .2 .2 .2 OV MX2 .1 .1 .1 .1 .1 .1 T2I1 .1 .1 .1 .1 F1 MX1 .0 .0 .0 .0 .0 .0 T2I0 .0 .0 .0 .0 P MX0 C8H2) T2CON CAH CBH CCH CDH D8H 2) CRCL CRCH TL2 TH2 D0H2) PSW ADCON0 00X00000B 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) C505 /C505C/C505A only 4) C505CA only Data Sheet 23 12.00 C505/C505C/C505A/C505CA Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont'd) Addr Register Content Bit 7 after Reset1) ADDAT 6) 00H ADDATH 00H 7) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D9H D9H DAH DAH DCH E0H2) E8H2) .7 .9 - .1 .6 .8 - .0 .5 .7 - - .4 .6 - - - .4 - .4 0 0 .4 .3 .5 - - - .3 - .3 0 0 .3 .2 .4 - - MX2 .2 - .2 1 1 .2 .1 .3 - - MX1 .1 RXDC .1 0 0 .1 .0 .2 - - MX0 .0 TXDC .0 1 1 .0 ADST 6) XXXXXXXXB 00XXXXXXB ADDATL 7) ADCON1 01XXX000B ACC P4 00H XXXXXX11B 00H C5H 05H 01H 12H 33H 8) 9) 10) ADCL1 ADCL0 - .7 - .7 1 0 .7 .6 - .6 1 0 .6 .5 - .5 0 0 .5 F0H2) B FCH3)4) VR0 FDH3)4) VR1 FEH3)4) VR2 5) 1) X means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual of the step C505 (eg. 01H or 11H or 21H for the first step) 6) C505 / C505C only 7) C505A / C505CA only 8) C505 / C505C AB step only 9) C505A-4E / C505CA-4E BA step only (11H for the AA step) 10) C505A-4R / C505CA-4R BB step only (32H for the BA step) Data Sheet 24 12.00 C505/C505C/C505A/C505CA Table 5 Contents of the CAN Registers in numeric order of their addresses (C505C/C505CA only) Register Content Bit 7 Addr. after n=1-FH 1) Reset 2) F700H F701H F702H F704H F705H F706H F707H F708H F709H F70AH F70BH CR SR IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 01H XXH XXH UUH 0UUU. 0 UUUUB UUH UUU1. 1111B UUH UUH UUH UUUU. U000B UUH UUH UUH UUUU. U000B UUH UUH UUH UUH UUH UUUU. U000B ID4-0 ID20-18 ID12-5 0 0 0 MSGVAL RMTPND ID4-0 TXIE TXRQ ID20-18 ID12-5 0 RXIE MSGLST CPUUPD ID28-21 ID17-13 0 0 INTPND NEWDAT ID4-0 ID28-21 ID17-13 ID20-18 1 TEST BOFF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CCE 0 0 EIE INTID SIE LEC2 IE LEC1 INIT LEC0 EWRN - RXOK TXOK SJW TSEG2 ID28-21 1 ID28-21 ID20-13 ID12-5 BRP TSEG1 1 1 1 0 0 0 F70CH UMLM0 F70DH UMLM1 F70EH F70FH F7n0H F7n1H F7n2H F7n3H F7n4H F7n5H LMLM0 LMLM1 MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 1) The notation "n" (n= 1 to F) in the address definition defines the number of the related message object. 2) "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged by a reset operation. "U" values are undefined (as "X") after a power-on reset operation Data Sheet 25 12.00 C505/C505C/C505A/C505CA Table 5 Contents of the CAN Registers in numeric order of their addresses (cont'd) (C505C/C505CA only) Register Content Bit 7 Addr. after n=1-FH 1) Reset 2) F7n6H F7n7H F7n8H F7n9H F7nAH F7nBH MCFG DB0 DB1 DB2 DB3 DB4 UUUU. UU00B XXH XXH XXH XXH XXH XXH XXH XXH .7 .7 .7 .7 .7 .7 .7 .7 .6 .6 .6 .6 .6 .6 .6 .6 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DLC .5 .5 .5 .5 .5 .5 .5 .5 .4 .4 .4 .4 .4 .4 .4 .4 DIR .3 .3 .3 .3 .3 .3 .3 .3 XTD .2 .2 .2 .2 .2 .2 .2 .2 0 .1 .1 .1 .1 .1 .1 .1 .1 0 .0 .0 .0 .0 .0 .0 .0 .0 F7nCH DB5 F7nDH DB6 F7nEH DB7 1) The notation "n" (n= 1 to F) in the address definition defines the number of the related message object. 2) "X" means that the value is undefined and the location is reserved. "U" means that the value is unchanged by a reset operation. "U" values are undefined (as "X") after a power-on reset operation Data Sheet 26 12.00 C505/C505C/C505A/C505CA I/O Ports The C505 has four 8-bit I/O ports and one 2-bit I/O port. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 4 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 4 will be pulled high and will source current when externally pulled low. Port 0 will float when configured as input. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents. In this function, port 0 is not an open-drain port, but uses a strong internal pullup FET . Port 4 is 2-bit I/O port with CAN controller specific alternate functions. The eight analog input lines are realized as mixed digital/analog inputs. The 8 analog inputs, AN0-AN7, are located at the port 1 pins P1.0 to P1.7. After reset, all analog inputs are disabled and the related pins of port 1 are configured as digital inputs. The analog function of a specific port 1 pin is enabled by bits in the SFR P1ANA. Writing a 0 to a bit position of P1ANA assigns the corresponding pin to operate as analog input. Note : P1ANA is a mapped SFR and can be only accessed if bit RMAP in SFR SYSCON is set. Data Sheet 27 12.00 C505/C505C/C505A/C505CA Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 6 : Table 6 Timer/Counter 0 and 1 Operating Modes Mode 0 1 2 3 Description 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops TMOD M1 0 0 1 1 M0 0 1 0 1 internal Input Clock external (max) fOSC/6x32 fOSC/12x32 fOSC/6 fOSC/12 In the "timer" function (C/T = `0') the register is incremented every machine cycle. Therefore the count rate is fOSC/6. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the input clock logic. OSC /6 C/T = 0 f OSC /6 Timer 0/1 Input Clock C/T = 1 P3.4/T0 P3.5/T1 TR0 TR1 _ <1 Control & Gate (TMOD) P3.2/INT0 P3.3/INT1 =1 MCS03117 Figure 10 Timer/Counter 0 and 1 Input Clock Logic Data Sheet 28 12.00 C505/C505C/C505A/C505CA Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C505 provides additional compare/capture/reload features. which allow the selection of the following operating modes: - Compare - Capture - Reload : up to 4 PWM signals with 16-bit/300 ns resolution (@ 20 MHz clock) : up to 4 high speed capture inputs with 300 ns resolution : modulation of timer 2 cycle time The block diagram in Figure 11 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as multifunctional port functions at port 1. P1.5/ T2EX P1.7/ T2 Sync. T2I0 T2I1 Sync. & /6 Reload EXEN2 EXF2 _ <1 Interrupt Request Reload OSC f OSC /12 T2PS Timer 2 TL2 TH2 TF2 Compare P1.0/ INT3/ CC0 P1.1/ INT4/ CC1 P1.2/ INT5/ CC2 P1.2/ INT6/ CC3 MCB02730 16 Bit Comparator 16 Bit Comparator 16 Bit Comparator 16 Bit Comparator Input/ Output Control Capture CCL3/CCH3 CCL2/CCH2 CCL1/CCH1 CRCL/CRCH Figure 11 Timer 2 Block Diagram Data Sheet 29 12.00 C505/C505C/C505A/C505CA Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1's to all 0's sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation. Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency. Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle. Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle. Reload of Timer 2 : Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1's to all 0's, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set. Data Sheet 30 12.00 C505/C505C/C505A/C505CA Timer 2 Compare Modes The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated. Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 12 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled. Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Timer Overflow Read Pin MCS02661 VDD Compare Match Internal Bus Write to Latch S D Q Port Latch CLK Q R Port Pin Figure 12 Port Latch in Compare Mode 0 Data Sheet 31 12.00 C505/C505C/C505A/C505CA Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value. In compare mode 1 (see Figure 13) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs. Port Circuit Read Latch Compare Register Circuit Compare Reg. 16 Bit Comparator 16 Bit Timer Register Timer Circuit Read Pin MCS02662 VDD Internal Bus Compare Match Write to Latch D Shadow Latch CLK Q Q Port Latch CLK Q D Port Pin Figure 13 Compare Function in Compare Mode 1 Timer 2 Capture Modes Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this function. In mode 0, the external event causing a capture is : - for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1 - for the CRC register: a positive or negative transition at the corresponding pin, depending on the status of the bit I3FR in SFR T2CON. In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2 contents will be latched into the appropriate capture register in the cycle following the write instruction. In this mode no interrupt request will be generated. Data Sheet 32 12.00 C505/C505C/C505A/C505CA Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 7. Table 7 USART Operating Modes Mode 0 SCON SM0 0 SM1 0 Shift register mode, fixed baud rate Serial data enters and exits through RxD; TxD outputs the shift clock; 8-bit are transmitted/received (LSB first) 8-bit UART, variable baud rate 10 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, fixed baud rate 11 bits are transmitted (through TxD) or received (at RxD) 9-bit UART, variable baud rate Like mode 2 Description 1 2 3 0 1 1 1 0 1 For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in Figure 14 to the serial interface which - there divided by 16 - results in the actual "baud rate". Further, the abbrevation fOSC refers to the oscillator frequency (crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1 or from a decdicated baud rate generator (see Figure 14). Data Sheet 33 12.00 C505/C505C/C505A/C505CA Timer 1 Overflow Baud Rate Generator (SRELH SRELL) ADCON0.7 (BD) 0 1 Mode 1 Mode 3 SCON.7 SCON.6 (SM0/ SM1) /2 PCON.7 (SMOD) 0 1 Baud Rate Clock f OSC Mode 2 /6 Mode 0 Only one mode can be selected MCS02733 Note: The switch configuration shows the reset state. Figure 14 Block Diagram of Baud Rate Generation for the Serial Interface Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 8 Serial Interface - Baud Rate Dependencies Serial Interface Operating Modes Mode 0 (Shift Register) Mode 1 (8-bit UART) Mode 3 (9-bit UART) Active Control Bits Baud Rate Calculation BD - 0 1 SMOD - X X fOSC / 6 Controlled by timer 1 overflow : (2SMOD x timer 1 overflow rate) / 32 Controlled by baud rate generator (2SMOD x fOSC) / (32 x baud rate generator overflow rate) Mode 2 (9-bit UART) - 0 1 fOSC / 32 fOSC / 16 Data Sheet 34 12.00 C505/C505C/C505A/C505CA CAN Controller (C505C and C505CA only) The on-chip CAN controller, compliant to version 2.0B, is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15). This includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. In order to implement the physical layer, external components have to be connected to the C505C/C505CA. The internal bus interface connects the on-chip CAN controller to the internal bus of the microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256 byte wide address range of the external data memory area (F700H to F7FFH) and can be accessed using MOVX instructions. Figure 15 shows a block diagram of the on-chip CAN controller. The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory. The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the CAN protocol. Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP. The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial. The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit Stream Processor. According to the values of the error counters, the CAN controller is set into the states error active, error passive and busoff. The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit timing according to the CAN protocol. The BTL synchronizes on a recessive to dominant busline transition at Start of Frame (hard synchronization) and on any further recessive to dominant busline transition, if the CAN controller itself does not transmit a dominant bit (resynchronization). The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time. The programming of the BTL depends on the baudrate and on external physical delay times. The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. After the initial configuration, the Intelligent Memory can handle the reception and transmission of data without further microcontroller actions. Data Sheet 35 12.00 C505/C505C/C505A/C505CA TXDC RXDC BTL-Configuration Bit Timing Logic Timing Generator CRC Gen./Check TX/RX Shift Register Messages Messages Handlers Intelligent Memory Interrupt Register Clocks (to all) Control Status + Control Bit Stream Processor Status Register Error Management Logic MCB02736 to internal Bus Figure 15 CAN Controller Block Diagram Data Sheet 36 12.00 C505/C505C/C505A/C505CA CAN Controller Software Initialization The very first step of the initialization is the CAN controller input clock selection. A divide-by-2 prescaler is enabled by default after reset (Figure 16). Setting bit CMOD (SYSCON.3) disables the prescaler. The purpose of the prescaler selection is: - to ensure that the CAN controller is operable when fosc is over 10 MHz (bit CMOD =0) - to achieve the maximum CAN baudrate of 1 Mbaud when fosc is 8 MHz (bit CMOD=1) SYSCON.3 (CMOD) f OSC 2 1 0 f CAN Full-CAN Module Condition: CMOD = 0, when f OSC > 10 MHz MCS03296 Frequency (MHz) fOSC 8 8 16 fCAN 8 4 8 CMOD BRP (SYSCON.3) (BTR0.0-5) 1 0 0 000000B 000000B 000000B CAN baudrate (Mbaud/sec) 1 0.5 1 Note : The switch configuration shows the reset state of bit CMOD. Figure 16 CAN controller Input Clock Selection Data Sheet 37 12.00 C505/C505C/C505A/C505CA 8-Bit A/D Converter (C505 and C505C only) The C505/C505C includes a high performance / high speed 8-bit A/D converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and provides the following features: - - - - - 8 multiplexed input channels (port 1), which can also be used as digital outputs/inputs 8-bit resolution Internal start-of-conversion trigger Interrupt request generation after each conversion Single or continuous conversion mode The 8-bit ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC) and the input clock fIN (1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the XTAL pins via the ADC clock prescaler as shown in Figure 17. The input clock is equal to fOSC. The conversion clock fADC is limited to a maximum frequency of 1.25 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 1.25 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. ADCL1 f OSC 32 16 8 4 Clock Prescaler MUX ADCL0 Conversion Clock f ADC A/D Converter Input Clock f IN Condition: f ADC max < 1.25 MHz f IN = f OSC = 1 CLP MCS03299 MCU System Clock fIN [MHz] Rate (fOSC) 2 MHz 5 MHz 6 MHz 10 MHz 12 MHz 16 MHz 20 MHz 2 5 6 10 12 16 20 Prescaler Ratio /4 /4 /8 /8 / 16 / 16 / 16 fADC [MHz] 0.5 1.25 0.75 1.25 0.75 1 1.25 ADCL1 0 0 0 0 1 1 1 ADCL0 0 0 1 1 0 0 0 Figure 17 8-Bit A/D Converter Clock Selection Data Sheet 38 12.00 C505/C505C/C505A/C505CA IEN1 (B8 H ) EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC Internal Bus IRCON (C0 H ) EXF2 P1ANA (90 H ) EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC ADCON1 (DC H ) ADCL1 ADCL0 MX2 MX1 MX0 ADCON0 (D8 H ) BD CLK BSY ADM MX2 MX1 MX0 Port 1 MUX S&H Single / Continuous Mode ADDAT ADST (D9 H ) (DA H ) LSB .1 .2 .3 .4 .5 .6 MSB f OSC Conversion Clock Prescaler Conversion Clock f ADC Input Clock f IN A/D Converter V AREF V AGND Start of conversion Shaded Bit locations are not used in ADC-functions. Internal Bus Write to ADST MCB03298 Figure 18 Block Diagram of the 8-Bit A/D Converter Data Sheet 39 12.00 C505/C505C/C505A/C505CA 10-Bit A/D Converter (C505A and C505CA only) The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features: - - - - - - - 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs 10-bit resolution Single or continuous conversion mode Internal start-of-conversion trigger capability Interrupt request generation after each conversion Using successive approximation conversion technique via a capacitor array Built-in hidden calibration of offset and linearity errors The 10-bit ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC) and the input clock fIN (=1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the XTAL pins. The input clock fIN is equal to fOSC The conversion fADC clock is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1. ADCL1 f OSC 32 16 8 4 Clock Prescaler ADCL0 Conversion Clock MUX f ADC A/D Converter Input Clock f IN Condition: f ADC max < 2 MHz f IN = f OSC = 1 CLP MCS03635 MCU System Clock fIN [MHz] Rate (fOSC) 2 MHz 6 MHz 8 MHz 12 MHz 16 MHz 20 MHz 2 6 8 12 16 20 Prescaler Ratio /4 /4 /4 /8 /8 / 16 fADC [MHz] 0.5 1.5 2 1.5 2 1.25 ADCL1 0 0 0 0 0 1 ADCL0 0 0 0 1 1 0 Figure 19 10-Bit A/D Converter Clock Selection Data Sheet 40 12.00 C505/C505C/C505A/C505CA IEN1 (B8 H ) EXEN2 SWDT EX6 EX5 EX4 EX3 ECAN EADC Internal Bus IRCON (C0 H ) EXF2 P1ANA (90 H ) EAN7 EAN6 EAN5 EAN4 EAN3 EAN2 EAN1 EAN0 TF2 IEX6 IEX5 IEX4 IEX3 SWI IADC ADCON1 (DC H ) ADCL1 ADCL0 MX2 MX1 MX0 ADCON0 (D8 H ) BD CLK BSY ADM MX2 MX1 MX0 Port 1 MUX S&H Single / Continuous Mode ADDAT ADST ADDATH ADDATL (D9 H ) (DA H ) (D9H) (DAH) .2 .3 .4 .5 .6 .7 .8 MSB LSB .1 f OSC Conversion Clock Prescaler Conversion Clock f ADC Input Clock f IN A/D Converter V AREF V AGND Start of conversion Internal Bus Shaded Bit locations are not used in ADC-functions. Write to ADDATL MCB03636 Figure 20 Block Diagram of the 10-Bit A/D Converter Data Sheet 41 12.00 C505/C505C/C505A/C505CA Interrupt System The C505 provides 12 interrupt vectors with four priority levels. Five interrupt requests can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter). One interrupt can be generated by the CAN controller (C505C and C505CA only) or by a software setting and in this case the interrupt vector is the same. Six interrupts may be triggered externally (P3.2/ INT0, P3.3/INT1, P1.0/AN0/INT3/CC0, P1.1/AN1/INT4/CC1, P1.2/AN2/INT5/CC2, P1.3/AN3/INT6/ CC3). Additionally, the P1.5/AN5/T2EX can trigger an interrupt. The wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at either pin P3.2/INT0 or the pin P4.1/RXDC. Figure 21 to Figure 23 give a general overview of the interrupt sources and illustrate the request and the control flags which are described in the next sections. Table 9 lists all interrupt sources with their request flags and interrupt vector addresses. Table 9 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload A/D Converter Interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH 0043H Interrupt Request Flags IE0 TF0 IE1 TF1 RI / TI TF2 / EXF2 IADC - / SWI IEX3 IEX4 IEX5 IEX6 - CAN Controller / Software Interrupt 004BH External interrupt 3 0053H External Interrupt 4 External Interrupt 5 External interrupt 6 Wake-up from power-down mode 005BH 0063H 006BH 007BH Data Sheet 42 12.00 C505/C505C/C505A/C505CA Highest Priority Level P3.2 / INT0 IT0 TCON.0 A / D Converter IADC IRCON.0 EADC IEN1.0 IE0 TCON.1 EX0 IEN0.0 0003 H Lowest Priority Level 0043 H IP1.0 IP0.0 P o l l i n g S e q u e n c e Timer 0 Overflow TF0 TCON.5 SWI IRCON.1 >1 ECAN ECAN ET0 IEN0.1 000B H Status SIE CR.2 004B H IEN1.1 CAN Controller Interrupt Sources >1 Error EIE CR.3 Message Transmit TXIE MCR0.5 / 4 Message Receive RXIE MCR0.3 / 2 IE CR.1 >1 INTPND MCR0.0 / 1 EA IEN0.7 IP1.1 IP0.1 Bit addressable Request flag is cleared by hardware C505C and C505CA Only MCB03303 Figure 21 Interrupt Structure, Overview Part 1 Note: Each of the 15 CAN controller message objects (C505C and C505CA only), shown in the shaded area of Figure 21 provides the bits/flags. Data Sheet 43 12.00 C505/C505C/C505A/C505CA Highest Priority Level P3.3 / INT1 IT1 TCON.2 P1.0 / AN0 / INT3 / CC0 I3FR T2CON.6 Timer 1 Overflow TF1 TCON.7 P1.1 / AN1 / INT4 / CC1 ET1 IEN0.3 IEX4 IRCON.3 EX4 IEN1.3 EA Bit addressable Request flag is cleared by hardware IEN0.7 MCB03304 IE1 TCON.3 EX1 IEN0.2 IEX3 IRCON.2 EX3 IEN1.2 0013 H Lowest Priority Level P o l l i n g S e q u e n c e IP1.3 IP0.3 0053 H IP1.2 IP0.2 001B H 005B H Figure 22 Interrupt Structure, Overview Part 2 Data Sheet 44 12.00 C505/C505C/C505A/C505CA RI USART SCON.0 TI P1.2 / AN2 / INT5 / CC2 SCON.1 >1 ES IEN0.4 IEX5 IRCON.4 EX5 IEN1.4 0063 H IP1.4 IP0.4 0023 H Highest Priority Level Lowest Priority Level P o l l i n g S e q u e n c e IP1.5 IP0.5 Timer 2 Overflow P1.5 / AN5 / T2EX P1.3 / INT6 / CC3 TF2 IRCON.6 EXF2 EXEN2 >1 ET2 IEN0.5 IEX6 002B H IRCON.7 IEN1.7 IRCON.5 EX6 IEN1.5 EA Bit addressable Request flag is cleared by hardware IEN0.7 006B H MCB03305 Figure 23 Interrupt Structure, Overview Part 3 Data Sheet 45 12.00 C505/C505C/C505A/C505CA Fail Save Mechanisms The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure : - a programmable watchdog timer (WDT), with variable time-out period from 192 s up to approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz). - an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on. The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of fOSC/12 upto fOSC/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit. 0 f OSC / 6 2 16 WDTL 14 WDT Reset - Request IP0 (A9 H ) OWDS WDTS 7 8 WDTH WDTPSEL External HW Reset 76 WDTREL (86 H ) Control Logic WDT SWDT 0 IEN0 (A8 H ) IEN1 (B8 H ) MCB03306 Figure 24 Block Diagram of the Programmable Watchdog Timer The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped during active mode of the device. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Data Sheet 46 12.00 C505/C505C/C505A/C505CA Oscillator Watchdog The oscillator watchdog unit serves for three functions: - Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part, in order to allow the oscillator to stabilize, executes a final reset phase of typ. 1 ms; then the oscillator watchdog reset is released and the part starts program execution from address 0000H again. - Fast internal reset after power-on The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function. - Control of external wake-up from software power-down mode When the power-down mode is left by a low level at the P3.2/INT0 pin or the P4.1/RXDC pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts program execution by processing a power down interrupt after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize. Data Sheet 47 12.00 C505/C505C/C505A/C505CA EWPD (PCON1.7) P4.1 / RXDC P3.2 / INT0 Control Logic WS (PCON1.4) Power - Down Mode Activated Power-Down Mode Wake - Up Interrupt Control Logic Internal Reset Start / Stop RC Oscillator f RC 3 MHz XTAL1 XTAL2 On-Chip Oscillator OWDS 10 f1 Frequency Comparator f 2 Start / Stop f2 IP0 (A9 H ) Int. Clock MCB03308 Figure 25 Functional Block Diagram of the Oscillator Watchdog Data Sheet 48 12.00 C505/C505C/C505A/C505CA Power Saving Modes The C505 provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode. - Idle mode In the idle mode the main oscillator of the C505 continues to run, but the CPU is gated off from the clock signal. All peripheral units are further provided with the clock. The CPU status is preserved in its entirety. The idle mode can be terminated by any enabled interrupt of a peripheral unit or by a hardware reset. - Power down mode The operation of the C505 is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. Power down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/ INT0.or P4.1/RXDC. - Slow down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency significantly reduces power consumption. In the power down mode of operation, VDD can be reduced to minimize power consumption. It must be ensured, however, that VDD is not reduced before the power down mode is invoked, and that VDD is restored to its normal operating level, before the power down mode is terminated. Table 10 gives a general overview of the entry and exit procedures of the power saving modes. Table 10 Power Saving Modes Overview Mode Entering (Instruction Example) ORL PCON, #01H ORL PCON, #20H Leaving by Remarks Idle Mode Ocurrence of an interrupt from a peripheral unit Hardware Reset CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock Oscillator is stopped; contents of on-chip RAM and SFR's are maintained; Oscillator frequency is reduced to 1/32 of its nominal frequency Power Down Mode ORL PCON, #02H ORL PCON, #40H Hardware Reset Short low pulse at pin P3.2/INT0 or P4.1/RXDC ANL PCON,#0EFH or Hardware Reset Slow Down Mode ORL PCON,#10H Data Sheet 49 12.00 C505/C505C/C505A/C505CA OTP Memory Operation (C505A-4E and C505CA-4E only) The C505A-4E/C505CA-4E contains a 32K byte one-time programmable (OTP) program memory. With the C505A-4E/C505CA-4E fast programming cycles are achieved (1 byte in 100 sec). Also several levels of OTP memory protection can be selected. For programming of the device, the C505A-4E/C505CA-4E must be put into the programming mode. This typically is done not in-system but in a special programming hardware. In the programming mode the C505A-4E/C505CA-4E operates as a slave device similar as an EPROM standalone memory device and must be controlled with address/data information, control lines, and an external 11.5V programming voltage. Figure 26 shows the pins of the C505A-4E/C505CA-4E which are required for controlling of the OTP programming mode. VDD VSS A0-A7 / A8-A14 PALE PMSEL0 PMSEL1 Port 2 Port 0 D0-D7 EA/VPP PROG PRD RESET PSEN PSEL C505A-4E C505CA-4E XTAL1 XTAL2 Figure 26 Programming Mode Configuration Data Sheet 50 12.00 C505/C505C/C505A/C505CA Pin Configuration in Programming Mode D3 D2 D1 D0 N.C. N.C. N.C. N.C. N.C. N.C. N.C. 33 32 31 30 29 28 27 26 25 24 23 22 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 67 8 21 20 19 D4 D5 D6 D7 EA / VPP N.C. PROG PSEN A7 A6 / A14 A5 / A13 C505A-4E C505CA-4E 18 17 16 15 14 13 12 9 10 11 A4 / A12 A3 / A11 A2 / A10 A1 / A9 A0 / A8 VDD VSS XTAL1 XTAL2 N.C. N.C. Figure 27 P-MQFP-44 Pin Configuration of the C505A-4E/C505CA-4E in Programming Mode (Top View) Data Sheet N.C. N.C. N.C. RESET PMSEL0 N.C. PMSEL1 PSEL PRD PALE N.C. 51 12.00 C505/C505C/C505A/C505CA The following Table 11 contains the functional description of all C505A-4E/C505CA-4E pins which are required for OTP memory programming. Table 11 Pin Definitions and Functions in Programming Mode Symbol RESET Pin Number I/O *) 4 I Function Reset This input must be at static "1" (active) level during the whole programming mode. Programming mode selection pins These pins are used to select the different access modes in programming mode. PMSEL1,0 must satisfy a setup time to the rising edge of PALE. When the logic level of PMSEL1,0 is changed, PALE must be at low level. PMSEL1 0 0 1 1 PMSEL0 0 1 0 1 Access Mode Reserved Read version bytes Program/read lock bits Program/read OTP memory byte PMSEL0 PMSEL1 5 7 I I PSEL 8 I Basic programming mode select This input is used for the basic programming mode selection and must be switched according Figure 28. Programming mode read strobe This input is used for read access control for OTP memory read, Version Register read, and lock bit read operations. Programming address latch enable PALE is used to latch the high address lines. The high address lines must satisfy a setup and hold time to/from the falling edge of PALE. PALE must be at low level when the logic level of PMSEL1,0 is changed. XTAL2 Output of the inverting oscillator amplifier. XTAL1 Input to the oscillator amplifier. Circuit ground potential must be applied in programming mode. Power supply terminal must be applied in programming mode. PRD 9 I PALE 10 I XTAL2 XTAL1 14 15 16 17 O I - - VSS VDD *) I = Input O = Output Data Sheet 52 12.00 C505/C505C/C505A/C505CA Table 11 Pin Definitions and Functions in Programming Mode (cont'd) Symbol P2.0-7 Pin Number I/O *) 18-25 I Function Address lines P2.0-7 are used as multiplexed address input lines A0-A7 and A8-A14. A8-A14 must be latched with PALE. Program store enable This input must be at static "0" level during the whole programming mode. Programming mode write strobe This input is used in programming mode as a write strobe for OTP memory program, and lock bit write operations During basic programming mode selection a low level must be applied to PROG. External Access / Programming voltage This pin must be at 11.5V (VPP) voltage level during programming of an OTP memory byte or lock bit. During an OTP memory read operation this pin must be at VIH high level. This pin is also used for basic programming mode selection. At basic programming mode selection a low level must be applied to EA/VPP. Data lines 0-7 During programming mode, data bytes are transferred via the bidirectional port 0 data lines. Not Connected These pins should not be connected in programming mode. PSEN 26 I PROG 27 I EA/VPP 29 - D7-0 30-37 I/O N.C. 1-3, 6, 11-13, 28, 38-44 - *) I = Input O = Output Data Sheet 53 12.00 C505/C505C/C505A/C505CA Basic Programming Mode Selection The basic programming mode selection scheme is shown in Figure 28. VDD Clock (XTAL1/XTAL2) RESET PSEN PMSEL1,0 PROG PRD PSEL PALE EA/VPP "0" "0" "1" 0,1 stable "1" "0" 5V 0V During this period signals are not actively driven VPP VIH Ready for access mode selection Figure 28 Basic Programming Mode Selection Data Sheet 54 12.00 C505/C505C/C505A/C505CA Table 12 Access Modes Selection Access Mode Program OTP memory byte Read OTP memory byte Program OTP lock bits Read OTP lock bits Read OTP version byte EA/ VPP VPP VIH VPP VIH VIH H H L H Byte addr. of sign. byte H H H L PROG PRD H PMSEL 1 H 0 H Address (Port 2) A0-7 A8-14 - Data (Port 0) D0-7 D1,D0 see Table 13 D0-7 Lock Bits Programming / Read The C505A-4E/C505CA-4E has two programmable lock bits which, when programmed according to Table 13, provide four levels of protection for the on-chip OTP code memory. The state of the lock bits can also be read. Table 13 Lock Bit Protection Types Lock Bits at D1,D0 D1 1 D0 1 Protection Protection Type Level Level 0 The OTP lock feature is disabled. During normal operation of the C505A-4E/C505CA-4E, the state of the EA pin is not latched on reset. During normal operation of the C505A-4E/C505CA-4E, MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory. EA is sampled and latched on reset. An OTP memory read operation is only possible using the ROM/OTP verification mode 2 for protection level 1. Further programming of the OTP memory is disabled (reprogramming security). Same as level 1, but also OTP memory read operation using OTP verification mode is disabled. Same as level 2; but additionally external code execution by setting EA=low during normal operation of the C505A-4E/ C505CA-4E is no more possible. External code execution, which is initiated by an internal program (e.g. by an internal jump instruction above the ROM boundary), is still possible. 1 0 Level 1 0 0 1 0 Level 2 Level 3 Data Sheet 55 12.00 C505/C505C/C505A/C505CA Absolute Maximum Ratings Parameter Storage temperature Symbol min. Limit Values max. 150 6.5 C V V mA mA W - - - - - - - 65 - 0.5 - 0.5 - 10 Unit Notes TST Voltage on VDD pins with respect VDD to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation VIN VDD + 0.5 10 | 100 mA | PDISS 1 Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 56 12.00 C505/C505C/C505A/C505CA Operating Conditions Parameter Symbol min. Supply voltage VDD 4.25 2 Ground voltage Ambient temperature SAB-C505 TA SAF-C505 TA SAH-C505 TA SAK-C505 TA Analog reference voltage Analog ground voltage Analog input voltage XTAL clock 0 -40 -40 -40 4 70 85 110 125 VSS 0 Limit Values max. 5.5 5.5 V V V Active mode, fosc max = 20 MHz PowerDown mode Reference voltage - Unit Notes C VAREF VAGND VAIN fosc VDD + 0.1 VSS + 0.2 VAREF +0.2 20 (with 50% duty cycle) V V V MHz - - - 1) VSS - 0.1 VAGND -0.2 2 1) For the extended temperature range -40 C to 110 C (SAH) and -40 C to 125 C (SAK), the devices C505-2R, C505-L, C505C-2R and C505C-L have the max. operating frequency of 16MHz with 50% clock duty cycle. Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C505 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C505 will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the C505. Data Sheet 57 12.00 C505/C505C/C505A/C505CA DC Characteristics (Operating Conditions apply) Parameter Input low voltages all except EA, RESET EA pin RESET pin Input high voltages all except XTAL1, RESET XTAL1 pin RESET pin Output low voltages Ports 1, 2, 3, 4 Port 0, ALE, PSEN Output high voltages Ports 1, 2, 3, 4 Port 0 in external bus mode, ALE, PSEN Logic 0 input current Ports 1, 2, 3, 4 Symbol min. Limit Values max. 0.2 VDD - 0.1 V 0.2 VDD - 0.3 V 0.2 VDD + 0.1 V V V V V V V V V V A A - - - - - - Unit Test Condition VIL VIL1 VIL2 VIH VIH1 VIH2 VOL VOL1 VOH VOH2 - 0.5 - 0.5 - 0.5 0.2 VDD + 0.9 VDD + 0.5 0.7 VDD VDD + 0.5 0.6 VDD VDD + 0.5 - - 2.4 0.9 VDD 2.4 0.9 VDD - 10 - 65 0.45 0.45 - - - - - 70 - 650 IOL = 1.6 mA 1) IOL = 3.2 mA 1) IOH = - 80 A IOH = - 10 A IOH = - 800 A IOH = - 80 A 2) VIN = 0.45 V VIN = 2 V IIL Logical 1-to-0 transition current ITL Ports 1, 2, 3, 4 Input leakage current Port 0, AN0-7 (Port 1), EA Input high current to RESET ILI IIH - 5 - - 10.9 1 100 10 A A pF mA V mA 0.45 < VIN < VDD 14) 0.6 VDD Pin capacitance Overload current Programming voltage Supply current at EA/VPP Notes see Page 60 CIO IOV VPP 5 12.1 30 11.5 V 5% 5) 6) Data Sheet 58 12.00 C505/C505C/C505A/C505CA Power Supply Currents Parameter C505 / C505C Active Mode Idle Mode 12 MHz 20 MHz 12 MHz 20 MHz Symbol Limit Values typ.12) max.13) 19.3 31.3 10.3 16.2 3.9 4.8 3.2 4.0 10 28.7 35.2 14.9 17.7 9.9 12.3 5.1 6.3 5.6 22.8 27.6 12.7 15.0 6.6 7.3 5.0 5.3 5.3 27.0 39 13.0 21.0 5.5 7.5 5.0 7.0 50 30.7 37.6 15.9 18.9 12.8 15.6 5.6 6.8 20 29.2 35.3 16.3 19.3 8.2 9.3 5.9 6.5 30 Unit Test Condition mA mA mA mA A mA mA mA mA A mA mA mA mA A 7) IDD IDD IDD IDD IDD IDD IDD IDD IPD IDD IDD IDD IDD IDD IDD IDD IDD IPD IDD IDD IDD IDD IDD IDD IDD IDD IPD 8) Active Mode with 12 MHz slow-down enabled 20 MHz Idle Mode with 12 MHz slow-down enabled 20 MHz Power down mode C505A-4E Active Mode /C505CA-4E Idle Mode 16 MHz 20 MHz 16 MHz 20 MHz 9) 10) VDD = 2..5.5 V 11) 7) 8) Active Mode with 16 MHz slow-down enabled 20 MHz Idle Mode with 16 MHz slow-down enabled 20 MHz Power down mode C505A-4R / Active Mode 16 MHz C505CA-4R 20 MHz /C505A-2R / Idle Mode 16 MHz C505CA-2R 20 MHz /C505A-L / Active Mode with 16 MHz C505CA-L slow-down enabled 20 MHz Idle Mode with 16 MHz slow-down enabled 20 MHz Power down mode Notes see Page 60 9) 10) VDD = 2..5.5 V 11) 7) 8) 9) 10) VDD = 2..5.5 V 11) Data Sheet 59 12.00 C505/C505C/C505A/C505CA Note: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VDD specification when the address lines are stabilizing. 3) Overload conditions under operating conditions occur if the voltage on the respective pin exceeds the specified operating range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input currents on all port pins may not exceed 50 mA. The supply voltage VDD and VSS must remain within the specified limits. 4) Not 100% tested, guaranteed by design characterization. 5) Only valid for C505A-4E and C505CA-4E. 6) Only valid for C505A-4E and C505CA-4E in programming mode. 7) XTAL1 driven with tR , tF = 5 ns, 50% duty cycle , VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; EA = Port 0 = RESET =VDD ; all other pins are disconnected. 8) IDD (active mode) is measured with: IDD (idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode by software; 9) IDD (active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; all other pins are disconnected; the microcontroller is put into slow-down mode by software; 10) IDD (idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tR , tF = 5 ns, 50% duty cycle, VIL = VSS + 0.5 V, VIH = VDD - 0.5 V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VDD ; all other pins are disconnected; the microcontroller is put into idle mode with slow-down enabled by software; 11) IPD (power-down mode) is measured under following conditions: Port 0 = EA = VDD ; RESET =VSS ; XTAL2 = N.C.; XTAL1 = VSS ; VAGND = VSS ; VAREF = VDD ; all other pins are disconnected. 12) The typical IDD values are periodically measured at TA = +25 C but not 100% tested. 13) The maximum IDD values are measured under worst case conditions (TA = 0 C or -40 C and VDD = 5.5 V) 14) The values are valid for C505CA-4R, C505CA-2R, C505CA-L, C505A-4R, C505A-2R and C505A-L only. Data Sheet 60 12.00 C505/C505C/C505A/C505CA IDD [mA] 40 C505 C505C 35 30 ive e od M e od 25 t Ac 20 A ive ct M IDD max IDD typ Idl od eM e 15 ode le M Id 10 own Slow-d Mode+ Active ow-down Idle Mode+Sl 5 4 8 12 16 20 fOSC [MHz] Figure 29 IDD Diagram of C505 and C505C C505/C505C : Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Note: Symbol Formula 1.5 * fOSC + 1.3 1.5 * fOSC + 9.0 0.74 * fOSC + 1.4 1.0 * fOSC + 1.0 0.11 * fOSC + 2.6 0.25 * fOSC + 2.5 0.1 * fOSC + 2.0 0.25 * fOSC + 2.0 IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max fosc is the oscillator frequency in MHz. IDD values are given in mA. Data Sheet 61 12.00 C505/C505C/C505A/C505CA IDD [mA] 40 C505A-4E C505CA-4E 35 30 t Ac ive M e od 25 IDD max IDD typ Idle de Mo 20 15 n -dow Slow e+ Mod ctive A 10 5 wn +Slow-do Idle Mode 4 8 12 16 20 fOSC [MHz] Figure 30 IDD Diagram of C505A-4E and C505CA-4E C505A-4E/C505CA-4E : Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Note: Symbol Formula 1.63 * fOSC + 2.6 1.74 * fOSC + 2.8 0.69 * fOSC + 3.9 0.74 * fOSC + 4.1 0.6 * fOSC + 0.3 0.7 * fOSC + 1.6 0.3 * fOSC + 0.3 0.3 * fOSC + 0.8 IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max fosc is the oscillator frequency in MHz. IDD values are given in mA. Data Sheet 62 12.00 C505/C505C/C505A/C505CA IDD [mA] 40 35 C505A-4R C505A-2R C505A-L C505CA-4R C505CA-2R C505CA-L 30 25 M e od IDD max IDD typ M Id l e ode 20 A iv ct e 15 -down +Slow Mode Active 10 5 Idle Mode+Slow-down 4 8 12 16 20 fOSC [MHz] Figure 31 IDD Diagram of C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L C505A-4R/C505A-2R/C505A-L/C505CA-4R/C505CA-2R/C505CA-L : Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Note: Symbol Formula 1.19 * fOSC + 3.77 1.54 * fOSC + 4.47 0.57 * fOSC + 3.55 0.75 * fOSC + 4.26 0.18 * fOSC + 3.74 0.28 * fOSC + 3.67 0.07 * fOSC + 3.91 0.14 * fOSC + 3.64 IDD typ IDD max IDD typ IDD max IDD typ IDD max IDD typ IDD max fosc is the oscillator frequency in MHz. IDD values are given in mA. Data Sheet 63 12.00 C505/C505C/C505A/C505CA A/D Converter Characteristics of C505 and C505C (Operating Conditions apply) Parameter Analog input voltage Sample time Symbol Limit Values min. max. Unit V ns Test Condition 1) VAIN tS VAGND 0.2 - VAREF + 0.2 64 x tIN 32 x tIN 16 x tIN 8 x tIN 320 x tIN 160 x tIN 80 x tIN 40 x tIN 2 -1 Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 4 2) Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 4 3) VSS+0.5V VAIN VDD-0.5V 4) Conversion cycle time tADCC - ns Total unadjusted error Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Notes see next page. TUE - - - - LSB RAREF RASRC CAIN tADC / 500 k tS / 500 -1 50 pF k tADC in [ns] tS in [ns] 6) 5) 6) 2) 6) Clock calculation table : Clock Prescaler ADCL1, 0 Ratio / 32 / 16 /8 /4 1 1 0 0 1 0 1 0 tADC 32 x tIN 16 x tIN 8 x tIN 4 x tIN tS 64 x tIN 32 x tIN 16 x tIN 8 x tIN tADCC 320 x tIN 160 x tIN 80 x tIN 40 x tIN Further timing conditions : tADC min = 800 ns tIN = 1 / fOSC = tCLP Data Sheet 64 12.00 C505/C505C/C505A/C505CA Note: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be 00H or FFH, respectively. 2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE (max.) is tested at -40 TA =125 C ; VDD 5.5 V; VAREF VDD + 0.1 V and VSS= VAGND. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Data Sheet 65 12.00 C505/C505C/C505A/C505CA A/D Converter Characteristics of C505A and C505CA (Operating Conditions apply) Parameter Analog input voltage Sample time Symbol Limit Values min. max. Unit V ns Test Condition 1) VAIN tS VAGND - VAREF 64 x tIN 32 x tIN 16 x tIN 8 x tIN 384 x tIN 192 x tIN 96 x tIN 48 x tIN 2 4 Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 4 2) Prescaler / 32 Prescaler / 16 Prescaler / 8 Prescaler / 4 3) VSS+0.5V VAIN VDD-0.5V 4) VSS < VAIN < VDD+0.5V VDD - 0.5 V < VAIN < VDD 4) Conversion cycle time tADCC - ns Total unadjusted error TUE - - LSB LSB Internal resistance of reference voltage source Internal resistance of analog source ADC input capacitance Notes see next page. RAREF RASRC CAIN - - - tADC / 250 k - 0.25 tADC in [ns] tS in [ns] 6) 5) 6) tS / 500 - 0.25 50 k pF 2) 6) Clock calculation table : Clock Prescaler ADCL1, 0 Ratio / 32 / 16 /8 /4 1 1 0 0 1 0 1 0 tADC 32 x tIN 16 x tIN 8 x tIN 4 x tIN tS 64 x tIN 32 x tIN 16 x tIN 8 x tIN tADCC 384 x tIN 192 x tIN 96 x tIN 48 x tIN Further timing conditions : tADC min = 500 ns tIN = 1 / fOSC = tCLP Data Sheet 66 12.00 C505/C505C/C505A/C505CA Note: 1) VAIN may exeed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. 2) During the sample time the input capacitance CAIN must be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach their final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. 3) This parameter includes the sample time tS, the time for determining the digital result and the time for the calibration. Values for the conversion clock tADC depend on programming and can be taken from the table on the previous page. 4) TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design characterization for all other voltages within the defined voltage range. If an overload condition occurs on maximum 2 unused analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible. 5) During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing. 6) Not 100% tested, but guaranteed by design characterization. Data Sheet 67 12.00 C505/C505C/C505A/C505CA AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 16-MHz clock Variable Clock Duty Cycle 1/CLP= 2 MHz to 16 MHz 0.4 to 0.6 min. ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Unit max. - - - 75 - - 38 - 15 - 95 - min. CLP - 15 TCLHmin -15 - TCLLmin -15 CLP+ TCLHmin -15 - 0 - TCLLmin - 5 - -5 max. - - 2 CLP - 50 - - ns ns ns ns ns ns tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV *) tAVIV tAZPL 48 10 10 - 10 73 - 0 - 20 - -5 TCLHmin -15 - CLP+ ns TCLHmin- 50 - TCLLmin -10 - 2 CLP + TCLHmin -55 - ns ns ns ns ns Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Data Sheet 68 12.00 C505/C505C/C505A/C505CA AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont'd) External Data Memory Characteristics Parameter Symbol 16-MHz clock Duty Cycle 0.4 to 0.6 min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 100 - 51 200 200 103 - 40 - - - 0 Limit Values Variable Clock 1/CLP= 2 MHz to 16 MHz min. 3 CLP - 30 3 CLP - 30 CLP - 15 - 0 - - - CLP + TCLLmin - 15 2 CLP - 30 TCLHmin - 15 TCLLmin - 20 3 CLP + TCLLmin - 50 TCLHmin - 20 - max. - - - 2 CLP+ TCLHmin - 50 - CLP - 12 4 CLP - 50 4 CLP + TCLHmin -75 CLP+ TCLLmin+ 15 - TCLHmin + 15 - - - 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 158 158 48 - 0 - - - 73 95 10 5 163 5 - Data Sheet 69 12.00 C505/C505C/C505A/C505CA AC Characteristics (16 MHz, 0.4 to 0.6 Duty Cycle, cont'd) External Clock Drive Characteristics Parameter Symbol CPU Clock = 16 MHz Duty Cycle 0.4 to 0.6 min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle Clock cycle CLP TCLH TCLL 62.5 25 25 - - 0.4 25 max. 62.5 - - 10 10 0.6 37.5 Variable CPU Clock 1/CLP = 2 to 16 MHz min. 62.5 25 25 - - 25 / CLP CLP * DCmin max. 500 CLP - TCLL CLP - TCLH 10 10 1 - 25 / CLP ns ns ns ns ns - Unit tR tF DC TCL CLP * DCmax ns Note: The 16 MHz values in the tables are given as an example for a typical duty cycle variation of the oscillator clock from 0.4 to 0.6. Data Sheet 70 12.00 C505/C505C/C505A/C505CA AC Characteristics (20 MHz, 0.5 Duty Cycle) (Operating Conditions apply) (CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF) Program Memory Characteristics Parameter Symbol Limit Values 20 MHz clock Variable Clock 0.5 Duty Cycle 1/CLP = 2 MHz to 20 MHz min. ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN *) Unit max. - - - 55 - - 25 - 20 - 65 - min. CLP - 15 CLP/2 - 15 CLP/2 - 15 - CLP/2 - 15 3/2 CLP - 15 - 0 - CLP/2 - 5 - -5 max. - - - 2 CLP - 45 - - 3/2 CLP - 50 - CLP/2 - 5 - 5/2 CLP - 60 - ns ns ns ns ns ns ns ns ns ns ns ns tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ *) tPXAV *) tAVIV tAZPL 35 10 10 - 10 60 - 0 - 20 - -5 Interfacing the C505 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. Data Sheet 71 12.00 C505/C505C/C505A/C505CA AC Characteristics (20 MHz, 0.5 Duty Cycle, cont'd) External Data Memory Characteristics Parameter Symbol 20 MHz clock 0.5 Duty Cycle min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD max. - - - 75 - 38 150 150 90 - 40 - - - 0 Limit Values Variable Clock 1/CLP = 2 MHz to 20 MHz min. 3 CLP - 30 3 CLP - 30 CLP - 15 - 0 - - - 3/2 CLP - 15 2 CLP - 30 CLP/2 - 15 CLP/2 - 20 7/2 CLP - 50 CLP/2 - 20 - max. - - - 5/2 CLP- 50 - CLP - 12 4 CLP - 50 9/2 CLP - 75 - CLP/2 + 15 - - - 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tRLRH tWLWH tLLAX2 tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ 120 120 35 - 0 - - - 60 70 10 5 125 5 - 3/2 CLP + 15 ns External Clock Drive Characteristics Parameter Symbol Limit Values Variable Clock Freq. = 2 MHz to 20 MHz min. Oscillator period High time Low time Rise time Fall time Oscillator duty cycle CLP TCLH TCLL tR tF DC 50 15 15 - - 0.5 max. 500 CLP-TCLL CLP-TCLH 10 10 0.5 ns ns ns ns ns - Unit Data Sheet 72 12.00 C505/C505C/C505A/C505CA t LHLL ALE t AVLL t LLPL t LLIV t PLIV PSEN t AZPL t LLAX t PXAV t PXIZ t PXIX t PLPH Port 0 A0 - A7 Instr.IN A0 - A7 t AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Figure 32 Program Memory Read Cycle Data Sheet 73 12.00 C505/C505C/C505A/C505CA t WHLH ALE PSEN t LLDV t LLWL RD t RLDV t AVLL t LLAX2 t RLAZ Port 0 A0 - A7 from Ri or DPL t AVWL t AVDV Data IN t RHDX A0 - A7 from PCL Instr. IN t RHDZ t RLRH Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00097 Figure 33 Data Memory Read Cycle Data Sheet 74 12.00 C505/C505C/C505A/C505CA t WHLH ALE PSEN t LLWL WR t QVWX t AVLL t LLAX2 A0 - A7 from Ri or DPL t AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 t WLWH t WHQX t QVWH Data OUT A0 - A7 from PCL Instr.IN Port 0 Figure 34 Data Memory Write Cycle TCL H tR tF XTAL1 TCL L CLP 0.7VDD 0.7 V DD 0.2V - - 0.1 0.2 V DD0.1 DD MCT03310 Figure 35 External Clock Drive on XTAL1 Data Sheet 75 12.00 C505/C505C/C505A/C505CA AC Characteristics of Programming Mode (C505A-4E and C505CA-4E only) VDD = 5 V 10 %; VPP = 11.5 V 5 %; Parameter PALE pulse width PMSEL setup to PALE rising edge Address setup to PALE, PROG, or PRD falling edge TA = 25 C 10 C Symbol min. Limit Values max. - - - - - - - - - - 75 20 - 20 - ns ns ns ns ns ns s ns ns ns ns ns s ns 500 ns ns 35 10 10 10 100 0 10 10 100 100 - - 0 - 1 100 83.3 Unit tPAW tPMS tPAS tPAH tPCS tPCH tPMS tPMH tPWW tPRW tPAD tPRD tPDH tPDF tPWH1 Address hold after PALE, PROG, or PRD falling edge Address, data setup to PROG or PRD Address, data hold after PROG or PRD PMSEL setup to PROG or PRD PMSEL hold after PROG or PRD PROG pulse width PRD pulse width Address to valid data out PRD to valid data out Data hold after PRD Data float after PRD PROG high between two consecutive PROG low pulses PRD high between two consecutive PRD low tPWH2 pulses XTAL clock period tCLKP Data Sheet 76 12.00 C505/C505C/C505A/C505CA t PAW PALE t PMS PMSEL1,0 t PAS Port 2 A8-A14 t PAH A0-A7 H, H Port 0 D0-D7 PROG t PCS Notes: PRD must be high during a programming write cycle. t PWW t PCH t PWH MCT03642 Figure 36 Programming Code Byte - Write Cycle Timing Data Sheet 77 12.00 C505/C505C/C505A/C505CA t PAW PALE t PMS PMSEL1,0 t PAS Port 2 A8-A14 t PAD Port 0 t PRD PRD t PCS Notes: PROG must be high during a programming read cycle. t PRW t PCH MCT03643 H, H t PAH A0-A7 t PDH D0-D7 t PDF t PWH Figure 37 Verify Code Byte - Read Cycle Timing Data Sheet 78 12.00 C505/C505C/C505A/C505CA PMSEL1,0 H, L H, L Port 0 D0, D1 t PCS t PMS t PCH t PMH D0, D1 PROG t PWW t PMS t PRD t PRW PRD Note: PALE should be low during a lock bit read / write cycle. t PDH t PDF t PMH MCT03644 Figure 38 Lock Bit Access Timing PMSEL1,0 L, H Port 2 e. g. FD H t PCH Port 0 t PCS D0-7 t PDH t PRD t PMS t PDF t PMH PRD t PRW MCT03645 Note: PROG must be high during a programming read cycle. Figure 39 Version Byte Read Timing Data Sheet 79 12.00 C505/C505C/C505A/C505CA ROM/OTP Verification Characteristics for C505 ROM Verification Mode 1 (C505(C)(A)-2R and C505(C)A-4R only) Parameter Address to valid data Symbol min. Limit Values max. 5 CLP ns - Unit tAVQV P1.0 - P1.7 P2.0 - P2.6 Address t AVQV Port 0 Address: P1.0 - P1.7 = A0 - A7 P2.0 - P2.6 = A8 - A14 P2.5 Data: P0.0 - P0.7 = D0 - D7 Data OUT Inputs: P2.7, PSEN = = V Inputs: P2.6, P2.7, PSENVSS SS ALE, EA = V ALE, EA = V IH IH RESET = VIH2 RESET = V IH2 MCT03693 Note: P2.6 should be connected to VSS for C505(C)(A)-2R Figure 40 ROM Verification Mode 1 Data Sheet 80 12.00 C505/C505C/C505A/C505CA ROM/OTP Verification Characteristics for C505 (cont'd) ROM/OTP Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency Symbol min. Limit Values typ CLP 6 CLP - - max. - - 2 CLP - - 6 ns ns ns ns ns MHz - - - 4 CLP - 4 Unit tAWD tACY tDVA tDSA tAS 1/ CLP tCL - t ACY t AWD ALE t DSA t DVA Port 0 t AS P3.5 MCT02613 Data Valid Figure 41 ROM/OTP Verification Mode 2 Data Sheet 81 12.00 C505/C505C/C505A/C505CA V DD -0.5 V 0.2 VDD +0.9 Test Points 0.2 VDD -0.1 MCT00039 0.45 V AC Inputs during testing are driven at VDD - 0.5 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIHmin for a logic '1' and VILmax for a logic '0'. Figure 42 AC Testing: Input, Output Waveforms VLoad +0.1 V VLoad VLoad -0.1 V Timing Reference Points VOH -0.1 V VOL +0.1 V MCT00038 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH 20 mA Figure 43 AC Testing : Float Waveforms Crystal Oscillator Mode C XTAL2 2 - 20 MHz C XTAL1 Driving from External Source N.C. XTAL2 External Oscillator Signal XTAL1 Crystal Mode: C = 20 pF 10 pF (incl. stray capacitance) MCS03311 Figure 44 Recommended Oscillator Circuits for Crystal Oscillator Data Sheet 82 12.00 C505/C505C/C505A/C505CA P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Package) Figure 45 P-MQFP-44 Package Outline Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Data Sheet 83 Dimensions in mm 12.00 GPM05622 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
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