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| DS1267 DS1267 Dual Digital Potentiometer Chip FEATURES PIN ASSIGNMENT VB H1 L1 W1 RST CLK GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC SOUT W0 H0 L0 COUT DQ VB NC H1 L1 W1 RST CLK GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC NC SOUT WO HO LO COUT DQ * Ultra-lowpower consumption, quiet, pumpless design * Two digitally controlled, 256-position potentiometers * Serial port provides means for setting and reading both potentiometers * Resistors can be connected in series to provide increased total resistance * 14-pin DIP, 16-pin SOIC, 20-pin TSSOP packages * Resistive elements are temperature 0.3 LSB relative linearity compensated to 14-Pin DIP (300 Mil) 16-Pin SOIC (300 Mil) * Standard resistance values: - DS1267-10 10K - DS1267-50 50K - DS1267-100 100K VB DNC H1 L1 W1 RST CLK DNC DNC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC DNC DNC SOUT W0 H0 L0 COUT DNC DQ * Temperature: - Commercial: 0C to 70C - Industrial: -40C to 85C DESCRIPTION The DS1267 consist of two digitally controlled solid- state potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper output. Communication and control of the device is accomplished via a 3-wire serial port interface. This interface allows the device wiper position to be read or written. Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. For multiple device-single processor environments, the DS1267 can be cascaded or daisy chained. This feature provides for control of multiple devices over a single 3-wire bus. 20-Pin TSSOP (173 Mil) PIN DESCRIPTION L0, L1 H0, H1 W0, W1 VB SOUT RST DQ CLK COUT VCC GND NC DNC - - - - - - - - - - - - - Low End of Resistor High End of Resistor Wiper Terminal of Resistor Substrate Bias Voltage Stacked Configuration Output Serial Port Reset Input Serial Port Data Input Serial Port Clock Input Cascade Port Output +5 Volt Supply Ground No Internal Connection Do Not Connect ECopyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor databooks. 052694 1/11 DS1267 The DS1267 is offered in three standard resistance values which include 10K, 50K, and 100K ohm versions. Commercial and industrial temperature parts are also available. Available packages for the device include a 14-pin DIP, 16-pin SOIC, and 20-pin TSSOP. OPERATION The DS1267 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value. These two 8-bit values are written to a 17-bit I/O shift register which is used to store the two wiper positions and the stack select bit when the device is powered. A block diagram of the DS1267 is presented in Figure 1. Communication and control of the DS1267 is accomplished through a 3-wire serial port interface that drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST, CLK, and DQ. The RST control signal is used to enable the 3-wire serial port operation of the device. The RST signal is an active high input and is required to begin any communication to the DS1267. The CLK signal input is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the DS1267. Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST signal input is low. Communication with the DS1267 requires the transistion of the RST input from a low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to high transistion of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing diagrams of Figure 9(b),(c). Data written to the DS1267 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift register contains the stack select bit. This bit will be discussed in the section entitled Stacked Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value. Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position with the MSB for the wiper position occupying bit 9 and the LSB bit 16. DS1267 BLOCK DIAGRAM Figure 1 L0 H0 L1 H1 256-1 MULTIPLEXER 256-1 MULTIPLEXER WIPER-0 8 BITS W0 WIPER-1 8 BITS W1 RST CLK DQ CONTROL LOGIC STACK MULTIPLEXER SOUT b16 17-BIT I/O SHIFT REGISTER b0 COUT 052694 2/11 DS1267 I/O SHIFT REGISTER Figure 2 STACK SELECT BIT b16 POTENTIOMETER-0 b9 b8 POTENTIOMETER-1 b1 b0 17-BIT I/O SHIFT REGISTER Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper position value and lastly the potentiometer-0 wiper position value. When wiper position data is to be written to the DS1267, 17 bits (or some integer multiple) of data should always be transmitted. Transactions which do not send a complete 17-bits (or multiple) will leave the register incomplete and possibly an error in the desired wiper positions. After a communication transaction has been completed the RST signal input should be taken to a low state to prevent any inadvertent changes to the device shift register. Once RST has reached a low state, the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position. A new wiper position will only engage after a RST transition to the inactive state. On device power-up the DS1267 wiper positions will be set at 50% of the total resistance or binary value 1000 0000. STACKED CONFIGURATION The potentiometers of the DS1267 can be connected in series as shown in Figure 3. This is referred to as the stacked configuration and allows the user to double the total end-to-end resistance of the part. The resolution of the combined potentiometers will remain the same as a single potentiometer but with a total of 512 wiper positions available. Device resolution is defined as Rtot/256 (per potentiometer); where Rtot equals the total potentiometer resistance. The wiper output for the combined stacked potentiometer will be taken at the SOUT pin, which is the multiplexed outputof the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer wiper selected at the SOUT output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O shift register. If the stack select bit has value 0, the multiplexed output, SOUT, will be that of the potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, SOUT, will be that of the potentiometer-1wiper. STACKED CONFIGURATION Figure 3 H1 POTENTIOMETER-1 W1 L1 STACK MULTIPLEXER SOUT H0 W0 POTENTIOMETER-0 L0 052694 3/11 DS1267 CASCADE OPERATION A feature of the DS1267 is the ability to control multiple devices from a single processor. Multiple DS1267s can be linked or daisy chained as shown in Figure 4. As a data bit is entered into the I/O shift register of the DS1267 a bit will appear at the COUT output after a minimum delay of 50 nanoseconds. The stack select bit of the DS1267 will always be the first out the part at the beginning of a transaction. Additionally the COUT pin is always active regardless of the state of RST. This allows one to read the I/O shift register without changing its value. CASCADING MULTIPLE DEVICES Figure 4 PROCESSOR DQ DS1267 #1 COUT DQ DS1267 #2 COUT DQ DS1267 #n COUT OPTIONAL FEEDBACK RESISTOR FOR READING DATA (2K TO 10K) The COUT output of the DS1267 can be used to drive the DQ input of another DS1267. When connecting multiple devices, the total number of bits transmitted is always 17 times the number of DS1267s in the daisy chain. An optional feedback resistor can be placed between the COUT terminal of the last device and the first DS1267 DQ input thus allowing the controlling processor to read, as well as, write data, or circularly clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range from 1K to 10K ohms. When reading data via the COUT pin and isolation resistor, the DQ line is left floating by the reading device. When RST is driven high, bit 17 is present on the COUT pin, which is fed back to the input DQ pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the first position of the I/O shift register and bit 16 becomes present on COUT and DQ of the next device. After 17 bits (or 17 times the number of DS1267s in the daisy chain), the data has shifted completely around and back to its original position. When RST transitions to the low state to end data transfer, the value (the same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register. ABSOLUTE AND RELATIVE LINEARITY Absolute linearity is defined as the difference between the actual measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute linearity is given in terms of a minimum increment or expected output when the wiper is moved one position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 10/512 volts. The equation for absolute linearity is given as follows: (1) ABSOLUTE LINEARITY AL={VO(actual) - VO(expected)}/MI Relative Linearity is a measure of error between two adjacent wiper position points and is given in terms of MI by equation (2). (2) RELATIVE LINEARITY RL={VO(n+1) - VO(n)}/MI Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267 at 25C. The specification for absolute linearity of the DS1267 is 0.75 MI typical. The specification for relative linearity of the DS1267 is 0.3 MI typical. 052694 4/11 DS1267 LINEARITY MEASUREMENT CONFIGURATION Figure 5 +5V H1 POTENTIOMETER-1 RW1 L1 STACK MULTIPLEXER SOUT + H0 RW0 POTENTIOMETER-0 L0 -5V W0 I0=0 VO W1 - NOTE: In this setup, a 2% delta in total resistance R0 to R1 would cause a 2.5 MI error. DS1267 ABSOLUTE AND RELATIVE LINEARITY Figure 6 Absolute and Relative Linearity (Normalized To 1 LSB) 1 0.8 0.6 0.4 0.2 Relative LSB 0 -0.2 -0.4 Absolute -0.6 -0.8 -1 0 50 100 150 200 250 300 350 400 450 500 Wiper Setting 052694 5/11 DS1267 TYPICAL APPLICATION CONFIGURATIONS Figures 7 and 8 show two typical application configurations for the DS1267. By connecting the wiper terminal of the part to a high impedance load, the effects of the wiper resistance is minimized, since the wiper resistance can vary from 400 to 1000 ohms depending on wiper voltage. Figure 7 presents the device connected in an inverting variblegain amplifier. The gain of the circuit on Figure 7 is given by the following equation: Av = -n/(255-n); where n = 0 to 255 Figure 8 shows the deivce operaing in a fixed gain attenuator where the potentiometer is used to attenuate an incoming signal. Note the resistance R1 is chosen to be much greater than the wiper resistance to minimize its effect on circuit gain. INVERTING VARIABLE GAIN AMPLIFIER Figure 7 DS1267 H0 n=255 n=0 L0 RW WIPER RESISTANCE W0 - VOUT + FIXED GAIN ATTENUATOR Figure 8 H0 RF RW W0 R1 - VOUT + WIPER RESISTANCE L0 R1>>RW 052694 6/11 DS1267 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground (VB=GND) Voltage on Resistor Pins when VB=-5.5V Voltage on VB Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7.0V -5.5V to +7.0V -5.5 to GND 0C to 70C commercial; -40C to +85C industrial -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Supply Voltage Input Logic 1 Input Logic 0 Substrate Bias Resistor Inputs SYMBOL VCC VIH VIL VB L, H, W MIN 4.5 2.0 -0.5 -5.5 VB-0.5 TYP (0C to 70C; VCC=5.0V 10%) MAX 5.5 VCC+0.5 +0.8 GND VCC+0.5 UNITS V V V V V NOTES 1 1, 2 1, 2 1 2 DC ELECTRICAL CHARACTERISTICS PARAMETER Supply Current Input Leakage Wiper Resistance Wiper Current Output Leakage Logic 1 Output @ 2.4 Volts Logic 0 Output @ 0.4 Volts Standby Current SYMBOL ICC ILI RW IW ILO IOH IOL ISTBY 22 -1 -1 -1 400 MIN TYP 22 (0C to 70C; VCC=5.0V 10%) MAX 650 +1 1000 1 +1 UNITS A A mA A mA 4 mA A 8, 9 8, 9 NOTES 12 ANALOG RESISTOR CHARACTERISTICS PARAMETER End-to-End Resistor Tolerance Absolute Linearity Relative Linearity -3 dB Cutoff Frequency Noise Figure Temperature Coefficient 800 FCUTOFF SYMBOL MIN -20 0.75 0.3 TYP (0C to 70C; VCC=5.0V 10%) MAX +20 UNITS % LSB LSB Hz 4 5 7 11 ppm/C NOTES 052694 7/11 DS1267 CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL CIN COUT MIN TYP MAX 5 7 UNITS pF pF (tA=25C) NOTES 3 3 AC ELECTRICAL CHARACTERISTICS PARAMETER CLK Frequency Width of CLK Pulse Data Setup Time Data Hold Time Propagation Delay Time Low to High Level Clock to Output Propagation Delay Time High to Low Level RST High to Clock Input High RST Low from Clock Input High RST Inactive Clock Low to Data Valid on a Read CLK Rise Time, CLK Fall Time SYMBOL fCLK tCH tDC tCDH tPLH tPLH tCC tHLT tRLT tCDD tCR 50 50 125 MIN DC 50 30 10 TYP (0C to 70C; VCC=5.0V 10%) MAX 10 UNITS MHz ns ns ns 50 50 ns ns ns ns ns 30 50 ns ns 10 10 NOTES 10 10 10 10 10 10 10 10 NOTES: 1. All voltages are referenced to ground. 2. Resistor inputs cannot exceed the substrate bias voltage, Vb, in the negative direction. 3. Capacitance values apply at 25C. 4. Absolute linearity is used to determine wiper voltage versus expected voltage as determined by wiper position. Device test limits 1.6 LSB. 5. Relative linearity is used to determined the change in voltage between successive tap positions. Device test limits 0.5 LSB. 6. Typical values are for ta = 25C and nominal supply voltage. 7. -3 dB cutoff frequency characteristics for the DS1267 depend on potentiometer total resistance: DS1267-010; 1 MHz, DS1267-050; 200 KHz, DS1267-100; 100 KHz. 8. Cout is active regardless of the state of RST. 9. VREF= 1.5 volts . 10. See Figure 9(a), (b), and (c). 11. Noise < -120 dB/Hz. Reference 1 volt (thermal). 12. See Figure 11. 052694 8/11 DS1267 TIMING DIAGRAMS Figure 9 (A) RST 3-WIRE INACTIVE b0 DQ STACK SELECT BIT POTENTIOMETER-1 WIPER VALUE POTENTIOMETER-0 WIPER VALUE b1 b8 b9 b16 3-WIRE SERIAL INTERFACE GENERAL OVERVIEW 3-WIRE ACTIVE 3-WIRE INACTIVE CLK (B) START OF COMMUNICATION TRANSACTION DEVICE ACTIVE DEVICE INACTIVE RST tCC tCH * ** * ** CLK tCDH tDC DQ * BIT 0 STACK SELECT BIT tPLH BIT 1 POTENTIOMETER-1 WIPER VALUE ** COUT (C) END OF COMMUNICATION TRANSACTION DEVICE ACTIVE DEVICE INACTIVE tRLT RST tCH tHLT CLK tCDH tDC DQ tPLH COUT LAST DATA BIT (b16) 052694 9/11 DS1267 DIGITAL OUTPUT LOAD SCHEMATIC Figure 10 +5V 1.1 K D.U.T. 680 50 pF TYPICAL SUPPLY CURRENT VS. SERIAL CLOCK RATE Figure 11 VCC = 5.5V, tA = 25C 350 300 250 200 I CC (mA) 150 100 50 0 1K 10K 100K Serial Clock Rate (bits/second) 1M 10M 052694 10/11 DS1267 DS1267E 20-PIN TSSOP D n E H SEE DETAIL A c B e1 A2 A A1 L DETAIL A phi G DIM A MM A1 MM A2 MM C MM L MM e1 MM B MM D MM E MM G MM H MM phi MIN - 0.05 0.75 0.09 0.50 MAX 1.10 - 1.05 0.18 0.70 0.65 BSC 0.18 6.40 0.30 6.90 4.40 NOM 0.25 REF 6.25 0 6.55 8 052694 11/11 |
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