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KM68S2000 Family Document Title 256Kx8 bit Low Power and Low Voltage CMOS Static RAM Preliminary CMOS SRAM Revision History Revision No. 0.0 History Initial draft Draft Date Remark September 30, 1997 Preliminary The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. Revision 0.0 September 1997 KM68S2000 Family 256Kx8 bit Low Power and Low Voltage CMOS Static RAM FEATURES * Process Technology : TFT * Organization : 256Kx8 * Power Supply Voltage KM68S2000 Family : 2.3~3.3V * Low Data Retention Voltage : 2V(Min) * Three state output and TTL Compatible * Package Type : 32-TSOP1-0820F, 32-TSOP1-0813.4F Preliminary CMOS SRAM GENERAL DESCRIPTION The KM68S2000 families are fabricated by SAMSUNGs advanced CMOS process technology. The families support various operating temperature ranges and wide voltage operation for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. PRODUCT FAMILY Power Dissipation Product Family Operating Temperature Vcc Range Speed(ns) Standby (ISB1, Max) 10A 1201)/150 15A Operating (ICC2, Max) 25mA 35mA 25mA 35mA 32-TSOP1-F 32-sTSOP1-F PKG Type KM68S2000L-L Commercial(0~70C) Industrial(-40~85C) 2.3~2.7V 2.7~3.3V KM68S2000LI-L 2.3~2.7V 2.7~3.3V 1. The parameter is measured with 30pF test load. PIN DESCRIPTION A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 FUNCTIONAL BLOCK DIAGRAM OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 Clk gen. Precharge circuit. Vcc Vss 32-TSOP 32-STSOP Type1 - Forward A3 A8 A9 A10 A11 A13 A14 A15 A17 A16 Row select Memory array 1024 rows 256x8 columns Name Function Name Function I/O1 I/O8 CS1,CS2 Chip Select Input OE WE Output Enable Input Write Enable Input I/O1~I/O8 Data Inputs/Outputs Vcc Vss N.C. Power Ground No Connection Data cont I/O Circuit Column select A0~A17 Address Inputs Data cont A0 A1 A2 A4 A5 A6 A7 A12 CS1 CS2 WE OE Control Logic SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications withoutce. Revision 0.0 September 1997 KM68S2000 Family PRODUCT LIST Commercial Temperature Products(0~70C) Part Name KM68S2000LT-12L KM68S2000LT-15L KM68S2000LTG-12L KM68S2000LTG-15L Function 32-TSOP F, 120ns, 2.3~3.3V, LL 32-TSOP F, 150ns, 2.3~3.3V, LL 32-sTSOP F, 120ns, 2.3~3.3V, LL 32-sTSOP F, 150ns, 2.3~3.3V, LL Preliminary CMOS SRAM Industrial Temperture Products(-40~85C) Part Name KM68S2000LTI-12L KM68S2000LTI-15L KM68S2000LTGI-12L KM68S2000LTGI-15L Function 32-TSOP F, 120ns, 2.3~3.3V, LL 32-TSOP F, 150ns, 2.3~3.3V, LL 32-sTSOP F, 120ns, 2.3~3.3V, LL 32-sTSOP F, 150ns, 2.3~3.3V, LL Note : LL - Low Low Standby Current FUNCTIONAL DESCRIPTION CS1 H X1) L L L CS2 X1) L H H H OE X1) X1) H L X1) WE X1) X1) H H L I/O High-Z High-Z High-Z Dout Din Mode Deselected Deselected Output Disabled Read Write Power Standby Standby Active Active Active 1. X means dont care (Must be in high or low states) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Soldering temperature and time Symbol VIN,VOUT VCC PD TSTG TA TSOLDER Ratings -0.5 to VCC+0.5 -0.3 to 4.6 1 -65 to 150 0 to 70 -40 to 85 260C, 10sec (Lead Only) Unit V V W C C C Remark KM68S2000L KM68S2000LI - 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Revision 0.0 September 1997 KM68S2000 Family RECOMMENDED DC OPERATING CONDITIONS1) Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Product KM68S2000 Family All Family 2.3~2.7V 2.7~3.3V KM68S2000 Family Min 2.3 0 2.0 2.2 -0.33) Typ 2.5/3.0 0 - Preliminary CMOS SRAM Max 3.3 0 Vcc+0.32) 0.6 Unit V V V Note: 1. Commercial Product : TA=0 to 70C, otherwise specified Industrial Product : TA=-40 to 85C, otherwise specified 2. Overshoot : Vcc+3.0V in case of pulse width30ns 3. Undershoot : -3.0V in case of pulse width30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC VIN=Vss to Vcc CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read 2.3~2.7V 2.7~3.3V Cycle time=1s, 100% duty, IIO=0mA CS10.2V, CS2Vcc-0.2V, VIN0.2V or VINVcc-0.2V Cycle time=Min, 100% duty, IIO=0mA CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL=0.5mA at 2.3~2.7V IOL=2.1mA at 2.7~3.3V IOH=-0.5mA at 2.3~2.7V IOH=-1.0mA at 2.7~3.3V Standby Current(TTL) Standby Current (CMOS) 1. Industrial product=15A Test Conditions Min -1 -1 2.0 2.4 - Typ - Max 1 1 2 5 3 10 5 15 25 35 0.4 0.3 10 1) Unit A A mA mA mA 2.3~2.7V Read Write ICC1 Average operating current 2.7~3.3V Read Write mA mA mA V V V mA A ICC2 2.3~2.7V 2.7~3.3V Output low voltage VOL Output high voltage VOH ISB ISB1 CS1=VIH, CS2=VIL, Other inputs=VIL or VIH CS1Vcc-0.2V, CS2Vcc-0.2V or CS20.2V, Other inputs=0~Vcc Revision 0.0 September 1997 KM68S2000 Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level : 0.4 to 2.2V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) : CL=100pF+1TTL CL=30pF+1TTL CL1) Preliminary CMOS SRAM 1. Including scope and jig capacitance AC CHARACTERISTICS (Vcc=2.3~3.3V, Commercial products:TA=0 to 70C, Industrial products:TA=-40 to85C) Speed Bins Parameter List Symbol Min Read cycle time Address access time Chip select to output Output enable to valid output Read Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write cycle time Write Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z 1. The parameter is measured with 30pF test load. 120ns1) Max 120 120 60 35 35 30 Min 150 20 20 0 0 15 150 120 0 120 100 0 0 60 0 5 150ns Max 150 150 75 40 40 40 - Units tRC tAA tCO1, tCO2 tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW1, tCW2 tAS tAW tWP tWR tWHZ tDW tDH tOW 120 20 20 15 120 100 0 100 80 0 0 50 0 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns DATA RETENTION CHARACTERISTICS Item Vcc for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR See data retention waveform tRDR 5 1. CS1 Vcc-0.2V, CS2Vcc-0.2V(CS1 Contrlled) or CS20.2V(CS2 Controlled) Test Condition CS1Vcc-0.2V1) Vcc=2.0V, CS1Vcc-0.2V or CS20.2V Min 2.0 0 Typ - Max 3.3 10 - Unit V A ms Revision 0.0 September 1997 KM68S2000 Family TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tRC Address tOH Data Out Previous Data Valid tAA Preliminary CMOS SRAM Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO1 CS1 tHZ(1,2) CS2 tCO2 tOE tOH OE tOLZ tLZ Data Valid tOHZ Data out NOTES (READ CYCLE) High-Z 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. Revision 0.0 September 1997 KM68S2000 Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tCW(2) CS1 tAW CS2 tCW(2) tWP(1) WE tAS(3) Data in tWHZ Data out Data Undefined tDW Data Valid tOW tDH tWR(4) Preliminary CMOS SRAM TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tWP(1) WE tDW Data in Data Valid tDH tCW(2) tWR(4) Data out High-Z High-Z Revision 0.0 September 1997 KM68S2000 Family TIMING WAVEFORM OF WRITE CYCLE(3) (CS1 Controlled) tWC Address tAS(3) CS1 tAW CS2 tCW(2) tWP(1) tDW Data in Data Valid tDH tCW(2) tWR(4) Preliminary CMOS SRAM WE Data out NOTES (WRITE CYCLE) High-Z High-Z 1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low, CS2 going high and WE going low : A write end at the earliest transition among CS1 going high, CS2 going low and WE going high, tWP is measured from the begining of write to the end of write. 2. tCW is measured from the CS1 going low or CS2 going high to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR(1) applied in case a write ends as CS1 or WE going high tWR(2) applied in case a write ends as CS2 going to low. DATA RETENTION WAVE FORM CS1 controlled VCC 2.3/2.7V1) tSDR Data Retention Mode tRDR 2.2V VDR CS1VCC - 0.2V CS1 GND CS2 controlled VCC 2.3/2.7V1) CS2 tSDR Data Retention Mode tRDR VDR 0.4V GND 1. 2.7V for 2.7~3.3V operation, 2.3V for 2.3~2.7V operation. CS20.2V Revision 0.0 September 1997 KM68S2000 Family PACKAGE DIMENSIONS 32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F) Preliminary CMOS SRAM Units : millimeter(Inch) 0.20 +0.10 -0.05 0.008+0.004 -0.002 20.000.20 0.7870.008 #32 ( 8.40 0.331 MAX 8.00 0.315 0.25 ) 0.010 #1 0.50 0.0197 #16 #17 1.000.10 0.0390.004 1.20 0.047 MAX +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.25 0.010 TYP 18.400.10 0.7240.004 0.15 0~8 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F) 0.20 +0.10 -0.05 0.008+0.004 -0.002 13.400.10 0.5280.008 #32 ( 8.00 0.315 0.25 ) 0.010 #1 8.40 0.331 MAX 0.50 0.0197 #16 #17 1.000.10 0.0390.004 1.20 0.047 MAX 11.800.10 0.4650.004 +0.10 -0.05 0.006+0.004 -0.002 0.05 0.002 MIN 0.25 0.010 TYP 0.15 0~8 0.45 ~0.75 0.018 ~0.030 ( 0.50 ) 0.020 September 1997 0.10 MAX 0.004 Revision 0.0 0.10 MAX 0.004 |
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