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| User's Manual VRC4173TM VR4100 SeriesTM Companion Chip PD31173 Document No. U14579EJ2V0UM00 (2nd edition) Date Published February 2002 N CP(K) Printed in Japan [MEMO] 2 User's Manual U14579EJ2V0UM NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. VR4100 Series, VR4121, VR4122, and VRC4173 are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. User's Manual U14579EJ2V0UM 3 * The information in this document is current as of November, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 4 User's Manual U14579EJ2V0UM Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-3067-58-00 Fax: 01-3067-58-99 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (France) S.A. Representacion en Espana Madrid, Spain Tel: 091-504-27-87 Fax: 091-504-28-60 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 * Branch The Netherlands NEC Electronics Italiana S.R.L. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 * Branch Sweden NEC Electronics Taiwan Ltd. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.12 User's Manual U14579EJ2V0UM 5 Major Revisions in This Edition (1/2) Page Throughout p.25 p.27 p.50 p.51 p.56 pp.58 to 61 p.86 p.89 p.90 p.91 p.96 p.102 p.111 p.112 p.127 p.129 p.129 p.130 p.134 p.135 p.145 p.147 p.152 p.154 p.158 p.161 p.164 p.165 p.187 p.196 pp.197 to 207 pp.209, 210 p.213 p.216 pp.251, 252 p.253 Description Deletion of descriptions related to 32-bit PC card (CardBus card) Modification of description in 1.1 Features Modification of description in 1.3 (14) CARDU1, CARDU2 (PC Card Units) Modification of pin I/O direction in Table 2-1 PCI Bus Interface Signals Modification of pin I/O direction in Table 2-4 PC Card Interface Signals Modification of Table 2-13 Test Interface Signals and Table 2-14 Test Modes Modification of Table 2-18 Pin Status and Recommended Connection Examples Modification of description in 6.1 General Addition of Note to 6.2.2 CMUSRST (base address + 0x042) Modification of register name in text of 7.1 General Modification of Figure 7-1 Interrupt Control Outline Diagram Modification of description in 7.2.2 PIUINTREG (base address + 0x062) Modification of description in 7.2.8 MPIUINTREG (base address + 0x06E) Modification of description in 8.2.3 GIUPIODL (base address + 0x084) Modification of description in 8.2.4 GIUPIODH (base address + 0x086) Modification of description in 9.1.1 Block diagrams Modification of Figure 9-4 Scan Sequencer State Transition Diagram Modification of description in 9.2 (3) ADPortScan state Modification of bit name in 9.2 (5) WaitPenTouch state Addition of Note to Table 9-2 PIUCNTREG Register Bit Manipulation and States Modification of description in 9.3.2 PIUINTREG (base address + 0x0A4) Modification of bit name in 9.4 (2) Transfer flow for auto scan coordinate detection Modification of bit name in 9.4 (7) Transfer flow when returning from Suspend mode (Disable state) Addition of Caution to 10.1 General Modification of description in 10.2.3 SODATREG (base address + 0x0E6) Modification of bit name in 10.2.7 MCNTREG (base address + 0x0F2) Addition of Note to 10.2.10 SEQREG (base address + 0x0FA) Modification of description in 10.3.1 (2) When not using DMA transfer Modification of bit name in 10.3.2 Input (MIC) Modification of description in 13.1 General Addition of Caution to 13.2.11 CSRBADR (offset address: 0x10 to 0x13) Addition of Caution to 13.2.13 to 13.2.25 Addition of Caution to 13.2.28 to 13.2.30 Addition of Caution to 13.2.32 SYSCNT (offset address: 0x80 to 0x83) Addition of Caution to 13.2.36 and 13.2.37 Addition of Caution to 13.3.60 and 13.3.61 Addition of Caution to 13.3.64 MEM0_CMD_TIM (PCI offset address: 0x885, ExCA extended offset address: 0x0A) 6 User's Manual U14579EJ2V0UM Major Revisions in This Edition (2/2) Page p.255 p.258 p.259 pp.262, 263 p.272 p.276 pp.284, 285 p.346 pp.354, 355 p.381 p.385 p.387 pp.394 to 396 p.398 p.402 pp.403 to 407 Description Addition of Caution to 13.3.67 MEM1_CMD_TIM (PCI offset address: 0x889, ExCA extended offset address: 0x0E) Modification of Table 13-4 CardBus Socket Registers Modification of description in 13.4.1 SKT_EV (offset address: 0x000) Addition of Note to 13.4.3 SKT_PRE_STATE (offset address: 0x008) Modification of Caution in 13.5.3 Power supply interface Modification of reset value of device ID register in Table 14-1 USB Host Control Configuration Registers Modification of bit name in 14.3.3 HcControl (offset address: 0x04) Modification of Table 15-2 AC97U Operational Registers Modification of description and addition of Note in 15.3.7 CTRL (offset address: 0x18) Modification of Figure 15-5 AC97U-Supported Slots Modification of Remark 2 in 15.5.6 (3) Filter function Modification of bit name in 15.6 (2) SDATAOUT slot 1: CMDADDR (Command Address Port) Modification of description in 15.9 (1) Data output to the Codec (slot 3, 4, or 5) Modification of description in 15.9 (2) Data input from the Codec (slot 3, 4, 5, or 6) Addition of APPENDIX A CAUTIONS Addition of APPENDIX B RESTRICTIONS The mark shows major revised points. User's Manual U14579EJ2V0UM 7 INTRODUCTION Target Readers This manual is intended for users who understand the functions of the VRC4173 and develop application systems using them. This manual is designed to help users understand the architecture of the VRC4173, as described below. This manual covers the following general topics. * Overview * Pin functions * On-chip peripheral functions Purpose Organization How to Read This Manual This manual assumes that the reader has general knowledge of electrical engineering, logic circuits, and microcomputers. * To gain a general understanding of VRC4173 functions Read this manual in the order of the contents. * To learn about the electrical specifications of the VRC4173 Refer to the Data Sheet (separate document) Conventions Data significance: Active low representation: Note: Caution: Remark: Numerical representation: Higher digits on the left and lower digits on the right XXX# (# after pin or signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary or decimal ... XXXX Hexadecimal ... 0xXXXX Prefix indicating power of 2 (address space, memory capacity): 10 K (kilo) 2 = 1,024 20 2 M (mega) 2 = 1,024 30 3 G (giga) 2 = 1,024 40 4 T (tera) 2 = 1,024 50 5 P (peta) 2 = 1,024 60 6 E (exa) 2 = 1,024 8 User's Manual U14579EJ2V0UM Related Documents See the following documents when using this manual. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. O Documents related to device Document Name VRC4173 User's Manual Document Number This manual U15338E U14327E To be prepared PD31173 (VRC4173) Data Sheet VR4122 User's Manual TM PD30122 (VR4122) Data Sheet User's Manual U14579EJ2V0UM 9 CONTENTS CHAPTER 1 OVERVIEW ..........................................................................................................................25 1.1 1.2 1.3 1.4 1.5 Features .....................................................................................................................................25 Ordering Information................................................................................................................26 Internal Block Configuration ...................................................................................................26 PCI Device Configuration.........................................................................................................28 Lists of Registers......................................................................................................................29 CHAPTER 2 PIN FUNCTIONS ................................................................................................................44 2.1 2.2 Pin Configuration......................................................................................................................44 Pin Function Lists.....................................................................................................................50 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 2.2.10 2.2.11 2.2.12 2.2.13 PCI bus interface signals..........................................................................................................50 USB interface signals ...............................................................................................................50 AC-Link interface signals..........................................................................................................50 PC card interface signals .........................................................................................................51 Keyboard interface signals .......................................................................................................54 PS/2 interface signals...............................................................................................................54 Touch panel interface signals...................................................................................................55 Audio interface signal ...............................................................................................................55 General-purpose I/O signals ....................................................................................................55 Interrupt interface signal...........................................................................................................56 Clock interface signals .............................................................................................................56 Test interface signals ...............................................................................................................56 Power supplies and grounds ....................................................................................................57 2.3 2.4 Pin Status and Recommended Connection Examples .........................................................58 Clock Oscillator Connection....................................................................................................62 CHAPTER 3 BCU (BUS CONTROL UNIT) ...........................................................................................64 3.1 3.2 General.......................................................................................................................................64 Register Set ...............................................................................................................................64 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 3.2.11 VID (offset address: 0x00 to 0x01)...........................................................................................65 DID (offset address: 0x02 to 0x03)...........................................................................................65 PCICMD (offset address: 0x04 to 0x05)...................................................................................66 PCISTS (offset address: 0x06 to 0x07) ....................................................................................67 RID (offset address: 0x08) .......................................................................................................68 CLASSC (offset address: 0x09 to 0x0B) ..................................................................................68 CACHELS (offset address: 0x0C) ............................................................................................68 MLT (offset address: 0x0D) ......................................................................................................69 HEDT (offset address: 0x0E)....................................................................................................69 BIST (offset address: 0x0F) .....................................................................................................69 BADR (offset address: 0x10 to 0x13) .......................................................................................70 10 User's Manual U14579EJ2V0UM 3.2.12 3.2.13 3.2.14 3.2.15 3.2.16 3.2.17 3.2.18 3.2.19 SUBVID (offset address: 0x2C to 0x2D) .................................................................................. 71 SUBID (offset address: 0x2E to 0x2F) ..................................................................................... 71 INTL (offset address: 0x3C) ..................................................................................................... 72 INTP (offset address: 0x3D)..................................................................................................... 72 MIN_GNT (offset address: 0x3E) ............................................................................................. 72 MAX_LAT (offset address: 0x3F) ............................................................................................. 73 BUSCNT (offset address: 0x40)............................................................................................... 73 IDSELNUM (offset address: 0x41) ........................................................................................... 74 CHAPTER 4 DMAAU (DMA ADDRESS UNIT) .....................................................................................75 4.1 4.2 General ......................................................................................................................................75 Register Set...............................................................................................................................76 4.2.1 4.2.2 4.2.3 4.2.4 AIU IN DMA base address registers ........................................................................................ 77 AIU IN DMA address registers ................................................................................................. 78 AIU OUT DMA base address registers .................................................................................... 79 AIU OUT DMA address registers ............................................................................................. 80 CHAPTER 5 DCU (DMA CONTROL UNIT) ..........................................................................................81 5.1 5.2 5.3 General ......................................................................................................................................81 DMA Priority Control ................................................................................................................81 Register Set...............................................................................................................................81 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 DMARSTREG (base address + 0x020).................................................................................... 82 DMAIDLEREG (base address + 0x022)................................................................................... 82 DMASENREG (base address + 0x024) ................................................................................... 83 DMAMSKREG (base address + 0x026) ................................................................................... 84 DMAREQREG (base address + 0x028) ................................................................................... 85 CHAPTER 6 CMU (CLOCK MASK UNIT).............................................................................................86 6.1 6.2 General ......................................................................................................................................86 Register Set...............................................................................................................................87 6.2.1 6.2.2 CMUCLKMSK (base address + 0x040).................................................................................... 87 CMUSRST (base address + 0x042)........................................................................................ 89 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT)................................................................................90 7.1 7.2 General ......................................................................................................................................90 Register Set...............................................................................................................................93 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 SYSINT1REG (base address + 0x060).................................................................................... 94 PIUINTREG (base address + 0x062)....................................................................................... 96 AIUINTREG (base address + 0x064)....................................................................................... 97 KIUINTREG (base address + 0x066)....................................................................................... 98 GIULINTREG (base address + 0x068) .................................................................................... 99 GIUHINTREG (base address + 0x06A).................................................................................... 99 User's Manual U14579EJ2V0UM 11 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 MSYSINT1REG (base address + 0x06C) ..............................................................................100 MPIUINTREG (base address + 0x06E)..................................................................................102 MAIUINTREG (base address + 0x070) ..................................................................................103 MKIUINTREG (base address + 0x072) ..................................................................................104 MGIULINTREG (base address + 0x074)................................................................................105 MGIUHINTREG (base address + 0x076) ...............................................................................105 7.3 Notes for Register Setting .....................................................................................................106 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) ...........................................................................107 8.1 8.2 General.....................................................................................................................................107 Register Set .............................................................................................................................108 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 8.2.11 8.2.12 8.2.13 8.2.14 8.2.15 GIUDIRL (base address + 0x080) ..........................................................................................109 GIUDIRH (base address + 0x082) .........................................................................................110 GIUPIODL (base address + 0x084) .......................................................................................111 GIUPIODH (base address + 0x086) .......................................................................................112 GIUINTSTATL (base address + 0x088) .................................................................................113 GIUINTSTATH (base address + 0x08A) ................................................................................114 GIUINTENL (base address + 0x08C) .....................................................................................115 GIUINTENH (base address + 0x08E).....................................................................................115 GIUINTTYPL (base address + 0x090) ...................................................................................116 GIUINTTYPH (base address + 0x092) ...................................................................................117 GIUINTALSELL (base address + 0x094) ...............................................................................118 GIUINTALSELH (base address + 0x096)...............................................................................119 GIUINTHTSELL (base address + 0x098) ...............................................................................120 GIUINTHTSELH (base address + 0x09A) ..............................................................................121 SELECTREG (base address + 0x09E)...................................................................................123 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) .....................................................................125 9.1 9.2 9.3 General.....................................................................................................................................125 9.1.1 Block diagrams .......................................................................................................................126 Scan Sequencer State Transition..........................................................................................129 Register Set .............................................................................................................................131 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.10 PIUCNTREG (base address + 0x0A2) ...................................................................................132 PIUINTREG (base address + 0x0A4).....................................................................................135 PIUSIVLREG (base address + 0x0A6)...................................................................................136 PIUSTBLREG (base address + 0x0A8)..................................................................................137 PIUCMDREG (base address + 0x0AA) ..................................................................................138 PIUASCNREG (base address + 0x0B0).................................................................................139 PIUAMSKREG (base address + 0x0B2) ................................................................................141 PIUCIVLREG (base address + 0x0BE) ..................................................................................142 PIUPBnmREG (base address + 0x0C0 to base address + 0x0CE, base address + 0x0DC to base address + 0x0DE)..........................................................................................................143 PIUABnREG (base address + 0x0D0 to base address + 0x0D2) ..........................................144 9.4 12 Status Transfer Flow ..............................................................................................................145 User's Manual U14579EJ2V0UM 9.5 9.6 Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States ...............................................................................................148 Timing......................................................................................................................................149 9.6.1 9.6.2 Touch/release detection timing .............................................................................................. 149 A/D port scan timing............................................................................................................... 149 9.7 Data Lost Generation Conditions .........................................................................................150 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) ..................................................................................152 10.1 10.2 General ....................................................................................................................................152 Register Set.............................................................................................................................152 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.2.8 10.2.9 10.2.10 10.2.11 MDMADATREG (base address + 0x0E0) .............................................................................. 153 SDMADATREG (base address + 0x0E2)............................................................................... 153 SODATREG (base address + 0x0E6) .................................................................................... 154 SCNTREG (base address + 0x0E8) ...................................................................................... 155 SCNVRREG (base address + 0x0EA) ................................................................................... 156 MIDATREG (base address + 0x0F0) ..................................................................................... 157 MCNTREG (base address + 0x0F2) ...................................................................................... 158 MCNVRREG (base address + 0x0F4) ................................................................................... 159 DVALIDREG (base address + 0x0F8) ................................................................................... 160 SEQREG (base address + 0x0FA) ........................................................................................ 161 INTREG (base address + 0x0FC) .......................................................................................... 162 Output (Speaker).................................................................................................................... 163 Input (MIC) ............................................................................................................................. 165 10.3 Operation Sequence...............................................................................................................163 10.3.1 10.3.2 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) .........................................................................166 11.1 11.2 General ....................................................................................................................................166 Register Set.............................................................................................................................166 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 KIUDATn (base address + 0x100 to base address + 0x10A) ................................................ 167 KIUSCANREP (base address + 0x110) ................................................................................. 169 KIUSCANS (base address + 0x112) ...................................................................................... 171 KIUWKS (base address + 0x114) .......................................................................................... 173 KIUWKI (base address + 0x116)............................................................................................ 175 KIUINT (base address + 0x118)............................................................................................. 176 KIURST (base address + 0x11A)........................................................................................... 177 SCANLINE (base address + 0x11E) ...................................................................................... 178 CHAPTER 12 PS2U (PS/2 UNIT) .........................................................................................................182 12.1 12.2 General ....................................................................................................................................182 Register Set.............................................................................................................................182 12.2.1 12.2.2 12.2.3 PS2CHnDATA (base address + 0x120, base address + 0x140) ........................................... 183 PS2CHnCTRL (base address + 0x122, base address + 0x142)............................................ 184 PS2CHnRST (base address + 0x124, base address + 0x144).............................................. 185 User's Manual U14579EJ2V0UM 13 12.3 Transmission Procedure........................................................................................................186 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS)......................................................................187 13.1 13.2 General.....................................................................................................................................187 Configuration Register Set ....................................................................................................188 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 13.2.9 13.2.10 13.2.11 13.2.12 13.2.13 13.2.14 13.2.15 13.2.16 13.2.17 13.2.18 13.2.19 13.2.20 13.2.21 13.2.22 13.2.23 13.2.24 13.2.25 13.2.26 13.2.27 13.2.28 13.2.29 13.2.30 13.2.31 13.2.32 13.2.33 13.2.34 13.2.35 13.2.36 13.2.37 13.2.38 13.2.39 VID (offset address: 0x00 to 0x01).........................................................................................190 DID (offset address: 0x02 to 0x03).........................................................................................190 PCICMD (offset address: 0x04 to 0x05).................................................................................191 PCISTS (offset address: 0x06 to 0x07) ..................................................................................193 RID (offset address: 0x08) .....................................................................................................194 CLASSC (offset address: 0x09 to 0x0B) ................................................................................194 CACHELS (offset address: 0x0C) ..........................................................................................194 MLT (offset address: 0x0D) ....................................................................................................195 HEDT (offset address: 0x0E)..................................................................................................195 BIST (offset address: 0x0F) ...................................................................................................195 CSRBADR (offset address: 0x10 to 0x13) .............................................................................196 CAP (offset address: 0x14) ....................................................................................................196 SECSTS (offset address: 0x16 to 0x17).................................................................................197 PCIBNUM (offset address: 0x18) ...........................................................................................198 CARDNUM (offset address: 0x19) .........................................................................................198 SUBBNUM (offset address: 0x1A) .........................................................................................198 CLT (offset address: 0x1B) ....................................................................................................199 MEMB0 (offset address: 0x1C to 0x1F) .................................................................................200 MEML0 (offset address: 0x20 to 0x23)...................................................................................201 MEMB1 (offset address: 0x24 to 0x27) ..................................................................................202 MEML1 (offset address: 0x28 to 0x2B) ..................................................................................203 IOB0 (offset address: 0x2C to 0x2F) ......................................................................................204 IOL0 (offset address: 0x30 to 0x33) .......................................................................................205 IOB1 (offset address: 0x34 to 0x37).......................................................................................206 IOL1 (offset address: 0x38 to 0x3B).......................................................................................207 INTL (offset address: 0x3C) ...................................................................................................207 INTP (offset address: 0x3D) ...................................................................................................208 BRGCNT (offset address: 0x3E to 0x3F) ...............................................................................208 SUBVID (offset address: 0x40 to 0x41)..................................................................................210 SUBID (offset address: 0x42 to 0x43) ....................................................................................210 PC16BADR (offset address: 0x44 to 0x47) ............................................................................211 SYSCNT (offset address: 0x80 to 0x83) ................................................................................212 DEVCNT (offset address: 0x91) .............................................................................................213 SKDMA0 (offset address: 0x94 to 0x97) ................................................................................214 SKDMA1 (offset address: 0x98 to 0x9B)................................................................................215 CHIPCNT (offset address: 0x9C) ...........................................................................................216 SERRDIS (offset address: 0x9F)............................................................................................216 CAPID (offset address: 0xA0) ................................................................................................217 NIP (offset address: 0xA1) .....................................................................................................217 14 User's Manual U14579EJ2V0UM 13.2.40 13.2.41 13.2.42 13.2.43 13.2.44 PMC (offset address: 0xA2 to 0xA3) ...................................................................................... 218 PMCSR (offset address: 0xA4 to 0xA5) ................................................................................. 219 PMCSR_BSE (offset address: 0xA6) ..................................................................................... 219 DATA (offset address: 0xA7) ................................................................................................. 220 TEST (offset address: 0xFC) ................................................................................................. 220 ID_REV (PCI offset address: 0x800, ExCA offset address: 0x00) ......................................... 226 IF_STATUS (PCI offset address: 0x801, ExCA offset address: 0x01)................................... 227 PWR_CNT (PCI offset address: 0x802, ExCA offset address: 0x02) .................................... 228 INT_GEN_CNT (PCI offset address: 0x803, ExCA offset address: 0x03) ............................. 229 CARD_SC (PCI offset address: 0x804, ExCA offset address: 0x04)..................................... 230 CARD_SCI (PCI offset address: 0x805, ExCA offset address: 0x05).................................... 231 ADR_WIN_EN (PCI offset address: 0x806, ExCA offset address: 0x06) .............................. 232 IO_WIN_CNT (PCI offset address: 0x807, ExCA offset address: 0x07)................................ 233 IO_WIN0_SAL (PCI offset address: 0x808, ExCA offset address: 0x08) .............................. 233 IO_WIN0_SAH (PCI offset address: 0x809, ExCA offset address: 0x09).............................. 234 IO_WIN0_EAL (PCI offset address: 0x80A, ExCA offset address: 0x0A).............................. 234 IO_WIN0_EAH (PCI offset address: 0x80B, ExCA offset address: 0x0B) ............................. 234 IO_WIN1_SAL (PCI offset address: 0x80C, ExCA offset address: 0x0C) ............................. 235 IO_WIN1_SAH (PCI offset address: 0x80D, ExCA offset address: 0x0D)............................. 235 IO_WIN1_EAL (PCI offset address: 0x80E, ExCA offset address: 0x0E).............................. 235 IO_WIN1_EAH (PCI offset address: 0x80F, ExCA offset address: 0x0F) ............................. 236 MEM_WIN0_SAL (PCI offset address: 0x810, ExCA offset address: 0x10).......................... 236 MEM_WIN0_SAH (PCI offset address: 0x811, ExCA offset address: 0x11) ......................... 236 MEM_WIN0_EAL (PCI offset address: 0x812, ExCA offset address: 0x12).......................... 237 MEM_WIN0_EAH (PCI offset address: 0x813, ExCA offset address: 0x13) ......................... 237 MEM_WIN0_OAL (PCI offset address: 0x814, ExCA offset address: 0x14) ......................... 237 MEM_WIN0_OAH (PCI offset address: 0x815, ExCA offset address: 0x15) ......................... 238 GEN_CNT (PCI offset address: 0x816, ExCA offset address: 0x16)..................................... 238 MEM_WIN1_SAL (PCI offset address: 0x818, ExCA offset address: 0x18).......................... 239 MEM_WIN1_SAH (PCI offset address: 0x819, ExCA offset address: 0x19) ......................... 239 MEM_WIN1_EAL (PCI offset address: 0x81A, ExCA offset address: 0x1A) ......................... 239 MEM_WIN1_EAH (PCI offset address: 0x81B, ExCA offset address: 0x1B)......................... 240 MEM_WIN1_OAL (PCI offset address: 0x81C, ExCA offset address: 0x1C) ........................ 240 MEM_WIN1_OAH (PCI offset address: 0x81D, ExCA offset address: 0x1D)........................ 240 GLO_CNT (PCI offset address: 0x81E, ExCA offset address: 0x1E) .................................... 241 MEM_WIN2_SAL (PCI offset address: 0x820, ExCA offset address: 0x20).......................... 241 MEM_WIN2_SAH (PCI offset address: 0x821, ExCA offset address: 0x21) ......................... 242 MEM_WIN2_EAL (PCI offset address: 0x822, ExCA offset address: 0x22).......................... 242 MEM_WIN2_EAH (PCI offset address: 0x823, ExCA offset address: 0x23) ......................... 242 MEM_WIN2_OAL (PCI offset address: 0x824, ExCA offset address: 0x24) ......................... 243 MEM_WIN2_OAH (PCI offset address: 0x825, ExCA offset address: 0x25) ......................... 243 MEM_WIN3_SAL (PCI offset address: 0x828, ExCA offset address: 0x28).......................... 243 MEM_WIN3_SAH (PCI offset address: 0x829, ExCA offset address: 0x29) ......................... 244 MEM_WIN3_EAL (PCI offset address: 0x82A, ExCA offset address: 0x2A) ......................... 244 User's Manual U14579EJ2V0UM 13.3 ExCA Register Set ..................................................................................................................221 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.3.8 13.3.9 13.3.10 13.3.11 13.3.12 13.3.13 13.3.14 13.3.15 13.3.16 13.3.17 13.3.18 13.3.19 13.3.20 13.3.21 13.3.22 13.3.23 13.3.24 13.3.25 13.3.26 13.3.27 13.3.28 13.3.29 13.3.30 13.3.31 13.3.32 13.3.33 13.3.34 13.3.35 13.3.36 13.3.37 13.3.38 13.3.39 15 13.3.40 13.3.41 13.3.42 13.3.43 13.3.44 13.3.45 13.3.46 13.3.47 13.3.48 13.3.49 13.3.50 13.3.51 13.3.52 13.3.53 13.3.54 13.3.55 13.3.56 13.3.57 13.3.58 13.3.59 13.3.60 13.3.61 13.3.62 13.3.63 13.3.64 13.3.65 13.3.66 13.3.67 13.3.68 13.3.69 13.3.70 13.3.71 MEM_WIN3_EAH (PCI offset address: 0x82B, ExCA offset address: 0x2B).........................244 MEM_WIN3_OAL (PCI offset address: 0x82C, ExCA offset address: 0x2C).........................245 MEM_WIN3_OAH (PCI offset address: 0x82D, ExCA offset address: 0x2D) ........................245 EXT_INDX (ExCA offset address: 0x2E)................................................................................245 EXT_DATA (ExCA offset address: 0x2F)...............................................................................246 MEM_WIN4_SAL (PCI offset address: 0x830, ExCA offset address: 0x30) ..........................246 MEM_WIN4_SAH (PCI offset address: 0x831, ExCA offset address: 0x31)..........................246 MEM_WIN4_EAL (PCI offset address: 0x832, ExCA offset address: 0x32) ..........................247 MEM_WIN4_EAH (PCI offset address: 0x833, ExCA offset address: 0x33)..........................247 MEM_WIN4_OAL (PCI offset address: 0x834, ExCA offset address: 0x34)..........................247 MEM_WIN4_OAH (PCI offset address: 0x835, ExCA offset address: 0x35) .........................248 IO_WIN0_OAL (PCI offset address: 0x836, ExCA offset address: 0x36) ..............................248 IO_WIN0_OAH (PCI offset address: 0x837, ExCA offset address: 0x37)..............................248 IO_WIN1_OAL (PCI offset address: 0x838, ExCA offset address: 0x38) ..............................249 IO_WIN1_OAH (PCI offset address: 0x839, ExCA offset address: 0x39)..............................249 MEM_WIN0_SAU (PCI offset address: 0x840, ExCA extended offset address: 0x00)..........249 MEM_WIN1_SAU (PCI offset address: 0x841, ExCA extended offset address: 0x01)..........250 MEM_WIN2_SAU (PCI offset address: 0x842, ExCA extended offset address: 0x02)..........250 MEM_WIN3_SAU (PCI offset address: 0x843, ExCA extended offset address: 0x03)..........250 MEM_WIN4_SAU (PCI offset address: 0x844, ExCA extended offset address: 0x04)..........251 IO_SETUP_TIM (PCI offset address: 0x880, ExCA extended offset address: 0x05) ............251 IO_CMD_TIM (PCI offset address: 0x881, ExCA extended offset address: 0x06) ................252 IO_HOLD_TIM (PCI offset address: 0x882, ExCA extended offset address: 0x07) ..............252 MEM0_SETUP_TIM (PCI offset address: 0x884, ExCA extended offset address: 0x09) ......253 MEM0_CMD_TIM (PCI offset address: 0x885, ExCA extended offset address: 0x0A) .........253 MEM0_HOLD_TIM (PCI offset address: 0x886, ExCA extended offset address: 0x0B)........254 MEM1_SETUP_TIM (PCI offset address: 0x888, ExCA extended offset address: 0x0D) .....254 MEM1_CMD_TIM (PCI offset address: 0x889, ExCA extended offset address: 0x0E) .........255 MEM1_HOLD_TIM (PCI offset address: 0x88A, ExCA extended offset address: 0x0F) .......255 MEM_TIM_SEL1 (PCI offset address: 0x88C, ExCA extended offset address: 0x11)...........256 MEM_TIM_SEL2 (PCI offset address: 0x88D, ExCA extended offset address: 0x12)...........256 MEM_WIN_PWEN (PCI offset address: 0x891, ExCA extended offset address: 0x16) ........257 SKT_EV (offset address: 0x000) ............................................................................................259 SKT_MASK (offset address: 0x004).......................................................................................261 SKT_PRE_STATE (offset address: 0x008)............................................................................262 SKT_FORCE_EV (offset address: 0x00C).............................................................................264 SKT_CNT (offset address: 0x010) .........................................................................................266 16-bit PC card support ...........................................................................................................268 Interrupts ................................................................................................................................270 Power supply interface ...........................................................................................................271 13.4 CardBus Socket Register Set ................................................................................................258 13.4.1 13.4.2 13.4.3 13.4.4 13.4.5 13.5 PC Card Unit Operation..........................................................................................................268 13.5.1 13.5.2 13.5.3 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT)...................................................................274 16 User's Manual U14579EJ2V0UM 14.1 14.2 Features...................................................................................................................................274 USB Host Control Configuration Registers .........................................................................275 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 Register set ............................................................................................................................ 276 Command register (offset address: 0x04) .............................................................................. 277 Status register (offset address: 0x06) .................................................................................... 278 Base address register (offset address: 0x10) ........................................................................ 279 Power management register (offset address: 0xE0) .............................................................. 280 Register set ............................................................................................................................ 282 HcRevision (offset address: 0x00) ......................................................................................... 283 HcControl (offset address: 0x04) ........................................................................................... 284 HcCommandStatus (offset address: 0x08) ............................................................................ 286 HcInterruptStatus (offset address: 0x0C)............................................................................... 288 HcInterruptEnable (offset address: 0x10) .............................................................................. 290 HcInterruptDisable (offset address: 0x14).............................................................................. 292 HcHCCA (offset address: 0x18) ............................................................................................. 294 HcPeriodCurrentED (offset address: 0x1C) ........................................................................... 295 HcControlHeadED (offset address: 0x20) .............................................................................. 296 HcControlCurrentED (offset address: 0x24)........................................................................... 297 HcBulkHeadED (offset address: 0x28) .................................................................................. 298 HcBulkCurrentED (offset address: 0x2C)............................................................................... 299 HcDoneHead (offset address: 0x30)...................................................................................... 300 HcFmInterval (offset address: 0x34) ...................................................................................... 301 HcFmRemaining (offset address: 0x38)................................................................................. 302 HcFmNumber (offset address: 0x3C)..................................................................................... 303 HcPeriodicStart (offset address: 0x40) .................................................................................. 304 HcLSThreshold (offset address: 0x44)................................................................................... 305 HcRhDescriptorA (offset address: 0x48)................................................................................ 306 HcRhDescriptorB (offset address: 0x4C) ............................................................................... 308 HcRhStatus (offset address: 0x50) ........................................................................................ 310 HcRhPortStatus1, 2 (offset address: 0x54, 0x58).................................................................. 312 General .................................................................................................................................. 316 Host controller communication methods ................................................................................ 318 ED (Endpoint Descriptor) ....................................................................................................... 321 ED format ............................................................................................................................... 321 ED fields................................................................................................................................. 322 TD (Transfer Descriptor) ........................................................................................................ 323 GeneralTD format................................................................................................................... 323 GeneralTD fields .................................................................................................................... 324 IsochronousTD format............................................................................................................ 326 IsochronousTD fields ............................................................................................................. 327 HCCA (Host Controller Communication Area) ....................................................................... 327 HCCA format .......................................................................................................................... 328 HCCA overview ...................................................................................................................... 328 User's Manual U14579EJ2V0UM 14.3 Operational Registers ............................................................................................................282 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 14.3.10 14.3.11 14.3.12 14.3.13 14.3.14 14.3.15 14.3.16 14.3.17 14.3.18 14.3.19 14.3.20 14.3.21 14.3.22 14.3.23 14.4 USB Specifications.................................................................................................................316 14.4.1 14.4.2 14.4.3 14.4.4 14.4.5 14.4.6 14.4.7 14.4.8 14.4.9 14.4.10 14.4.11 14.4.12 14.4.13 17 14.4.14 14.4.15 HC state transitions ................................................................................................................329 List service flow ......................................................................................................................330 CHAPTER 15 AC97U (AC97 UNIT)......................................................................................................336 15.1 15.2 General.....................................................................................................................................336 Configuration Register Set ....................................................................................................336 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.2.6 15.2.7 15.2.8 15.2.9 15.2.10 15.2.11 15.2.12 15.2.13 15.2.14 15.2.15 15.2.16 15.2.17 15.2.18 VID (offset address: 0x00 to 0x01).........................................................................................337 DID (offset address: 0x02 to 0x03).........................................................................................337 PCICMD (offset address: 0x04 to 0x05).................................................................................338 PCISTS (offset address: 0x06 to 0x07) ..................................................................................339 RID (offset address: 0x08) .....................................................................................................340 CLASSC (offset address: 0x09 to 0x0B) ................................................................................340 CACHELS (offset address: 0x0C) ..........................................................................................340 MLT (offset address: 0x0D) ....................................................................................................341 HEDT (offset address: 0x0E)..................................................................................................341 BIST (offset address: 0x0F) ...................................................................................................341 BASEADR (offset address: 0x10 to 0x13)..............................................................................342 SVID (offset address: 0x2C to 0x2D) .....................................................................................343 SUBID (offset address: 0x2E to 0x2F) ...................................................................................343 EXROMADR (offset address: 0x30 to 0x33) ..........................................................................344 INTL (offset address: 0x3C) ...................................................................................................344 INTP (offset address: 0x3D) ...................................................................................................345 MIN_GNT (offset address: 0x3E) ...........................................................................................345 MAX_LAT (offset address: 0x3F) ...........................................................................................345 INT_CLR/INT_STATUS (offset address: 0x00)......................................................................347 CODEC_WR (offset address: 0x04).......................................................................................349 CODEC_RD (offset address: 0x08)........................................................................................350 CODEC_REQ (offset address: 0x0C) ....................................................................................351 SLOT12_WR (offset address: 0x10) ......................................................................................352 SLOT12_RD (offset address: 0x14) .......................................................................................353 CTRL (offset address: 0x18) ..................................................................................................354 ACLINK_CTRL (offset address: 0x1C)...................................................................................356 SRC_RAM_DATA (offset address: 0x20)...............................................................................358 INT_MASK (offset address: 0x24)..........................................................................................359 DAC1_CTRL (offset address: 0x30).......................................................................................361 DAC1L (offset address: 0x34) ................................................................................................362 DAC1_BADDR (offset address: 0x38)....................................................................................363 DAC2_CTRL (offset address: 0x3C) ......................................................................................364 DAC2L (offset address: 0x40) ................................................................................................365 DAC2_BADDR (offset address: 0x44)....................................................................................366 DAC3_CTRL (offset address: 0x48).......................................................................................367 DAC3L (offset address: 0x4C)................................................................................................368 DAC3_BADDR (offset address: 0x50)....................................................................................369 15.3 Operational Register Set ........................................................................................................346 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 15.3.10 15.3.11 15.3.12 15.3.13 15.3.14 15.3.15 15.3.16 15.3.17 15.3.18 15.3.19 18 User's Manual U14579EJ2V0UM 15.3.20 15.3.21 15.3.22 15.3.23 15.3.24 15.3.25 15.3.26 15.3.27 15.3.28 ADC1_CTRL (offset address: 0x54)....................................................................................... 370 ADC1L (offset address: 0x58)................................................................................................ 371 ADC1_BADDR (offset address: 0x5C)................................................................................... 372 ADC2_CTRL (offset address: 0x60)....................................................................................... 373 ADC2L (offset address: 0x64)................................................................................................ 374 ADC2_BADDR (offset address: 0x68) ................................................................................... 375 ADC3_CTRL (offset address: 0x6C) ...................................................................................... 376 ADC3L (offset address: 0x70)................................................................................................ 377 ADC3_BADDR (offset address: 0x74) ................................................................................... 378 15.4 15.5 AC97 Interface Configuration................................................................................................379 AC97U Function Overview.....................................................................................................380 15.5.1 15.5.2 15.5.3 15.5.4 15.5.5 15.5.6 Block diagram ........................................................................................................................ 380 AC-Link interface support format ........................................................................................... 381 Cache buffer........................................................................................................................... 381 DMA control ........................................................................................................................... 382 Interrupt control ...................................................................................................................... 383 SRC (sample rate converter).................................................................................................. 383 15.6 15.7 15.8 15.9 AC-Link Interface Data Transfer Format ..............................................................................386 Data Output to Codec.............................................................................................................392 Data Input from Codec ...........................................................................................................393 DMA Transfer ..........................................................................................................................394 15.10 Special Interrupts ...................................................................................................................399 15.11 AC97U Suspend Transition Procedure ................................................................................400 15.12 Filter RAM................................................................................................................................401 APPENDIX A CAUTIONS.......................................................................................................................402 A.1 Adjusting Skew of PCI Clock.................................................................................................402 APPENDIX B RESTRICTIONS...............................................................................................................403 B.1 Noise During Operation of AC97...........................................................................................403 B.1.1 B.1.2 Phenomenon.......................................................................................................................... 403 Preventive measures ............................................................................................................. 403 Phenomenon.......................................................................................................................... 404 Preventive measures ............................................................................................................. 405 Phenomenon.......................................................................................................................... 406 Preventive measures ............................................................................................................. 406 Phenomenon.......................................................................................................................... 407 Preventive measures ............................................................................................................. 407 B.2 Erroneous Recognition of PC Card ......................................................................................404 B.2.1 B.2.2 B.3 Pulling up PC Card Pins ........................................................................................................406 B.3.1 B.3.2 B.4 Incorrect Playback with AIU ..................................................................................................407 B.4.1 B.4.2 APPENDIX C INDEX...............................................................................................................................408 User's Manual U14579EJ2V0UM 19 LIST OF FIGURES (1/2) Figure No. Title Page 1-1 2-1 2-2 4-1 7-1 7-2 7-3 9-1 9-2 9-3 9-4 9-5 9-6 9-7 10-1 10-2 11-1 11-2 11-3 11-4 11-5 12-1 13-1 13-2 13-3 13-4 13-5 14-1 14-2 14-3 Internal Block Diagram and Connection Example with External Blocks.........................................................26 External Circuit of Clock Oscillator .................................................................................................................62 Examples of Improperly Connected Resonators ............................................................................................63 DMA Space Used in DMA Transfers ..............................................................................................................75 Interrupt Control Outline Diagram...................................................................................................................91 Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with SCLK) ........................92 Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with PCLK) ........................93 PIU Peripheral Block Diagram......................................................................................................................126 Coordinate Detection Equivalent Circuits .....................................................................................................127 PIU Internal Block Diagram ..........................................................................................................................128 Scan Sequencer State Transition Diagram ..................................................................................................129 Interval Times and States.............................................................................................................................136 Touch/Release Detection Timing .................................................................................................................149 A/D Port Scan Timing ...................................................................................................................................149 Speaker Output and AUDIOOUT Pin ...........................................................................................................164 AUDIOIN Pin and MIC Operation .................................................................................................................165 Scan Operation and Key Data Store Register..............................................................................................168 KSCAN Signal Status and KPORT Signal Sampling Timing ........................................................................174 Key Scan Interval .........................................................................................................................................175 Transition of Sequencer Status ....................................................................................................................179 Basic Operation Timing Chart ......................................................................................................................180 Data Pattern .................................................................................................................................................183 Access to ExCA Registers (Memory Access from Primary Side) .................................................................221 Access to ExCA Registers (I/O Access from Primary Side) .........................................................................221 ExCA Extended Registers ............................................................................................................................222 CardBus Socket Registers ...........................................................................................................................258 Power Supply Control Serial Signal (PWCDATA, PWCCLK, PWCLATCH) Timing .....................................273 USB Host Control Configuration Space........................................................................................................275 Bus Topology................................................................................................................................................316 Full-Speed Device Cable and Resistor Connections....................................................................................316 User's Manual U14579EJ2V0UM 20 LIST OF FIGURES (2/2) Figure No. Title Page 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 15-13 15-14 A-1 B-1 B-2 B-3 B-4 Low-Speed Device Cable and Resistor Connections...................................................................................317 Relationship Between EDs and TDs ............................................................................................................318 InterruptED List ............................................................................................................................................319 Bandwidth Allocation Method .......................................................................................................................320 4:1 Control Bulk Service Ratio .....................................................................................................................320 ED Format ....................................................................................................................................................321 GeneralTD Format .......................................................................................................................................323 Current Buffer Pointer, Buffer End, and 4 KB Boundary ..............................................................................325 IsochronousTD Format.................................................................................................................................326 HC State Transitions ....................................................................................................................................329 List Service Flow ..........................................................................................................................................330 ED Service Flow...........................................................................................................................................331 TD Service Flow ...........................................................................................................................................333 Transfer Completed Queue Operation .........................................................................................................335 SYNC Signal ................................................................................................................................................357 reset_b Signal (Internal Signal) ....................................................................................................................357 AC97 Interface Configuration .......................................................................................................................379 AC97U Block Diagram .................................................................................................................................380 AC97U-Supported Slots ...............................................................................................................................381 Buffer Format ...............................................................................................................................................381 Data Transfer (Buffer AC-Link) ................................................................................................................382 Data Transfer (AC-Link Buffer) ................................................................................................................382 Interrupt Control ...........................................................................................................................................383 Input Data.....................................................................................................................................................383 Converter Function (for Output) ...................................................................................................................384 Filter Function ..............................................................................................................................................385 AC-Link Interface Data Transfer Format ......................................................................................................386 RAM Data Format ........................................................................................................................................401 Adjusting Skew of PCI Clock........................................................................................................................402 Rate Conversion...........................................................................................................................................403 Initializing PC Card.......................................................................................................................................404 Example of Circuit Preventing Shift to IDE Mode.........................................................................................405 Example of Inserting Diode ..........................................................................................................................406 User's Manual U14579EJ2V0UM 21 LIST OF TABLES (1/3) Table No. Title Page 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-17 1-18 1-19 1-20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 PCI Devices and Component Units ................................................................................................................28 BCU Configuration Registers .........................................................................................................................29 DMAAU Registers ..........................................................................................................................................30 DCU Registers................................................................................................................................................30 CMU Registers ...............................................................................................................................................30 ICU Registers .................................................................................................................................................31 GIU Registers .................................................................................................................................................31 PIU Registers .................................................................................................................................................32 AIU Registers .................................................................................................................................................33 KIU Registers .................................................................................................................................................33 PS2CH1 Registers .........................................................................................................................................34 PS2CH2 Registers .........................................................................................................................................34 CARDU Configuration Registers ....................................................................................................................35 ExCA Registers ..............................................................................................................................................37 ExCA Extended Registers ..............................................................................................................................39 CardBus Socket Registers .............................................................................................................................39 USB Host Control Configuration Registers.....................................................................................................40 Host Control Operational Registers................................................................................................................41 AC97U PCI Configuration Registers ..............................................................................................................42 AC97U Operational Registers ........................................................................................................................43 PCI Bus Interface Signals...............................................................................................................................50 USB Interface Signals ....................................................................................................................................50 AC-Link Interface Signals ...............................................................................................................................50 PC Card Interface Signals ..............................................................................................................................51 Correspondence of Signal Names for Each PC Card Interface Mode............................................................52 Keyboard Interface Signals ............................................................................................................................54 PS/2 Interface Signals ....................................................................................................................................54 Touch Panel Interface Signals........................................................................................................................55 Audio Interface Signal ....................................................................................................................................55 General-Purpose I/O Signals..........................................................................................................................55 Interrupt Interface Signal ................................................................................................................................56 Clock Interface Signals...................................................................................................................................56 Test Interface Signals.....................................................................................................................................56 Test Modes.....................................................................................................................................................56 A/D Converter Power Supplies and Grounds .................................................................................................57 D/A Converter Power Supply and Ground......................................................................................................57 Digital Power Supplies and Grounds..............................................................................................................57 Pin Status and Recommended Connection Examples ...................................................................................58 User's Manual U14579EJ2V0UM 22 LIST OF TABLES (2/3) Table No. Title Page 3-1 4-1 5-1 5-2 6-1 7-1 7-2 8-1 8-2 8-3 8-4 9-1 9-2 9-3 9-4 9-5 9-6 9-7 10-1 11-1 12-1 12-2 13-1 13-2 13-3 13-4 13-5 13-6 13-7 BCU Configuration Registers .........................................................................................................................64 DMAAU Registers ..........................................................................................................................................76 DMA Priority Levels........................................................................................................................................81 DCU Registers ...............................................................................................................................................81 CMU Registers ...............................................................................................................................................87 Assignment of Sampling Clocks and Interrupt Sources .................................................................................92 ICU Registers .................................................................................................................................................93 GPIO Pin Outline..........................................................................................................................................107 GIU Registers...............................................................................................................................................108 Correspondences Between Interrupt Mask and Interrupt Hold ....................................................................122 Alternate Function Correspondence Table of VRC4173................................................................................124 PIU Registers ...............................................................................................................................................131 PIUCNTREG Register Bit Manipulation and States .....................................................................................134 PIUASCNREG Register Bit Manipulation and States...................................................................................140 Detected Data and Page Buffers..................................................................................................................143 A/D Ports and Data Buffers ..........................................................................................................................144 Mask Clear During Scan Sequencer Operation ...........................................................................................145 Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States........................148 AIU Registers ...............................................................................................................................................152 KIU Registers ...............................................................................................................................................166 PS2CH1 Registers .......................................................................................................................................182 PS2CH2 Registers .......................................................................................................................................182 CARDU Configuration Registers ..................................................................................................................188 ExCA Registers ............................................................................................................................................223 ExCA Extended Registers............................................................................................................................225 CardBus Socket Registers ...........................................................................................................................258 Registers Related to Memory Windows .......................................................................................................268 Registers Related to I/O Windows ...............................................................................................................269 Interrupt Sources and Corresponding Masks...............................................................................................270 User's Manual U14579EJ2V0UM 23 LIST OF TABLES (3/3) Table No. Title Page 13-8 13-9 13-10 13-11 14-1 14-2 14-3 14-4 14-5 14-6 15-1 15-2 CARDU1 (Slot 1) VPP Settings......................................................................................................................271 CARDU1 (Slot 1) VCC Settings .....................................................................................................................271 CARDU2 (Slot 2) VPP Settings......................................................................................................................272 CARDU2 (Slot 2) VCC Settings .....................................................................................................................272 USB Host Control Configuration Registers...................................................................................................276 Host Control Operational Registers..............................................................................................................282 ED Fields ......................................................................................................................................................322 GeneralTD Fields .........................................................................................................................................324 IsochronousTD Fields...................................................................................................................................327 HCCA Format ...............................................................................................................................................328 AC97U PCI Configuration Registers ............................................................................................................336 AC97U Operational Registers ......................................................................................................................346 24 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW This chapter presents an overview of the VRC4173. 1.1 Features The VRC4173 is a companion chip that is to be connected to a product having a PCI bus in the VR4100 Series such as NEC's 64-bit RISC processor VR4122. The VRC4173 incorporates the I/O macros necessary for a handheld PC running WindowsTM CE, and can also access design resources on a personal computer by means of the PCI bus interface. The VRC4173 has the following features. Processor interface * PCI bus: Compliant with PCI Local Bus Specification Revision 2.1 33 MHz operation * CLKRUN signal support On-chip USB host controller * Compliant with Open HCI Specification Release 1.0 * USB ports: 2 ports * Full speed (12 Mbps) and low speed (1.5 Mbps) support * On-chip FIFO: 4 x 4 double word (PCI side), 64 x 1 byte (USB side) On-chip PC card controller * Compliant with 1997 PC Card standard (excluding 32-bit PC card) * Supports two card slots * Buffer with 5 V withstand voltage * On-chip interface for an external power supply control IC On-chip AC-Link interface * Compliant with AC97 (Audio Codec '97) standard Rev 2.1 * DMA support On-chip PS/2 controller On-chip keyboard controller * 96-key support (compatible with KIU of VR4121 ) On-chip audio controller * Playback (10-bit D/A converter), recording (12-bit A/D converter) * Compatible with AIU of VR4121 On-chip touch panel controller * Touch panel driver, coordinate detection (12-bit A/D) * General-purpose analog input: 1 port * Compatible with PIU function of VR4121 GPIO (general-purpose I/O pin) * Supports a total of 21 pins * Compatible with GIU of VR4121 On-chip 48 MHz oscillator Power supply voltage: 3.3 V (some internals with 5 V withstand voltage) Note This becomes 64-key support when the PS/2 is used with two channels because of exclusive use relative to the PS/2. TM Note User's Manual U14579EJ2V0UM 25 CHAPTER 1 OVERVIEW 1.2 Ordering Information Part Number Package 304-pin plastic FBGA (19 x 19) Internal Maximum Operating Frequency 33 MHz PD31173F1-33-HN1 1.3 Internal Block Configuration Figure 1-1 shows an internal block diagram of the VRC4173 and connection example with external blocks. Figure 1-1. Internal Block Diagram and Connection Example with External Blocks Memory VR4122 PCI bus (33 MHz) 9.216 MHz LCD USB OSB AC-Link Bus bridge USBU PC Card CARDU1 CARDU2 DMAAU DCU CMU ICU KIU PS2CH1 PS2CH2 AC97U PIB (33 MHz) BCU GIU AIU ADU PIU D/A A/D AC97 Codec VRC4173 The various peripheral units are briefly described below. (1) PCI bridge The PCI bridge controls the PCI bus for the BCU and AC97U units and controls the CLKRUN# signal for controlling the PCI bus clock. (2) PIB bridge The PIB bridge is a bus bridge between the internal local bus having a 32-bit width and the internal local bus having a 16-bit width (PIB: Peripheral Internal Bus). (3) BCU (Bus Control Unit) The BCU controls the PIB to which various units are connected. 26 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW (4) DMAAU (DMA Address Unit) The DMAAU controls the addresses of DMA transfers that are used by the audio interface (MIC, speakers). (5) DCU (DMA Control Unit) The DCU controls the arbitration of DMA transfers that are used by the audio interface (MIC, speakers). (6) CMU (Clock Mask Unit) The CMU controls the supply of PCI clock (PCICLK), PIB bus clock (TClock, internal), and 48 MHz clock pulses to internal peripheral units. TClock is a clock having the same speed and timing as the PCI clock. (7) ICU (Interrupt Control Unit) The ICU controls interrupt requests that are generated due to external and internal sources and reports interrupt requests to the VR4122. Interrupts from the various on-chip macros of the VRC4173 are requested by a single level interrupt signal, and the source is determined according to the ICU register. (8) GIU (General-purpose I/O Unit) The GIU controls the 21 GPIO pins. (9) PIU (Touch Panel Interface Unit) The PIU controls an on-chip A/D converter and detects touches on the touch panel. (10) AIU (Audio Interface Unit) The AIU controls on-chip A/D and D/A converters and controls MIC sampling and audio output. (11) KIU (Keyboard Interface Unit) The KIU, which has 12 scan lines and 8 detection lines, can detect 64, 80, or 96 key inputs. The scan lines are exclusively used relative to the PS2U. When the PS2U is used with 1 channel, the KIU supports 64 or 80 keys. When the PS2U is used with 2 channels, the KIU supports 64 keys. (12) PS2U (PS/2 Unit) The PS2U controls the PS/2 (Personal Computer Standard Keyboard) interface with two channels, PS2CH1 and PS2CH2. The PS2U is exclusively controlled relative to the key scan lines of the KIU. When the PS/2 is used with 1 channel, the KIU supports 64 or 80 keys. When the PS/2 is used with 2 channels, the KIU supports 64 keys. (13) ADU (A/D Converter Unit) The ADU provides an interface with the on-chip A/D converter of the VRC4173. This A/D converter is a serial comparison type. (14) CARDU1, CARDU2 (PC Card Units) The CARDU1 and CARDU2 control the 16-bit PC card interface, which is compliant with the 1997 PC Card Standard. The 32-bit PC card (CardBus card) is not supported. (15) USBU (Universal Serial Bus Unit) The USBU controls the USB interface, which is compliant with Open HCI Specification Release 1.0. (16) AC97U (AC97 Unit) The AC97U controls the AC-Link, which is compliant with AC97 (Audio Codec '97) standard Rev 2.1. User's Manual U14579EJ2V0UM 27 CHAPTER 1 OVERVIEW 1.4 PCI Device Configuration The VRC4173 consists of a total of five PCI devices, which include three multifunction devices having BCU, AC97, and USB functions and two single function devices for PCMCIA channel 1 and channel 2. The following table shows the PCI devices and the corresponding units comprising each one. Table 1-1. PCI Devices and Component Units PCI Device Name Multifunction BCU (Function 0) DMAAU DCU CMU ICU GIU PIU AIU Component Unit Supports two channels for MIC and speaker Supports two channels for MIC and speaker Controls internal clock in low power consumption mode Integrates peripheral unit interrupts Manages 21 general-purpose I/O pins Incorporates A/D converter (12-bit conversion precision) Sampling rate: Maximum 44 ksps 8-bit/16-bit, two channels (D/A converter, A/D converter) Key scanner (12 x 8 line scan) PS/2 control channel 1 PS/2 control channel 2 Compliant with AC97 standard Rev 2.1 USB control PC card control channel 1 PC card control channel 2 KIU PS2CH1 PS2CH2 AC97 (Function 1) USB (Function 2) Single function PCMCIA Ch1 PCMCIA Ch2 AC97U USBU CARDU1 CARDU2 28 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW 1.5 Lists of Registers The following tables list the registers of each unit. Table 1-2. BCU Configuration Registers Register Symbol VID DID PCICMD PCISTS RID CLASSC CACHELS MLT HEDT BIST BADR - SUBVID SUBID - INTL INTP MIN_GNT MAX_LAT BUSCNT IDSELNUM Vendor ID register Device ID register PCI command register PCI device status register Revision ID register Class code register Cache line size register Master latency timer register Header type register Built-in self-test register PIB I/O base address register Reserved Subsystem vendor ID register Subsystem ID register Reserved Interrupt line register Interrupt pin register Burst cycle minimum request time register Bus usage right request frequency register PIB bus control register PC card IDSEL selection register Function Offset Address 0x00 to 0x01 0x02 to 0x03 0x04 to 0x05 0x06 to 0x07 0x08 0x09 to 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x13 0x14 to 0x2B 0x2C to 0x2D 0x2E to 0x2F 0x30 to 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 User's Manual U14579EJ2V0UM 29 CHAPTER 1 OVERVIEW Table 1-3. DMAAU Registers Register Symbol AIUIBALREG AIUIBAHREG AIUIALREG AIUIAHREG AIUOBALREG AIUOBAHREG AIUOALREG AIUOAHREG Function AIU IN DMA base address lower register AIU IN DMA base address higher register AIU IN DMA address lower register AIU IN DMA address higher register AIU OUT DMA base address lower register AIU OUT DMA base address higher register AIU OUT DMA address lower register AIU OUT DMA address higher register Address 0x000 0x002 0x004 0x006 0x008 0x00A 0x00C 0x00E Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. Table 1-4. DCU Registers Register Symbol DMARSTREG DMAIDLEREG DMASENREG DMAMSKREG DMAREQREG DMA reset register DMA sequencer status register DMA sequencer enable register DMA mask register DMA request register Function Address 0x020 0x022 0x024 0x026 0x028 Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. Table 1-5. CMU Registers Register Symbol CMUCLKMSK CMUSRST CMU clock mask register CMU soft reset register Function Address 0x040 0x042 Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. 30 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-6. ICU Registers Register Symbol SYSINT1REG PIUINTREG AIUINTREG KIUINTREG GIULINTREG GIUHINTREG MSYSINT1REG MPIUINTREG MAIUINTREG MKIUINTREG MGIULINTREG MGIUHINTREG Function System interrupt register 1 (level 1) PIU interrupt register (level 2) AIU interrupt register (level 2) KIU interrupt register (level 2) GIUL interrupt register (level 2) GIUH interrupt register (level 2) System interrupt mask register 1 (level 1) PIU interrupt mask register (level 2) AIU interrupt mask register (level 2) KIU interrupt mask register (level 2) GIUL interrupt mask register (level 2) GIUH interrupt mask register (level 2) Address 0x060 0x062 0x064 0x066 0x068 0x06A 0x06C 0x06E 0x070 0x072 0x074 0x076 Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. Table 1-7. GIU Registers Register Symbol GIUDIRL GIUDIRH GIUPIODL GIUPIODH GIUINTSTATL GIUINTSTATH GIUINTENL GIUINTENH GIUINTTYPL GIUINTTYPH GIUINTALSELL GIUINTALSELH GIUINTHTSELL GIUINTHTSELH SELECTREG GPIO I/O select register L GPIO I/O select register H GPIO port I/O data register L GPIO port I/O data register H GPIO interrupt status register L GPIO interrupt status register H GPIO interrupt enable register L GPIO interrupt enable register H Function Address 0x080 0x082 0x084 0x086 0x088 0x08A 0x08C 0x08E 0x090 0x092 0x094 0x096 0x098 0x09A 0x09E GPIO interrupt type (edge or level) select register L GPIO interrupt type (edge or level) select register H GPIO interrupt active level select register L GPIO interrupt active level select register H GPIO interrupt hold/through select register L GPIO interrupt hold/through select register H Alternate function pin select register Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. User's Manual U14579EJ2V0UM 31 CHAPTER 1 OVERVIEW Table 1-8. PIU Registers Register Symbol PIUCNTREG PIUINTREG PIUSIVLREG PIUSTBLREG PIUCMDREG PIUASCNREG PIUAMSKREG PIUCIVLREG PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUAB0REG PIUAB1REG PIUPB04REG PIUPB14REG PIU control register PIU interrupt register PIU data sampling period setting register PIU A/D converter delay time setting register PIU A/D command register PIU A/D port scan register PIU A/D scan mask register PIU delay time count register PIU page 0 buffer 0 register PIU page 0 buffer 1 register PIU page 0 buffer 2 register PIU page 0 buffer 3 register PIU page 1 buffer 0 register PIU page 1 buffer 1 register PIU page 1 buffer 2 register PIU page 1 buffer 3 register PIU A/D scan buffer 0 register PIU A/D scan buffer 1 register PIU page 0 buffer 4 register PIU page 1 buffer 4 register Function Address 0x0A2 0x0A4 0x0A6 0x0A8 0x0AA 0x0B0 0x0B2 0x0BE 0x0C0 0x0C2 0x0C4 0x0C6 0x0C8 0x0CA 0x0CC 0x0CE 0x0D0 0x0D2 0x0DC 0x0DE Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. 32 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-9. AIU Registers Register Symbol MDMADATREG SDMADATREG SODATREG SCNTREG SCNVRREG MIDATREG MCNTREG MCNVRREG DVALIDREG SEQREG INTREG MIC DMA data register Speaker DMA data register Speaker output data register Speaker output control register Speaker conversion rate register MIC input data register MIC input control register MIC conversion rate register Data valid register Sequential register Interrupt register Function Address 0x0E0 0x0E2 0x0E6 0x0E8 0x0EA 0x0F0 0x0F2 0x0F4 0x0F8 0x0FA 0x0FC Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. Table 1-10. KIU Registers Register Symbol KIUDAT0 KIUDAT1 KIUDAT2 KIUDAT3 KIUDAT4 KIUDAT5 KIUSCANREP KIUSCANS KIUWKS KIUWKI KIUINT KIURST SCANLINE KIU data0 register KIU data1 register KIU data2 register KIU data3 register KIU data4 register KIU data5 register KIU scan/repeat register KIU scan status register KIU wait keyscan stable register Function Address 0x100 0x102 0x104 0x106 0x108 0x10A 0x110 0x112 0x114 0x116 0x118 0x11A 0x11E KIU wait keyscan interval register KIU interrupt register KIU reset register KIU scan line register Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. User's Manual U14579EJ2V0UM 33 CHAPTER 1 OVERVIEW Table 1-11. PS2CH1 Registers Register Symbol PS2CH1DATA PS2CH1CTRL PS2CH1RST Function PS/2 channel 1 transmission/reception data register PS/2 channel 1 control register PS/2 channel 1 reset register Address 0x120 0x122 0x124 Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. Table 1-12. PS2CH2 Registers Register Symbol PS2CH2DATA PS2CH2CTRL PS2CH2RST Function PS/2 channel 2 transmission/reception data register PS/2 channel 2 control register PS/2 channel 2 reset register Address 0x140 0x142 0x144 Remark The sum of a value in the Address column added to the base address that is set according to the BADR register of the BCU will be the physical address. 34 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-13. CARDU Configuration Registers (1/2) Register Symbol VID DID PCICMD PCISTS RID CLASSC CACHELS MLT HEDT BIST CSRBADR CAP - SECSTS PCIBNUM CARDNUM SUBBNUM CLT MEMB0 MEML0 MEMB1 MEML1 IOB0 IOL0 IOB1 IOL1 Vendor ID register Device ID register PCI command register PCI device status register Revision ID register Class code register Cache line size register Master latency timer register Header type register Built-in self-test register CardBus socket/ExCA base address register PCI additional specifications code register Reserved Second status register PCI bus number register Card number register Subordinate bus number register CardBus latency timer register Memory base address register 0 Memory space boundary register 0 Memory base address register 1 Memory space boundary register 1 I/O base address register 0 I/O space boundary register 0 I/O base address register 1 I/O space boundary register 1 Function Offset Address 0x00 to 0x01 0x02 to 0x03 0x04 to 0x05 0x06 to 0x07 0x08 0x09 to 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x13 0x14 0x15 0x16 to 0x17 0x18 0x19 0x1A 0x1B 0x1C to 0x1F 0x20 to 0x23 0x24 to 0x27 0x28 to 0x2B 0x2C to 0x2F 0x30 to 0x33 0x34 to 0x37 0x38 to 0x3B User's Manual U14579EJ2V0UM 35 CHAPTER 1 OVERVIEW Table 1-13. CARDU Configuration Registers (2/2) Register Symbol INTL INTP BRGCNT SUBVID SUBID PC16BADR - SYSCNT - DEVCNT - SKDMA0 SKDMA1 CHIPCNT - SERRDIS CAPID NIP PMC PMCSR PMCSR_BSE DATA - TEST - Interrupt line register Interrupt pin register Bridge control register Subsystem vendor ID register Subsystem ID register PC card 16-bit interface legacy mode base address register Reserved System control register Reserved Device control register Reserved Socket DMA register 0 Socket DMA register 1 Chip control register Reserved SERR# signal disable register Capability ID register Power management additional function register Power management characteristic register Power management control/status register PMCSR bridge support extension register Data register Reserved Test register Reserved Function Offset Address 0x3C 0x3D 0x3E to 0x3F 0x40 to 0x41 0x42 to 0x43 0x44 to 0x47 0x48 to 0x7F 0x80 to 0x83 0x84 to 0x90 0x91 0x92 to 0x93 0x94 to 0x97 0x98 to 0x9B 0x9C 0x9D to 0x9E 0x9F 0xA0 0xA1 0xA2 to 0xA3 0xA4 to 0xA5 0xA6 0xA7 0xA8 to 0xFB 0xFC 0xFD to 0xFFH 36 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-14. ExCA Registers (1/2) Register Symbol Function Offset Address PCI Memory ID_REV IF_STATUS PWR_CNT INT_GEN_CNT CARD_SC CARD_SCI ADR_WIN_EN IO_WIN_CNT IO_WIN0_SAL IO_WIN0_SAH IO_WIN0_EAL IO_WIN0_EAH IO_WIN1_SAL IO_WIN1_SAH IO_WIN1_EAL IO_WIN1_EAH MEM_WIN0_SAL MEM_WIN0_SAH MEM_WIN0_EAL MEM_WIN0_EAH MEM_WIN0_OAL MEM_WIN0_OAH GEN_CNT - MEM_WIN1_SAL MEM_WIN1_SAH MEM_WIN1_EAL MEM_WIN1_EAH MEM_WIN1_OAL ID/revision register Interface status register Power control register Interrupt/general-purpose control register Card status change register Card status change interrupt configuration register Address window enable register I/O window control register I/O window 0 start address lower byte register I/O window 0 start address higher byte register I/O window 0 end address lower byte register I/O window 0 end address higher byte register I/O window 1 start address lower byte register I/O window 1 start address higher byte register I/O window 1 end address lower byte register I/O window 1 end address higher byte register Memory window 0 start address lower byte register Memory window 0 start address higher byte register Memory window 0 end address lower byte register Memory window 0 end address higher byte register Memory window 0 offset address lower byte register Memory window 0 offset address higher byte register General control register Reserved Memory window 1 start address lower byte register Memory window 1 start address higher byte register Memory window 1 end address lower byte register Memory window 1 end address higher byte register Memory window 1 offset address lower byte register 0x800 0x801 0x802 0x803 0x804 0x805 0x806 0x807 0x808 0x809 0x80A 0x80B 0x80C 0x80D 0x80E 0x80F 0x810 0x811 0x812 0x813 0x814 0x815 0x816 0x817 0x818 0x819 0x81A 0x81B 0x81C ExCA 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C User's Manual U14579EJ2V0UM 37 CHAPTER 1 OVERVIEW Table 1-14. ExCA Registers (2/2) Register Symbol Function Offset Address PCI Memory MEM_WIN1_OAH GLO_CNT - MEM_WIN2_SAL MEM_WIN2_SAH MEM_WIN2_EAL MEM_WIN2_EAH MEM_WIN2_OAL MEM_WIN2_OAH - MEM_WIN3_SAL MEM_WIN3_SAH MEM_WIN3_EAL MEM_WIN3_EAH MEM_WIN3_OAL MEM_WIN3_OAH EXT_INDX EXT_DATA MEM_WIN4_SAL MEM_WIN4_SAH MEM_WIN4_EAL MEM_WIN4_EAH MEM_WIN4_OAL MEM_WIN4_OAH IO_WIN0_OAL IO_WIN0_OAH IO_WIN1_OAL IO_WIN1_OAH - Memory window 1 offset address higher byte register Global control register Reserved Memory window 2 start address lower byte register Memory window 2 start address higher byte register Memory window 2 end address lower byte register Memory window 2 end address higher byte register Memory window 2 offset address lower byte register Memory window 2 offset address higher byte register Reserved Memory window 3 start address lower byte register Memory window 3 start address higher byte register Memory window 3 end address lower byte register Memory window 3 end address higher byte register Memory window 3 offset address lower byte register Memory window 3 offset address higher byte register Extended index register Extended data register Memory window 4 start address lower byte register Memory window 4 start address higher byte register Memory window 4 end address lower byte register Memory window 4 end address higher byte register Memory window 4 offset address lower byte register Memory window 4 offset address higher byte register I/O window 0 offset address lower byte register I/O window 0 offset address higher byte register I/O window 1 offset address lower byte register I/O window 1 offset address higher byte register Reserved 0x81D 0x81E 0x81F 0x820 0x821 0x822 0x823 0x824 0x825 0x826 to 0x827 0x828 0x829 0x82A 0x82B 0x82C 0x82D - - 0x830 0x831 0x832 0x833 0x834 0x835 0x836 0x837 0x838 0x839 0x83A to 0x83F ExCA 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 to 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A to 0x3F 38 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-15. ExCA Extended Registers Register Symbol Function Offset Address PCI Memory MEM_WIN0_SAU MEM_WIN1_SAU MEM_WIN2_SAU MEM_WIN3_SAU MEM_WIN4_SAU IO_SETUP_TIM IO_CMD_TIM IO_HOLD_TIM - MEM0_SETUP_TIM MEM0_CMD_TIM MEM0_HOLD_TIM - MEM1_SETUP_TIM MEM1_CMD_TIM MEM1_HOLD_TIM - MEM_TIM_SEL1 MEM_TIM_SEL2 - MEM_WIN_PWEN Memory window 0 start address higher byte register Memory window 1 start address higher byte register Memory window 2 start address higher byte register Memory window 3 start address higher byte register Memory window 4 start address higher byte register I/O setup timing register I/O command timing register I/O hold timing register Reserved Memory setup timing 0 register Memory command timing 0 register Memory hold timing 0 register Reserved Memory setup timing 1 register Memory command timing 1 register Memory hold timing 1 register Reserved Memory timing selection 1 register Memory timing selection 2 register Reserved Memory window post write enable register 0x840 0x841 0x842 0x843 0x844 0x880 0x881 0x882 0x883 0x884 0x885 0x886 0x887 0x888 0x889 0x88A 0x88B 0x88C 0x88D 0x88E to 0x890 0x891 ExCA Extension 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 to 0x15 0x16 Table 1-16. CardBus Socket Registers Register Symbol SKT_EV SKT_MASK SKT_PRE_STATE SKT_FORCE_EV SKT_CNT - Socket event register Socket mask register Socket present state register Socket force event register Socket control register Reserved Function Offset Address 0x000 0x004 0x008 0x00C 0x010 0x014 to 0x7FF User's Manual U14579EJ2V0UM 39 CHAPTER 1 OVERVIEW Table 1-17. USB Host Control Configuration Registers Name Vendor ID register Device ID register Command register Status register Revision ID register Class code base address register Class code sub class register Class code programming interface register Cache line size register Latency timer register Header type register Built-in self-test register Base address register Subsystem vendor ID register Subsystem ID register Interrupt line register Interrupt pin register Min_Gnt register (burst cycle minimum request time register) Max_lat register (bus usage right request frequency register) Power management register 0x0C 0x0D 0x0E 0x0F 0x10 0x2C 0x2E 0x3C 0x3D 0x3E 0x3F 0xE0 Offset Address 0x00 0x02 0x04 0x06 0x08 0x09 40 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-18. Host Control Operational Registers Register Symbol HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 HC revision register HC control register HC command register HC interrupt request detection register HC interrupt request enable register HC interrupt request disable register HC base address register HC period current ED register HC control list 1st ED register HC control list current ED register HC bulk list 1st ED register HC bulk list current ED register HC last TD register HC frame interval register HC frame bit time remaining register HC frame counter register HC list processing start register HC low speed transfer diagnosis register HC power supply status register A HC power supply status register B HC status register HC port status register 1 HC port status register 2 Function Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 User's Manual U14579EJ2V0UM 41 CHAPTER 1 OVERVIEW Table 1-19. AC97U PCI Configuration Registers Register Symbol VID DID PCICMD PCISTS RID CLASSC CACHELS MLT HEDT BIST BASEADR - SVID SUBID EXROMADR - INTL INTP MIN_GNT MAX_LAT - Vendor ID register Device ID register PCI command register PCI device status register Revision ID register Class code register Cache line size register Master latency timer register Header type register Built-in self-test register Base address register Reserved Subsystem vendor ID register Subsystem ID register Extended ROM base address register Reserved Interrupt line register Interrupt pin register Burst cycle minimum request time register Bus usage right request frequency register Reserved Function Offset Address 0x00 to 0x01 0x02 to 0x03 0x04 to 0x05 0x06 to 0x07 0x08 0x09 to 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x13 0x14 to 0x2B 0x2C to 0x2D 0x2E to 0x2F 0x30 to 0x33 0x34 to 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 to 0xFF 42 User's Manual U14579EJ2V0UM CHAPTER 1 OVERVIEW Table 1-20. AC97U Operational Registers Register Symbol INT_CLR/INT_STATUS CODEC_WR CODEC_RD CODEC_REQ SLOT12_WR SLOT12_RD CTRL ACLINK_CTRL SRC_RAM_DATA INT_MASK - DAC1_CTRL DAC1L DAC1_BADDR DAC2_CTRL DAC2L DAC2_BADDR DAC3_CTRL DAC3L DAC3_BADDR ADC1_CTRL ADC1L ADC1_BADDR ADC2_CTRL ADC2L ADC2_BADDR ADC3_CTRL ADC3L ADC3_BADDR Interrupt clear/status register Codec write register Codec read register Codec slot request register Slot 12 write register Slot 12 read register Codec/SRC control register AC-Link control register Sample rate converter RAM data register Interrupt mask register Reserved DAC1 DMA control register DAC1 DMA length register DAC1 DMA base address register DAC2 DMA control register DAC2 DMA length register DAC2 DMA base address register DAC3 DMA control register DAC3 DMA length register DAC3 DMA base address register ADC1 DMA control register ADC1 DMA length register ADC1 DMA base address register ADC2 DMA control register ADC2 DMA length register ADC2 DMA base address register ADC3 DMA control register ADC3 DMA length register ADC3 DMA base address register Function Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 to 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 User's Manual U14579EJ2V0UM 43 CHAPTER 2 PIN FUNCTIONS This chapter describes the pin functions of the VRC4173. 2.1 Pin Configuration * 304-pin plastic FBGA (19 x 19) PD31173F1-33-HN1 Bottom View Top View 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABAA Y W V U T R P N M L K J H G F E D C B A A B C D E F G H J K L M N P R T U V W Y AAAB Index mark 44 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS Pin No. A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 VDD2 TEST2 TEST0 Pin Name Pin No. B20 B21 B22 C1 C2 C21 C22 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D21 D22 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 CD22# BVD22# VDD2 Pin Name Pin No. E14 E15 E16 E17 E18 E19 E21 E22 F1 F2 F4 F5 F6 F7 F8 F9 F10 F13 F14 F15 F16 F17 F18 F19 F21 F22 G1 G2 G4 G5 G6 G17 G18 G19 G21 G22 H1 H2 H4 Pin Name KSCAN2/GPIO2 VDD3 KPORT3/GPIO11 GND2 GND2 GND2 IOWR2# IORD2# CE11# CE12# OE1# GND2 C1A0 ADX DAAVDD TPY1/GPIO19 TPX0/GPIO16 KSCAN7/GPIO7 VDD2 KSCAN0/GPIO0 GND2 KPORT4/GPIO12 GND2 VS22# VS21# WP2 WE1# WP1 IORD1# IOWR1# GND2 WE2# OE2# CE22# CE21# C2D15 C1A1 VDD3 C1A2 ADAGND ADY ADDVDD TESTC TPX1/GPIO17 VDD3 SYNC KSCAN8/PS2CLK2 KSCAN3/GPIO3 GND3 KPORT5/GPIO13 KPORT0/GPIO8 OCI2 READY2 WAIT2# CD21# GND2 GND2 PWCDATA TEST3 TEST1 ADDGND ADIN ADAVREFP DAAGND GND2 ACLINKRST# BCLK KSCAN9/PS2DATA2 KSCAN4/GPIO4 KSCAN1/GPIO1 KPORT6/GPIO14 KPORT1/GPIO9 PPON1 OCI1 INPACK2# PWCCLK PWCLATCH RCVBE BVD21# VS11# VS12# GND2 GND2 AUDIOIN ADAVREFM AUDIOOUT TPY0/GPIO18 GND3 SDATAOUT KSCAN10/PS2CLK1 KSCAN5/GPIO5 GND2 KPORT7/GPIO15 KPORT2/GPIO10 PPON2 GND2 GND2 RESET2 REG2# RESET1 REG1# GND2 GND2 GND2 ADAVDD DAAVREF VDD2 TPEN/GPIO20 SDATAIN KSCAN11/PS2DATA1 KSCAN6/GPIO6 Remark # indicates active low. User's Manual U14579EJ2V0UM 45 CHAPTER 2 PIN FUNCTIONS Pin No. H5 H6 H17 H18 H19 H21 H22 J1 J2 J4 J5 J6 J17 J18 J19 J21 J22 K1 K2 K4 K5 K6 K17 K18 K19 K21 K22 L1 L2 L4 L5 L18 L19 L21 L22 M1 M2 M4 M5 GND3 C1A3 C2D14 C2D13 C2D12 C2D11 GND3 GND2 C1A4 VDD2 C1A5 C1A6 C2D10 VDD3 C2D9 VDD2 C2D8 C1A7 C1A8 C1A9 C1A10 C1A11 GND2 DN2 DP2 DN1 DP1 C1A12 C1A13 C1A14 C1A15 C2D7 C2D6 C2D5 C2D4 C1A17 C1A18 C1A19 C1A20 Pin Name Pin No. M18 M19 M21 M22 N1 N2 N4 N5 N6 N17 N18 N19 N21 N22 P1 P2 P4 P5 P6 P17 P18 P19 P21 P22 R1 R2 R4 R5 R6 R17 R18 R19 R21 R22 T1 T2 T4 T5 T6 C2D3 C2D2 C2D1 C2D0 C1A21 C1A22 C1A23 C1A24 GND2 C2A25 C2A24 C2A23 C2A22 C2A21 C1A16 VDD2 C1A25 VDD3 C1D0 VDD2 C2A16 GND2 C2A20 GND3 GND3 C1D1 C1D2 C1D3 C1D4 C2A19 VDD3 C2A18 C2A17 C2A15 C1D5 C1D6 C1D7 C1D8 C1D9 Pin Name Pin No. T17 T18 T19 T21 T22 U1 U2 U4 U5 U6 U7 U8 U9 U10 U13 U14 U15 U16 U17 U18 U19 U21 U22 V1 V2 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 GND2 C2A13 C2A12 C2A11 C2A10 C1D10 C1D11 C1D12 GND2 AD23 GND2 AD18 GND2 AD12 AD0 CBE2# VRCINT PAR C2A14 GND2 C2A9 C2A8 C2A7 C1D13 C1D14 GND2 GND2 GND2 AD24 AD19 AD16 AD13 AD9 AD5 AD1 VDD2 CBE0# FRAME# GND2 Pin Name Remark # indicates active low. User's Manual U14579EJ2V0UM 46 CHAPTER 2 PIN FUNCTIONS Pin No. V18 V19 V21 V22 W1 W2 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W21 W22 GND2 GND2 C2A6 C2A5 C1D15 BVD11# GND2 GND2 AD28 AD25 AD20 GND3 AD14 AD10 AD6 AD2 CBE3# GND3 Pin Name Pin No. Y1 Y2 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 BVD12# Pin Name Pin No. AA21 AA22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 C2A0 VDD2 VDD2 READY1 CD11# PCLK AD30 AD27 AD22 VDD3 AD15 AD11 AD8 AD4 Pin Name INPACK1# C2A2 C2A1 GND2 WAIT1# SCLK CD12# AD31 AD29 AD26 AD21 AD17 VDD2 IDSEL AD7 AD3 GND2 CBE1# TRDY# STOP# GNT# CLK48M CLK48MX2 PCIRST# VDD3 IRDY# PERR# REQ# SERR# CLK48MX1 GND2 DEVSEL# CLKRUN# GND2 GND2 C2A4 C2A3 Remark # indicates active low. User's Manual U14579EJ2V0UM 47 CHAPTER 2 PIN FUNCTIONS Pin Identification ACLINKRST#: AD(31:0): ADAGND: ADAVDD: ADAVREFM: ADAVREFP: ADDGND: ADDVDD: ADIN: ADX: ADY: AUDIOIN: AUDIOOUT: BCLK: BVD11#, BVD12#, BVD21#, BVD22#: C1A(25:0): C1D(15:0): C2A(25:0): C2D(15:0): CBE(3:0)#: CD11#, CD12#, CD21#, CD22#: CE11#, CE12#, CE21#, CE22#: CLK48M : Card Enable 48 MHz Clock Output 48 MHz Crystal Clock Input CLKRUN#: DAAGND: DAAVDD: Clock Run Analog Ground for D/A Converter Analog VDD for D/A Converter Card Detect PWCCLK: PWCDATA: PWCLATCH: RCVBE: READY1, READY2: REG1#, REG2#: REQ#: RESET1, RESET2: SCLK: SDATAIN: SDATAOUT: Remark # indicates active low. Battery Voltage Detect Card Slot 1 Address Card Slot 1 Data Card Slot 2 Address Card Slot 2 Data Chipset Byte Enable AC-Link Reset Address/Data Bus A/D Converter Analog Ground A/D Converter Analog VDD Analog Reference Minus Voltage for A/D Converter Analog Reference Plus Voltage for A/D Converter Digital Ground for A/D Converter Digital VDD for A/D Converter A/D Converter General Input A/D Converter Input for X Axis Port A/D Converter Input for Y Axis Port Audio Input Audio Output Bit Clock IORD1#, IORD2#: IOWR1#, IOWR2#: IRDY#: KPORT(7:0): KSCAN(11:0): OCI1, OCI2: OE1#, OE2#: PAR: PCIRST#: PCLK: PERR#: PPON1, PPON2: DEVSEL#: DN1, DN2: DP1, DP2: FRAME#: GND2: GND3: GNT#: GPIO(20:0): IDSEL: DAAVREF: Analog Reference Voltage for D/A Converter Device Select Data Negative Data Positive Frame Ground for I/O Buffer Ground for Internal Circuit Grant General Purpose Input/Output Identifier Select Input Acknowledge I/O Read I/O Write Initiator Ready Key Port Key Scan Over Current Indicator Output Enable Parity PCI Reset PCI Clock Parity Error Port Power On INPACK1#, INPACK2#: PS2CLK1, PS2CLK2: PS/2 Clock PS2DATA1, PS2DATA2: PS/2 Data Power Control Clock Power Control Data Power Control Latch Receiver Buffer Enable Ready Attribute Memory Select Request Reset Suspend Less Clock Serial Data Input Serial Data Output CLK48MX1, CLK48MX2: 48 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS SERR#: STOP#: SYNC: TEST(3:0): TESTC: TPEN: TPX(1:0): TPY(1:0): System Error Stop Synchronization Test Test Clock Touch Panel Interface Enable Touch Panel Interface X Axis Port Touch Panel Interface Y Axis Port TRDY#: VDD2: VDD3: VRCINT: VS11#, VS12#, VS21#, VS22#: WAIT1#, WAIT2#: WE1#, WE2#: WP1, WP2: Target Ready Power Supply for I/O Buffer Power Supply Internal Circuit VR Series Companion Chip Interrupt Voltage Sense Wait Write Enable Write Protect Remark # indicates active low. User's Manual U14579EJ2V0UM 49 CHAPTER 2 PIN FUNCTIONS 2.2 2.2.1 Pin Function Lists PCI bus interface signals Table 2-1. PCI Bus Interface Signals Signal Name I/O I/O I/O I I/O I/O I/O I/O I/O O I I I/O I/O I/O O Function This is a 32-bit bus that multiplexes the address bus and data bus. This is a signal that multiplexes the bus command and byte enable signals. This is an initialization device selection signal (for a PCI multifunction device). This is a cycle frame signal. This is a device selection signal. This is an initiator ready signal. This is a target ready signal. This is a stop signal. This is a PCI bus request signal. This is a PCI bus request acknowledge signal. This is a PCI reset signal. This is a PCI clock run signal. This is an even parity signal. This signal becomes active when a parity error occurs. This signal becomes active when a system error occurs. AD(31:0) CBE(3:0)# IDSEL FRAME# DEVSEL# IRDY# TRDY# STOP# REQ# GNT# PCIRST# CLKRUN# PAR PERR# SERR# 2.2.2 USB interface signals Table 2-2. USB Interface Signals Signal Name I/O I I/O I/O O I Function Set these signals to active when an over current is detected. These are USB serial data positive signals. These are USB serial data negative signals. These are USB root hub port power supply control signals. This is a buffer enable signal. Set this to active to make the input signal to the USB port valid. OCI1, OCI2 DP1, DP2 DN1, DN2 PPON1, PPON2 RCVBE 2.2.3 AC-Link interface signals Table 2-3. AC-Link Interface Signals Signal Name I/O I I O O O Function This is the serial data signal from the AC97 Codec. This is the bit clock (28 MHz) signal from the AC97 Codec. This is the serial data signal to the AC97 Codec. This is the SYNC output signal to the AC97 Codec. This is the AC97 Codec reset signal. SDATAIN BCLK SDATAOUT SYNC ACLINKRST# 50 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS 2.2.4 PC card interface signals Table 2-4. PC Card Interface Signals Signal Name I/O I/O I/O I/O I I/O O I I/O I/O I/O I/O O I I I/O I I/O I/O I/O I I/O O I I/O I/O I/O I/O O I I I/O I O O O This is the PC card slot 1 address bus. This is the PC card slot 1 data bus. This is the PC card slot 1 chip select signal. This is the PC card slot 1 card detect signal. This is the PC card slot 1 output enable signal. This is the PC card slot 1 write enable signal. This is the PC card slot 1 ready signal. This is the PC card slot 1 write protect signal. This is the PC card slot 1 card power supply identification signal. This is the PC card slot 1 I/O read signal. This is the PC card slot 1 I/O write signal. This is the PC card slot 1 reset signal. This is the PC card slot 1 wait signal. This is the PC card slot 1 input acknowledge signal. This is the PC card slot 1 memory chip select signal. This is the PC card slot 1 battery voltage detect signal. This is the PC card slot 2 address bus. This is the PC card slot 2 data bus. This is the PC card slot 2 chip select signal. This is the PC card slot 2 card detect signal. This is the PC card slot 2 output enable signal. This is the PC card slot 2 write enable signal. This is the PC card slot 2 ready signal. This is the PC card slot 2 write protect signal. This is the PC card slot 2 card power supply identification signal. This is the PC card slot 2 I/O read signal. This is the PC card slot 2 I/O write signal. This is the PC card slot 2 reset signal. This is the PC card slot 2 wait signal. This is the PC card slot 2 input acknowledge signal. This is the PC card slot 2 memory chip select signal. This is the PC card slot 2 battery voltage detect signal. This is the serial data signal to the power supply control IC (TPS2202A compatible). This is the clock signal to the power supply control IC (TPS2202A compatible). This is the data latch signal to the power supply control IC (TPS2202A compatible). Function C1A(25:0) C1D(15:0) CE1(2:1)# CD1(2:1)# OE1# WE1# READY1 WP1 VS1(2:1)# IORD1# IOWR1# RESET1 WAIT1# INPACK1# REG1# BVD1(2:1)# C2A(25:0) C2D(15:0) CE2(2:1)# CD2(2:1)# OE2# WE2# READY2 WP2 VS2(2:1)# IORD2# IOWR2# RESET2 WAIT2# INPACK2# REG2# BVD2(2:1)# PWCDATA PWCCLK PWCLATCH User's Manual U14579EJ2V0UM 51 CHAPTER 2 PIN FUNCTIONS Table 2-5. Correspondence of Signal Names for Each PC Card Interface Mode (1/2) VRC4173 Slot 1 C1A25 C1A24 C1A23 C1A22 C1A21 C1A20 C1A19 C1A18 C1A17 C1A16 C1A15 C1A14 C1A13 C1A12 C1A11 C1A10 C1A9 C1A8 C1A7 C1A6 C1A5 C1A4 C1A3 C1A2 C1A1 C1A0 C1D15 C1D14 C1D13 C1D12 C1D11 C1D10 C1D9 C1D8 C1D7 C1D6 C2A25 C2A24 C2A23 C2A22 C2A21 C2A20 C2A19 C2A18 C2A17 C2A16 C2A15 C2A14 C2A13 C2A12 C2A11 C2A10 C2A9 C2A8 C2A7 C2A6 C2A5 C2A4 C2A3 C2A2 C2A1 C2A0 C2D15 C2D14 C2D13 C2D12 C2D11 C2D10 C2D9 C2D8 C2D7 C2D6 Slot 2 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 16-Bit PC Card Memory Card A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 I/O Card 52 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS Table 2-5. Correspondence of Signal Names for Each PC Card Interface Mode (2/2) VRC4173 Slot 1 C1D5 C1D4 C1D3 C1D2 C1D1 C1D0 CE12# CE11# OE1# WE1# IORD1# IOWR1# WAIT1# REG1# INPACK1# WP1 BVD11# BVD12# READY1 CD12# CD11# VS12# VS11# RESET1 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CE22# CE21# OE2# WE2# IORD2# IOWR2# WAIT2# REG2# INPACK2# WP2 BVD21# BVD22# READY2 CD22# CD21# VS22# VS21# RESET2 Slot 2 D5 D4 D3 D2 D1 D0 CE2# CE1# OE# WE# - - WAIT# REG# - WP BVD1 BVD2 READY CD2# CD1# VS2# VS1# RESET 16-Bit PC Card Memory Card D5 D4 D3 D2 D1 D0 CE2# CE1# OE# WE# IORD0# IOWR0# WAIT# REG# INPACK# IOIS16# STSCHG# SPKR# IREQ# CD2# CD1# VS2# VS1# RESET I/O Card User's Manual U14579EJ2V0UM 53 CHAPTER 2 PIN FUNCTIONS 2.2.5 Keyboard interface signals Table 2-6. Keyboard Interface Signals Signal Name I/O I/O Function These are keyboard scan data input signals. They are used to scan for pressed keys on the keyboard. When these are used as KPORT signals, external pull-down resistors are required. When these are not used as KPORT signals, they can be used as general-purpose I/O ports. These are keyboard scan data output signals. The scan line is set to active when scanning for pressed keys on the keyboard. When these are not used as KSCAN signals, they can be used as general-purpose I/O ports. This is a keyboard scan data output signal. The scan line is set to active when scanning for pressed keys on the keyboard. When this is not used as a KSCAN signal, it can be used as a PS2CLK2 signal. This is a keyboard scan data output signal. The scan line is set to active when scanning for pressed keys on the keyboard. When this is not used as a KSCAN signal, it can be used as a PS2DATA2 signal. This is a keyboard scan data output signal. The scan line is set to active when scanning for pressed keys on the keyboard. When this is not used as a KSCAN signal, it can be used as a PS2CLK1 signal. This is a keyboard scan data output signal. The scan line is set to active when scanning for pressed keys on the keyboard. When this is not used as a KSCAN signal, it can be used as a PS2DATA1 signal. KPORT(7:0)/GPIO(15:8) KSCAN(7:0)/GPIO(7:0) I/O KSCAN8/PS2CLK2 I/O KSCAN9/PS2DATA2 I/O KSCAN10/PS2CLK1 I/O KSCAN11/PS2DATA1 I/O 2.2.6 PS/2 interface signals Table 2-7. PS/2 Interface Signals Signal Name I/O I/O Function This is a PS/2 port 1 clock signal. When this is not used as a PS2CLK1 signal, it can be used as a KSCAN10 signal. This is a PS/2 port 2 clock signal. When this is not used as a PS2CLK2 signal, it can be used as a KSCAN8 signal. This is a PS/2 port 1 serial data signal. When this is not used as a PS2DATA1 signal, it can be used as a KSCAN11 signal. This is a PS/2 port 2 serial data signal. When this is not used as a PS2DATA2 signal, it can be used as a KSCAN9 signal. PS2CLK1/KSCAN10 PS2CLK2/KSCAN8 I/O PS2DATA1/KSCAN11 I/O PS2DATA2/KSCAN9 I/O 54 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS 2.2.7 Touch panel interface signals Table 2-8. Touch Panel Interface Signals Signal Name I/O I/O Function These are touch panel I/O signals. The coordinates at which the touch panel was pressed are detected by applying voltage to the X coordinate and inputting the voltage of the Y coordinate. The TPX1 signal should be connected to the ADX signal externally. When these are not used as TPX signals, they can be used as general-purpose I/O ports. These are touch panel I/O signals. The coordinates at which the touch panel was pressed are detected by applying voltage to the Y coordinate and inputting the voltage of the X coordinate. The TPY1 signal should be connected to the ADY signal externally. The TYP1 signal is also used as a touch panel touch status interrupt request input to the PIU (see 9.3.2 PIUINTREG (base address + 0x0A4)). When these are not used as TPY signals, they can be used as general-purpose I/O ports. This is the touch panel pull-down resistor enable signal. When this is not used as a TPEN signal, it can be used as a general-purpose I/O port. This is an analog input signal. It should be connected to the TPX1 signal externally when the touch panel is used. This is an analog input signal. It should be connected to the TPY1 signal externally when the touch panel is used. This is a general-purpose analog input signal. This is an audio analog input signal. TPX(1:0)/GPIO(17:16) TPY(1:0)/GPIO(19:18) I/O TPEN/GPIO20 I/O ADX I ADY I ADIN AUDIOIN I I 2.2.8 Audio interface signal Table 2-9. Audio Interface Signal Signal Name I/O O This is an audio analog output signal. Function AUDIOOUT 2.2.9 General-purpose I/O signals Table 2-10. General-Purpose I/O Signals Signal Name I/O I/O I/O I/O I/O I/O Function These are general-purpose I/O signals. See 2.2.5 Keyboard interface signals. These are general-purpose I/O signals. See 2.2.5 Keyboard interface signals. These are general-purpose I/O signals. See 2.2.7 Touch panel interface signals. These are general-purpose I/O signals. See 2.2.7 Touch panel interface signals. This is a general-purpose I/O signal. See 2.2.7 Touch panel interface signals. GPIO(7:0)/KSCAN(7:0) GPIO(15:8)/KPORT(7:0) GPIO(17:16)/TPX(1:0) GPIO(19:18)/TPY(1:0) GPIO20/TPEN User's Manual U14579EJ2V0UM 55 CHAPTER 2 PIN FUNCTIONS 2.2.10 Interrupt interface signal Table 2-11. Interrupt Interface Signal Signal Name VRCINT I/O O Function This is an integrated interrupt request signal to the CPU. 2.2.11 Clock interface signals Table 2-12. Clock Interface Signals Signal Name PCLK SCLK CLK48MX1Note CLK48MX2 CLK48M Note I/O I I I O O Function This is the 33 MHz clock input signal. It is used internally as the PCI clock (PCICLK). This is the 9.216 MHz clock input signal. This is the 48 MHz oscillator's USB clock input signal. This is the 48 MHz oscillator's USB clock output signal. This is the 48 MHz clock output signal. Note For information about how to connect the clock oscillator to CLK48MX1 and CLK48MX2, see 2.4 Clock Oscillator Connection. 2.2.12 Test interface signals Table 2-13. Test Interface Signals Signal Name TESTC TEST(3:0) I/O I I Function These are LSI evaluation test signals. Set TESTC to 0 and TEST(3:0) to 1000. Table 2-14 lists the test modes. Table 2-14. Test Modes TESTC Signal 0 Other than above TEST(3:0) Signals 1000 Normal operation mode LSI evaluation mode Test Mode Caution Normal operation mode is set when TESTC = 0, TEST(3:0) = 1000. The LSI evaluation mode is set for all other settings. Operations are not guaranteed in the LSI evaluation mode. 56 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS 2.2.13 Power supplies and grounds Table 2-15. A/D Converter Power Supplies and Grounds Signal Name ADAVDD ADAGND ADDVDD ADDGND ADAVREFP ADAVREFM Function This signal is for the dedicated analog power supply for the A/D converter. This signal is for the dedicated analog ground for the A/D converter. This signal is for the dedicated digital power supply for the A/D converter. This signal is for the dedicated digital ground for the A/D converter. This signal is for the A/D converter's positive pole reference voltage (connected to the ADAVDD pin). This signal is for the A/D converter's negative pole reference voltage (connected to the ADAGND pin). Table 2-16. D/A Converter Power Supply and Ground Signal Name DAAVDD DAAGND DAAVREF Function This signal is for the dedicated analog power supply for the D/A converter. This signal is for the dedicated analog ground for the D/A converter. This signal is for the D/A converter's reference voltage (connected to the DAAVDD pin). Table 2-17. Digital Power Supplies and Grounds Signal Name VDD2 GND2 VDD3 GND3 Function This signal is for the internal digital power supply. This signal is for the internal digital ground. This signal is for the I/O buffer's digital power supply. This signal is for the I/O buffer's digital ground. User's Manual U14579EJ2V0UM 57 CHAPTER 2 PIN FUNCTIONS 2.3 Pin Status and Recommended Connection Examples Table 2-18 shows the status of the pins when the VRC4173 is reset (when the PCIRST# signal is at low level) and examples of recommended, logically required pin processing. Table 2-18. Pin Status and Recommended Connection Examples (1/4) Pin Name I/O Drive Capacity (mA) 12 12 12 12 12 12 12 12 12 12 18 - 6 - - - - - 3 - 6 - 6 - 6 Withstand Voltage (V) 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 5 5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 Internal Processing - - - - - - - - - - - - Open drain - - - - - - - - - - - - External Processing - - Pull-up Pull-up Pull-up Pull-up Pull-up - Pull-up Pull-up - - Pull-up - - - - Note - Note - Note - Note - Status After Reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z - - Hi-Z Hi-Z - Hi-Z - 0 - 0 - 0 PCI interface AD(31:0) CBE(3:0)# FRAME# IRDY# TRDY# STOP# DEVSEL# PAR PERR# CLKRUN# REQ# GNT# SERR# IDSEL PCIRST# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I O I I I/O I/O I O I O I O I O USBU DP1, DP2 DN1, DN2 OCI1, OCI2 PPON1, PPON2 RCVBE AC97U SYNC BCLK SDATAOUT SDATAIN ACLINKRST# Note This should be fixed at low level when the relevant unit is unused. Remark 0: Low level, Hi-Z: High impedance 58 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS Table 2-18. Pin Status and Recommended Connection Examples (2/4) Pin Name I/O Drive Capacity (mA) 3 3 3 9 3 3 3 3 3 3 3 3 3 3 3 3 3 3 - - - - - - - Withstand Voltage (V) 5 5 5 3.3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Internal ProcessingNote 1 - Pull-up - - Pull-up - - - - - - Pull-up Pull-up Pull-up - - - - - - - - - Pull-up/ pull-down - External Processing - - - - - - - - - - - - - - - - - - Pull-up Pull-up Pull-upNote 3 Pull-up Pull-up - Pull-upNote 3 Note 3 Status After Reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 Hi-Z Hi-Z Hi-Z 0Note 2 - - - - - - - CARDU1 C1A(25:23) C1A(22:20) C1A(19:17) C1A16 C1A(15:14) C1A(13:0) C1D(15:0) CE11# CE12# OE1# WE1# WP1 VS11# VS12# IORD1# IOWR1# REG1# RESET1 CD11# CD12# WAIT1# INPACK1# READY1 BVD11# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O O I I I I I I Note 3 BVD12# I 5 Notes 1. The switching of the pull-up/pull-down resistors and their on/off status are automatically switched by the internal sequencer. 2. Card resetting is controlled by writing to registers. 3. Set a pull-up resistor for the external PC card power supply. Remark 0: Low level, Hi-Z: High impedance User's Manual U14579EJ2V0UM 59 CHAPTER 2 PIN FUNCTIONS Table 2-18. Pin Status and Recommended Connection Examples (3/4) Pin Name I/O Drive Capacity (mA) 3 3 3 9 3 3 3 3 3 3 3 3 3 3 3 3 3 3 - - - - - - - 3 3 3 Withstand Voltage (V) 5 5 5 3.3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Internal ProcessingNote 1 - Pull-up - - Pull-up - - - - - - Pull-up Pull-up Pull-up - - - - - - - - - Pull-up/ pull-down - - - - External Processing - - - - - - - - - - - - - - - - - - Pull-up Pull-up Pull-upNote 3 Pull-up Pull-up - Pull-upNote 3 - - - Note 3 Status After Reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 0 Hi-Z Hi-Z Hi-Z 0Note 2 - - - - - - - 0 0 0 CARDU2 C2A(15:23) C2A(22:20) C2A(19:17) C2A16 C2A(15:14) C2A(13:0) C2D(15:0) CE21# CE22# OE2# WE2# WP2 VS21# VS22# IORD2# IOWR2# REG2# RESET2 CD21# CD22# WAIT2# INPACK2# READY2 BVD21# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O O I I I I I I Note 3 BVD22# Common to CARDU1 and CARDU2 PWCDATA PWCCLK PWCLATCH I O O O 5 5 5 5 Notes 1. The switching of the pull-up/pull-down resistors and their on/off status are automatically switched by the internal sequencer. 2. Card resetting is controlled by writing to registers. 3. Set a pull-up resistor for the external PC card power supply. Remark 0: Low level, Hi-Z: High impedance 60 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS Table 2-18. Pin Status and Recommended Connection Examples (4/4) Pin Name I/O Drive Capacity (mA) 3 Withstand Voltage (V) 3.3 Internal Processing - - - - - - Slew rate buffer Slew rate buffer - - - - - - - - - - - - - - External Processing Pull-upNote 1 -Note 2 - - Note 2 Status After Reset Hi-Z KIU/PS2U KPORT(7:0)/ GPIO(15:8) KSCAN11/PS2DATA1 KSCAN10/PS2CLK1 KSCAN9/PS2DATA2 KSCAN8/PS2CLK2 KSCAN(7:0)/ GPIO(7:0) I/O I/O I/O I/O I/O I/O 3 3 3 3 3 5 5 5 5 3.3 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 2 -Note 2 - - - Pull-downNote 3 - - - - Note 4 - Resonator Resonator - 9.126 MHz clock - GND connection Fixed at 1000 PIU TPX(1:0)/ GPIO(17:16) TPY(1:0)/ GPIO(19:18) TPEN/GPIO20 ADX ADY ADIN AUDIOIN I/O 18 3.3 1 I/O 18 3.3 Hi-Z I/O I I I I O O I O I I O I I 3 - - - - - 3 - - - - 3 - - 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 0 - - - - 0 0 - - - - 1 - - AIU Interrupt Clock AUDIOOUT VRCINT CLK48MX1 CLK48MX2 PCLK SCLK CLK48M Test TESTC TEST(3:0) Notes 1. When these pins are used as KPORT(7:0) signals, an external pull-down resistor is required. 2. When the PS2U is used, set a pull-up resistor. 3. When the PIU is used, a switched pull-down resistor is required for the TPEN signal. 4. As the AUDIOOUT pin is a high-resistance output, power cannot be supplied. Connect a JFET input type operational amplifier (input bias below 100 nA). Remark 0: Low level, 1: High level, Hi-Z: High impedance User's Manual U14579EJ2V0UM 61 CHAPTER 2 PIN FUNCTIONS 2.4 Clock Oscillator Connection Figure 2-1. External Circuit of Clock Oscillator (a) Crystal oscillation (b) External clock VRC4173 GND External clock CLK48MX1 VRC4173 CLK48MX1 CLK48MX2 Open CLK48MX2 Cautions 1. When using a clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Also, do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as GND. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When inputting an external clock, make sure that no load such as the wiring capacitance is applied to the CLK48MX2 pin. 3. When using an external clock, the oscillator stop function cannot be used according to the CMUCLKMSK register of the CMU. If this function is used, operation cannot be guaranteed. 62 User's Manual U14579EJ2V0UM CHAPTER 2 PIN FUNCTIONS Figure 2-2. Examples of Improperly Connected Resonators (a) Connection circuit wiring is too long (b) Signal lines are crossed GND CLK48MX1 CLK48MX2 GND CLK48MX1 CLK48MX2 (c) A high fluctuating current flows near the signal line (d) A current flows over the ground line of the oscillator (the potentials of points A, B, and C change) VDD GND CLK48MX1 CLK48MX2 GND CLK48MX1 CLK48MX2 High current C B A (e) A signal is fetched GND CLK48MX1 CLK48MX2 User's Manual U14579EJ2V0UM 63 CHAPTER 3 BCU (BUS CONTROL UNIT) 3.1 General The BCU controls the PIB (Peripheral Internal Bus), which is an internal bus. The DMAAU, DCU, CMU, ICU, GIU, PIU, AIU, KIU, PS2CH1, PS2CH2, and ADU are connected to the PIB. 3.2 Register Set Table 3-1 lists the BCU configuration registers. Table 3-1. BCU Configuration Registers Offset Address 0x00 to 0x01 0x02 to 0x03 0x04 to 0x05 0x06 to 0x07 0x08 0x09 to 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x13 0x14 to 0x2B 0x2C to 0x2D 0x2E to 0x2F 0x30 to 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 R/W R R R/W R/W R R R R/W R R R/W - R/W R/W - R/W R R R R/W R/W Register Symbol VID DID PCICMD PCISTS RID CLASSC CACHELS MLT HEDT BIST BADR - SUBVID SUBID - INTL INTP MIN_GNT MAX_LAT BUSCNT IDSELNUM Vendor ID register Device ID register PCI command register PCI device status register Revision ID register Class code register Cache line size register Master latency timer register Header type register Built-in self-test register PIB I/O base address register Reserved Subsystem vendor ID register Subsystem ID register Reserved Interrupt line register Interrupt pin register Burst cycle minimum request time register Bus usage right request frequency register PIB bus control register PC card IDSEL selection register Function These registers are described in detail below. 64 User's Manual U14579EJ2V0UM CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.1 Bit VID (offset address: 0x00 to 0x01) 15 VID15 R 0 14 VID14 R 0 13 VID13 R 0 12 VID12 R 1 11 VID11 R 0 10 VID10 R 0 9 VID9 R 0 8 VID8 R 0 Name R/W After reset Bit Name R/W After reset 7 VID7 R 0 6 VID6 R 0 5 VID5 R 1 4 VID4 R 1 3 VID3 R 0 2 VID2 R 0 1 VID1 R 1 0 VID0 R 1 Bit 15:0 Name VID(15:0) Vendor ID 0x1033: NEC Function 3.2.2 Bit DID (offset address: 0x02 to 0x03) 15 DID15 R 0 14 DID14 R 0 13 DID13 R 0 12 DID12 R 0 11 DID11 R 0 10 DID10 R 0 9 DID9 R 0 8 DID8 R 0 Name R/W After reset Bit Name R/W After reset 7 DID7 R 1 6 DID6 R 0 5 DID5 R 1 4 DID4 R 0 3 DID3 R 0 2 DID2 R 1 1 DID1 R 0 0 DID0 R 1 Bit 15:0 Name DID(15:0) Device ID 0x00A5: BCU Function User's Manual U14579EJ2V0UM 65 CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.3 Bit PCICMD (offset address: 0x04 to 0x05) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 FBTB_EN R 0 8 SERR_EN R/W 0 Name R/W After reset Bit Name 7 AD_STEP 6 PERR_EN 5 VGA_P_ SNOOP R 0 4 MEMW_ INV_EN R 0 3 SP_CYC 2 MASTER_ EN R/W 0 1 MEM_EN 0 IO_EN R/W After reset R 0 R/W 0 R 0 R 0 R/W 0 Bit 15:10 9 Name RFU FBTB_EN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables fast Back to Back. This function is not supported by the BCU. Enables/disables SERR# signal output. 1: Enable The SERR# signal is set to active if an address parity error is detected and the PERR_EN bit is 1. 0: Disable Enables/disables address/data stepping. This function is not supported by the BCU. Enables/disables parity error. 1: Enable output of the PERR# signal The PERR# signal is set to active if a data parity error is detected. The SERR# signal is set to active if an address parity error is detected and the SERR_EN bit is 1. 0: Disable output of the PERR# signal VGA palette snoop. This function is not supported by the BCU. Enables/disables memory write and invalidate. This function is not supported by the BCU. Special cycle. This function is not supported by the BCU. Controls bus master operation. 1: Operate as bus master on the PCI bus. 0: Do not operate as bus master on the PCI bus. Controls memory space. This function is not supported by the BCU. Controls I/O space. 1: Respond to an I/O access to the PIB. 0: Do not respond to an I/O access to the PIB. 8 SERR_EN 7 AD_STEP 6 PERR_EN 5 VGA_P_SNOOP 4 MEMW_INV_EN 3 SP_CYC 2 MASTER_EN 1 MEM_EN 0 IO_EN 66 User's Manual U14579EJ2V0UM CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.4 Bit PCISTS (offset address: 0x06 to 0x07) 15 DETECT_ PERR R/W 0 14 SIG_SERR 13 RV_ MABORT R/W 0 12 RV_ TABORT R/W 0 11 SIG_ TABOT R/W 0 10 DEVSEL1 9 DEVSEL0 8 DETECT_ D_PERR R/W 0 Name R/W After reset R/W 0 R 0 R 1 Bit Name R/W After reset 7 FBTB_CAP R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 15 Name DETECT_PERR Function Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected SERR# signal status. Cleared to 0 when 1 is written. 1: Active 0: Inactive Master abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reporting. Cleared to 0 when 1 is written. 1: Reported 0: Not reported DEVSEL# timing 01: Medium speed Set to 1 when the following three conditions are satisfied. Cleared to 0 when 1 is written. * The BCU is the master of the bus cycle in which the data parity error occurred. * Either the BCU set the PERR# signal to active or the BCU detected that the PERR# signal became active due to the target. * The PERR_EN bit of the PCICMD register has been set to 1. Response to fast Back to Back. This is fixed at 0 (disabled). Reserved. Write 0 to these bits. 0 is returned after a read. 14 SIG_SERR 13 RV_MABORT 12 RV_TABORT 11 SIG_TABOT 10:9 DEVSEL(1:0) 8 DETECT_D_PERR 7 FBTB_CAP 6:0 RFU User's Manual U14579EJ2V0UM 67 CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.5 Bit RID (offset address: 0x08) 7 RID7 R 0 6 RID6 R 0 5 RID5 R 0 4 RID4 R 0 3 RID3 R 0 2 RID2 R 0 1 RID1 R 0 0 RID0 R 0 Name R/W After reset Bit 7:0 Name RID(7:0) Revision ID Function 3.2.6 Bit CLASSC (offset address: 0x09 to 0x0B) 23 CLASSC23 R 0 22 CLASSC22 R 0 21 CLASSC21 R 0 20 CLASSC20 R 0 19 CLASSC19 R 0 18 CLASSC18 R 1 17 CLASSC17 R 1 16 CLASSC16 R 0 Name R/W After reset Bit Name R/W After reset 15 CLASSC15 R 1 14 CLASSC14 R 0 13 CLASSC13 R 0 12 CLASSC12 R 0 11 CLASSC11 R 0 10 CLASSC10 R 0 9 CLASSC9 R 0 8 CLASSC8 R 0 Bit Name R/W After reset 7 CLASSC7 R 0 6 CLASSC6 R 0 5 CLASSC5 R 0 4 CLASSC4 R 0 3 CLASSC3 R 0 2 CLASSC2 R 0 1 CLASSC1 R 0 0 CLASSC0 R 0 Bit 23:0 Name CLASSC(23:0) Class code 0x068000: Bridge device Function 3.2.7 Bit CACHELS (offset address: 0x0C) 7 CACHELS7 R 0 6 CACHELS6 R 0 5 CACHELS5 R 0 4 CACHELS4 R 0 3 CACHELS3 R 0 2 CACHELS2 R 0 1 CACHELS1 R 0 0 CACHELS0 R 0 Name R/W After reset Bit 7:0 Name CACHELS(7:0) Function Sets the cache line size. This function is not supported by the BCU. 68 User's Manual U14579EJ2V0UM CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.8 Bit MLT (offset address: 0x0D) 7 MLT7 R/W 0 6 MLT6 R/W 0 5 MLT5 R/W 0 4 MLT4 R/W 0 3 MLT3 R 0 2 MLT2 R 0 1 MLT1 R 0 0 MLT0 R 0 Name R/W After reset Bit 7:4 Name MLT(7:4) Sets the latency timer. 1111: 30 PCLK (900 ns) : 0010: 17 PCLK (510 ns) 0001: 16 PCLK (480 ns) 0000: 0 PCLK (0 ns) Function 3:0 MLT(3:0) Write 0 to these bits. 0 is returned after a read. Remark 3.2.9 Bit Name R/W After reset Values enclosed in parentheses are for PCICLK = 33 MHz. HEDT (offset address: 0x0E) 7 HEDT7 R 1 6 HEDT6 R 0 5 HEDT5 R 0 4 HEDT4 R 0 3 HEDT3 R 0 2 HEDT2 R 0 1 HEDT1 R 0 0 HEDT 0 R 0 Bit 7:0 Name HEDT(7:0) Header type Function 0x80: This is a multifunction device and offset address 0x10 to 0x3F of the configuration register are default settings. 3.2.10 BIST (offset address: 0x0F) Bit Name R/W After reset 7 BIST7 R 0 6 BIST6 R 0 5 BIST5 R 0 4 BIST4 R 0 3 BIST3 R 0 2 BIST2 R 0 1 BIST1 R 0 0 BIST0 R 0 Bit 7:0 Name BIST(7:0) Function Built-in self-test. This function is not supported by the BCU. User's Manual U14579EJ2V0UM 69 CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.11 BADR (offset address: 0x10 to 0x13) Bit Name R/W After reset 31 BADR31 R/W 0 30 BADR30 R/W 0 29 BADR29 R/W 0 28 BADR28 R/W 0 27 BADR27 R/W 0 26 BADR26 R/W 0 25 BADR25 R/W 0 24 BADR24 R/W 0 Bit Name R/W After reset 23 BADR23 R/W 0 22 BADR22 R/W 0 21 BADR21 R/W 0 20 BADR20 R/W 0 19 BADR19 R/W 0 18 BADR18 R/W 0 17 BADR17 R/W 0 16 BADR16 R/W 0 Bit Name R/W After reset 15 BADR15 R/W 0 14 BADR14 R/W 0 13 BADR13 R/W 0 12 BADR12 R/W 0 11 BADR11 R/W 0 10 BADR10 R/W 0 9 BADR9 R/W 0 8 BADR8 R 0 Bit Name R/W After reset 7 BADR7 R 0 6 BADR6 R 0 5 BADR5 R 0 4 BADR4 R 0 3 BADR3 R 0 2 BADR2 R 0 1 BADR1 R 0 0 BADR0 R 1 Bit 31:9 8:1 0 Name BADR(31:9) BADR(8:1) BADR0 Sets the PIB I/O base address. Function Write 0 to these bits. 0 is returned after a read. Write 1 to this bit. 1 is returned after a read. 70 User's Manual U14579EJ2V0UM CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.12 SUBVID (offset address: 0x2C to 0x2D) Bit Name R/W After reset 15 SUBVID15 R/W 0 14 SUBVID14 R/W 0 13 SUBVID13 R/W 0 12 SUBVID12 R/W 0 11 SUBVID11 R/W 0 10 SUBVID10 R/W 0 9 SUBVID9 R/W 0 8 SUBVID8 R/W 0 Bit Name R/W After reset 7 SUBVID7 R/W 0 6 SUBVID6 R/W 0 5 SUBVID5 R/W 0 4 SUBVID4 R/W 0 3 SUBVID3 R/W 0 2 SUBVID2 R/W 0 1 SUBVID1 R/W 0 0 SUBVID0 R/W 0 Bit 15:0 Name SUBVID(15:0) Function Subsystem vendor ID This is a vendor identification number to be used for recognizing the system or option card. The operating system writes and uses this ID. 3.2.13 SUBID (offset address: 0x2E to 0x2F) Bit Name R/W After reset 15 SUBID15 R/W 0 14 SUBID14 R/W 0 13 SUBID13 R/W 0 12 SUBID12 R/W 0 11 SUBID11 R/W 0 10 SUBID10 R/W 0 9 SUBID9 R/W 0 8 SUBID8 R/W 0 Bit Name R/W After reset 7 SUBID7 R/W 0 6 SUBID6 R/W 0 5 SUBID5 R/W 0 4 SUBID4 R/W 0 3 SUBID3 R/W 0 2 SUBID2 R/W 0 1 SUBID1 R/W 0 0 SUBID0 R/W 0 Bit 15:0 Name SUBID(15:0) Function Subsystem ID This is a controller identification number to be used for recognizing the system or option card. The operating system writes and uses this ID. User's Manual U14579EJ2V0UM 71 CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.14 INTL (offset address: 0x3C) Bit Name R/W After reset 7 INTL7 R/W 0 6 INTL6 R/W 0 5 INTL5 R/W 0 4 INTL4 R/W 0 3 INTL3 R/W 0 2 INTL2 R/W 0 1 INTL1 R/W 0 0 INTL0 R/W 0 Bit 7:0 Name INTL(7:0) Function Sets the interrupt request line. Since this function is not supported by the BCU, settings for these bits are invalid. Use the ICU to set the interrupt request line. 3.2.15 INTP (offset address: 0x3D) Bit Name R/W After reset 7 INTP7 R 0 6 INTP6 R 0 5 INTP5 R 0 4 INTP4 R 0 3 INTP3 R 0 2 INTP2 R 0 1 INTP1 R 0 0 INTP0 R 1 Bit 7:0 Name INTP(7:0) PCI interrupt pin 0x01: Serial Function 3.2.16 MIN_GNT (offset address: 0x3E) Bit Name R/W After reset 7 MIN_GNT7 R 0 6 MIN_GNT6 R 0 5 MIN_GNT5 R 0 4 MIN_GNT4 R 0 3 MIN_GNT3 R 0 2 MIN_GNT2 R 0 1 MIN_GNT1 R 0 0 MIN_GNT0 R 0 Bit 7:0 Name MIN_GNT(7:0) Burst cycle minimum request time. These bits are fixed at 0x00. Function 72 User's Manual U14579EJ2V0UM CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.17 MAX_LAT (offset address: 0x3F) Bit Name R/W After reset 7 MAX_LAT7 R 0 6 MAX_LAT6 R 1 5 MAX_LAT5 R 0 4 MAX_LAT4 R 1 3 MAX_LAT3 R 1 2 MAX_LAT2 R 0 1 MAX_LAT1 R 1 0 MAX_LAT0 R 0 Bit 7:0 Name MAX_LAT(7:0) Function Maximum delay time until a response is returned when the PCI bus usage right is requested. These bits are fixed at 0x56. 3.2.18 BUSCNT (offset address: 0x40) Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 POSTON R/W 0 Bit 7:1 0 Name RFU POSTON Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables PCI I/O post write cycle. 1: Enable 0: Disable User's Manual U14579EJ2V0UM 73 CHAPTER 3 BCU (BUS CONTROL UNIT) 3.2.19 IDSELNUM (offset address: 0x41) Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 C2IDSEL1 R/W 0 4 C2IDSEL0 R/W 0 3 RFU R 0 2 RFU R 0 1 C1IDSEL1 R/W 0 0 C1IDSEL0 R/W 0 Bit 7:6 5:4 Name RFU C2IDSEL(1:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Selects the IDSEL signal of CARDU2 (PC card channel 2). 11: Reserved 10: Selects the AD25 signal as the IDSEL signal. 01: Selects the AD19 signal as the IDSEL signal. 00: Selects the AD13 signal as the IDSEL signal. When 11 is set, it is treated as if 00 were set (the AD13 signal is selected). Reserved. Write 0 to these bits. 0 is returned after a read. Selects the IDSEL signal of CARDU1 (PC card channel 1). 11: Reserved 10: Selects the AD24 signal as the IDSEL signal. 01: Selects the AD18 signal as the IDSEL signal. 00: Selects the AD12 signal as the IDSEL signal. When 11 is set, it is treated as if 00 were set (the AD12 signal is selected). 3:2 1:0 RFU C1IDSEL(1:0) The AD12 or AD13 signal is selected by default and connected for the IDSEL signal of CARDU1 or CARDU2, respectively. When this address bit has been used for the IDSEL signal of another PCI device in the system, change it to a different address bit by setting the C1IDSEL(1:0) area or C2IDSEL(1:0) area. 74 User's Manual U14579EJ2V0UM CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.1 General The DMAAU register controls the DMA addresses for the AIU. The DMA channel used for each unit can set a DMA start address as any half-word address in the physical address from 0x0000 0000 to 0xFFFF FFFE, and is retained in DRAM as a 2 KB block that starts at the address which is generated by masking the lower 10 bits of the DMA start address. Caution DMA operations are not guaranteed if an address overlaps with another DMA buffer. After a DMA start address is set to the DMA base address register, the VRC4173 performs DMA transfer using the registers of DMAAU as below. (1) When the DMA start address is included in the first page of the DMA space <1> The VRC4173 starts a DMA transfer after writing the start address to the DMA address register. <2> When the DMA transfer reaches the first page boundary, the VRC4173 adds 1 KB to the contents of the DMA base address register, writes the value to the DMA address register, and continues the DMA transfer. <3> When the DMA transfer reaches the second page boundary, the VRC4173 writes the contents of the DMA base address register to the DMA address register and continues the DMA transfer. <4> The VRC4173 repeats <2> and <3> until all the data is transferred. (2) When the DMA start address is included in the second page of the DMA space <1> The VRC4173 starts a DMA transfer after writing the start address to the DMA address register. <2> When the DMA transfer reaches the second page boundary, the VRC4173 subtracts 1 KB from the contents of the DMA base address register, writes the value to the DMA address register, and continues the DMA transfer. <3> When the DMA transfer reaches the first page boundary, the VRC4173 writes the contents of the DMA base address register to the DMA address register and continues the DMA transfer. <4> The VRC4173 repeats <2> and <3> until all the data is transferred. Figure 4-1. DMA Space Used in DMA Transfers (a) When the DMA start address is included in the first page of the DMA space Second page boundary <2> <4> <6> <8> (b) When the DMA start address is included in the second page of the DMA space Second page boundary Base address First page boundary Base address <1> <3> <5> <7> First page boundary <1> <3> <5> <7> <2> <4> <6> <8> DMA space address DMA space address User's Manual U14579EJ2V0UM 75 CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2 Register Set Table 4-1 lists the DMAAU registers. Table 4-1. DMAAU Registers Address BASE + 0x000 BASE + 0x002 BASE + 0x004 BASE + 0x006 BASE + 0x008 BASE + 0x00A BASE + 0x00C BASE + 0x00E R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbol AIUIBALREG AIUIBAHREG AIUIALREG AIUIAHREG AIUOBALREG AIUOBAHREG AIUOALREG AIUOAHREG Function AIU IN DMA Base Address Register Low AIU IN DMA Base Address Register High AIU IN DMA Address Register Low AIU IN DMA Address Register High AIU OUT DMA Base Address Register Low AIU OUT DMA Base Address Register High AIU OUT DMA Address Register Low AIU OUT DMA Address Register High Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. 76 User's Manual U14579EJ2V0UM CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.1 AIU IN DMA base address registers (1) AIUIBALREG (base address + 0x000) Bit Name R/W After reset 15 AIUIBA15 R/W 1 14 AIUIBA14 R/W 1 13 AIUIBA13 R/W 1 12 AIUIBA12 R/W 1 11 AIUIBA11 R/W 1 10 AIUIBA10 R/W 0 9 AIUIBA9 R/W 0 8 AIUIBA8 R/W 0 Bit Name R/W After reset 7 AIUIBA7 R/W 0 6 AIUIBA6 R/W 0 5 AIUIBA5 R/W 0 4 AIUIBA4 R/W 0 3 AIUIBA3 R/W 0 2 AIUIBA2 R/W 0 1 AIUIBA1 R/W 0 0 AIUIBA0 R 0 Bit 15:1 0 Name AIUIBA(15:1) AIUIBA0 DMA base address 15:1 for AIU input Function DMA base address 0 for AIU input Write 0 to this bit. 0 is returned after a read. (2) AIUIBAHREG (base address + 0x002) Bit Name R/W After reset 15 AIUIBA31 R/W 1 14 AIUIBA30 R/W 1 13 AIUIBA29 R/W 1 12 AIUIBA28 R/W 1 11 AIUIBA27 R/W 1 10 AIUIBA26 R/W 1 9 AIUIBA25 R/W 1 8 AIUIBA24 R/W 1 Bit Name R/W After reset 7 AIUIBA23 R/W 1 6 AIUIBA22 R/W 1 5 AIUIBA21 R/W 1 4 AIUIBA20 R/W 1 3 AIUIBA19 R/W 1 2 AIUIBA18 R/W 1 1 AIUIBA17 R/W 1 0 AIUIBA16 R/W 1 Bit 15:0 Name AIUIBA(31:16) Function DMA base address 31:16 for AIU input AIUIBALREG and AIUIBAHREG registers are used to set the base addresses for the DMA channel used for audio input (recording). The addresses set to these registers become DMA transfer start addresses. The DMA channel used for audio input is retained in DRAM as a 2 KB buffer that starts at the address which is generated by masking the lower 10 bits of the DMA start address. User's Manual U14579EJ2V0UM 77 CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.2 AIU IN DMA address registers (1) AIUIALREG (base address + 0x004) Bit Name R/W After reset 15 AIUIA15 R/W 1 14 AIUIA14 R/W 1 13 AIUIA13 R/W 1 12 AIUIA12 R/W 1 11 AIUIA11 R/W 1 10 AIUIA10 R/W 0 9 AIUIA9 R/W 0 8 AIUIA8 R/W 0 Bit Name R/W After reset 7 AIUIA7 R/W 0 6 AIUIA6 R/W 0 5 AIUIA5 R/W 0 4 AIUIA4 R/W 0 3 AIUIA3 R/W 0 2 AIUIA2 R/W 0 1 AIUIA1 R/W 0 0 AIUIA0 R 0 Bit 15:0 Name AIUIA(15:0) Function Next DMA address 15:0 to be accessed for AIU input channel (2) AIUIAHREG (base address + 0x006) Bit Name R/W After reset 15 AIUIA31 R/W 1 14 AIUIA30 R/W 1 13 AIUIA29 R/W 1 12 AIUIA28 R/W 1 11 AIUIA27 R/W 1 10 AIUIA26 R/W 1 9 AIUIA25 R/W 1 8 AIUIA24 R/W 1 Bit Name R/W After reset 7 AIUIA23 R/W 1 6 AIUIA22 R/W 1 5 AIUIA21 R/W 1 4 AIUIA20 R/W 1 3 AIUIA19 R/W 1 2 AIUIA18 R/W 1 1 AIUIA17 R/W 1 0 AIUIA16 R/W 1 Bit 15:0 Name AIUIA(31:16) Function Next DMA address 31:16 to be accessed for AIU input channel 78 User's Manual U14579EJ2V0UM CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.3 AIU OUT DMA base address registers (1) AIUOBALREG (base address + 0x008) Bit Name R/W After reset 15 AIUOBA15 R/W 1 14 AIUOBA14 R/W 1 13 AIUOBA13 R/W 1 12 AIUOBA12 R/W 1 11 AIUOBA11 R/W 1 10 AIUOBA10 R/W 0 9 AIUOBA9 R/W 0 8 AIUOBA8 R/W 0 Bit Name R/W After reset 7 AIUOBA7 R/W 0 6 AIUOBA6 R/W 0 5 AIUOBA5 R/W 0 4 AIUOBA4 R/W 0 3 AIUOBA3 R/W 0 2 AIUOBA2 R/W 0 1 AIUOBA1 R/W 0 0 AIUOBA0 R 0 Bit 15:1 0 Name AIUOBA(15:1) AIUOBA0 Function DMA base address 15:1 for AIU output DMA base address 0 for AIU output Write 0 to this bit. 0 is returned after a read. (2) AIUOBAHREG (base address + 0x00A) Bit Name R/W After reset 15 AIUOBA31 R/W 1 14 AIUOBA30 R/W 1 13 AIUOBA29 R/W 1 12 AIUOBA28 R/W 1 11 AIUOBA27 R/W 1 10 AIUOBA26 R/W 1 9 AIUOBA25 R/W 1 8 AIUOBA24 R/W 1 Bit Name R/W After reset 7 AIUOBA23 R/W 1 6 AIUOBA22 R/W 1 5 AIUOBA21 R/W 1 4 AIUOBA20 R/W 1 3 AIUOBA19 R/W 1 2 AIUOBA18 R/W 1 1 AIUOBA17 R/W 1 0 AIUOBA16 R/W 1 Bit 15:0 Name AIUOBA(31:16) Function DMA base address 31:16 for AIU output AIUOBALREG and AIUOBAHREG registers are used to set the base addresses for the DMA channel used for audio output (playback). The addresses set to these registers become DMA transfer start addresses. The DMA channel used for audio output is retained in DRAM as a 2 KB buffer that starts at the address which is generated by masking the lower 10 bits of the DMA start address. User's Manual U14579EJ2V0UM 79 CHAPTER 4 DMAAU (DMA ADDRESS UNIT) 4.2.4 AIU OUT DMA address registers (1) AIUOALREG (base address + 0x00C) Bit Name R/W After reset 15 AIUOA15 R/W 1 14 AIUOA14 R/W 1 13 AIUOA13 R/W 1 12 AIUOA12 R/W 1 11 AIUOA11 R/W 1 10 AIUOA10 R/W 0 9 AIUOA9 R/W 0 8 AIUOA8 R/W 0 Bit Name R/W After reset 7 AIUOA7 R/W 0 6 AIUOA6 R/W 0 5 AIUOA5 R/W 0 4 AIUOA4 R/W 0 3 AIUOA3 R/W 0 2 AIUOA2 R/W 0 1 AIUOA1 R/W 0 0 AIUOA0 R 0 Bit 15:0 Name AIUOA(15:0) Function Next DMA address 15:0 to be accessed for AIU output channel (2) AIUOAHREG (base address + 0x00E) Bit Name R/W After reset 15 AIUOA31 R/W 1 14 AIUOA30 R/W 1 13 AIUOA29 R/W 1 12 AIUOA28 R/W 1 11 AIUOA27 R/W 1 10 AIUOA26 R/W 1 9 AIUOA25 R/W 1 8 AIUOA24 R/W 1 Bit Name R/W After reset 7 AIUOA23 R/W 1 6 AIUOA22 R/W 1 5 AIUOA21 R/W 1 4 AIUOA20 R/W 1 3 AIUOA19 R/W 1 2 AIUOA18 R/W 1 1 AIUOA17 R/W 1 0 AIUOA16 R/W 1 Bit 15:0 Name AIUOA(31:16) Function Next DMA address 31:16 to be accessed for AIU output channel 80 User's Manual U14579EJ2V0UM CHAPTER 5 DCU (DMA CONTROL UNIT) 5.1 General The DCU register is used for DMA control. Specifically, it controls acknowledgment from the BCU that handles bus arbitration and DMA requests from the on-chip peripheral I/O unit (AIU). It also controls DMA enable/disable settings. 5.2 DMA Priority Control When a conflict occurs between DMA requests sent from on-chip peripheral I/O unit, the following priority levels are used to resolve the conflict. These priority levels cannot be changed. Table 5-1. DMA Priority Levels Priority Level High Low Type of DMA Operation Audio input (recording) Audio output (playback) 5.3 Register Set Table 5-2 lists the DCU registers. Table 5-2. DCU Registers Address BASE + 0x020 BASE + 0x022 BASE + 0x024 BASE + 0x026 BASE + 0x028 R/W R/W R R/W R/W R Register Symbol DMARSTREG DMAIDLEREG DMASENREG DMAMSKREG DMAREQREG DMA Reset Register DMA Sequencer Status Register DMA Sequencer Enable Register DMA Mask Register DMA Request Register Function Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. User's Manual U14579EJ2V0UM 81 CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.1 Bit DMARSTREG (base address + 0x020) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 DMARST W 0 Bit 15:1 0 Name RFU DMARST Function Reserved. Write 0 to these bits. 0 is returned after a read. Reset DMA controller 1: Reset 0: Normal This register is used to reset the DMA controller. Reset the DMA controller after confirming that the DMA is not executed (idle status). 5.3.2 Bit Name R/W After reset DMAIDLEREG (base address + 0x022) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 DMAISTAT R 1 Bit 15:1 0 Name RFU DMAISTAT Function Reserved. Write 0 to these bits. 0 is returned after a read. Display DMA sequencer status 1: Idle status 0: Sequencer busy This register is used to display the DMA sequencer status. 82 User's Manual U14579EJ2V0UM CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.3 Bit DMASENREG (base address + 0x024) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 DMASEN R/W 0 Bit 15:1 0 Name RFU DMASEN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enable DMA sequencer 1: Enable 0: Disable This register is used to enable/disable the DMA sequencer. User's Manual U14579EJ2V0UM 83 CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.4 Bit DMAMSKREG (base address + 0x026) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 DMAMSKA IN R/W 0 2 DMAMSKA OUT R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit 15:4 3 Name RFU DMAMSKAIN Function Reserved. Write 0 to these bits. 0 is returned after a read. Audio input DMA transfer enable/disable 1: Enable 0: Disable Audio output DMA transfer enable/disable 1: Enable 0: Disable Reserved. Write 0 to these bits. 0 is returned after a read. 2 DMAMSKAOUT 1:0 RFU This register is used to enable/disable various types of DMA transfers. The DMA transfer enable bits should be set when the units that receive DMA service have been stopped or when there are no pending DMA requests. If any of the above bits are set to a unit while a DMA request is pending for that unit, the operation of the VRC4173 will be undefined. 84 User's Manual U14579EJ2V0UM CHAPTER 5 DCU (DMA CONTROL UNIT) 5.3.5 Bit DMAREQREG (base address + 0x028) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 DRQAIN R 0 2 DRQAOUT R 0 1 RFU R 0 0 RFU R 0 Bit 15:4 3 Name RFU DRQAIN Function Reserved. Write 0 to these bits. 0 is returned after a read. Audio input DMA transfer request 1: Request pending 0: No request Audio output DMA transfer request 1: Request pending 0: No request Reserved. Write 0 to these bits. 0 is returned after a read. 2 DRQAOUT 1:0 RFU This register is used to indicate whether or not there are any DMA transfer requests. User's Manual U14579EJ2V0UM 85 CHAPTER 6 CMU (CLOCK MASK UNIT) 6.1 General As various input clocks are supplied from the CPU to each unit, a masking method enables power consumption to be curtailed in units that are not used. The units for which this masking method are used are the USBU, CARDU1, CARDU2, KIU, PIU, AIU, PS2CH1, PS2CH2, and AC97U units. The basic functions are described below. * Control of PCICLK (internal) supplied to USBU, CARDU1, CARDU2, and AC97U * Control of TClock (internal clock synchronized with PCICLK) supplied to KIU, PIU, AIU, PS2CH1, and PS2CH2 * Control of 48 MHz clock supplied to USBU and CLK48M output pin * Control of on-chip 48 MHz oscillator The initial value is "0", which specifies masking all supplied clocks. No clock is supplied unless the CPU writes "1" to the register. 86 User's Manual U14579EJ2V0UM CHAPTER 6 CMU (CLOCK MASK UNIT) 6.2 Register Set Table 6-1 lists the CMU registers. Table 6-1. CMU Registers Address BASE + 0x040 BASE + 0x042 R/W R/W R/W Register Symbol CMUCLKMSK CMUSRST CMU Clock Mask Register CMU Soft Reset Register Function Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. 6.2.1 Bit Name CMUCLKMSK (base address + 0x040) (1/2) 15 RFU 14 RFU 13 RFU 12 MSK 48MOSC R/W 0 11 MSK 48MPIN R/W 0 10 MSK 48MUSB R/W 0 9 RFU 8 MSK AC97 R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit Name 7 MSK CARD2 R/W 0 6 MSK CARD1 R/W 0 5 MSKUSB 4 MSK PS2CH2 R/W 0 3 MSK PS2CH1 R/W 0 2 MSKAIU 1 MSKKIU 0 MSKPIU R/W After reset R/W 0 R/W 0 R/W 0 R/W 0 Bit 15:13 12 Name RFU MSK48MOSC Function Reserved. Write 0 to these bits. 0 is returned after a read. Control on-chip 48 MHz oscillator 1: Oscillation 0: Stop Supply/mask 48 MHz clock to external pin (CLK48M) 1: Supply 0: Mask Supply/mask 48 MHz clock to USBU unit 1: Supply 0: Mask Reserved. Write 0 to this bit. 0 is returned after a read. Supply/mask PCICLK to AC97U unit 1: Supply 0: Mask Supply/mask PCICLK to CARDU1 unit 1: Supply 0: Mask 11 MSK48MPIN 10 MSK48MUSB 9 8 RFU MSKAC97 7 MSKCARD2 User's Manual U14579EJ2V0UM 87 CHAPTER 6 CMU (CLOCK MASK UNIT) (2/2) Bit 6 Name MSKCARD1 Function Supply/mask PCICLK to CARDU2 unit 1: Supply 0: Mask Supply/mask PCICLK to USBU unit 1: Supply 0: Mask Supply/mask TClock to PS2CH2 unit 1: Supply 0: Mask Supply/mask TClock to PS2CH1 unit 1: Supply 0: Mask Supply/mask TClock to AIU unit 1: Supply 0: Mask Supply/mask TClock to KIU unit 1: Supply 0: Mask Supply/mask TClock to PIU unit 1: Supply 0: Mask 5 MSKUSB 4 MSKPS2CH2 3 MSKPS2CH1 2 MSKAIU 1 MSKKIU 0 MSKPIU This register is used to mask the clocks that are supplied to the AC97U, CARDU1, CARDU2, USBU, KIU, PIU, AIU, PS2CH1, and PS2CH2 units. Cautions 1. Set the clock supplied to USBU, CARDU1, CARDU2, and AC97U units during the soft reset period by the CMUSRST register (see 6.2.2). 2. Supply clock to the CLK48M pin after setting the MSK48MOSC bit to 1 (oscillator oscillation) and setting the MSK48MPIN bit to 1 (clock supply). 88 User's Manual U14579EJ2V0UM CHAPTER 6 CMU (CLOCK MASK UNIT) 6.2.2 Bit CMUSRST (base address + 0x042) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 AC97RST R/W 0 2 CARD2RST R/W 0 Note 1 CARD1RST R/W 0 Note 0 USBRST R/W 0 Bit 15:4 3 Name RFU AC97RST Function Reserved. Write 0 to these bits. 0 is returned after a read. Soft reset to AC97U unit 1: Soft reset 0: Soft reset released Soft reset to CARDU2 unit 1: Soft reset 0: Soft reset released Soft reset to CARDU1 unit 1: Soft reset 0: Soft reset released Soft reset to USBU unit 1: Soft reset 0: Soft reset released 2 CARD2RSTNote 1 CARD1RSTNote 0 USBRST Note When either CARDU unit is reset via software, the power of the other CARDU unit will be initialized. Therefore, if a soft reset has been performed, set the registers of both units again. User's Manual U14579EJ2V0UM 89 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.1 General The ICU collects interrupt requests from the various on-chip peripheral units and transfers these interrupt request signals to the CPU. The functions of the ICU's internal blocks are briefly described below. * ADDECICU ... Decodes read/write addresses from the CPU that are used for ICU registers. * REGICU ... This includes a register for interrupt masking. The initial value is "0", which specifies masking. No interrupt request signal is supplied to CPU unless the CPU writes "1" to this register. * OUTICU ... This block collects interrupt requests after masking them, and generates an interrupt request signal to output to the CPU. During Suspend mode, it also controls the masking of interrupt requests and output of the general interrupt source signal. For details of the interrupt sources, see 7.2 Register Set. How an interrupt request is notified to the CPU core is shown below. If an interrupt request occurs in the peripheral units, the corresponding bit in the interrupt status register of Level 2 (xxxINTREG register) is set to 1. The interrupt status register is ANDed bit-wise with the corresponding interrupt mask register of Level 2 (MxxxINTREG register). If the occurred interrupt request is enabled (set to 1) in the mask register, the interrupt request is notified to the interrupt status register of Level 1 (SYSINT1REG register) and the corresponding bit is set to 1. At this time, the interrupt requests from the same register of Level 2 are notified to the SYSINT1REG register as a single interrupt request. Interrupt requests from some units directly set their corresponding bits in the SYSINT1REG register. The SYSINT1REG register is ANDed bit-wise with the interrupt mask register of Level 1 (MSYSINT1REG register). If the interrupt request is enabled by MSYSINT1REG register (set to 1), a corresponding interrupt request signal is output from the ICU to the CPU. Figure 7-1 shows an outline of interrupt control in the ICU. 90 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) Figure 7-1. Interrupt Control Outline Diagram Level 2 Level 1 dozepiuint 16 GIULINTREG 16 MGIULINTREG 5 GIUHINTREG 5 MGIUHINTREG 3 KIUINTREG 3 MKIUINTREG 7 AIUINTREG 7 MAIUINTREG 6 PIUINTREG 6 MPIUINTREG 12 AND/OR AND/OR AND/OR SYSINT1REG AND/OR 4 7 AC97int1 AC97int PS2CH1int AND/OR PS2CH2int PCMCIA1int PCMCIA2int USBint 12 VRCINT MSYSINT1REG Interrupt status register Interrupt mask register AND/OR logic (Checking masks bit by bit and summarizing interrupt requests from the registers) User's Manual U14579EJ2V0UM 91 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) The VRCINT signal (interrupt request signal) output timing and the timing of the status change of each interrupt status register are described below. In the ICU, the sampling clock differs depending on the interrupt source. The assignment of sampling clock and interrupt sources are shown in the following table. Table 7-1. Assignment of Sampling Clocks and Interrupt Sources Sampling Clock SCLK Interrupt Source DOZEPIUINTR, AC97INTR1, PS2CH1INTR, PS2CH2INTR, INTS(20:0) (GIUINTR), SCANINT (KIUINTR) Other than above PCLK VRCINT signal is output in synchronization with the rising or falling edge of SCLK for all interrupt requests. Due to differences in the sampling clocks and the synchronization of VRCINT output, there is a time lag between when the internal interrupt source changes and when this change is reflected in the interrupt status register and the VRCINT signal. These relationships are shown in Figures 7-2 and 7-3 below. Figure 7-2. Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with SCLK) PCLK (input) SCLK (input) Internal interrupt source change Reflection in ICU status register VRCINT internal synchronization VRCINT (output) a b Remark a: The time between when the internal interrupt source changes and when this change is reflected in the ICU status register (MAX. 1 x SCLK) b: Time between when the change is reflected in the ICU status register and when it is output to VRCINT (1.5 x SCLK) 92 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) Figure 7-3. Time Lag Until Status Change Is Reflected in VRCINT Signal (When Sampling with PCLK) PCLK (input) SCLK (input) Internal interrupt source change Reflection in ICU status register VRCINT internal synchronization VRCINT (output) a b Remark a: The time between when the internal interrupt source changes and when this change is reflected in the ICU status register (MAX. 1 x PCLK) b: Time between when the change is reflected in the ICU status register and when it is output to VRCINT (MAX. 1.5 x SCLK) 7.2 Register Set Table 7-2 lists the ICU registers. Table 7-2. ICU Registers Address BASE + 0x060 BASE + 0x062 BASE + 0x064 BASE + 0x066 BASE + 0x068 BASE + 0x06A BASE + 0x06C BASE + 0x06E BASE + 0x070 BASE + 0x072 BASE + 0x074 BASE + 0x076 R/W R R R R R R R/W R/W R/W R/W R/W R/W Register Symbol SYSINT1REG PIUINTREG AIUINTREG KIUINTREG GIULINTREG GIUHINTREG MSYSINT1REG MPIUINTREG MAIUINTREG MKIUINTREG MGIULINTREG MGIUHINTREG Function System interrupt register 1 (Level 1) PIU interrupt register (Level 2) AIU interrupt register (Level 2) KIU interrupt register (Level 2) GIUL interrupt register (Level 2) GIUH interrupt register (Level 2) Mask system interrupt register 1 (Level 1) Mask PIU interrupt register (Level 2) Mask AIU interrupt register (Level 2) Mask KIU interrupt register (Level 2) Mask GIUL interrupt register (Level 2) Mask GIUH interrupt register (Level 2) Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. User's Manual U14579EJ2V0UM 93 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.1 Bit SYSINT1REG (base address + 0x060) (1/2) 15 RFU 14 RFU 13 DOZE PIUINTR R 0 12 RFU 11 RFU 10 AC97INTR1 9 AC97INTR 8 GIUINTR Name R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name 7 KIUINTR 6 AIUINTR 5 PIUINTR 4 PS2CH1 INTR R 0 3 PS2CH2 INTR R 0 2 PCMCIA1 INTR R 0 1 PCMCIA2 INTR R 0 0 USBINTR R/W After reset R 0 R 0 R 0 R 0 Bit 15:14 13 Name RFU DOZEPIUINTR Function Reserved. Write 0 to these bits. 0 is returned after a read. PIU interrupt request during Suspend mode 1: Occurred 0: Normal Reserved. Write 0 to these bits. 0 is returned after a read. AC97int1 interrupt request 1: Occurred 0: Normal AC97 interrupt request 1: Occurred 0: Normal GIU interrupt request 1: Occurred 0: Normal KIU interrupt request 1: Occurred 0: Normal AIU interrupt request 1: Occurred 0: Normal PIU interrupt request 1: Occurred 0: Normal PS2CH1 interrupt request 1: Occurred 0: Normal PS2CH2 interrupt request 1: Occurred 0: Normal 12:11 10 RFU AC97INTR1 9 AC97INTR 8 GIUINTR 7 KIUINTR 6 AIUINTR 5 PIUINTR 4 PS2CH1INTR 3 PS2CH2INTR 94 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) (2/2) Bit 2 Name PCMCIA1INTR PCMCIA1 interrupt request 1: Occurred 0: Normal PCMCIA2 interrupt request 1: Occurred 0: Normal USB interrupt request 1: Occurred 0: Normal Function 1 PCMCIA2INTR 0 USBINTR This register indicates when various interrupt requests occur in the VRC4173 system. User's Manual U14579EJ2V0UM 95 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.2 Bit PIUINTREG (base address + 0x062) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name 7 RFU 6 PADCMD INTR R 0 5 PADADP INTR R 0 4 PADPAGE1 INTR R 0 3 PADPAGE0 INTR R 0 2 PADDLO STINTR R 0 1 RFU 0 PENCHG INTR R 0 R/W After reset R 0 R 0 Bit 15:7 6 Name RFU PADCMDINTR Function Reserved. Write 0 to these bits. 0 is returned after a read. PIU command scan interrupt request. This interrupt occurs when command scan found valid data. 1: Occurred 0: Normal PIU A/D port scan interrupt request. This interrupt occurs when A/D port scan found a set of valid data. 1: Occurred 0: Normal PIU data buffer page 1 interrupt request. This interrupt occurs when a set of valid data is stored in page 1 of data buffer. 1: Occurred 0: Normal PIU data buffer page 0 interrupt request. This interrupt occurs when a set of valid data is stored in page 0 of data buffer. 1: Occurred 0: Normal Data lost interrupt request. This interrupt occurs when a set of data did not found within specified time. 1: Occurred 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. Touch panel contact status change interrupt request 1: Change has occurred 0: No change 5 PADADPINTR 4 PADPAGE1INTR 3 PADPAGE0INTR 2 PADDLOSTINTR 1 0 RFU PENCHGINTR This register indicates when various PIU-related interrupt requests occur. 96 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.3 Bit AIUINTREG (base address + 0x064) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 INTMEND R 0 10 INTM R 0 9 INTMIDLE R 0 8 INTMST R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 INTSEND R 0 2 INTS R 0 1 INTSIDLE R 0 0 RFU R 0 Bit 15:12 11 Name RFU INTMEND Function Reserved. Write 0 to these bits. 0 is returned after a read. Audio input (MIC) DMA buffer 2 page interrupt request 1: Occurred 0: Normal Audio input (MIC) DMA buffer 1 page interrupt request 1: Occurred 0: Normal Audio input (MIC) idle interrupt request (received data is lost). This interrupt occurs if valid data exists in MIDATREG register when data was received from A/D converter. 1: Occurred 0: Normal Audio input (MIC) receive completion interrupt request. This interrupt occurs when 12-bit converted data was received from the A/D converter. 1: Occurred 0: Normal Reserved. Write 0 to these bits. 0 is returned after a read. Audio output (speaker) DMA buffer 2 page interrupt request 1: Occurred 0: Normal Audio output (speaker) DMA buffer 1 page interrupt request 1: Occurred 0: Normal Audio output (speaker) idle interrupt request (mute). This interrupt occurs if there is no valid data in SODATREG register when data was transferred to D/A converter. 1: Occurred 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. 10 INTM 9 INTMIDLE 8 INTMST 7:4 3 RFU INTSEND 2 INTS 1 INTSIDLE 0 RFU This register indicates when various AIU-related interrupt requests occur. User's Manual U14579EJ2V0UM 97 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.4 Bit KIUINTREG (base address + 0x066) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 KDATLOST R 0 1 KDATRDY R 0 0 SCANINT R 0 Bit 15:3 2 Name RFU KDATLOST Function Reserved. Write 0 to these bits. 0 is returned after a read. Key scan data lost interrupt request 1: Occurred 0: Normal Key data scan complete interrupt request 1: Occurred 0: Normal Key input detect interrupt request 1: Occurred 0: Normal 1 KDATRDY 0 SCANINT This register indicates when various KIU-related interrupt requests occur. 98 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.5 Bit GIULINTREG (base address + 0x068) 15 INTS15 R 0 14 INTS14 R 0 13 INTS13 R 0 12 INTS12 R 0 11 INTS11 R 0 10 INTS10 R 0 9 INTS9 R 0 8 INTS8 R 0 Name R/W After reset Bit Name R/W After reset 7 INTS7 R 0 6 INTS6 R 0 5 INTS5 R 0 4 INTS4 R 0 3 INTS3 R 0 2 INTS2 R 0 1 INTS1 R 0 0 INTS0 R 0 Bit 15:0 Name INTS(15:0) Function Interrupt request input to GPIO(15:0) pin 1: Occurred 0: Normal This register indicates when various GIU-related interrupt requests occur. 7.2.6 Bit Name R/W After reset GIUHINTREG (base address + 0x06A) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTS20 R 0 3 INTS19 R 0 2 INTS18 R 0 1 INTS17 R 0 0 INTS16 R 0 Bit 15:5 4:0 Name RFU INTS(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. Interrupt request input to GPIO(20:16) pin 1: Occurred 0: Normal This register indicates when various GIU-related interrupt requests occur. User's Manual U14579EJ2V0UM 99 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.7 Bit MSYSINT1REG (base address + 0x06C) (1/2) 15 RFU 14 RFU 13 DOZE PIUINTR R/W 0 12 RFU 11 RFU 10 AC97INTR1 9 AC97INTR 8 GIUINTR Name R/W After reset R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 Bit Name 7 KIUINTR 6 AIUINTR 5 PIUINTR 4 PS2CH1 INTR R/W 0 3 PS2CH2 INTR R/W 0 2 PCMCIA1 INTR R/W 0 1 PCMCIA2 INTR R/W 0 0 USBINTR R/W After reset R/W 0 R/W 0 R/W 0 R/W 0 Bit 15:14 13 Name RFU DOZEPIUINTR Function Reserved. Write 0 to these bits. 0 is returned after a read. PIU interrupt enable during Suspend mode 1: Enabled 0: Disabled Reserved. Write 0 to these bits. 0 is returned after a read. AC97int1 interrupt enable 1: Enabled 0: Disabled AC97 interrupt enable 1: Enabled 0: Disabled GIU interrupt enable 1: Enabled 0: Disabled KIU interrupt enable 1: Enabled 0: Disabled AIU interrupt enable 1: Enabled 0: Disabled PIU interrupt enable 1: Enabled 0: Disabled PS2CH1 interrupt enable 1: Enabled 0: Disabled PS2CH2 interrupt enable 1: Enabled 0: Disabled 12:11 10 RFU AC97INTR1 9 AC97INTR 8 GIUINTR 7 KIUINTR 6 AIUINTR 5 PIUINTR 4 PS2CH1INTR 3 PS2CH2INTR 100 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) (2/2) Bit 2 Name PCMCIA1INTR PCMCIA1 interrupt enable 1: Enabled 0: Disabled PCMCIA2 interrupt enable 1: Enabled 0: Disabled USB interrupt enable 1: Enabled 0: Disabled Function 1 PCMCIA2INTR 0 USBINTR This register is used to mask various interrupt requests that occur in the VRC4173 system. User's Manual U14579EJ2V0UM 101 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.8 Bit MPIUINTREG (base address + 0x06E) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name 7 RFU 6 PADCMD INTR R/W 0 5 PADADP INTR R/W 0 4 PADPAGE1 INTR R/W 0 3 PADPAGE0 INTR R/W 0 2 PADDLO STINTR R/W 0 1 RFU 0 PENCHG INTR R/W 0 R/W After reset R 0 R 0 Bit 15:7 6 Name RFU PADCMDINTR Function Reserved. Write 0 to these bits. 0 is returned after a read. PIU command scan interrupt enable 1: Enabled 0: Disabled PIU A/D port scan interrupt enable 1: Enabled 0: Disabled PIU A/D data buffer page 1 interrupt enable 1: Enabled 0: Disabled PIU A/D data buffer page 0 interrupt enable 1: Enabled 0: Disabled Data lost interrupt enable 1: Enabled 0: Disabled Reserved. Write 0 to this bit. 0 is returned after a read. Touch panel contact status change interrupt enable 1: Enabled 0: Disabled 5 PADADPINTR 4 PADPAGE1INTR 3 PADPAGE0INTR 2 PADDLOSTINTR 1 0 RFU PENCHGINTR This register is used to mask various PIU-related interrupt requests. 102 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.9 Bit MAIUINTREG (base address + 0x070) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 INTMEND R/W 0 10 INTM R/W 0 9 INTMIDLE R/W 0 8 INTMST R/W 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 INTSEND R/W 0 2 INTS R/W 0 1 INTSIDLE R/W 0 0 RFU R 0 Bit 15:12 11 Name RFU INTMEND Function Reserved. Write 0 to these bits. 0 is returned after a read. Audio input (MIC) DMA buffer 2 page interrupt enable 1: Enabled 0: Disabled Audio input (MIC) DMA buffer 1 page interrupt enable 1: Enabled 0: Disabled Audio input (MIC) idle interrupt (received data is lost) enable 1: Enabled 0: Disabled Audio input (MIC) receive complete interrupt enable 1: Enabled 0: Disabled Reserved. Write 0 to these bits. 0 is returned after a read. Audio output (speaker) DMA buffer 2 page interrupt enable 1: Enabled 0: Disabled Audio output (speaker) DMA buffer 1 page interrupt enable 1: Enabled 0: Disabled Audio output (speaker) idle interrupt (mute) enable 1: Enabled 0: Disabled Reserved. Write 0 to this bit. 0 is returned after a read. 10 INTM 9 INTMIDLE 8 INTMST 7:4 3 RFU INTSEND 2 INTS 1 INTSIDLE 0 RFU This register is used to mask various AIU-related interrupt requests. User's Manual U14579EJ2V0UM 103 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.10 MKIUINTREG (base address + 0x072) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 KDAT LOST R/W 0 1 KDAT RDY R/W 0 0 SCAN INT R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 Bit 15:3 2 Name RFU KDATLOST Function Reserved. Write 0 to these bits. 0 is returned after a read. Key scan data lost interrupt enable 1: Enabled 0: Disabled Key data scan complete interrupt enable 1: Enabled 0: Disabled Key input detect interrupt enable 1: Enabled 0: Disabled 1 KDATRDY 0 SCANINT This register is used to mask various KIU-related interrupt requests. 104 User's Manual U14579EJ2V0UM CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.2.11 MGIULINTREG (base address + 0x074) Bit Name R/W After reset 15 INTS15 R/W 0 14 INTS14 R/W 0 13 INTS13 R/W 0 12 INTS12 R/W 0 11 INTS11 R/W 0 10 INTS10 R/W 0 9 INTS9 R/W 0 8 INTS8 R/W 0 Bit Name R/W After reset 7 INTS7 R/W 0 6 INTS6 R/W 0 5 INTS5 R/W 0 4 INTS4 R/W 0 3 INTS3 R/W 0 2 INTS2 R/W 0 1 INTS1 R/W 0 0 INTS0 R/W 0 Bit 15:0 Name INTS(15:0) GPIO(15:0) pin interrupt input enable 1: Enabled 0: Disabled Function This register is used to mask various GIU-related interrupt requests. 7.2.12 MGIUHINTREG (base address + 0x076) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTS20 R/W 0 3 INTS19 R/W 0 2 INTS18 R/W 0 1 INTS17 R/W 0 0 INTS16 R/W 0 Bit 15:5 4:0 Name RFU INTS(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. GPIO(20:16) pin interrupt input enable 1: Enabled 0: Disabled This register is used to mask various GIU-related interrupt requests. User's Manual U14579EJ2V0UM 105 CHAPTER 7 ICU (INTERRUPT CONTROL UNIT) 7.3 Notes for Register Setting There is no register setting flow in relation to the ICU. With regard to the interrupt mask registers, the initial setting is "initial = 0 = mask" after setting. Therefore, enough masks must be cleared to provide sufficient interrupts for the CPU's start-up processing. 106 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.1 General The GIU controls the GPIO(20:0) pins. GPIO is a general-purpose port for which input and output are available. An interrupt request signal input function can be assigned to GPIO with input signal change (rising edge or falling edge of signal), low level, or high level used as the trigger. Table 8-1 shows the clock to be used for interrupt request detection and the type of input buffer of the GPIO(20:0) pins. Table 8-1. GPIO Pin Outline Pin Name Interrupt Request Detection Clock (Internal) SCLK Input Buffer Type GPIO(20:0) IO normal When not used for an interrupt, the registers corresponding to these pins can be written to output a low-level or high-level signal. Each register can be read to check the state of the signal currently being input to the corresponding pin. The GPIO pins can be used as transition factors from the Suspend or Standby mode to the Fullspeed mode. User's Manual U14579EJ2V0UM 107 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2 Register Set Table 8-2 lists the GIU registers. Table 8-2. GIU Registers Address BASE + 0x080 BASE + 0x082 BASE + 0x084 BASE + 0x086 BASE + 0x088 BASE + 0x08A BASE + 0x08C BASE + 0x08E BASE + 0x090 BASE + 0x092 BASE + 0x094 BASE + 0x096 BASE + 0x098 BASE + 0x09A BASE + 0x09E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbol GIUDIRL GIUDIRH GIUPIODL GIUPIODH GIUINTSTATL GIUINTSTATH GIUINTENL GIUINTENH GIUINTTYPL GIUINTTYPH GIUINTALSELL GIUINTALSELH GIUINTHTSELL GIUINTHTSELH SELECTREG GPIO I/O Select Register L GPIO I/O Select Register H GPIO Port I/O Data Register L GPIO Port I/O Data Register H GPIO Interrupt Status Register L GPIO Interrupt Status Register H GPIO Interrupt Enable Register L GPIO Interrupt Enable Register H GPIO Interrupt Type (Edge or Level) Select Register L GPIO Interrupt Type (Edge or Level) Select Register H GPIO Interrupt Active Level Select Register L GPIO Interrupt Active Level Select Register H GPIO Interrupt Hold/Through Select Register L GPIO Interrupt Hold/Through Select Register H Alternate Function Pin Select Register Function Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). 108 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.1 Bit GIUDIRL (base address + 0x080) 15 IOS15 R/W 0 14 IOS14 R/W 0 13 IOS13 R/W 0 12 IOS12 R/W 0 11 IOS11 R/W 0 10 IOS10 R/W 0 9 IOS9 R/W 0 8 IOS8 R/W 0 Name R/W After reset Bit Name R/W After reset 7 IOS7 R/W 0 6 IOS6 R/W 0 5 IOS5 R/W 0 4 IOS4 R/W 0 3 IOS3 R/W 0 2 IOS2 R/W 0 1 IOS1 R/W 0 0 IOS0 R/W 0 Bit 15:0 Name IOS(15:0) GPIO(15:0) pin I/O select 1: Output 0: Input Function This register is used to set I/O modes for GPIO(15:0) pins. The IOS(15:0) bits correspond to the GPIO(15:0) pins. When the IOS bit is set to 1, the corresponding GPIO pin is set for output and the value that has been written to the corresponding PIOD bit in the GIUPIODL register is output. When this bit is set to 0, the corresponding GPIO pin is set for input. Caution The GPIO(15:0) pins are also used as KIU pins. When using as GPIO pins, setting is required in the SELECTREG register (see 8.2.15). User's Manual U14579EJ2V0UM 109 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.2 GIUDIRH (base address + 0x082) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 IOS20 R/W 0 3 IOS19 R/W 0 2 IOS18 R/W 0 1 IOS17 R/W 0 0 IOS16 R/W 0 Bit 15:5 4:0 Name RFU IOS(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. GPIO(20:16) pin I/O select 1: Output 0: Input This register is used to set I/O modes for GPIO(20:16) pins. The IOS(20:16) pins correspond to the GPIO(20:16) pins. When the IOS bit is set to 1, the corresponding GPIO pin is set for output and the value that has been written to the corresponding PIOD bit in the GIUPIODH register is output. When this bit is set to 0, the corresponding GPIO pin is set for input. Caution The GPIO(20:16) pins are also used as PIU pins. When using as GPIO pins, setting is required in the SELECTREG register (see 8.2.15). 110 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.3 GIUPIODL (base address + 0x084) Bit Name R/W After reset 15 PIOD15 R/W 0 14 PIOD14 R/W 0 13 PIOD13 R/W 0 12 PIOD12 R/W 0 11 PIOD11 R/W 0 10 PIOD10 R/W 0 9 PIOD9 R/W 0 8 PIOD8 R/W 0 Bit Name R/W After reset 7 PIOD7 R/W 0 6 PIOD6 R/W 0 5 PIOD5 R/W 0 4 PIOD4 R/W 0 3 PIOD3 R/W 0 2 PIOD2 R/W 0 1 PIOD1 R/W 0 0 PIOD0 R/W 0 Bit 15:0 Name PIOD(15:0) Function GPIO(15:0) pin output data specification 1: High 0: Low This register is used to read GPIO(15:0) pins and write data. The PIOD(15:0) bits correspond to the GPIO(15:0) pins. When 1 is set to the corresponding IOS bit in the GIUDIRL register, the data written to the PIOD bit is output via the corresponding GPIO pin. When the value of the corresponding IOS bit in the GIUDIRL register is 0, writing a value to the PIOD bit does not affect the GPIO pin (writing to the PIOD bit is performed normally). When the value of the IOS bit in the GIUDIRL register is 0, reading the PIOD bit enables the corresponding GPIO pin's state to be read. Caution The GPIO(15:0) pins are also used as KIU pins. When using as GPIO pins, setting is required in the SELECTREG register (see 8.2.15). User's Manual U14579EJ2V0UM 111 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.4 GIUPIODH (base address + 0x086) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 PIOD20 R/W 0 3 PIOD19 R/W 0 2 PIOD18 R/W 0 1 PIOD17 R/W 0 0 PIOD16 R/W 0 Bit 15:5 4:0 Name RFU PIOD(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. GPIO(20:16) pin output data specification 1: High 0: Low This register is used to read GPIO(20:16) pins and write data. The PIOD(20:16) bits correspond to the GPIO(20:16) pins. When 1 is set to the corresponding IOS bit in the GIUDIRH register, the data written to the PIOD bit is output via the corresponding GPIO pin. When the value of the corresponding IOS bit in the GIUDIRH register is 0, writing a value to the PIOD bit does not affect the GPIO pin (writing to the PIOD bit is performed normally). When the value of the IOS bit in the GIUDIRH register is 0, reading the PIOD bit enables the corresponding GPIO pin's state to be read. Caution The GPIO(20:16) pins are also used as PIU pins. When using as GPIO pins, setting is required in the SELECTREG register (see 8.2.15). 112 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.5 GIUINTSTATL (base address + 0x088) Bit Name R/W After reset 15 INTS15 R/W 1 14 INTS14 R/W 1 13 INTS13 R/W 1 12 INTS12 R/W 1 11 INTS11 R/W 1 10 INTS10 R/W 1 9 INTS9 R/W 1 8 INTS8 R/W 1 Bit Name R/W After reset 7 INTS7 R/W 1 6 INTS6 R/W 1 5 INTS5 R/W 1 4 INTS4 R/W 1 3 INTS3 R/W 1 2 INTS2 R/W 1 1 INTS1 R/W 1 0 INTS0 R/W 1 Bit 15:0 Name INTS(15:0) Function Interrupt to GPIO(15:0) pins. Cleared to 0 when 1 is written. 1: Interrupt occurred 0: No interrupt This register indicates the interrupt status of GPIO(15:0) pins. The INTS(15:0) bits correspond to the GPIO(15:0) pins. The corresponding INTS bit is set to 1 when the signal input to the GPIO pin meets the condition set via the GIUINTTYPL register or the GIUINTALSELL register. Even if the corresponding bit is set to 1, however, no interrupt occurs when the GIUINTENL register is set to 0 (disable interrupt). When the GPIO pin is not selected in the SELECTREG register, this register indicates 1, but the register value is invalid (interrupt status is not indicated). When the GPIO pin is not selected in the SELECTREG register, disable the interrupt with the GIUINTENL register. When using this register, it should be cleared to 0 once after the GIUINTTYPL and GIUINTALSELL registers are set to enable interrupt. User's Manual U14579EJ2V0UM 113 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.6 GIUINTSTATH (base address + 0x08A) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTS20 R/W 1 3 INTS19 R/W 1 2 INTS18 R/W 1 1 INTS17 R/W 1 0 INTS16 R/W 1 Bit 15:5 4:0 Name RFU INTS(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. Interrupt to GPIO(20:16) pins. Cleared to 0 when 1 is written. 1: Interrupt occurred 0: No interrupt This register indicates the interrupt status of GPIO(20:16) pins. The INTS(20:16) bits correspond to the GPIO(20:16) pins. The corresponding INTS bit is set to 1 when the signal input to the GPIO pin meets the condition set via the GIUINTTYPH register or GIUINTALSELH register. Even if the corresponding bit is set to 1, however, no interrupt occurs when the GIUINTENH register is set to 0 (disable interrupt). When the GPIO pin is not selected in the SELECTREG register, this register indicates 1, but the register value is invalid (interrupt status is not indicated). When the GPIO pin is not selected in the SELECTREG register, disable the interrupt with the GIUINTENH register. When using this register, it should be cleared to 0 once after the GIUINTTYPH and GIUINTALSELH registers are set to enable interrupt. 114 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.7 GIUINTENL (base address + 0x08C) Bit Name R/W After reset 15 INTE15 R/W 0 14 INTE14 R/W 0 13 INTE13 R/W 0 12 INTE12 R/W 0 11 INTE11 R/W 0 10 INTE10 R/W 0 9 INTE9 R/W 0 8 INTE8 R/W 0 Bit Name R/W After reset 7 INTE7 R/W 0 6 INTE6 R/W 0 5 INTE5 R/W 0 4 INTE4 R/W 0 3 INTE3 R/W 0 2 INTE2 R/W 0 1 INTE1 R/W 0 0 INTE0 R/W 0 Bit 15:0 Name INTE(15:0) Interrupt enable to GPIO(15:0) pins 1: Interrupt enable 0: Interrupt disable Function This register is used to set interrupt enable status for GPIO(15:0) pins. The INTE(15:0) bits correspond to the GPIO(15:0) pins. When 1 is set to the corresponding INTE bit, interrupts are enabled for the corresponding GPIO pins. 8.2.8 GIUINTENH (base address + 0x08E) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTE20 R/W 0 3 INTE19 R/W 0 2 INTE18 R/W 0 1 INTE17 R/W 0 0 INTE16 R/W 0 Bit 15:5 4:0 Name RFU INTE(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. Interrupt enable to GPIO(20:16) pins 1: Interrupt enable 0: Interrupt disable This register is used to set interrupt enable status for GPIO(20:16) pins. The INTE(20:16) bits correspond to the GPIO(20:16) pins. When 1 is set to the corresponding INTE bit, interrupts are enabled for the corresponding GPIO pins. User's Manual U14579EJ2V0UM 115 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.9 GIUINTTYPL (base address + 0x090) Bit Name R/W After reset 15 INTT15 R/W 0 14 INTT14 R/W 0 13 INTT13 R/W 0 12 INTT12 R/W 0 11 INTT11 R/W 0 10 INTT10 R/W 0 9 INTT9 R/W 0 8 INTT8 R/W 0 Bit Name R/W After reset 7 INTT7 R/W 0 6 INTT6 R/W 0 5 INTT5 R/W 0 4 INTT4 R/W 0 3 INTT3 R/W 0 2 INTT2 R/W 0 1 INTT1 R/W 0 0 INTT0 R/W 0 Bit 15:0 Name INTT(15:0) Interrupt request detection trigger 1: Edge 0: Level Function This register is used to set the trigger to detect an interrupt request for GPIO(15:0) pins. The INTT(15:0) bits correspond to the GPIO(15:0) pins. When 1 is set to the corresponding INTT bit, the edge detection method is used for the interrupt request signal at the corresponding GPIO pin (an interrupt request is triggered when the signal state changes from low to high or from high to low). The level detection method is used when 0 is set, in which case the level set to the corresponding INTL bit in the GIUINTALSELL register is detected. 116 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.10 GIUINTTYPH (base address + 0x092) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTT20 R/W 0 3 INTT19 R/W 0 2 INTT18 R/W 0 1 INTT17 R/W 0 0 INTT16 R/W 0 Bit 15:5 4:0 Name RFU INTT(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. Interrupt request detection trigger 1: Edge 0: Level This register is used to set the trigger to detect an interrupt request for GPIO(20:16) pins. The INTT(20:16) bits correspond to the GPIO(20:16) pins. When 1 is set to the corresponding INTT bit, the edge detection method is used for the interrupt request signal at the corresponding GPIO pin (an interrupt request is triggered when the signal state changes from low to high or from high to low). The level detection method is used when 0 is set, in which case the level set to the corresponding INTL bit in the GIUINTALSELH register is detected. User's Manual U14579EJ2V0UM 117 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.11 GIUINTALSELL (base address + 0x094) Bit Name R/W After reset 15 INTL15 R/W 0 14 INTL14 R/W 0 13 INTL13 R/W 0 12 INTL12 R/W 0 11 INTL11 R/W 0 10 INTL10 R/W 0 9 INTL9 R/W 0 8 INTL8 R/W 0 Bit Name R/W After reset 7 INTL7 R/W 0 6 INTL6 R/W 0 5 INTL5 R/W 0 4 INTL4 R/W 0 3 INTL3 R/W 0 2 INTL2 R/W 0 1 INTL1 R/W 0 0 INTL0 R/W 0 Bit 15:0 Name INTL(15:0) Interrupt request detection level 1: High active 0: Low active Function This register is used to set the active level when using the level detection method for interrupts to GPIO(15:0) pins. The INTL(15:0) bits correspond to the GPIO(15:0) pins. The contents of this register are not reflected when the edge detection method is selected via the GIUINTTYPL register. When using this register, be sure to set the level detection method via the GIUINTTYPL register. 118 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.12 GIUINTALSELH (base address + 0x096) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTL20 R/W 0 3 INTL19 R/W 0 2 INTL18 R/W 0 1 INTL17 R/W 0 0 INTL16 R/W 0 Bit 15:5 4:0 Name RFU INTL(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. Interrupt request detection level 1: High active 0: Low active This register is used to set the active level when using the level detection method for interrupts to GPIO(20:16) pins. The INTL(20:16) bits correspond to the GPIO(20:16) pins. The contents of this register are not reflected when the edge detection method is selected via the GIUINTTYPH register. When using this register, be sure to set the level detection method via the GIUINTTYPH register. User's Manual U14579EJ2V0UM 119 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.13 GIUINTHTSELL (base address + 0x098) Bit Name R/W After reset 15 INTH15 R/W 0 14 INTH14 R/W 0 13 INTH13 R/W 0 12 INTH12 R/W 0 11 INTH11 R/W 0 10 INTH10 R/W 0 9 INTH9 R/W 0 8 INTH8 R/W 0 Bit Name R/W After reset 7 INTH7 R/W 0 6 INTH6 R/W 0 5 INTH5 R/W 0 4 INTH4 R/W 0 3 INTH3 R/W 0 2 INTH2 R/W 0 1 INTH1 R/W 0 0 INTH0 R/W 0 Bit 15:0 Name INTH(15:0) Function GPIO(15:0) pin interrupt signal hold/through 1: Hold 0: Through This register is used to set whether or not interrupt signals to the GPIO(15:0) pins should be held. The INTH(15:0) bits correspond to the GPIO(15:0) pins. When 1 is set to the corresponding INTH bit, any interrupt signal input to the corresponding GPIO pin is held. When 0 is set to this bit, any interrupt signal input to the corresponding GPIO pin is not held and is instead allowed to pass through. Any held interrupt signal is cleared when 1 is set to the corresponding INTS bit in the GIUINTSTATL register. INTH bits are not affected by GIUINTENL register. If 1 (hold) is set to the INTH bit while the INTE bit in the GIUINTENL register is set to 0 (disable interrupts), any change in the pin state is retained as change data. Therefore, an interrupt still occurs when the INTE bit is again set to 1 (enable interrupts). 120 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.14 GIUINTHTSELH (base address + 0x09A) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 INTH20 R/W 0 3 INTH19 R/W 0 2 INTH18 R/W 0 1 INTH17 R/W 0 0 INTH16 R/W 0 Bit 15:5 4:0 Name RFU INTH(20:16) Function Reserved. Write 0 to these bits. 0 is returned after a read. GPIO(20:16) pin interrupt signal hold/through 1: Hold 0: Through This register is used to set whether or not interrupt signals to the GPIO(20:16) pins should be held. The INTH(20:16) bits correspond to the GPIO(20:16) pins. When 1 is set to the corresponding INTH bit, any interrupt signal input to the corresponding GPIO pin is held. When 0 is set to this bit, any interrupt signal input to the corresponding GPIO pin is not held and is instead allowed to pass through. Any held interrupt signal is cleared when 1 is set to the corresponding INTS bit in the GIUINTSTATH register. INTH bits are not affected by GIUINTENH register. If 1 (hold) is set to the INTH bit while the INTE bit in the GIUINTENH register is set to 0 (disable interrupts), any change in the pin state is retained as change data. Therefore, an interrupt still occurs when the INTE bit is again set to 1 (enable interrupts). User's Manual U14579EJ2V0UM 121 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) The relationship between settings of GPIO interrupts enable/disable and hold/through is shown in Table 8-3. Table 8-3. Correspondences Between Interrupt Mask and Interrupt Hold Interrupt Trigger Level Setting of GIUINTHTSEL Register Hold Setting of GIUINTEN Register Masked Not masked Masked canceled Through Masked Not masked Masked canceled Edge Hold Masked Not masked Masked canceled Through Masked Not masked Masked canceled Held Held Held Through Through Through Held Held Held Through Prohibited Through Hold in GIU Notation to ICU Not noticed Noticed Noticed Not noticed Noticed Not noticed Not noticed Noticed Noticed Not noticed Prohibited Not noticed 122 User's Manual U14579EJ2V0UM CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) 8.2.15 SELECTREG (base address + 0x09E) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 SEL3 R/W 0 2 SEL2 R/W 0 1 SEL1 R/W 0 0 SEL0 R/W 0 Bit 15:4 3 Name RFU SEL3 Function Reserved. Write 0 to these bits. 0 is returned after a read. Function selection of TPEN/GPIO20, TPY(1:0)/GPIO(19:18), TPX(1:0)/GPIO(17:16) pins 1: Used as GPIO(20:16) pins 0: Used as TPEN, TPY(1:0), TPX(1:0) pins Function selection of KSCAN11/PS2DATA1, KSCAN10/PS2CLK1 pins 1: Used as PS2DATA1, PS2CLK1 pins 0: Used as KSCAN(11:10) pins Function selection of KSCAN9/PS2DATA2, KSCAN8/PS2CLK2 pins 1: Used as PS2DATA2, PS2CLK2 pins 0: Used as KSCAN(9:8) pins Function selection of KPORT(7:0)/GPIO(15:8), KSCAN(7:0)/GPIO(7:0) pins 1: Used as GPIO(15:0) pins 0: Used as KPORT(7:0), KSCAN(7:0) pins 2 SEL2 1 SEL1 0 SEL0 This register is used to select the alternate function pins of the VRC4173. GPIO(20:0) pins, KIU, PIU, and PS2U pins are used exclusively from other function pins. Therefore, when setting the GPIO(20:0) pins to be used by using this register, set the enable bit to prohibit in the corresponding unit. The correspondences of the alternate function pins are listed in the table on the next page. User's Manual U14579EJ2V0UM 123 CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT) Table 8-4. Alternate Function Correspondence Table of VRC4173 VRC4173 Pin TPEN/GPIO20 TPY1/GPIO19 TPY0/GPIO18 TPX1/GPIO17 TPX0/GPIO16 KPORT7/GPIO15 KPORT6/GPIO14 KPORT5/GPIO13 KPORT4/GPIO12 KPORT3/GPIO11 KPORT2/GPIO10 KPORT1/GPIO9 KPORT0/GPIO8 KSCAN11/PS2DATA1 KSCAN10/PS2CLK1 KSCAN9/PS2DATA2 KSCAN8/PS2CLK2 KSCAN7/GPIO7 KSCAN6/GPIO6 KSCAN5/GPIO5 KSCAN4/GPIO4 KSCAN3/GPIO3 KSCAN2/GPIO2 KSCAN1/GPIO1 KSCAN0/GPIO0 GPIO GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8 - - - - GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 PIU TPEN TPY1 TPY0 TPX1 TPX0 - - - - - - - - - - - - - - - - - - - - PS2CH1 - - - - - - - - - - - - - PS2DATA1 PS2CLK1 - - - - - - - - - - PS2CH2 - - - - - - - - - - - - - - - PS2DATA2 PS2CLK2 - - - - - - - - KIU - - - - - KPORT7 KPORT6 KPORT5 KPORT4 KPORT3 KPORT2 KPORT1 KPORT0 KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4 KSCAN3 KSCAN2 KSCAN1 KSCAN0 Caution When using PS/2 for 1 channel, the KIU supports 64/80 keys. When using PS/2 for 2 channels, the KIU supports only 64 keys. 124 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.1 General The PIU uses an on-chip A/D converter and detects the X and Y coordinates of pen contact locations on the touch panel and scans the general-purpose A/D input port. Since the touch panel control circuit and the A/D converter (conversion precision: 12 bits) are both on-chip, the touch panel is connected directly to the VRC4173. The PIU's function, namely the detection of X and Y coordinates, is performed partly by hardware and partly by software. Hardware tasks: * Touch panel applied voltage control * Reception of coordinate data Software task: * Processing of coordinate data based on data sampled by hardware Features of the PIU's hardware tasks are described below. * Can be directly connected to touch panel with four-pin resistance layers (on-chip touch panel driver) * Interface for on-chip A/D converter * Voltage detection at general-purpose A/D port and audio input port * Operation of A/D converter based on various settings and control of voltage applied to touch panel * Sampling of X-coordinate and Y-coordinate data * Variable coordinate data sampling interval * Interrupt request is triggered if pen touch occurs regardless of CPU operation mode (interrupt requests do not occur when in Hibernate mode) * Four dedicated buffers for up to two pages each of coordinate data * Two buffers for A/D port scan * Auto/manual options for coordinate data sampling start/stop control User's Manual U14579EJ2V0UM 125 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.1.1 Block diagrams Figure 9-1. PIU Peripheral Block Diagram VRC4173 Digital I/O buffer Touch panel TPX0 TPX1 TPY0 TPY1 TPEN touchen ADX ADY Tr1 ADIN 10 k AUDIOIN A/D converter Analog input buffer Remark When Tr1 is ON, pull down the TPY1 signal. When Tr1 is OFF, leave the TPY1 signal open. 126 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) * Touch panel A set of four pins are located at the edges of the X-axis and Y-axis resistance layers, and the two layers have high resistance when there is no pen contact and low resistance when there is pen contact. The resistance between the two edges of the resistance layers is about 1 k. When a voltage is applied to both edges of the Y-axis resistance layer, the voltage (VY1 and VY2 in Figure 9-2) is measured at the X-axis resistance layer's pins to determine the Y coordinate. Similarly, when a voltage is applied to both edges of the X-axis resistance layer, the voltage (VX1 and VX2 in Figure 9-2) is measured at the Y-axis resistance layer's pins to determine the X coordinate. For greater precision, voltage applied to individual resistance-layer pins can be measured to obtain X and Y coordinate data based on four voltage measurements. The obtained data is stored into the PIUPBnmREG register (n = 0 or 1, m = 0 to 4). Figure 9-2. Coordinate Detection Equivalent Circuits (a) Y-coordinate detection TPY1 pin: 3 V TPY1 pin: 0 V VY2 ADX pin VY1 ADX pin TPY0 pin: 0 V TPY0 pin: 3 V (b) X-coordinate detection ADY pin VX1 ADY pin VX2 TPX0 pin: 3 V TPX1 pin: 0 V TPX0 pin: 0 V TPX1 pin: 3 V User's Manual U14579EJ2V0UM 127 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Figure 9-3. PIU Internal Block Diagram VRC4173 (internal) PIU Internal bus Scan sequencer Internal bus controller PIU registers Touch panel Touch panel interface controller A/D converter General-purpose A/D port, Audio input port The PIU includes three blocks: an internal bus controller, a scan sequencer, and a touch panel interface controller. (1) Internal bus controller The internal bus controller controls the internal bus, the PIU registers, and interrupts and performs serial/parallel conversion of data from the A/D converter. (2) Scan sequencer The scan sequencer is used for PIU state management. (3) Touch panel interface controller The touch panel interface controller is used to control the touch panel. 128 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.2 Scan Sequencer State Transition Figure 9-4. Scan Sequencer State Transition Diagram Disable Reset = 1 PIUPWR = 0 PIUPWR = 1 PIUSEQEN = 0 ADPSSTART = 1 PIUSEQEN = 1 & ADPSSTART = 1 & PIUMODE = 00 ADPortScan Release & PADATSTOP = 1 PIUSEQEN = 0 ADPSSTART = 1 Touch Interval NextScan auto Timeout Standby PIUSEQEN = 1 & PADATSTART = 1 & PIUMODE = 00 PIUSEQEN = 1 & PIUMODE = 01 WaitPenTouch PenDataScan Release PIUSEQEN = 1 & PADSCANSTART = 1 & PIUMODE = 00 PIUSEQEN = 0 or PADSCANSTOP = 1 CmdScan PIUSEQEN = 0 (1) Disable state In this state, the A/D converter is in standby mode, the output pins are in touch detection mode and the input pins are in mask mode (to prevent misoperation when an undefined input is applied). State transition to Suspend mode is possible, however, it is necessary to wait for the time set by STABLE(5:0) area in the PIUSTBLREG register to ensure stabilization. (2) Standby state In this state, the unit is in scan idle mode. The touch panel is in low-power mode (0 V voltage is applied to the touch panel and the A/D converter is in disable mode). Normally, this is the state from which various mode settings are made. Caution State transitions occur when the PIUSEQEN bit is active, so the PIUSEQEN bit must be set as active after each mode setting has been completed. (3) ADPortScan state This is the state in which voltage is measured at the A/D converter's general-purpose port and audio input port. After the A/D converter is activated and voltage data is obtained, the data is stored in the PIU's internal data buffer (PIUABnREG register). After the two ports are scanned, an A/D port scan interrupt occurs inside the PIU. After this interrupt occurs, the ADPSSTART bit is automatically set as inactive and the state changes to the state in which the ADPSSTART bit was active. User's Manual U14579EJ2V0UM 129 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (4) CmdScan state When in this state, the A/D converter operates using various settings. Voltage data from one port only is fetched based on a combination of the touch panel I/O signal setting (TPX(1:0), TPY(1:0)) and the selection of an input port (ADX, ADY, AUDIOIN, ADIN) connected to the A/D converter. Use PIUCMDREG register to make the touch panel pin setting and to select the input port. (5) WaitPenTouch state This is the standby state that waits for a touch panel "Touch" state. When the PIU detects a touch panel "Touch" state, a touch panel contact status change interrupt occurs inside the PIU. At this point, if the PADATSTART bit is active, the state changes to the PenDataScan state. In the WaitPenTouch state, it is possible to change to Suspend mode, however, the PCICLK stops and panel status detection is not performed. (6) PenDataScan state This is the state in which touch panel coordinates are detected. The A/D converter is activated and the four sets of data for each coordinate are sampled. Caution If one complete pair of coordinates is not obtained during the interval between one pair of coordinates and the next coordinate data, a data lost interrupt occurs inside the PIU. (7) IntervalNextScan state This is the standby state that waits for the next coordinate sampling period and the touch panel's "Release" state. After the touch panel state is detected, the time period specified via PIUSIVLREG register elapses before the transition to the PenDataScan state. If the PIU detects the "Release" state within the specified time period, a touch panel contact status change interrupt occurs inside the PIU. At this point, the state changes to the WaitPenTouch state if the PADATSTOP bit is active. If the PADATSTOP bit is inactive, it changes to the PenDataScan state after the specified time period has elapsed. 130 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3 Register Set Table 9-1 lists the PIU registers. Table 9-1. PIU Registers Address BASE + 0x0A2 BASE + 0x0A4 BASE + 0x0A6 BASE + 0x0A8 BASE + 0x0AA BASE + 0x0B0 BASE + 0x0B2 BASE + 0x0BE BASE + 0x0C0 BASE + 0x0C2 BASE + 0x0C4 BASE + 0x0C6 BASE + 0x0C8 BASE + 0x0CA BASE + 0x0CC BASE + 0x0CE BASE + 0x0D0 BASE + 0x0D2 BASE + 0x0DC BASE + 0x0DE R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbol PIUCNTREG PIUINTREG PIUSIVLREG PIUSTBLREG PIUCMDREG PIUASCNREG PIUAMSKREG PIUCIVLREG PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUAB0REG PIUAB1REG PIUPB04REG PIUPB14REG PIU Control register PIU Interrupt cause register PIU Data sampling interval register PIU A/D converter start delay register PIU A/D command register PIU A/D port scan register PIU A/D scan mask register PIU Check interval register PIU Page 0 Buffer 0 register PIU Page 0 Buffer 1 register PIU Page 0 Buffer 2 register PIU Page 0 Buffer 3 register PIU Page 1 Buffer 0 register PIU Page 1 Buffer 1 register PIU Page 1 Buffer 2 register PIU Page 1 Buffer 3 register PIU A/D scan Buffer 0 register PIU A/D scan Buffer 1 register PIU Page 0 Buffer 4 register PIU Page 1 Buffer 4 register Function Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. User's Manual U14579EJ2V0UM 131 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.1 Bit PIUCNTREG (base address + 0x0A2) (1/2) 15 RFU 14 RFU 13 PENSTC 12 11 10 9 PADAT STOP R/W 0 8 PADAT START R/W 0 Name PADSTATE2 PADSTATE1 PADSTATE0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit Name 7 PADSCAN STOP R/W 0 6 PADSCAN START R/W 0 5 PADSCAN TYPE R/W 0 4 PIUMODE1 3 PIUMODE0 2 PIUSEQEN 1 PIUPWR 0 PADRST R/W After reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 15:14 13 Name RFU PENSTC Function Reserved. Write 0 to these bits. 0 is returned after a read. Touch/release when touch panel contact state changes 1: Touch 0: Release Scan sequencer status 111: CmdScan 110: IntervalNextScan 101: PenDataScan 100: WaitPenTouch 011: Reserved 010: ADPortScan 001: Standby 000: Disable Sequencer auto stop setting during touch panel release state 1: Auto stop after sampling data for one set of coordinates during release state 0: No auto stop (even during release state) Sequencer auto start setting during touch panel touch state 1: Auto start during touch state 0: No auto start during touch state Forced stop setting for touch panel sequencer 1: Forced stop after sampling data for one set of coordinates 0: Do not stop Start setting for touch panel sequencer 1: Forced start 0: Do not start Touch pressure sampling enable 1: Enable 0: Disable 12:10 PADSTATE(2:0) 9 PADATSTOP 8 PADATSTART 7 PADSCANSTOP 6 PADSCANSTART 5 PADSCANTYPE 132 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (2/2) Bit 4:3 Name PIUMODE(1:0) Function PIU mode setting 11: Reserved 10: Reserved 01: Operate A/D converter using any command 00: Sample coordinate data Scan sequencer operation enable 1: Enable 0: Disable PIU power mode setting 1: Set PIU output as active and change to standby mode 0: Set panel to touch detection state and shift to PIU operation stop enabled mode PIU reset. Once the PADRST bit is set to 1, it is automatically cleared to 0 after four PCICLK cycles. 1: Reset 0: Normal 2 PIUSEQEN 1 PIUPWR 0 PADRST This register is used to make various settings for the PIU. The PENSTC bit indicates the touch panel contact state at the time when the PENCHGINTR bit of PIUINTREG register is set to 1. This bit's state remains as it is until PENCHGINTR bit is cleared to 0. Also, when PENCHGINTR bit is cleared to 0, PENSTC bit indicates the touch panel contact state. However, PENSTC bit does not change while PENCHGINTR bit is set to 1, even if the touch panel contact state changes between release and touch. Some bits in this register cannot be set in a specific state of scan sequencer. The combination of the setting of this register and the sequencer state is as follows. User's Manual U14579EJ2V0UM 133 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Table 9-2. PIUCNTREG Register Bit Manipulation and States PIUCNTREG Bit Manipulation PADRST PIUPWR Note 1 Scan Sequencer's State Disable - Standby ? x ? x x x x x x x x Standby Disable ? Disable Note 2 ? - - - - Note 4 WaitPenTouch Disable x x ? Standby Note 3 PenDataScan Disable x x ? Standby x x x x x x Note 5 01 01 10 PIUSEQEN 01 10 PADATSTART 01 10 PenDataScan - x x x x x x PADATSTOP 01 10 PADSCANSTART 01 10 PenDataScan - - - Scan Sequencer's State PADSCANSTOP 01 10 Standby - PIUCNTREG Bit Manipulation PADRST PIUPWR Note 1 IntervalNextScan Disable ? x ? Standby x x x x x x Note 5 ADPortScan Disable ? x ? Standby x x x x x x Note 5 CmdScan Disable ? x ? Standby x x x x x x Note 5 01 01 10 PIUSEQEN 01 10 PADATSTART 01 10 PADATSTOP 01 10 PADSCANSTART 01 10 PADSCANSTOP 01 10 Standby ? Standby - Standby - Notes 1. 2. 3. 4. 5. After 1 is written, the PADRST bit is automatically cleared to 0 after four PCICLK cycles. The transition to WaitPenTouch state occurs when the PIUMODE(1:0) area is 00, and the transition to CmdScan state occurs when the PIUMODE(1:0) area is 01. State transition occurs during touch state State transition occurs when PIUSEQEN = 1 State transition occurs after one set of data is sampled. The PADSCANSTOP bit is cleared to 0 after the state transition occurs. Remark -: The bit change is retained but there is no state transition. x: Setting prohibited (operation not guaranteed) ?: Combination of state and bit status before setting does not exist. 134 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.2 Bit PIUINTREG (base address + 0x0A4) 15 OVP R/W 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name 7 RFU 6 PADCMD INTR R/W 0 5 PADADP INTR R/W 0 4 PADPAGE1 INTER R/W 0 3 PADPAGE0 INTER R/W 0 2 PADDLOST INTR R/W 0 1 RFU 0 PENCHG INTR R/W 0 R/W After reset R 0 R 0 Bit 15 Name OVP Function Valid page ID bit (older valid page) 1: Valid data older than page 1 buffer data is retained 0: Valid data older than page 0 buffer data is retained Reserved. Write 0 to these bits. 0 is returned after a read. PIU command scan interrupt. Cleared to 0 when 1 is written. 1: Indicates that command scan found valid data 0: Indicates that command scan did not find valid data in buffer PIU A/D port scan interrupt. Cleared to 0 when 1 is written. 1: Indicates that A/D port scan found valid data with 1 value in buffer 0: Indicates that A/D port scan did not find valid data with 1 value in buffer PIU data buffer page 1 interrupt. Cleared to 0 when 1 is written. 1: Valid data with 1 value is stored in page 1 of data buffer 0: No valid data with 1 value in page 1 of data buffer PIU data buffer page 0 interrupt. Cleared to 0 when 1 is written. 1: Valid data with 1 value is stored in page 0 of data buffer 0: No valid data with 1 value in page 0 of data buffer Data lost interrupt. Cleared to 0 when 1 is written. 1: Not data with 1 value found within specified time 0: No timeout Reserved. Write 0 to this bit. 0 is returned after a read. Change in touch panel contact state interrupt. Cleared to 0 when 1 is written. 1: Change has occurred 0: No change 14:7 6 RFU PADCMDINTR 5 PADADPINTR 4 PADPAGE1INTER 3 PADPAGE0INTER 2 PADDLOSTINTR 1 0 RFU PENCHGINTR This register sets and indicates the interrupt request generation of PIU. When the TPY1 signal changes, the PENCHGINTR bit is set to 1. When the PENCHGINTR bit is set to1, the PENSTC bit indicates the touch panel contact state (touch or release) when a contact state changes. The PENSTC bit's state remains until PENCHGINTR bit is cleared to 0. Also, when PENCHGINTR bit is cleared to 0, PENSTC bit indicates the touch panel contact state. However, PENSTC bit does not change while PENCHGINTR bit is set to 1, even if the touch panel contact state changes between release and touch. User's Manual U14579EJ2V0UM 135 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Caution In the Suspend mode, the VRC4173 retains the touch panel state. Therefore, if the Suspend mode has been entered while the touch panel is touched, the contact state may be mistakenly recognized as having changed, when the Fullspeed mode returns. This may result in PENCHGINTR bit being set to 1, when a touch panel state change interrupt occurs immediately after the Fullspeed mode returns from the Suspend mode. Similarly, other bits of PIUINTREG register may be set to 1 on returning from the Suspend mode. Therefore, set each bit of PIUINTREG register to 1 to clear an interrupt request, immediately after the Fullspeed mode returns from the Suspend mode. 9.3.3 Bit PIUSIVLREG (base address + 0x0A6) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 SCAN INTVAL10 R/W 0 9 SCAN INTVAL9 R/W 0 8 SCAN INTVAL8 R/W 0 Name R/W After reset Bit Name R/W After reset 7 SCAN INTVAL7 R/W 1 6 SCAN INTVAL6 R/W 0 5 SCAN INTVAL5 R/W 1 4 SCAN INTVAL4 R/W 0 3 SCAN INTVAL3 R/W 0 2 SCAN INTVAL2 R/W 1 1 SCAN INTVAL1 R/W 1 0 SCAN INTVAL0 R/W 1 Bit 15:11 10:0 Name RFU SCANINTVAL(10:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Coordinate data scan interval time setting Sampling interval = SCANINTVAL(10:0) x 30 s This register sets the interval time (sampling interval) for coordinate data scan. The interval time for one pair of coordinate data is the value set via SCANINTVAL(10:0) multiplied by 30 s. Accordingly, the logical range of interval times that can be set in 30 s units is from 0 ms to about 60 ms. Actually, if the interval time setting is shorter than the time required for obtaining a pair of coordinate data or ADPScan data, a data lost interrupt will occur. If data lost interrupts occur frequently, set a longer interval time. Figure 9-5. Interval Times and States State Operation PenDataScan SASASASA IntervalNextScan ADPortScan ST AA IntervalNextScan T PenDataScan SASASASA Interval time Remark S: Voltage stabilization standby time (STABLE(5:0) bits in PIUSTBLREG register) A: A/D converter conversion time (about 10 s) T: Touch/release detection 136 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.4 Bit PIUSTBLREG (base address + 0x0A8) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 STABLE5 R/W 0 4 STABLE4 R/W 0 3 STABLE3 R/W 0 2 STABLE2 R/W 1 1 STABLE1 R/W 1 0 STABLE0 R/W 1 Bit 15:6 5:0 Name RFU STABLE(5:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Panel applied voltage stabilization standby time (PenDataScan, CmdScan state) A/D scan timeout time (ADPortScan state) Touch detection start standby time (Disable, WaitPenTouch, IntervalNextScan state) Standby time = STABLE(5:0) x 30 s The voltage stabilization standby time for the voltage applied to the touch panel can be set via STABLE(5:0) in 30 s units between 0 s and 1,890 s. User's Manual U14579EJ2V0UM 137 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.5 Bit PIUCMDREG (base address + 0x0AA) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 STABLEON R/W 0 11 TPYEN1 R/W 0 10 TPYEN0 R/W 0 9 TPXEN1 R/W 0 8 TPXEN0 R/W 0 Name R/W After reset Bit Name R/W After reset 7 TPYD1 R/W 0 6 TPYD0 R/W 0 5 TPXD1 R/W 0 4 TPXD0 R/W 0 3 ADCMD3 R/W 1 2 ADCMD2 R/W 1 1 ADCMD1 R/W 1 0 ADCMD0 R/W 1 Bit 15:13 12 Name RFU STABLEON Function Reserved. Write 0 to these bits. 0 is returned after a read. Touch panel applied voltage stabilization time set during command scan (STABLE(5:0) area of PIUSTBLREG register) enable 1: Retain panel voltage stabilization time 0: Ignore panel voltage stabilization time (voltage stabilization standby time = 0) TPY port output enable switching during command scan 11: TPY1 output, TPY0 output 10: TPY1 output, TPY0 OFF (Hi-Z) 01: TPY1 OFF (Hi-Z), TPY0 output 00: TPY1 OFF (Hi-Z), TPY0 OFF (Hi-Z) TPX port output enable switching during command scan 11: TPX1 output, TPX0 output 10: TPX1 output, TPX0 OFF (Hi-Z) 01: TPX1 OFF (Hi-Z), TPX0 output 00: TPX1 OFF (Hi-Z), TPX0 OFF (Hi-Z) TPY output level during command scan 11: TPY1 = High, TPY0 = High 10: TPY1 = High, TPY0 = Low 01: TPY1 = Low, TPY0 = High 00: TPY1 = Low, TPY0 = Low TPX output level during command scan 11: TPX1 = High, TPX0 = High 10: TPX1 = High, TPX0 = Low 01: TPX1 = Low, TPX0 = High 00: TPX1 = Low, TPX0 = Low A/D converter input port selection for command scan 1111: A/D converter standby mode request 1110: Reserved : 0100: Reserved 0011: AUDIOIN port 0010: ADIN port 0001: ADY port 0000: ADX port 11:10 TPYEN(1:0) 9:8 TPXEN(1:0) 7:6 TPYD(1:0) 5:4 TPXD(1:0) 3:0 ADCMD(3:0) This register switches input/output and sets output level for each port during a command scanning operation. Setting of the TPYD bit is invalid when the port output is set to OFF by the TPYEN bit. Setting of the TPXD bit is invalid when the port output is set to OFF by the TPXEN bit. 138 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.6 Bit PIUASCNREG (base address + 0x0B0) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 TPPSCAN 0 ADPS START R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 Bit 15:2 1 Name RFU TPPSCAN Function Reserved. Write 0 to these bits. 0 is returned after a read. Port selection for ADPortScan 1: Select ADX, ADY (for touch panel) as A/D port 0: Select ADIN (general-purpose) as A/D port and AUDIOIN as audio input port ADPortScan start 1: Start ADPortScan 0: Do not perform ADPortScan 0 ADPSSTART This register is used for ADPortScan setting. The ADPortScan begins when the ADPSSTART bit is set. After the ADPortScan is completed, the state returns to the state when ADPortScan was started. The ADPSSTART bit is automatically cleared to 0. If the ADPortScan is not completed within the time period set via PIUSTBLREG register's STABLE(5:0) area, a data lost interrupt occurs as a timeout interrupt. Caution TPPSCAN bit operation is only valid during Standby state. The operation is not guaranteed during other states. Some bits in this register cannot be set in a specific state of scan sequencer. The combination of the setting of this register and the sequencer state is as follows. User's Manual U14579EJ2V0UM 139 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) Table 9-3. PIUASCNREG Register Bit Manipulation and States PIUASCNREG Bit Manipulation ADPSSTART 01 10 TPPSCAN 01 10 PIUASCNREG Bit Manipulation ADPSSTART 01 10 TPPSCAN 01 10 Scan Sequencer's State Disable x x - - Standby Note WaitPenTouch x x - - PenDataScan x x - - ADPortScan Disable - - Scan Sequencer's State IntervalNextScan x x x ? ADPortScan Note CmdScan x x ? Standby ADPortScan Disable WaitPenTouch ? Note After ADPortScan is completed, the bit is automatically cleared to 0. Remark -: The bit change is retained but there is no state transition. x: Setting prohibited (operation not guaranteed) ?: Combination of state and bit status before setting does not exist. 140 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.7 Bit PIUAMSKREG (base address + 0x0B2) 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Name R/W After reset Bit Name R/W After reset 7 AUDINM R/W 0 6 RFU R 0 5 ADINM R/W 0 4 RFU R 0 3 ADYM R/W 0 2 RFU R 0 1 ADXM R/W 0 0 RFU R 0 Bit 15:8 7 Name RFU AUDINM Function Reserved. Write 0 to these bits. 0 is returned after a read. Audio input port mask 1: Mask 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. General-purpose A/D port mask 1: Mask 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. Touch panel A/D port (ADY) mask 1: Mask 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. Touch panel A/D port (ADX) mask 1: Mask 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. 6 5 RFU ADINM 4 3 RFU ADYM 2 1 RFU ADXM 0 RFU This register is used to set masking each A/D port. One bit corresponds to one port. When a port is masked (1), the analog data of that port is not converted into digital data. The setting of this register is valid only in the ADPortScan state. User's Manual U14579EJ2V0UM 141 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.8 Bit PIUCIVLREG (base address + 0x0BE) 15 RFU 14 RFU 13 RFU 12 RFU 11 RFU 10 CHECK INTVAL10 R 0 9 CHECK INTVAL9 R 0 8 CHECK INTVAL8 R 0 Name R/W After reset R 0 R 0 R 0 R 0 R 0 Bit Name 7 CHECK INTVAL7 R 1 6 CHECK INTVAL6 R 0 5 CHECK INTVAL5 R 1 4 CHECK INTVAL4 R 0 3 CHECK INTVAL3 R 0 2 CHECK INTVAL2 R 1 1 CHECK INTVAL1 R 1 0 CHECK INTVAL0 R 1 R/W After reset Bit 15:11 10:0 Name RFU CHECKINTVAL(10:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Interval count value This register is used for real-time reading of internal register values being counted down based on the PIUSIVLREG register setting. 142 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.9 PIUPBnmREG (base address + 0x0C0 to base address + 0x0CE, base address + 0x0DC to base address + 0x0DE) Remark n = 0, 1, m = 0 to 4 PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB04REG (base address + 0x0C0) (base address + 0x0C2) (base address + 0x0C4) (base address + 0x0C6) (base address + 0x0DC) 14 RFU R 0 13 RFU R 0 12 RFU R 0 PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUPB14REG 11 (base address + 0x0C8) (base address + 0x0CA) (base address + 0x0CC) (base address + 0x0CE) (base address + 0x0DE) 10 9 8 PADDATA8 R/W 0 Bit Name R/W After reset 15 VALID R/W 0 PADDATA11 PADDATA10 PADDATA9 R/W 0 R/W 0 R/W 0 Bit Name R/W After reset 7 PADDATA7 R/W 0 6 5 4 PADDATA4 R/W 0 3 PADDATA3 R/W 0 2 PADDATA2 R/W 0 1 PADDATA1 R/W 0 0 PADDATA0 R/W 0 PADDATA6 PADDATA5 R/W 0 R/W 0 Bit 15 Name VALID Function Indicates validity of data in page buffer 1: Valid 0: Invalid Reserved. Write 0 to these bits. 0 is returned after a read. A/D converter's sampling data 14:12 11:0 RFU PADDATA(11:0) These registers are used to store coordinate data or touch pressure data. There are four coordinate data buffers and one touch pressure data buffer, each of which holds two pages of coordinate data or pressure data, and the addresses (register addresses) where the coordinate data or the pressure data is stored are fixed. Read coordinate data from the corresponding register in a valid page. The VALID bit, which indicates when the data is valid, is automatically rendered invalid when the page buffer interrupt source (PADPAGE0INTR or PADPAGE1INTR bit in PIUINTREG register) is cleared to 0. Table 9-4 shows correspondences between the sampled data and the register in which the sampled data is stored. Table 9-4. Detected Data and Page Buffers Detected Data X- X+ Y- Y+ Z (Touch pressure) Page 0 Buffer PIUPB00REG PIUPB01REG PIUPB02REG PIUPB03REG PIUPB04REG Page 1 Buffer PIUPB10REG PIUPB11REG PIUPB12REG PIUPB13REG PIUPB14REG User's Manual U14579EJ2V0UM 143 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.3.10 PIUABnREG (base address + 0x0D0 to base address + 0x0D2) Remark n = 0, 1 PIUAB0REG PIUAB1REG Bit Name R/W After reset 15 VALID R/W 0 (base address + 0x0D0) (base address + 0x0D2) 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 10 9 8 PADDATA8 R/W 0 PADDATA11 PADDATA10 PADDATA9 R/W 0 R/W 0 R/W 0 Bit Name R/W After reset 7 PADDATA7 R/W 0 6 PADDATA6 R/W 0 5 PADDATA5 R/W 0 4 PADDATA4 R/W 0 3 PADDATA3 R/W 0 2 PADDATA2 R/W 0 1 PADDATA1 R/W 0 0 PADDATA0 R/W 0 Bit 15 Name VALID Indicates validity of data in buffer 1: Valid 0: Invalid Function 14:12 11:0 RFU PADDATA(11:0) Reserved. Write 0 to these bits. 0 is returned after a read. A/D converter's sampling data These registers are used to store general-purpose A/D port/audio input port sampling data or command scan data. There are two data buffers and the addresses (register address) where the data is stored are fixed. The VALID bit, which indicates when the data is valid, is automatically rendered invalid when the page buffer interrupt source (PADADPINTR bit in PIUINTREG register) is cleared. Table 9-5 shows correspondences between the sampled data and the register in which the sampled data is stored. Table 9-5. A/D Ports and Data Buffers Register During ADPortScan TPPSCAN = 0 PIUAB0REG PIUAB1REG ADIN AUDIOIN TPPSCAN = 1 ADX ADY CMDScanDATA - During CmdScan 144 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.4 Status Transfer Flow Be sure to reset the PIU before operating the scan sequencer. Setting initial values via a reset sets particular values for the sequence interval, etc., that are required. The following registers require initial settings. SCANINTVAL(10:0) area in PIUSITVLREG register STABLE(5:0) area in PIUSTBLREG register Interrupt mask cancellation settings are required for registers other than the PIU registers. Table 9-6. Mask Clear During Scan Sequencer Operation Setting Interrupt mask clear Unit ICU ICU Clock mask clear CMU Register MSYSINT1REG MPIUINTREG CMUCLKMSK Bit PIUINTR Bits 6:0 MSKPIU Value 1 0x7F 1 (1) Transfer flow for voltage detection at A/D general-purpose ports and audio input port Standby, WaitPenTouch, or IntervalNextScan state <1> PIUAMSKREG register <2> PIUASCNREG register ADPortScan state <3> PIUASCNREG register Standby, WaitPenTouch, or IntervalNextScan state (2) Transfer flow for auto scan coordinate detection Standby state <1> PIUCNTREG register PIUMODE(1:0) = 00 PADATSTART = 1 PADATSTOP = 1 <2> PIUCNTREG register WaitPenTouch state PIUSEQEN = 1 ADPSSTART = 0 Mask setting for A/D port and audio input port ADPSSTART = 1 User's Manual U14579EJ2V0UM 145 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (3) Transfer flow for manual scan coordinate detection Disable state <1> PIUCNTREG register Standby state <2> PIUCNTREG register <3> PIUCNTREG register PenDataScan state (4) Transfer flow during Suspend mode transition (WaitPenTouch state) WaitPenTouch state <1> Only waiting for the time set in PIUSTBLREG register's STABLE(5:0) area <2> Execution of the SUSPEND instruction (Touch panel contact status change interrupt request does not occur) (5) Transfer flow when returning from Suspend mode (WaitPenTouch state) WaitPenTouch state (Register setting and stabilization wait are not needed.) Touch detected PenDataScan state (6) Transfer flow during Suspend mode transition (Disable state) Standby, WaitPenTouch, or IntervalNextScan state <1> PIUCNTREG register Standby state <2> PIUCNTREG register Disable state <3> Only waiting for the time set in PIUSTBLREG register's STABLE(5:0) area <4> Execution of the SUSPEND instruction PIUPWR = 1 PIUSEQEN = 0 PIUMODE(1:0) = 00 PADSCANSTART = 1 PIUSEQEN = 1 PIUPWR = 1 146 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (7) Transfer flow when returning from Suspend mode (Disable state) Disable state <1> PIUCNTREG register Standby state <2> PIUCNTREG register PIUMODE(1:0) = 00 PADATSTART = 1 PADATSTOP = 1 <3> PIUCNTREG register WaitPenTouch state Touch detected PenDataScan state (8) Transfer flow of command scan Disable state <1> PIUCNTREG register Standby state <2> PIUCNTREG register <3> PIUCNTREG register <4> PIUCNTREG register CmdScan state PIUMODE(1:0) = 01 Touch panel pin setup and input port selection PIUSEQEN = 1 PIUPWR = 1 PIUSEQEN = 1 PIUPWR = 1 User's Manual U14579EJ2V0UM 147 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.5 Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States Table 9-7. Relationships Among TPX, TPY, ADX, ADY, TPEN, ADIN, and AUDIOIN Pins and States State PADSTATE(2:0) DisableNote Standby WaitPenTouch/ IntervalNextScan ADPortScan ADPortScan PadDataScan PadDataScan PadDataScan PadDataScan PadDataScan TPX1(ADX), TPX0 HH 00 HH TPY1(ADY), TPY0 D- 00 D- TPEN AUDIOIN, ADIN -- -- -- -I I- -- -- -- -- -- PIU disable (pen status detection) Low-power standby Pen status detection H L H Voltage detection at general-purpose AD port Voltage detection at audio input port TPY1 = H, TPY0 = L, ADX = samp (X+) TPY1 = L, TPY0 = H, ADX = samp (X-) TPX1 = H, TPX0 = L, ADY = samp (Y+) TPX1 = L, TPX0 = H, ADY = samp (Y-) Touch pressure detection (Z) 00 00 I- I- HL LH HH 00 00 HL LH I- I- d- L L L L L L H Note The states of pins are not guaranteed when the PADSTATE(2:0) area that precedes the CPU's SUSPEND instruction execution is in a state other then the Disable state. Remark 0: Low-level input 1: High-level input L: Low-level output H: High-level output l: A/D converter input D: Touch interrupt input (with a pull-down resistor) d: No touch interrupt input (with a pull-down resistor) -: don't care 148 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.6 9.6.1 Timing Touch/release detection timing Touch/release detection does not use the A/D converter but instead uses the voltage level of the TPY1 pin to determine the panel's touch/release state. The following figure shows a touch/release detection timing diagram. Figure 9-6. Touch/Release Detection Timing State Standby WaitPenTouch PenDataScan IntervalNextScan TPY, TPX (PADSCANTYPE = 0) TPY, TPX (PADSCANTYPE = 1) (TPY1) LowPower Touch detected X-, X+, Y-, Y+ Release detected LowPower L Touch detected 0 (Release) 1 (Touch) Z, X-, X+, Y-, Y+ Release detected 1 (Touch) 0 (Release) 9.6.2 A/D port scan timing The A/D port scan function sequentially scans the A/D converter's two input channel port pins and stores the data in the data buffer used for A/D port scanning. The following figure shows an A/D port scan timing diagram. Figure 9-7. A/D Port Scan Timing State XXX ADPortScan XXX AUDIOIN, ADIN ADPSSTART bit (PIUASCNREG) AUDIOIN, ADIN XXX state: Standby, WaitPenTouch, or IntervalNextScan User's Manual U14579EJ2V0UM 149 CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) 9.7 Data Lost Generation Conditions The PIU issues a data lost interrupt when any of the following four conditions exist. 1. 2. 3. 4. Data for one coordinate has not been obtained within the interval period The A/D port scan has not been completed within the time set via PIUSTBLREG register Transfer of the next coordinate data has begun while valid data for both pages remains in the buffer The next data transfer starts while there is valid data in the ADPortScan buffer Once a data lost interrupt occurs, the sequencer is forcibly changed to the Standby state. The causes and responses are shown below for the four conditions. (1) When data for one coordinate has not been obtained within the interval period (a) Cause This condition occurs when the AIU has exclusive use of the A/D converter and the PIU is therefore unable to use the A/D converter. If a data lost interrupt occurs frequently, implement a countermeasure that temporarily prohibits the AIU's use of the A/D converter. (b) Response After clearing the data lost interrupt by writing 1 to the PADDLOSTINTR bit of the PIUINTREG register, set the PIUCNTREG register's PADATSTART bit or PADSCANSTART bit to restart the coordinate detection operation. Once the data lost interrupt is cleared, the page in which the loss occurred becomes invalid. If the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt. (2) When the A/D port scan has not been completed within the time set via PIUSTBLREG register (a) Cause Same as cause of condition (1) (b) Response After clearing the data lost interrupt by writing 1 to the PADDLOSTINTR bit of the PIUINTREG register, set the PIUASCNREG register's ADPSSTART bit to restart the A/D port scan operation. Once the data lost interrupt is cleared, the page in which the loss occurred becomes invalid. If the valid data prior to the data loss is needed, be sure to save the data that is being stored in the page buffer before clearing the data lost interrupt. 150 User's Manual U14579EJ2V0UM CHAPTER 9 PIU (TOUCH PANEL INTERFACE UNIT) (3) When transfer of the next coordinate data has begun while valid data for both pages remains in the buffer (a) Cause This condition is caused when the data buffer contains two pages of valid data (both the data buffer page 1 and data buffer page 0 interrupts have occurred) but the valid data has not been processed. If the A/D converter is used frequently, this may shorten the time that would normally be required from when both pages become full until when the data loss occurs. (b) Response In condition (3), valid data contained in the pages when the interrupt occurs is never overwritten. After two pages of valid data are processed, write 1 to the PADPAGE0INTR, PADPAGE1INTR, and PADDLOSTINTR bits of the PIUINTREG register to clear the three interrupts. After clearing these interrupts, set the PADATSTART bit or PADSCANSTART bit of PIUCNTREG register to restart the coordinate detection operation. (4) When the next data transfer starts while there is valid data in the ADPortScan buffer (a) Cause This condition is caused when valid data is not processed even while the ADPortScan buffer holds valid data (A/D port scan interrupt occurrence). (b) Response In condition (4), valid data contained in the buffer when the interrupt occurs is never overwritten. After valid data in the buffer is processed, write 1 to the PADDLOSTINTR and PADADPINTR bits of the PIUINTREG register to clear the two interrupts. After clearing these interrupts, set the ADPSSTART bit of PIUASCNREG register to restart the generalpurpose A/D port scan. User's Manual U14579EJ2V0UM 151 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.1 General The AIU supports speaker output and MIC input. The settings related to A/D converter and D/A converter are also performed by AIU. The resolution of the D/A converter used for a speaker is 10 bits, and the resolution of the A/D converter used for a microphone is 12 bits. Caution As the A/D converter and D/A converter are exclusively controlled, recording and playback by AIU cannot be performed simultaneously. 10.2 Register Set Table 10-1 lists the AIU registers. Table 10-1. AIU Registers Address BASE + 0x0E0 BASE + 0x0E2 BASE + 0x0E6 BASE + 0x0E8 BASE + 0x0EA BASE + 0x0F0 BASE + 0x0F2 BASE + 0x0F4 BASE + 0x0F8 BASE + 0x0FA BASE + 0x0FC R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbol MDMADATREG SDMADATREG SODATREG SCNTREG SCNVRREG MIDATREG MCNTREG MCNVRREG DVALIDREG SEQREG INTREG MIC DMA Data Register Speaker DMA Data Register Speaker Output Data Register Speaker Output Control Register Speaker Conversion Rate Register MIC Input Data Register MIC Input Control Register MIC Conversion Rate Register Data Valid Register Sequential Register Interrupt Register Function Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. 152 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.1 MDMADATREG (base address + 0x0E0) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 MDMA11 R/W 1 10 MDMA10 R/W 0 9 MDMA9 R/W 0 8 MDMA8 R/W 0 Bit Name R/W After reset 7 MDMA7 R/W 0 6 MDMA6 R/W 0 5 MDMA5 R/W 0 4 MDMA4 R/W 0 3 MDMA3 R/W 0 2 MDMA2 R/W 0 1 MDMA1 R/W 0 0 MDMA0 R/W 0 Bit 15:12 11:0 Name RFU MDMA(11:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. MIC input DMA data This register is used prior to DMA transfer to store 12-bit data that has been converted by the A/D converter and stored in MIDATREG register. Write is used for debugging and is enabled when AIUMEN bit of SEQREG register is set to 1. This register is initialized (0x0800) by resetting AIUMEN bit of SEQREG register to 0. Therefore, if the AIUMEN bit is set to 0 during DMA transfer, invalid data may be transferred. 10.2.2 SDMADATREG (base address + 0x0E2) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 SDMA9 R/W 1 8 SDMA8 R/W 0 Bit Name R/W After reset 7 SDMA7 R/W 0 6 SDMA6 R/W 0 5 SDMA5 R/W 0 4 SDMA4 R/W 0 3 SDMA3 R/W 0 2 SDMA2 R/W 0 1 SDMA1 R/W 0 0 SDMA0 R/W 0 Bit 15:10 9:0 Name RFU SDMA(9:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Speaker output DMA data This register is used to store 10-bit DMA data for speaker output. When SODATREG register is empty, the data is transferred to SODATREG register. Write is used for debugging and is enabled when AIUSEN bit of SEQREG register is set to 1. This register is initialized (0x0200) by resetting AIUSEN bit of SEQREG register to 0. User's Manual U14579EJ2V0UM 153 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.3 SODATREG (base address + 0x0E6) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 SODAT9 R/W 1 8 SODAT8 R/W 0 Bit Name R/W After reset 7 SODAT7 R/W 0 6 SODAT6 R/W 0 5 SODAT5 R/W 0 4 SODAT4 R/W 0 3 SODAT3 R/W 0 2 SODAT2 R/W 0 1 SODAT1 R/W 0 0 SODAT0 R/W 0 Bit 15:10 9:0 Name RFU SODAT(9:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Speaker output data This register is used to store 10-bit data for speaker output. Data is received from SDMADATREG register and is sent to the D/A converter. Write is used for debugging and is enabled when AIUSEN bit of SEQREG register is set to 1. This register is initialized (0x0200) by resetting AIUSEN bit of SEQREG register to 0. 154 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.4 SCNTREG (base address + 0x0E8) Bit Name R/W After reset 15 DAENAIU R/W 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 SSTATE R 0 2 RFU R 0 1 SSTOPEN R/W 0 0 RFU R 0 Bit 15 Name DAENAIU Function This is the speaker D/A (DAAVREF connection) enable bit. 1: ON 0: OFF Reserved. Write 0 to these bits. 0 is returned after a read. Indicates speaker operation state 1: In operation 0: Stopped Reserved. Write 0 to this bit. 0 is returned after a read. Speaker output DMA transfer page boundary interrupt stop 1: Stop DMA request at 1-page boundary 0: Stop DMA request at 2-page boundary Reserved. Write 0 to this bit. 0 is returned after a read. 14:4 3 RFU SSTATE 2 1 RFU SSTOPEN 0 RFU This register is used to control the AIU's speaker block. The DAENAIU bit controls the connection of DAAVDD and DAAVREF input to ladder type resistors in the D/A converter. Setting this bit to 0 (OFF) allows low power consumption when not using the D/A converter. When using the D/A converter, this bit must be set to 1 following the sequence described in 10.3 Operation Sequence. The content of the SSTATE bit is valid only when the AIUSEN bit of SEQREG register is set to 1. User's Manual U14579EJ2V0UM 155 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.5 SCNVRREG (base address + 0x0EA) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 SCNVR2 R/W 0 1 SCNVR1 R/W 0 0 SCNVR0 R/W 0 Bit 15:3 2:0 Name RFU SCNVR(2:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. D/A conversion rate 111: Reserved : 101: Reserved 100: 8 ksps 011: Reserved 010: 44.1 ksps 001: 22.05 ksps 000: 11.025 ksps This register is used to select a conversion rate for the D/A converter. 156 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.6 MIDATREG (base address + 0x0F0) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 MIDAT11 R/W 1 10 MIDAT10 R/W 0 9 MIDAT9 R/W 0 8 MIDAT8 R/W 0 Bit Name R/W After reset 7 MIDAT7 R/W 0 6 MIDAT6 R/W 0 5 MIDAT5 R/W 0 4 MIDAT4 R/W 0 3 MIDAT3 R/W 0 2 MIDAT2 R/W 0 1 MIDAT1 R/W 0 0 MIDAT0 R/W 0 Bit 15:12 11:0 Name RFU MIDAT(11:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. MIC input data This register is used to store 12-bit MIC input data that has been converted by the A/D converter. Data is sent to MDMADATREG register and is received from the A/D converter. Write is used for debugging and is enabled when AIUMEN bit of SEQREG register is set to 1. This register is initialized (0x0800) by resetting AIUMEN bit of SEQREG register to 0. User's Manual U14579EJ2V0UM 157 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.7 MCNTREG (base address + 0x0F2) Bit Name R/W After reset 15 ADENAIU R/W 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 MSTATE R 0 2 RFU R 0 1 MSTOPEN R/W 0 0 ADREQAIU R 0 Bit 15 Name ADENAIU Function This is the MIC A/D (ADAVREFP connection) enable bit. 1: ON 0: OFF Reserved. Write 0 to these bits. 0 is returned after a read. Indicates MIC operation state 1: In operation 0: Stopped Reserved. Write 0 to this bit. 0 is returned after a read. MIC input DMA transfer page boundary interrupt stop 1: Stop DMA request at 1-page boundary 0: Stop DMA request at 2-page boundary A/D use request bit 1: Request 0: Normal 14:4 3 RFU MSTATE 2 1 RFU MSTOPEN 0 ADREQAIU This register is used to control the AIU's MIC block. The ADENAIU bit controls the connection of ADAVDD and ADAVREFP input to ladder type resistors in the A/D converter. Setting this bit to 0 (OFF) allows low power consumption when not using the A/D converter. When using the A/D converter, this bit must be set to 1 following the sequence described in 10.3 Operation Sequence. The content of the MSTATE bit is valid only when the AIUMEN bit of SEQREG register is set to 1. This unit has priority when a conflict occurs with the PIU in relation to A/D conversion requests. 158 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.8 MCNVRREG (base address + 0x0F4) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 MCNVR2 R/W 0 1 MCNVR1 R/W 0 0 MCNVR0 R/W 0 Bit 15:3 2:0 Name RFU MCNVR(2:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. A/D conversion rate 111: Reserved : 101: Reserved 100: 8 ksps 011: Reserved 010: 44.1 ksps 001: 22.05 ksps 000: 11.025 ksps This register is used to select a conversion rate for the A/D converter. User's Manual U14579EJ2V0UM 159 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.9 DVALIDREG (base address + 0x0F8) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 SODATV R/W 0 2 SDMAV R/W 0 1 MIDATV R/W 0 0 MDMAV R/W 0 Bit 15:4 3 Name RFU SODATV Function Reserved. Write 0 to these bits. 0 is returned after a read. This indicates when valid data has been stored in SODATREG register. 1: Valid data exists 0: No valid data This indicates when valid data has been stored in SDMADATREG register. 1: Valid data exists 0: No valid data This indicates when valid data has been stored in MIDATREG register. 1: Valid data exists 0: No valid data This indicates when valid data has been stored in MDMADATREG register. 1: Valid data exists 0: No valid data 2 SDMAV 1 MIDATV 0 MDMAV This register indicates when valid data has been stored in SODATREG, SDMADATREG, MIDATREG, or MDMADATREG register. If data has been written directly to SODATREG, SDMADATREG, MIDATREG, or MDMADATREG register via software, the bits in this register are not active, so write 1 via software. Write is used for debugging and is enabled when AIUSEN or AIUMEN bit of SEQREG register is set to 1. If AIUSEN bit = 0 or AIUMEN bit = 0 in SEQREG register, then SODATV bit = SDMAV bit = 0 or MIDATV bit = MDMAV bit = 0. 160 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.10 SEQREG (base address + 0x0FA) Bit Name R/W After reset 15 AIURST R/W 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 AIUMEN R/W 0 Note 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 AIUSENNote R/W 0 Bit 15 Name AIURST AIU reset via software 1: Reset 0: Normal Function 14:5 4 RFU AIUMEN Note Reserved. Write 0 to these bits. 0 is returned after a read. MIC block operation enable, DMA enable 1: Enable operation 0: Disable operation Reserved. Write 0 to these bits. 0 is returned after a read. Note 3:1 0 RFU AIUSEN Speaker block operation enable, DMA enable 1: Enable operation 0: Disable operation Note As the MIC block and speaker block cannot be operated simultaneously, do not set these bits to 1 at the same time. If both are set to 1, unintended data may be played back. This register is used to enable/disable the AIU's operation. User's Manual U14579EJ2V0UM 161 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.2.11 INTREG (base address + 0x0FC) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 MENDINTR R/W 0 10 MINTR R/W 0 9 MIDLEINTR R/W 0 8 MSTINTR R/W 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 SENDINTR R/W 0 2 SINTR R/W 0 1 SIDLEINTR R/W 0 0 RFU R 0 Bit 15:12 11 Name RFU MENDINTR Function Reserved. Write 0 to these bits. 0 is returned after a read. MIC DMA 2 page interrupt. Cleared to 0 when 1 is written. 1: Occurred 0: Normal MIC DMA 1 page interrupt. Cleared to 0 when 1 is written. 1: Occurred 0: Normal MIC idle interrupt (receive data loss). Cleared to 0 when 1 is written. 1: Occurred 0: Normal MIC receive complete interrupt. Cleared to 0 when 1 is written. 1: Occurred 0: Normal Reserved. Write 0 to these bits. 0 is returned after a read. SPEAKER DMA 2 page interrupt. Cleared to 0 when 1 is written. 1: Occurred 0: Normal SPEAKER DMA 1 page interrupt. Cleared to 0 when 1 is written. 1: Occurred 0: Normal SPEAKER idle interrupt (mute). Cleared to 0 when 1 is written. 1: Occurred 0: Normal Reserved. Write 0 to this bit. 0 is returned after a read. 10 MINTR 9 MIDLEINTR 8 MSTINTR 7:4 3 RFU SENDINTR 2 SINTR 1 SIDLEINTR 0 RFU This register is used to set/indicate whether AIU interrupts have occurred or not. When data is received from the A/D converter, MIDLEINTR bit is set if valid data still exists in MIDATREG register (MIDATV bit = 1). In this case, MIDATREG register is overwritten. MSTINTR bit is set when data is received in MDMADATREG register. When data is passed to the D/A converter, SIDLEINTR bit is set if there is no valid data in SODATREG register (SODATV bit = 0). However, this interrupt is valid only after AIUSEN bit = 1, after which SODATV bit = 1 in DVALIDREG register. 162 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.3 Operation Sequence 10.3.1 Output (Speaker) (1) When using DMA transfer <1> Set D/A conversion rate (SCNVR(2:0) area in SCNVRREG register = any value) <2> Set output data area to DMAAU <3> DMA enable in DCU <4> Set D/A converter's DAAVREF to ON (DAENAIU bit of SCNTREG register = 1) <5> Wait for DAAVREF resistor stabilization time (about 5 s) (use the RTC counter) Even if speaker power is set to ON and speaker operation is enabled (AIUSEN bit = 1) without waiting for DAAVREF resistor stabilization time, speaker output starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8 ksps) (s) In this case, however, a noise may occur when speaker power is set to ON. <6> Set speaker power to ON via GPIO <7> Speaker operation enable (AIUSEN bit of SEQREG register = 1) When the speaker operation is enabled, the following internal operations occur. 1. DMA request 2. Receive acknowledge and DMA data from DMA * DVALIDREG register's SDMAV bit = SODATV bit = 1 3. Output 10-bit data (SODAT(9:0) area in SODATREG register) to D/A converter * SODATV bit = 0, SDMAV bit = 1 * Send SDMADATREG register data to SODATREG register. * SODATV bit = 1, SDMAV bit = 0 4. Output DMA request and store the data after the next into SDMADATREG register. * SODATV bit = 1, SDMAV bit = 1 5. Refresh data at each conversion timing interval * Becomes SIDLEINTR bit = 1 when DMA is slow and SODATV bit = 0 during conversion timing interval, and (mute) interrupt occurs 6. DMA page boundary interrupt occurs at page boundary * Clear the page interrupt request to continue output. <8> Speaker operation disable (AIUSEN bit of SEQREG register = 0) <9> Set speaker power to OFF via GPIO <10> Set D/A converter's DAAVREF to OFF (DAENAIU bit of SCNTREG register = 0) <11> DMA disable in DCU User's Manual U14579EJ2V0UM 163 CHAPTER 10 AIU (AUDIO INTERFACE UNIT) Figure 10-1. Speaker Output and AUDIOOUT Pin AUDIOOUT <1> <2> <3> <4> <5> <6> <7> <8><9> <10> <11> VDD/2 Time (2) When not using DMA transfer <1> Enable clock supply to AIU in CMU <2> Set D/A conversion rate (SCNVR(2:0) area in SCNVRREG register = any value) <3> DMA disable in DCU (disable set as initial value) <4> Set D/A converter's DAAVREF to ON (DAENAIU bit of SCNTREG register = 1) <5> Wait for DAAVREF resistor stabilization time (about 5 s) <6> Set speaker power to ON via GPIO <7> Speaker operation enable (AIUSEN bit of SEQREG register = 1) Sampling counter begins to count up <8> Set data to SODATREG register <9> Speaker operation disable (AIUSEN bit of SEQREG register = 0) <10> Set speaker power to OFF via GPIO <11> Set D/A converter's DAAVREF to OFF (DAENAIU bit of SCNTREG register = 0) Remark The interrupt request caused by mute is valid after setting AIUSEN bit = 1 and then SODATV bit = 1. However, SODATV bit does not become 1 until DVALIDREG register is written by the DMA or software. Therefore mute interrupt requests will not occur as long as DMA is disabled and SODATV bit is not converted by software. 164 User's Manual U14579EJ2V0UM CHAPTER 10 AIU (AUDIO INTERFACE UNIT) 10.3.2 Input (MIC) <1> Set A/D conversion rate (MCNVR(2:0) area in MCNVRREG register = any value) <2> Set input data area in DMAAU <3> DMA enable in DCU <4> Set A/D converter's ADAVREFP to ON (ADENAIU bit of MCNTREG register = 1) MIC power can be set ON and MIC operation can be enabled (AIUMEN bit = 1) without waiting for ADAVREFP resistor stabilization time (about 5 s). However, in such a case, sampling starts after the period calculated with the formula below. 5 + 1/conversion rate (44.1, 22.05, 11.025, or 8 ksps) (s) <5> Set MIC power to ON via GPIO. <6> MIC operation enable (AIUMEN bit of SEQREG register = 1) When the MIC operation is enabled, the following internal operations occur. 1. Output A/D conversion request to A/D converter 2. Return acknowledge and 12-bit conversion data from A/D converter. 3. Store data in MIDATREG register. * DVALIDREG register's MDMAV bit = 0, MIDATV bit = 1 4. Transfer data from MIDATREG register to MDMADATREG register. * MDMAV bit = 1, MIDATV bit = 0 * The INTMST bit becomes 1 and an interrupt (receive complete) occurs. 5. Issue DMA request and store MIDMADATREG register data to memory. * MDMAV bit = 0, MIDATV bit = 0 6. An A/D request is issued once per conversion timing interval and 12-bit data is received * Becomes MIDLEINTR bit = 1 when DMA is slow and MIDATV bit = 1 during conversion timing interval, and (data loss) interrupt occurs 7. DMA page boundary interrupt occurs at page boundary * Clear the page interrupt request to continue output. <7> MIC operation disable (AIUMEN bit of SEQREG register = 0) <8> Set MIC power to OFF via GPIO. <9> Set A/D converter's ADAVREFP to OFF (ADENAIU bit of MCNTREG register = 0) <10> DMA disable in DCU Figure 10-2. AUDIOIN Pin and MIC Operation <1> to <3> <4> <5> <6> AUDIOIN <7> <8> <9><10> Sampling Time User's Manual U14579EJ2V0UM 165 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.1 General The KIU includes 12 scan lines and 8 detection lines. The number of key inputs to be detected can be selected from 96/80/64, by switching the number of scan lines from 12/10/8. The register can be set to enable the 12 scan lines to be used as a general-purpose I/O port or PS/2 interface signals. For details, see CHAPTER 8 GIU (GENERAL-PURPOSE I/O UNIT). 11.2 Register Set Table 11-1 lists the KIU registers. Table 11-1. KIU Registers Address BASE + 0x100 BASE + 0x102 BASE + 0x104 BASE + 0x106 BASE + 0x108 BASE + 0x10A BASE + 0x110 BASE + 0x112 BASE + 0x114 BASE + 0x116 BASE + 0x118 BASE + 0x11A BASE + 0x11E R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W W R/W Register Symbol KIUDAT0 KIUDAT1 KIUDAT2 KIUDAT3 KIUDAT4 KIUDAT5 KIUSCANREP KIUSCANS KIUWKS KIUWKI KIUINT KIURST SCANLINE KIU Data0 Register KIU Data1 Register KIU Data2 Register KIU Data3 Register KIU Data4 Register KIU Data5 Register KIU Scan/Repeat Register KIU Scan Status Register KIU Wait Keyscan Stable Register KIU Wait Keyscan Interval Register KIU Interrupt Register KIU Reset Register KIU Scan Line Register Function Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. 166 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.1 KIUDATn (base address + 0x100 to base address + 0x10A) Remark n = 0 to 5 KIUDAT0 (base address + 0x100) KIUDAT1 (base address + 0x102) KIUDAT2 (base address + 0x104) KIUDAT3 (base address + 0x106) KIUDAT4 (base address + 0x108) KIUDAT5 (base address + 0x10A) 15 KEYDAT15 R/W 0 14 KEYDAT14 R/W 0 13 KEYDAT13 R/W 0 12 KEYDAT12 R/W 0 11 KEYDAT11 R/W 0 10 KEYDAT10 R/W 0 9 KEYDAT9 R/W 0 8 KEYDAT8 R/W 0 Bit Name R/W After reset Bit Name R/W After reset 7 KEYDAT7 R/W 0 6 KEYDAT6 R/W 0 5 KEYDAT5 R/W 0 4 KEYDAT4 R/W 0 3 KEYDAT3 R/W 0 2 KEYDAT2 R/W 0 1 KEYDAT1 R/W 0 0 KEYDAT0 R/W 0 Bit 15:8 7:0 Name KEYDAT(15:8) KEYDAT(7:0) Function Scan data from odd-numbered scans (scan by KSCAN1, 3, 5, 7, 9, or 11 pin) Scan data from even-numbered scans (scan by KSCAN0, 2, 4, 6, 8, or 10 pin) These registers are used to hold key scan data. Each KIU data register is able to hold the data from one scan operation. How scan data is input to the registers is as below. Figure 11-1 shows a scan operation and storing timing. Register KIUDAT0 Bits KEYDAT(7:0) KEYDAT(15:8) KIUDAT1 KEYDAT(7:0) KEYDAT(15:8) KIUDAT2 KEYDAT(7:0) KEYDAT(15:8) KIUDAT3 KEYDAT(7:0) KEYDAT(15:8) KIUDAT4 KEYDAT(7:0) KEYDAT(15:8) KIUDAT5 KEYDAT(7:0) KEYDAT(15:8) Data Stores the data scanned by the KSCAN0 pin. Stores the data scanned by the KSCAN1 pin. Stores the data scanned by the KSCAN2 pin. Stores the data scanned by the KSCAN3 pin. Stores the data scanned by the KSCAN4 pin. Stores the data scanned by the KSCAN5 pin. Stores the data scanned by the KSCAN6 pin. Stores the data scanned by the KSCAN7 pin. Stores the data scanned by the KSCAN8 pin. Stores the data scanned by the KSCAN9 pin. Stores the data scanned by the KSCAN10 pin. Stores the data scanned by the KSCAN11 pin. User's Manual U14579EJ2V0UM 167 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) The data in the KIUDAT00 to KIUDAT05 registers should be read out in the interval time between two key scan operations. Scan interval is set by the KIUWKI register. When data is not read before the next key scan operation starts, the key scan data lost interrupt occurs (see 11.2.6). The data registers KIUDAT00 through KIUDAT05 overwrite the following scan data. Figure 11-1. Scan Operation and Key Data Store Register KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4 KSCAN3 KSCAN2 KSCAN1 KSCAN0 KPORT(7:0) Stored to KIUDAT5(15:8) Stored to KIUDAT5(7:0) Stored to KIUDAT4(15:8) Stored to KIUDAT4(7:0) Stored to KIUDAT3(15:8) Stored to KIUDAT3(7:0) Stored to KIUDAT2(15:8) Stored to KIUDAT2(7:0) Stored to KIUDAT1(15:8) Stored to KIUDAT1(7:0) Stored to KIUDAT0(15:8) Stored to KIUDAT0(7:0) 168 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.2 KIUSCANREP (base address + 0x110) Bit Name R/W After reset 15 KEYEN R/W 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 STPREP5 R/W 0 8 STPREP4 R/W 0 Bit Name R/W After reset 7 STPREP3 R/W 0 6 STPREP2 R/W 0 5 STPREP1 R/W 0 4 STPREP0 R/W 0 3 SCANSTP R/W 0 2 SCANSTART R/W 0 1 ATSTP R/W 0 0 ATSCAN R/W 1 Bit 15 Name KEYEN Key scan enable 1: Enable 0: Disable Function 14:10 9:4 RFU STPREP(5:0) Reserved. Write 0 to these bits. 0 is returned after a read. KIU sequencer stop count setting 111111: 63 times : 000001: 1 time 000000: Reserved Key scan stop 1: Stop 0: Operate Key scan start 1: Start 0: Stop Key auto stop setting 1: Auto stop 0: Not auto stop Key auto scan setting 1: Auto scan 0: Not auto scan 3 SCANSTP 2 SCANSTART 1 ATSTP 0 ATSCAN This register is used to enable operation of the key scan unit and to make settings for key scan and the KIU sequencer. When the number of scan lines is set to 0 in the SCANLINE register, the KEYEN bit cannot be set to 1. Each mode is described in detail below. User's Manual U14579EJ2V0UM 169 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) * Key scan stop The SCANSTP bit should be set to 1 when the KIU sequencer stops the key scan operation in Scanning or IntervalNextScan mode. When this bit is set to 1, the key scan operation stops. However, if this bit is set to 1 during a key scan operation, the KIU sequencer stops after the current set of key data is received. This bit becomes 0 when the key scan operation stops. When the key scan operation is started by setting this bit to 1 during Stopped or WaitKeyIn state, the key scan operation stops immediately after a set of key scan operation is completed. * Key scan start When the SCANSTART bit is set to 1, the KIU sequencer starts regardless of key contact detection. This bit becomes 0 when the key scan operation starts. This bit cannot be set while the KEYEN bit is 0. * Key scan auto stop setting In the key scan auto stop mode, the key scan operation stops automatically when the data of all zeros is input to the KPORT(7:0) pins (no key contact is detected). The number of zeros is set by the STPREP(5:0) area. * Key auto scan setting When the ATSCAN bit is set to 1, the key touch wait state is entered, and key scan operation starts automatically upon a key touch (1 is input to any of the KPORT(7:0) pins). When the KEYEN bit is 0, the key touch wait state is not entered even if this bit is set to 1. The key wait state is entered and the key auto scan mode is set from the point when the KEYEN bit is set to 1. For details, see Figure 11-4 Transition of Sequencer Status and Figure 11-5 Basic Operation Timing Chart. 170 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.3 KIUSCANS (base address + 0x112) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 SSTAT1 R 0 0 SSTAT0 R 0 Bit 15:2 1:0 Name RFU SSTAT(1:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. KIU sequencer status 11: Scanning 10: IntervalNextScan 01: WaitKeyIn 00: Stopped This register indicates the current KIU sequencer status. Details of the status of the KIU sequencer are described below. * Scanning: This is the state where the KIU sequencer performs key scan to load key data. Note * IntervalNextScan: This is the state where the scan of a set of key data has completed and the start of the next key scan is being waited for. The interval time is set in the KIUWKI register. Note The number of bits differs according to the number of KSCAN pins used. The number of KSCAN pins is set in the SCANLINE register. KSCAN Pins 8 10 12 Data Bits 64 bits 80 bits 96 bits User's Manual U14579EJ2V0UM 171 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) * WaitKeyIn: This is the state of waiting for key input in the key auto scan mode. When the ATSCAN bit of the KIUSCANREP register is set to 1 and the KIU sequencer is enabled, key input is waited for. In this state, all the KSCAN pin Note outputs are high level. Prior to shifting the CPU into Suspend mode, KIU must always be set in auto scan mode and whether the state of the sequencer is WaitKeyIn must be confirmed. Note The setting of the SCANLINE register's LINE(1:0) area determines the number of KSCAN pins used, as follows. LINE(1:0) 10 01 00 * Stopped: KSCAN Pins 8 10 12 This is the state where the KIU sequencer is disabled. 172 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.4 KIUWKS (base address + 0x114) Bit Name R/W After reset 15 RFU R 0 14 T3CNT4 R/W 1 13 T3CNT3 R/W 1 12 T3CNT2 R/W 1 11 T3CNT1 R/W 1 10 T3CNT0 R/W 1 9 T2CNT4 R/W 1 8 T2CNT3 R/W 1 Bit Name R/W After reset 7 T2CNT2 R/W 1 6 T2CNT1 R/W 1 5 T2CNT0 R/W 1 4 T1CNT4 R/W 1 3 T1CNT3 R/W 1 2 T1CNT2 R/W 1 1 T1CNT1 R/W 1 0 T1CNT0 R/W 1 Bit 15 14:10 Name RFU T3CNT(4:0) Function Reserved. Write 0 to this bit. 0 is returned after a read. Wait time setting ((T3CNT(4:0) + 1) x 30 s) 11111: 960 s : 00001: 60 s 00000: Reserved Off time setting ((T2CNT(4:0) + 1) x 30 s) 11111: 960 s : 00001: 60 s 00000: Reserved Stabilization time setting ((T1CNT(4:0) + 1) x 30 s) 11111: 960 s : 00001: 60 s 00000: Reserved 9:5 T2CNT(4:0) 4:0 T1CNT(4:0) This register is used to set the wait time between when the KIU sequencer sets the KSCAN signal active during a key matrix scan and when the status is read from the KPORT signal. The T1CNT(4:0) area is used to set the stabilization time between when the KSCAN signal becomes high and when the key scan data is read. The T2CNT(4:0) area is used to set the time between when the key data is read and when the KSCAN signal becomes high impedance. The T3CNT(4:0) area is used to set the time between when the KSCAN signal becomes high impedance and when it becomes high again. The status of output from the KSCAN signal and the timing of KPORT signal sampling are shown below. User's Manual U14579EJ2V0UM 173 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) Figure 11-2. KSCAN Signal Status and KPORT Signal Sampling Timing : : KSCAN1 (output) KSCAN0 (output) Hi-Z T1CNT T2CNT T3CNT Hi-Z Hi-Z Hi-Z Sampling timing KPORT(7:0) (input) 174 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.5 KIUWKI (base address + 0x116) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 WINTVL9 R/W 0 8 WINTVL8 R/W 0 Bit Name R/W After reset 7 WINTVL7 R/W 0 6 WINTVL6 R/W 0 5 WINTVL5 R/W 0 4 WINTVL4 R/W 0 3 WINTVL3 R/W 0 2 WINTVL2 R/W 0 1 WINTVL1 R/W 0 0 WINTVL0 R/W 0 Bit 15:10 9:0 Name RFU WINTVL(9:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Key scan interval time setting (WINTVL(9:0) x 30 s) 1111111111: 30,690 s : 0000000001: 30 s 0000000000: No wait This register is used to set the interval time between when one set of key data is obtained by the KIU sequencer and when the next set of key data is obtained. The following figure shows the key scan interval time. Figure 11-3. Key Scan Interval Key scan interval time KSCAN11 (output) KSCAN10 (output) : : KSCAN1 (output) KSCAN0 (output) 1 set of key scan data 1 set of key scan data : : User's Manual U14579EJ2V0UM 175 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.6 KIUINT (base address + 0x118) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 KDATLOST R/W 0 1 KDATRDY R/W 0 0 SCANINT R/W 0 Bit 15:3 2 Name RFU KDATLOST Function Reserved. Write 0 to these bits. 0 is returned after a read. Key scan data lost interrupt. Cleared to 0 when 1 is written. 1: Yes 0: No Key data scan complete interrupt. Cleared to 0 when 1 is written. 1: Yes 0: No Key input detection interrupt. Cleared to 0 when 1 is written. 1: Yes 0: No 1 KDATRDY 0 SCANINT This register indicates the type of interrupt that has occurred in the KIU. The key scan data lost interrupt occurs when data is not read out from the KIU data register (KIUDAT0 through KIUDAT5) between when data is input to the KIU data register after a key scan and when the next scan operation starts. The contents of the KIU data registers are overwritten to the new key scan data. Key data scan complete interrupt occurs when all the key data is input after one scan operation is completed. Key input detection interrupt occurs in the key auto scan mode when a key touch is detected (1 is detected from any of the KPORT(7:0) pins) in the key touch wait state, when a key scan operation starts after setting the start of key scan, or when a key scan operation starts after returning from the Suspend mode upon key touch detection. 176 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.7 KIURST (base address + 0x11A) Bit Name R/W After reset 15 RFU R Undefined 14 RFU R Undefined 13 RFU R Undefined 12 RFU R Undefined 11 RFU R Undefined 10 RFU R Undefined 9 RFU R Undefined 8 RFU R Undefined Bit Name R/W After reset 7 RFU R Undefined 6 RFU R Undefined 5 RFU R Undefined 4 RFU R Undefined 3 RFU R Undefined 2 RFU R Undefined 1 RFU R Undefined 0 KIURST W 0 Bit 15:1 0 Name RFU KIURST Function Reserved. Write 0 to these bits. The value is undefined after a read. KIU reset. Cleared to 0 when 1 is written. 1: Reset 0: Normal operation This register is used to reset the KIU registers. User's Manual U14579EJ2V0UM 177 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) 11.2.8 SCANLINE (base address + 0x11E) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 LINE1 R/W 0 0 LINE0 R/W 0 Bit 15:2 1:0 Name RFU LINE(1:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. KSCAN pin use/do not use setting 11: Do not use KSCAN pins for key scan (All the KSCAN pins are used as general-purpose I/O ports or PS/2 ports) 10: Use eight key scan pins (KSCAN(7:0)) (Supports 64 keys, the remaining four pins can be used as PS/2 port) 01: Use ten key scan pins (KSCAN(9:0)) (Supports 80 keys, the remaining two pins can be used as PS2CH1 port) 00: Use twelve key scan pins (KSCAN(11:0)) (Supports 96 keys, no pins can be used as general-purpose I/O port and PS/2 port) This register is used to switch the number of scan lines. Select the alternate function pins with the SELECTREG register of the GIU (see 8.2.15). 178 User's Manual U14579EJ2V0UM CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) Figure 11-4. Transition of Sequencer Status Reset (software reset) (KEYEN = 0)Note 1 < Stopped > KEYEN: SCANSTP: SCANSTART: ATSTP: ATSCAN: (software reset) 0 0 0 0 1 (KEYEN = 0) (set KEYEN = 0) or (software reset) (set KEYEN = 1)Note 2 Note 3 < WaitKeyIn > KEYEN: 1 SCANSTP: 0 SCANSTART: 0 ATSTP: 1 or 0 ATSCAN: 1 (set SCANSTP = 1)Note 5 or (set ATSTP = 1 and stop repeat number full) < Scanning > KEYEN: SCANSTP: SCANSTART: ATSTP: ATSCAN: (SCANSTP = 1)Note 4 (set SCANSTART = 1)Note 6 or (set ATSCAN = 1 and KPORT touch) (1 cycle scan end) 1 0 0 1 or 0 1 (next scan start) < IntervalNextScan > KEYEN: 1 SCANSTP: 0 SCANSTART: 0 ATSTP: 1 or 0 ATSCAN: 1 WAIT INTERVAL COUNT WAIT KEYSCAN STABLE COUNT 1 cycle scanning STOP REPEAT NUMBER COUNT (STPREP) Remark Stopped: WaitKeyIn: IntervalNextScan: Scanning: KEYEN: STPREP: SCANSTP: SCANSTART: ATSTP: ATSCAN: software reset: KPORT touch: stop repeat number full: KIUSCANS register bit 1 = 0, bit 0 = 0 KIUSCANS register bit 1 = 0, bit 0 = 1 KIUSCANS register bit 1 = 1, bit 0 = 0 KIUSCANS register bit 1 = 1, bit 0 = 1 KIUSCANREP register bit 15 KIUSCANREP register bits 9, 8, 7, 6, 5, 4 KIUSCANREP register bit 3 KIUSCANREP register bit 2 KIUSCANREP register bit 1 KIUSCANREP register bit 0 KIURST register bit 0 = 1 write When any of KPORT(7:0) signals is 1 When the scan data is 0 for the number of times specified by the STPREP register Notes 1. When the KEYEN is set to 0 during a scanning operation, the status changes to the Stopped status after that scanning operation has completed. 2. The KEYEN bit cannot be set to 1 while both bits 1 and 0 of the SCANLINE register are 1. 3. When the status changes from the WaitKeyIn mode to the Scanning mode after the SCANSTP bit is set to 1, the status returns to the WaitKeyIn mode again after scanning a set of data. 4. When the SCANSTP bit is set to 1 in the IntervalNextScan mode, the status changes to the WaitKeyIn mode and the SCANSTP bit becomes 0 simultaneously. 5. If the SCANSTP bit is set to 1 during a scanning operation, that one set of data scanning is continued. After this scanning is completed, the status changes to the WaitKeyIn mode and the SCANSTP bit becomes 0 automatically. 6. The SCANSTART bit becomes automatically 0 when the status changes to the Scanning mode, except if the SCANSTART bit was set to 1 during the IntervalNextScan or Scanning mode. User's Manual U14579EJ2V0UM 179 180 KSCAN11 KSCAN10 KSCAN9 KSCAN8 KSCAN7 KSCAN6 KSCAN5 KSCAN4 KSCAN3 KSCAN2 KSCAN1 KSCAN0 KPORT(7:0) KDATARDY interrupt SCANINT interrupt KIUDAT register read According to the alternate function pin setting Figure 11-5. Basic Operation Timing Chart (1/2) (a) Auto Start/Auto Stop Setting the KIUWKS register Setting the KIUWKI register KIUSCANREP register setting * ATSTART = 1 * ATSTP = 1 * STPREP(5:0) = 000001 SCANLINE register setting * LINE(1:0) = 10 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) User's Manual U14579EJ2V0UM KEYEN = on Key touch wait ATSCAN bit ATSTP bit H Key touch scanint occurs Scan starts rdyint occurs Key data register read The next scanning starts after the interval time elapsed The data of all zeros is detected once by a scanning operation The key touch off state continues for the period specified by the STOPREP register, then scanning stops and waits for a key touch detection KEYEN = off Transition of KIU status (KIUSCANS register) Stopped WaitKeyIn Scanning Scanning IntervalNextScan (set by the KIUWKI register) Scanning WaitKeyIn Stopped Figure 11-5. Basic Operation Timing Chart (2/2) (b) Key Scan Start/Key Scan Stop KSCAN11 Setting the KIUWKS register KSCAN10 KSCAN9 KSCAN8 According to the alternate function pin setting Setting the KIUWKI register SCANLINE register setting * LINE(1:0) = 10 CHAPTER 11 KIU (KEYBOARD INTERFACE UNIT) KSCAN7 KSCAN6 KSCAN5 KSCAN4 KSCAN3 KSCAN2 KSCAN1 KSCAN0 KPORT(7:0) KDATARDY interrupt SCANINT interrupt KIUDAT register read User's Manual U14579EJ2V0UM KEYEN = on Scan starts scanint occurs Scan starts rdyint occurs Key data register read The next scanning starts after the interval time elapsed The scanning operation stops The scanning operation stops after the scanning during which the SCANSTP bit is set to 1 is completed KEYEN = off SCANSTART bit SCANSTP bit This signal becomes 0 in asynchronous with the scanning stop Transition of KIU status (KIUSCANS register) Stopped WaitKeyIn Scanning Scanning IntervalNextScan (set by the KIUWKI register) Scanning WaitKeyIn Stopped 181 CHAPTER 12 PS2U (PS/2 UNIT) 12.1 General The PS2U controls the PS/2 interface with two channels, PS2CH1 and PS2CH2. The PS/2 interface performs bidirectional data transfers by using the PS2CLK1n and PS2DATA1n signals (n = 1, 2). The PS2U pins are alternate function pins that are shared with the KIU pins. Use the SELECTREG register of the GIU (see 8.2.15) to select the functions of the alternate function pins. 12.2 Register Set Table 12-1 lists the PS2CH1 registers (for channel 1). Table 12-2 lists the PS2CH2 registers (for channel 2). Table 12-1. PS2CH1 Registers Physical Address BASE + 0x120 BASE + 0x122 BASE + 0x124 R/W R/W R/W W Register Symbol PS2CH1DATA PS2CH1CTRL PS2CH1RST Function PS/2 channel 1 transmission/reception data register PS/2 channel 1 control register PS/2 channel 1 reset register Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). Table 12-2. PS2CH2 Registers Physical Address BASE + 0x140 BASE + 0x142 BASE + 0x144 R/W R/W R/W W Register Symbol PS2CH2DATA PS2CH2CTRL PS2CH2RST Function PS/2 channel 2 transmission/reception data register PS/2 channel 2 control register PS/2 channel 2 reset register Remark BASE: Base address. This is set by using the BADR register of the BCU (see 3.2.11). These registers are described in detail below. 182 User's Manual U14579EJ2V0UM CHAPTER 12 PS2U (PS/2 UNIT) 12.2.1 PS2CHnDATA (base address + 0x120, base address + 0x140) Remark n = 1, 2 PS2CH1DATA (base address + 0x120) PS2CH2DATA (base address + 0x140) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 PSDATA7 R/W 0 6 PSDATA6 R/W 0 5 PSDATA5 R/W 0 4 PSDATA4 R/W 0 3 PSDATA3 R/W 0 2 PSDATA2 R/W 0 1 PSDATA1 R/W 0 0 PSDATA0 R/W 0 Bit 15:8 7:0 Name RFU PSDATA(7:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. PS/2 transmission/reception data When writing: Transmission data When reading: Reception data This register stores transmission data that is output from the PS2DATAn pins or reception data that is input to the PS2DATAn pins (n = 1, 2). Reception data can be obtained by reading this register. The PS2U can transmit/receive data in the following pattern. Figure 12-1. Data Pattern PS2DATA1, PS2DATA2 (I/O) Start bit Data0 Data1 Data7 Parity Stop bit User's Manual U14579EJ2V0UM 183 CHAPTER 12 PS2U (PS/2 UNIT) 12.2.2 PS2CHnCTRL (base address + 0x122, base address + 0x142) Remark n = 1, 2 PS2CH1CTRL (base address + 0x122) PS2CH2CTRL (base address + 0x142) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 PERR R 0 4 RVEN R/W 0 3 INTEN R/W 0 2 PS2EN R/W 0 1 TEMT R 0 0 REMT R 0 Bit 15:6 5 Name RFU PERR Function Reserved. Write 0 to these bits. 0 is returned after a read. Reception data parity error detection (valid only when REMT bit = 1, even parity). 1: An error is detected 0: No error is detected Allows/denies use of reception FIFO. 1: Use 0: Do not use Enables/disables interrupt request detection. 1: Enable 0: Disable Enables/disables use of PS/2 interface. 1: Disable 0: Enable Transmission data ready 1: Transmission data exists 0: No transmission data exists Reception data ready 1: Reception data exists 0: No reception data exists 4 RVEN 3 INTEN 2 PS2EN 1 TEMT 0 REMT This register is used to set various types of controls and display status information for the PS/2 interface. When the PS2EN bit is set to 0, data can be transmitted/received by using the PS/2 interface. When the RVEN bit is 1, the reception FIFO (8 bits x 8 stages) is used. When data is received from an external source, the REMT bit becomes 1, which indicates that reception data exists in the PS2CHnDATA register (n = 1, 2). This bit is cleared to 0 by reading the reception data. When the reception FIFO is used, this bit is cleared to 0 when all reception data is read and the FIFO is empty. 184 User's Manual U14579EJ2V0UM CHAPTER 12 PS2U (PS/2 UNIT) The INTEN bit controls whether detection of reception completion interrupt requests is enabled or disabled. If the INTEN bit is 1, when the reception of one group of data from the PS2DATAn pins is completed, the REMT bit is set to 1 and an interrupt request is reported to the CPU at the same time (n = 1, 2). When the CPU reads the reception data from the PS2CHnDATA register, it inactivates the interrupt request signal (n = 1, 2). The PERR bit is set to 1 when a parity error is detected for the reception data. Be sure to always confirm the PERR bit before reading reception data. Before setting this register, use the SELECTREG register of the GIU (see 8.2.15) to set the alternate-function pins. 12.2.3 PS2CHnRST (base address + 0x124, base address + 0x144) Remark n = 1, 2 PS2CH1RST (base address + 0x124) PS2CH2RST (base address + 0x144) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 PS2RST W 0 Bit 15:1 0 Name RFU PS2RST Function Reserved. Write 0 to these bits. 0 is returned after a read. PS/2 reset. Cleared to 0 when 1 is written. 1: Reset 0: Normal operation This register is used when the PS/2U is internally reset. User's Manual U14579EJ2V0UM 185 CHAPTER 12 PS2U (PS/2 UNIT) 12.3 Transmission Procedure Use the following procedure to transmit data. <1> Set the PS2EN bit of the PS2CHnCTRL register to 1 to disable reception. <2> After waiting 100 s, confirm whether any reception data exists. <3> If reception data exists, read all of the reception data (until the REMT bit of the PS2CHnCTRL register becomes 0). <4> Set transmission data in the PS2CHnDATA register (the TEMT bit of the PS2CHnCTRL register will become 1). <5> After waiting 100 s (Inhibit output time), set the PS2EN bit to 0 to begin transmission. <6> Poll the TEMT bit to check for the completion of transmission. Caution To transmit data continuously, after confirming that the TEMT bit has become 0 (completion of transmission), perform the next transmission operation according to the transmission procedure. Remarks 1. n = 1, 2 2. Inhibit output time: Delay time from when the transmission data is set until transmission is enabled. 186 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.1 General The VRC4173, which has two on-chip PC card unit (CARDU) channels for controlling PC cards that are compliant with the 1997 PC Card Standard, supports a total of two card slots. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). The main specifications are as follows. * Compliant with 1997 PC Card Standard (excluding 32-bit PC card). * Supports 5 V and 3 V cards. * Supports PCI interrupts for interrupts to the system. * Independent on-chip read/write buffers for each direction. * Five memory windows and two I/O windows can be set. * Supports the clock run protocol for the PCI. However, the following functions are not supported. * 32-bit PC card (CardBus card) * Distributed DMA functions * DMA between the PC card and PCI bus * PCI power management functions (Revision 0.6) * ZOOM Video mode * Ring Indicate signal User's Manual U14579EJ2V0UM 187 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2 Configuration Register Set Table 13-1 lists the configuration registers. CARDU1 and CARDU2 each have these registers. Table 13-1. CARDU Configuration Registers (1/2) Offset Address 0x00 to 0x01 0x02 to 0x03 0x04 to 0x05 0x06 to 0x07 0x08 0x09 to 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x13 0x14 0x15 0x16 to 0x17 0x18 0x19 0x1A 0x1B 0x1C to 0x1F 0x20 to 0x23 0x24 to 0x27 0x28 to 0x2B 0x2C to 0x2F 0x30 to 0x33 0x34 to 0x37 0x38 to 0x3B R/W R R R/W R/W R R R/W R/W R R R/W R - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbol VID DID PCICMD PCISTS RID CLASSC CACHELS MLT HEDT BIST CSRBADR CAP - SECSTS PCIBNUM CARDNUM SUBBNUM CLT MEMB0 MEML0 MEMB1 MEML1 IOB0 IOL0 IOB1 IOL1 Vendor ID register Device ID register PCI command register PCI device status register Revision ID register Class code register Cache line size register Master latency timer register Header type register Built-in self-test register CardBus socket/ExCA base address register PCI additional specifications code register Reserved Second status register PCI bus number register Card number register Subordinate bus number register CardBus latency timer register Memory base address register 0 Memory space boundary register 0 Memory base address register 1 Memory space boundary register 1 I/O base address register 0 I/O space boundary register 0 I/O base address register 1 I/O space boundary register 1 Function 188 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-1. CARDU Configuration Registers (2/2) Offset Address 0x3C 0x3D 0x3E to 0x3F 0x40 to 0x41 0x42 to 0x43 0x44 to 0x47 0x48 to 0x7F 0x80 to 0x83 0x84 to 0x90 0x91 0x92 to 0x93 0x94 to 0x97 0x98 to 0x9B 0x9C 0x9D to 0x9E 0x9F 0xA0 0xA1 0xA2 to 0xA3 0xA4 to 0xA5 0xA6 0xA7 0xA8 to 0xFB 0xFC 0xFD to 0xFF R/W R/W R R/W R/W R/W R/W - R/W - R/W - R/W R/W R/W - R/W R R R/W R/W R R - R/W - Register Symbol INTL INTP BRGCNT SUBVID SUBID PC16BADR - SYSCNT - DEVCNT - SKDMA0 SKDMA1 CHIPCNT - SERRDIS CAPID NIP PMC PMCSR PMCSR_BSE DATA - TEST - Interrupt line register Interrupt pin register Bridge control register Subsystem vendor ID register Subsystem ID register PC card 16-bit interface legacy mode base address register Reserved System control register Reserved Device control register Reserved Socket DMA register 0 Socket DMA register 1 Chip control register Reserved SERR# signal disable register Capability ID register Power management additional function register Power management characteristic register Power management control/status register PMCSR bridge support extension register Data register Reserved Test register Reserved Function These registers are described in detail below. User's Manual U14579EJ2V0UM 189 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.1 VID (offset address: 0x00 to 0x01) Bit Name R/W After reset 15 VID15 R 0 14 VID14 R 0 13 VID13 R 0 12 VID12 R 1 11 VID11 R 0 10 VID10 R 0 9 VID9 R 0 8 VID8 R 0 Bit Name R/W After reset 7 VID7 R 0 6 VID6 R 0 5 VID5 R 1 4 VID4 R 1 3 VID3 R 0 2 VID2 R 0 1 VID1 R 1 0 VID0 R 1 Bit 15:0 Name VID(15:0) Vendor ID 0x1033: NEC Function 13.2.2 DID (offset address: 0x02 to 0x03) Bit Name R/W After reset 15 DID15 R 0 14 DID14 R 0 13 DID13 R 0 12 DID12 R 0 11 DID11 R 0 10 DID10 R 0 9 DID9 R 0 8 DID8 R 0 Bit Name R/W After reset 7 DID7 R 0 6 DID6 R 0 5 DID5 R 1 4 DID4 R 1 3 DID3 R 1 2 DID2 R 1 1 DID1 R 1 0 DID0 R 0 Bit 15:0 Name DID(15:0) Device ID 0x003E: CARDU Function 190 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.3 PCICMD (offset address: 0x04 to 0x05) (1/2) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 FBTB_EN R 0 8 SERR_EN R/W 0 Bit Name 7 AD_STEP 6 PERR_EN 5 VGA_P_ SNOOP R/W 0 4 MEMW_ INV_EN R 0 3 SP_CYC 2 MASTER_ EN R/W 0 1 MEM_EN 0 IO_EN R/W After reset R 0 R/W 0 R 0 R/W 0 R/W 0 Bit 15:10 9 Name RFU FBTB_EN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables fast Back to Back. This function is not supported by the CARDU. Enables/disables system errors. 1: Enable The SERR# signal is set to active if an address parity error is detected and the PERR_EN bit is 1. 0: Disable Enables/disables address/data stepping. This function is not supported by the CARDU. Enables/disables parity error. 1: Enable output of the PERR# signal The PERR# signal is set to active if a data parity error is detected. The SERR# signal is set to active if an address parity error is detected and the SERR_EN bit is 1. 0: Disable output of the PERR# signal VGA palette snoop. This bit setting is valid only when the VGA_EN bit of the BRGCNT register is 0. 1: React to a write access to a VGA palette address from the PCI bus side. Do not react to a read access to a VGA palette address or to an access to another VGA address. Do not react to a write access to a VGA palette address from the PC card side, and react to a read access to a VGA palette address or to an access to another VGA address. 0: Do not react to an access to a VGA address from the PCI bus side. React to an access to a VGA address from the PC card side. Enables/disables memory write and invalidate. This function is not supported by the CARDU. Special cycle. This function is not supported by the CARDU. 8 SERR_EN 7 AD_STEP 6 PERR_EN 5 VGA_P_SNOOP 4 MEMW_INV_EN 3 SP_CYC User's Manual U14579EJ2V0UM 191 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 2 Name MASTER_EN Function Controls bus master operation. 1: Operate as bus master on the PCI bus. 0: Do not operate as bus master on the PCI bus. Controls memory space. 1: Respond to a memory access to the PC card. 0: Do not respond to a memory access to the PC card. Controls I/O space. 1: Respond to an I/O access to the PC card. 0: Do not respond to an I/O access to the PC card. 1 MEM_EN 0 IO_EN 192 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.4 PCISTS (offset address: 0x06 to 0x07) Bit Name 15 DETECT_ PERR R/W 0 14 SIG_SERR 13 RV_ MABORT R/W 0 12 RV_ TABORT R/W 0 11 SIG_ TABOT R/W 0 10 DEVSEL1 9 DEVSEL0 8 DETECT_ D_PERR R/W 0 R/W After reset R/W 0 R 0 R 1 Bit Name R/W After reset 7 FBTB_CAP R 1 6 RFU R 0 5 RFU R 0 4 NEW_CAP R 1 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 15 Name DETECT_PERR Function Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected SERR# signal status. Cleared to 0 when 1 is written. 1: Active 0: Inactive Master abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reporting. Cleared to 0 when 1 is written. 1: Reported 0: Not reported DEVSEL# timing 01: Medium speed Set to 1 when the following three conditions are satisfied. Cleared to 0 when 1 is written. * The CARDU is the master of the bus cycle in which the data parity error occurred. * Either the CARDU set the PERR# signal to active or the CARDU detected that the PERR# signal became active due to the target. * The PERR_EN bit of the PCICMD register has been set to 1. Response to fast Back to Back. This is fixed at 1 (enabled). Reserved. Write 0 to these bits. 0 is returned after a read. Use of PCI power management. This is fixed at 1 (enabled). Reserved. Write 0 to these bits. 0 is returned after a read. 14 SIG_SERR 13 RV_MABORT 12 RV_TABORT 11 SIG_TABOT 10:9 DEVSEL(1:0) 8 DETECT_D_PERR 7 FBTB_CAP 6:5 4 RFU NEW_CAP 3:0 RFU This register shows the status of the PCI bus side. User's Manual U14579EJ2V0UM 193 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.5 RID (offset address: 0x08) Bit Name R/W After reset 7 RID7 R 0 6 RID6 R 0 5 RID5 R 0 4 RID4 R 0 3 RID3 R 0 2 RID2 R 0 1 RID1 R 0 0 RID0 R 1 Bit 7:0 Name RID(7:0) Revision ID Function 13.2.6 CLASSC (offset address: 0x09 to 0x0B) Bit Name R/W After reset 23 CLASSC23 R 0 22 CLASSC22 R 0 21 CLASSC21 R 0 20 CLASSC20 R 0 19 CLASSC19 R 0 18 CLASSC18 R 1 17 CLASSC17 R 1 16 CLASSC16 R 0 Bit Name R/W After reset 15 CLASSC15 R 0 14 CLASSC14 R 0 13 CLASSC13 R 0 12 CLASSC12 R 0 11 CLASSC11 R 0 10 CLASSC10 R 1 9 CLASSC9 R 1 8 CLASSC8 R 1 Bit Name R/W After reset 7 CLASSC7 R 0 6 CLASSC6 R 0 5 CLASSC5 R 0 4 CLASSC4 R 0 3 CLASSC3 R 0 2 CLASSC2 R 0 1 CLASSC1 R 0 0 CLASSC0 R 0 Bit 23:0 Name CLASSC(23:0) Class code 0x060700: Bridge device Function 13.2.7 CACHELS (offset address: 0x0C) Bit Name R/W After reset 7 CACHELS7 R/W 0 6 CACHELS6 R/W 0 5 CACHELS5 R/W 0 4 CACHELS4 R/W 0 3 CACHELS3 R/W 0 2 CACHELS2 R/W 0 1 CACHELS1 R/W 0 0 CACHELS0 R/W 0 Bit 7:0 Name CACHELS(7:0) Function Sets the cache line size. The units are 32 bits (4 bytes). 194 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.8 MLT (offset address: 0x0D) Bit Name R/W After reset 7 MLT7 R/W 0 6 MLT6 R/W 0 5 MLT5 R/W 0 4 MLT4 R/W 0 3 MLT3 R/W 0 2 MLT2 R 0 1 MLT1 R 0 0 MLT0 R 0 Bit 7:3 Name MLT(7:3) Sets the latency timer. 11111: 38 PCLK (1140 ns) : 00010: 9 PCLK (270 ns) 00001: 8 PCLK (240 ns) 00000: 0 PCLK (0 ns) Function 2:0 MLT(2:0) Write 0 to these bits. 0 is returned after a read. Remark Values enclosed in parentheses are for PCICLK = 33 MHz. 13.2.9 HEDT (offset address: 0x0E) Bit Name R/W After reset 7 HEDT7 R 0 6 HEDT6 R 0 5 HEDT5 R 0 4 HEDT4 R 0 3 HEDT3 R 0 2 HEDT2 R 0 1 HEDT1 R 1 0 HEDT0 R 0 Bit 7:0 Name HEDT(7:0) Function Header type 0x02: This is a single function power management register definition. 13.2.10 BIST (offset address: 0x0F) Bit Name R/W After reset 7 BIST7 R 0 6 BIST6 R 0 5 BIST5 R 0 4 BIST4 R 0 3 BIST3 R 0 2 BIST2 R 0 1 BIST1 R 0 0 BIST0 R 0 Bit 7:0 Name BIST(7:0) Function Built-in self-test. This function is not supported by the CARDU. User's Manual U14579EJ2V0UM 195 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.11 CSRBADR (offset address: 0x10 to 0x13) Bit Name R/W After reset 31 30 29 28 27 26 25 24 CSRBADR31 CSRBADR30 CSRBADR29 CSRBADR28 CSRBADR27 CSRBADR26 CSRBADR25 CSRBADR24 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Name R/W After reset 23 22 21 20 19 18 17 16 CSRBADR23 CSRBADR22 CSRBADR21 CSRBADR20 CSRBADR19 CSRBADR18 CSRBADR17 CSRBADR16 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Name R/W After reset 15 14 13 12 11 10 9 8 CSRBADR8 R 0 CSRBADR15 CSRBADR14 CSRBADR13 CSRBADR12 CSRBADR11 CSRBADR10 CSRBADR9 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 Bit Name R/W After reset 7 CSRBADR7 R 0 6 CSRBADR6 R 0 5 CSRBADR5 R 0 4 CSRBADR4 R 0 3 CSRBADR3 R 0 2 CSRBADR2 R 0 1 CSRBADR1 R 0 0 CSRBADR0 R 0 Bit 31:12 11:0 Name CSRBADR(31:12) CSRBADR(11:0) Function Sets the CardBus socket register/ExCA base address. Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.12 CAP (offset address: 0x14) Bit Name R/W After reset 7 CAP7 R 1 6 CAP6 R 0 5 CAP5 R 1 4 CAP4 R 0 3 CAP3 R 0 2 CAP2 R 0 1 CAP1 R 0 0 CAP 0 R 0 Bit 7:0 Name CAP(7:0) Function Capability pointer Indicates the offset address 0xA0 of the CAPID register (see 13.2.38). 196 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.13 SECSTS (offset address: 0x16 to 0x17) Bit Name 15 S_DETECT_ PERR R/W 0 14 S_SIG_ SERR R/W 0 13 S_RV_ MABORT R/W 0 12 S_RV_ TABORT R/W 0 11 S_SIG_ TABOT R/W 0 10 9 8 S_DEVSEL1 S_DEVSEL0 S_DETECT_ D_PERR R 0 R 1 R/W 0 R/W After reset Bit Name 7 S_FBTB_ CAP R 1 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 RFU 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit 15 Name S_DETECT_PERR Function Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected SERR# signal status. Cleared to 0 when 1 is written. 1: Active 0: Inactive Master abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reporting. Cleared to 0 when 1 is written. 1: Reported 0: Not reported DEVSEL# timing 01: Medium speed Set to 1 when the following three conditions are satisfied. * The CardBus is the master of the bus cycle in which the data parity error occurred. * Either the CardBus set the PERR# signal to active or the CardBus detected that the PERR# signal became active due to the target. * The PERR_EN bit of the PCICMD register has been set to 1. Response to fast Back to Back. This is fixed at 1 (enabled). Reserved. Write 0 to these bits. 0 is returned after a read. 14 S_SIG_SERR 13 S_RV_MABORT 12 S_RV_TABORT 11 S_SIG_TABOT 10:9 S_DEVSEL(1:0) 8 S_DETECT_D_PERR 7 S_FBTB_CAP 6:0 RFU This register shows the status of the CardBus side. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 197 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.14 PCIBNUM (offset address: 0x18) Bit Name R/W After reset 7 PCIBNUM7 R/W 0 6 PCIBNUM6 R/W 0 5 PCIBNUM5 R/W 0 4 PCIBNUM4 R/W 0 3 PCIBNUM3 R/W 0 2 PCIBNUM2 R/W 0 1 PCIBNUM1 R/W 0 0 PCIBNUM0 R/W 0 Bit 7:0 Name PCIBNUM(7:0) Function PCI bus number The value of this register is set and managed by software. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.15 CARDNUM (offset address: 0x19) Bit Name R/W After reset 7 6 5 4 3 2 1 0 CARDNUM7 CARDNUM6 CARDNUM5 CARDNUM4 CARDNUM3 CARDNUM2 CARDNUM1 CARDNUM0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 7:0 Name CARDNUM(7:0) Function CardBus card number The value of this register is set and managed by software. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.16 SUBBNUM (offset address: 0x1A) Bit Name R/W After reset 7 6 5 4 3 2 1 0 SUBBNUM7 SUBBNUM6 SUBBNUM5 SUBBNUM4 SUBBNUM3 SUBBNUM2 SUBBNUM1 SUBBNUM0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 7:0 Name SUBBNUM(7:0) Function Subordinate bus number Write the maximum number among the bus numbers of busses to which the PC card is connected. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 198 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.17 CLT (offset address: 0x1B) Bit Name R/W After reset 7 CLT7 R/W 0 6 CLT6 R/W 0 5 CLT5 R/W 0 4 CLT4 R/W 0 3 CLT3 R/W 0 2 CLT2 R 0 1 CLT1 R 0 0 CLT0 R 0 Bit 7:3 Name CLT(7:3) Sets the CardBus latency timer. 11111: 38 PCLK (1140 ns) : 00010: 9 PCLK (270 ns) 00001: 8 PCLK (240 ns) 00000: 0 PCLK (0 ns) Function 2:0 CLT(2:0) Write 0 to these bits. 0 is returned after a read. Remark Caution Values enclosed in parentheses are for PCICLK = 33 MHz. The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 199 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.18 MEMB0 (offset address: 0x1C to 0x1F) Bit Name R/W After reset 31 MEMB031 R/W 0 30 MEMB030 R/W 0 29 MEMB029 R/W 0 28 MEMB028 R/W 0 27 MEMB027 R/W 0 26 MEMB026 R/W 0 25 MEMB025 R/W 0 24 MEMB024 R/W 0 Bit Name R/W After reset 23 MEMB023 R/W 0 22 MEMB022 R/W 0 21 MEMB021 R/W 0 20 MEMB020 R/W 0 19 MEMB019 R/W 0 18 MEMB018 R/W 0 17 MEMB017 R/W 0 16 MEMB016 R/W 0 Bit Name R/W After reset 15 MEMB015 R/W 0 14 MEMB014 R/W 0 13 MEMB013 R/W 0 12 MEMB012 R/W 0 11 MEMB011 R 0 10 MEMB010 R 0 9 MEMB09 R 0 8 MEMB08 R 0 Bit Name R/W After reset 7 MEMB07 R 0 6 MEMB06 R 0 5 MEMB05 R 0 4 MEMB04 R 0 3 MEMB03 R 0 2 MEMB02 R 0 1 MEMB01 R 0 0 MEMB00 R 0 Bit 31:12 11:0 Name MEMB0(31:12) MEMB0(11:0) Sets the memory base address 0. Function Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 200 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.19 MEML0 (offset address: 0x20 to 0x23) Bit Name R/W After reset 31 MEML031 R/W 0 30 MEML030 R/W 0 29 MEML029 R/W 0 28 MEML028 R/W 0 27 MEML027 R/W 0 26 MEML026 R/W 0 25 MEML025 R/W 0 24 MEML024 R/W 0 Bit Name R/W After reset 23 MEML023 R/W 0 22 MEML022 R/W 0 21 MEML021 R/W 0 20 MEML020 R/W 0 19 MEML019 R/W 0 18 MEML018 R/W 0 17 MEML017 R/W 0 16 MEML016 R/W 0 Bit Name R/W After reset 15 MEML015 R/W 0 14 MEML014 R/W 0 13 MEML013 R/W 0 12 MEML012 R/W 0 11 MEML011 R 0 10 MEML010 R 0 9 MEML09 R 0 8 MEML08 R 0 Bit Name R/W After reset 7 MEML07 R 0 6 MEML06 R 0 5 MEML05 R 0 4 MEML04 R 0 3 MEML03 R 0 2 MEML02 R 0 1 MEML01 R 0 0 MEML00 R 0 Bit 31:12 11:0 Name MEML0(31:12) MEML0(11:0) Sets the memory space boundary 0. Function Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 201 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.20 MEMB1 (offset address: 0x24 to 0x27) Bit Name R/W After reset 31 MEMB131 R/W 0 30 MEMB130 R/W 0 29 MEMB129 R/W 0 28 MEMB128 R/W 0 27 MEMB127 R/W 0 26 MEMB126 R/W 0 25 MEMB125 R/W 0 24 MEMB124 R/W 0 Bit Name R/W After reset 23 MEMB123 R/W 0 22 MEMB122 R/W 0 21 MEMB121 R/W 0 20 MEMB120 R/W 0 19 MEMB119 R/W 0 18 MEMB118 R/W 0 17 MEMB117 R/W 0 16 MEMB116 R/W 0 Bit Name R/W After reset 15 MEMB115 R/W 0 14 MEMB114 R/W 0 13 MEMB113 R/W 0 12 MEMB112 R/W 0 11 MEMB111 R 0 10 MEMB110 R 0 9 MEMB19 R 0 8 MEMB18 R 0 Bit Name R/W After reset 7 MEMB17 R 0 6 MEMB16 R 0 5 MEMB15 R 0 4 MEMB14 R 0 3 MEMB13 R 0 2 MEMB12 R 0 1 MEMB11 R 0 0 MEMB10 R 0 Bit 31:12 11:0 Name MEMB1(31:12) MEMB1(11:0) Sets the memory base address 1. Function Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 202 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.21 MEML1 (offset address: 0x28 to 0x2B) Bit Name R/W After reset 31 MEML131 R/W 0 30 MEML130 R/W 0 29 MEML129 R/W 0 28 MEML128 R/W 0 27 MEML127 R/W 0 26 MEML126 R/W 0 25 MEML125 R/W 0 24 MEML124 R/W 0 Bit Name R/W After reset 23 MEML123 R/W 0 22 MEML122 R/W 0 21 MEML121 R/W 0 20 MEML120 R/W 0 19 MEML119 R/W 0 18 MEML118 R/W 0 17 MEML117 R/W 0 16 MEML116 R/W 0 Bit Name R/W After reset 15 MEML115 R/W 0 14 MEML114 R/W 0 13 MEML113 R/W 0 12 MEML112 R/W 0 11 MEML111 R 0 10 MEML110 R 0 9 MEML19 R 0 8 MEML18 R 0 Bit Name R/W After reset 7 MEML17 R 0 6 MEML16 R 0 5 MEML15 R 0 4 MEML14 R 0 3 MEML13 R 0 2 MEML12 R 0 1 MEML11 R 0 0 MEML10 R 0 Bit 31:12 11:0 Name MEML1(31:12) MEML1(11:0) Sets the memory space boundary 1. Function Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 203 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.22 IOB0 (offset address: 0x2C to 0x2F) Bit Name R/W After reset 31 IOB031 R/W 0 30 IOB030 R/W 0 29 IOB029 R/W 0 28 IOB028 R/W 0 27 IOB027 R/W 0 26 IOB026 R/W 0 25 IOB025 R/W 0 24 IOB024 R/W 0 Bit Name R/W After reset 23 IOB023 R/W 0 22 IOB022 R/W 0 21 IOB021 R/W 0 20 IOB020 R/W 0 19 IOB019 R/W 0 18 IOB018 R/W 0 17 IOB017 R/W 0 16 IOB016 R/W 0 Bit Name R/W After reset 15 IOB015 R/W 0 14 IOB014 R/W 0 13 IOB013 R/W 0 12 IOB012 R/W 0 11 IOB011 R/W 0 10 IOB010 R/W 0 9 IOB09 R/W 0 8 IOB08 R/W 0 Bit Name R/W After reset 7 IOB07 R/W 0 6 IOB06 R/W 0 5 IOB05 R/W 0 4 IOB04 R/W 0 3 IOB03 R/W 0 2 IOB02 R/W 0 1 IOB01 R 0 0 IOB00 R 0 Bit 31:2 1:0 Name IOB0(31:2) IOB0(1:0) Sets the I/O base address 0. Function Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 204 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.23 IOL0 (offset address: 0x30 to 0x33) Bit Name R/W After reset 31 IOL031 R 0 30 IOL030 R 0 29 IOL029 R 0 28 IOL028 R 0 27 IOL027 R 0 26 IOL026 R 0 25 IOL025 R 0 24 IOL024 R 0 Bit Name R/W After reset 23 IOL023 R 0 22 IOL022 R 0 21 IOL021 R 0 20 IOL020 R 0 19 IOL019 R 0 18 IOL018 R 0 17 IOL017 R 0 16 IOL016 R 0 Bit Name R/W After reset 15 IOL015 R/W 0 14 IOL014 R/W 0 13 IOL013 R/W 0 12 IOL012 R/W 0 11 IOL011 R/W 0 10 IOL010 R/W 0 9 IOL09 R/W 0 8 IOL08 R/W 0 Bit Name R/W After reset 7 IOL07 R/W 0 6 IOL06 R/W 0 5 IOL05 R/W 0 4 IOL04 R/W 0 3 IOL03 R/W 0 2 IOL02 R/W 0 1 IOL01 R 0 0 IOL00 R 0 Bit 31:16 15:2 1:0 Name IOL0(31:16) IOL0(15:2) IOL0(1:0) Function Write 0 to these bits. 0 is returned after a read. Sets the I/O space boundary 0. Write 0 to these bits. 0 is returned after a read. Address comparisons for the IOL0(31:16) area are performed using the values set in the IOB0 register. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 205 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.24 IOB1 (offset address: 0x34 to 0x37) Bit Name R/W After reset 31 IOB131 R/W 0 30 IOB130 R/W 0 29 IOB129 R/W 0 28 IOB128 R/W 0 27 IOB127 R/W 0 26 IOB126 R/W 0 25 IOB125 R/W 0 24 IOB124 R/W 0 Bit Name R/W After reset 23 IOB123 R/W 0 22 IOB122 R/W 0 21 IOB121 R/W 0 20 IOB120 R/W 0 19 IOB119 R/W 0 18 IOB118 R/W 0 17 IOB117 R/W 0 16 IOB116 R/W 0 Bit Name R/W After reset 15 IOB115 R/W 0 14 IOB114 R/W 0 13 IOB113 R/W 0 12 IOB112 R/W 0 11 IOB111 R/W 0 10 IOB110 R/W 0 9 IOB19 R/W 0 8 IOB18 R/W 0 Bit Name R/W After reset 7 IOB17 R/W 0 6 IOB16 R/W 0 5 IOB15 R/W 0 4 IOB14 R/W 0 3 IOB13 R/W 0 2 IOB12 R/W 0 1 IOB11 R 0 0 IOB10 R 0 Bit 31:2 1:0 Name IOB1(31:2) IOB1(1:0) Sets the I/O base address 1. Function Write 0 to these bits. 0 is returned after a read. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 206 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.25 IOL1 (offset address: 0x38 to 0x3B) Bit Name R/W After reset 31 IOL131 R 0 30 IOL130 R 0 29 IOL129 R 0 28 IOL128 R 0 27 IOL127 R 0 26 IOL126 R 0 25 IOL125 R 0 24 IOL124 R 0 Bit Name R/W After reset 23 IOL123 R 0 22 IOL122 R 0 21 IOL121 R 0 20 IOL120 R 0 19 IOL119 R 0 18 IOL118 R 0 17 IOL117 R 0 16 IOL116 R 0 Bit Name R/W After reset 15 IOL115 R/W 0 14 IOL114 R/W 0 13 IOL113 R/W 0 12 IOL112 R/W 0 11 IOL111 R/W 0 10 IOL110 R/W 0 9 IOL19 R/W 0 8 IOL18 R/W 0 Bit Name R/W After reset 7 IOL17 R/W 0 6 IOL16 R/W 0 5 IOL15 R/W 0 4 IOL14 R/W 0 3 IOL13 R/W 0 2 IOL12 R/W 0 1 IOL11 R 0 0 IOL10 R 0 Bit 31:16 15:2 1:0 Name IOL1(31:16) IOL1(15:2) IOL1(1:0) Function Write 0 to these bits. 0 is returned after a read. Sets the I/O space boundary 1. Write 0 to these bits. 0 is returned after a read. Address comparisons for the IOL1(31:16) area are performed using the values set in the IOB1 register. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.26 INTL (offset address: 0x3C) Bit Name R/W After reset 7 INTL7 R/W 1 6 INTL6 R/W 1 5 INTL5 R/W 1 4 INTL4 R/W 1 3 INTL3 R/W 1 2 INTL2 R/W 1 1 INTL1 R/W 1 0 INTL0 R/W 1 Bit 7:0 Name INTL(7:0) Function Sets the interrupt request line. Since this function is not supported by the CARDU, settings for these bits are invalid. User's Manual U14579EJ2V0UM 207 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.27 INTP (offset address: 0x3D) Bit Name R/W After reset 7 INTP7 R 0 6 INTP6 R 0 5 INTP5 R 0 4 INTP4 R 0 3 INTP3 R 0 2 INTP2 R 0 1 INTP1 R 0 0 INTP0 R 1 Bit 7:0 Name INTP(7:0) PCI interrupt pin 0x01: Serial Function 13.2.28 BRGCNT (offset address: 0x3E to 0x3F) (1/2) Bit Name 15 RFU 14 RFU 13 RFU 12 RFU 11 RFU 10 POST_ WR_EN R/W 0 9 MEM1_ PREF_EN R/W 1 8 MEM0_ PERF_EN R/W 1 R/W After reset R 0 R 0 R 0 R 0 R 0 Bit Name 7 IREQ_INT 6 CARD_RST 5 MABORT_ MODE R/W 0 4 RFU 3 VGA_EN 2 ISA_EN 1 SERR_EN 0 PERR_EN R/W After reset R/W 0 R/W 1 R 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 15:11 10 Name RFU POST_WR_EN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables posts for transactions to or from sockets. 1: Enable 0: Disable Enables/disables prefetches in a memory window defined by the MEMB1 and MEML1 registers. 1: Enable 0: Disable Enables/disables prefetches in a memory window defined by the MEMB0 and MEML0 registers. 1: Enable 0: Disable Selects function interrupt mode from PC card. 1: Setting prohibited 0: Parallel The CARDU unit supports only parallel mode. Status of the CRST# signal (corresponds to the RESET1 or RESET2 signal of the VRC4173) of the CardBus card. 1: Set the CRST# signal to active (initialize PC card) 0: Do not set the CRST# signal to active. User's Manual U14579EJ2V0UM 9 MEM1_PREF_EN 8 MEM0_PREF_EN 7 IREQ_INT 6 CARD_RST 208 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 5 Name MABORT_MODE Function Controls operation when a master abort occurs in the PCI bus and CardBus. 1: For a delayed transaction, return a target abort. For a post transaction, set the SERR# signal to active when the SERR_EN bit is 1. 0: When reading, return all 1's. When writing, discard the write data. Reserved. Write 0 to this bit. 0 is returned after a read. Access to VGA address 1: React to an access to a VGA address from the PCI bus side. Do not react to an access to a VGA address from the CardBus card side. 0: Do not react to an access to a VGA address from the PCI bus side. However, when the VGA_P_SNOOP bit of the PCICMD register is 1, react to a write access to a VGA pallet address. React to an access to a VGA address from the CardBus card side. However, when the VGA_P_SNOOP bit is 1, do not react to a write access to a VGA pallet address. Reaction for an I/O window defined by the IOB1 or IOB0 register and IOL1 or IOL0 register 1: Setting prohibited 0: React according to IOB1 or IOB0 register and IOL1 or IOL0 register. The CARDU unit only supports the PCI bus. Enables/disables reporting of the CardBus CSERR# signal (corresponds to the WAIT1 or WAIT2 signal of the VRC4173) according to the PCI bus SERR# signal. 1: Enable 0: Disable Parity error processing on the CardBus 1: Check for and report parity errors 0: Ignore parity errors 4 3 RFU VGA_EN 2 ISA_EN 1 SERR_EN 0 PERR_EN Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 209 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.29 SUBVID (offset address: 0x40 to 0x41) Bit Name R/W After reset 15 SUBVID15 R/W 0 14 SUBVID14 R/W 0 13 SUBVID13 R/W 0 12 SUBVID12 R/W 0 11 SUBVID11 R/W 0 10 SUBVID10 R/W 0 9 SUBVID9 R/W 0 8 SUBVID8 R/W 0 Bit Name R/W After reset 7 SUBVID7 R/W 0 6 SUBVID6 R/W 0 5 SUBVID5 R/W 0 4 SUBVID4 R/W 0 3 SUBVID3 R/W 0 2 SUBVID2 R/W 0 1 SUBVID1 R/W 0 0 SUBVID0 R/W 0 Bit 15:0 Name SUBVID(15:0) Function Subsystem vendor ID This is a vendor identification number to be used for recognizing the system or option card. The operating system writes and uses this ID. The read/write attribute for this register changes according to the SUB_ID_WR_EN bit of the SYSCNT register. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.30 SUBID (offset address: 0x42 to 0x43) Bit Name R/W After reset 15 SUBID15 R/W 0 14 SUBID14 R/W 0 13 SUBID13 R/W 0 12 SUBID12 R/W 0 11 SUBID11 R/W 0 10 SUBID10 R/W 0 9 SUBID9 R/W 0 8 SUBID8 R/W 0 Bit Name R/W After reset 7 SUBID7 R/W 0 6 SUBID6 R/W 0 5 SUBID5 R/W 0 4 SUBID4 R/W 0 3 SUBID3 R/W 0 2 SUBID2 R/W 0 1 SUBID1 R/W 0 0 SUBID0 R/W 0 Bit 15:0 Name SUBID(15:0) Function Subsystem ID This is a controller identification number to be used for recognizing the system or option card. The operating system writes and uses this ID. The read/write attribute for this register changes according to the SUB_ID_WR_EN bit of the SYSCNT register. Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 210 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.31 PC16BADR (offset address: 0x44 to 0x47) Bit Name 31 PC16BADR 31 R/W 0 30 PC16BADR 30 R/W 0 29 PC16BADR 29 R/W 0 28 PC16BADR 28 R/W 0 27 PC16BADR 27 R/W 0 26 PC16BADR 26 R/W 0 25 PC16BADR 25 R/W 0 24 PC16BADR 24 R/W 0 R/W After reset Bit Name 23 PC16BADR 23 R/W 0 22 PC16BADR 22 R/W 0 21 PC16BADR 21 R/W 0 20 PC16BADR 20 R/W 0 19 PC16BADR 19 R/W 0 18 PC16BADR 18 R/W 0 17 PC16BADR 17 R/W 0 16 PC16BADR 16 R/W 0 R/W After reset Bit Name 15 PC16BADR 15 R/W 0 14 PC16BADR 14 R/W 0 13 PC16BADR 13 R/W 0 12 PC16BADR 12 R/W 0 11 PC16BADR 11 R/W 0 10 PC16BADR 10 R/W 0 9 PC16BADR 9 R/W 0 8 PC16BADR 8 R/W 0 R/W After reset Bit Name 7 PC16BADR 7 R/W 0 6 PC16BADR 6 R/W 0 5 PC16BADR 5 R/W 0 4 PC16BADR 4 R/W 0 3 PC16BADR 3 R/W 0 2 PC16BADR 2 R/W 0 1 PC16BADR 1 R 0 0 PC16BADR 0 R 1 R/W After reset Bit 31:2 1:0 Name PC16BADR(31:2) PC16BADR(1:0) Function Sets the PC card 16-bit interface legacy mode base address. 01 is returned after a read. User's Manual U14579EJ2V0UM 211 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.32 SYSCNT (offset address: 0x80 to 0x83) (1/2) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name 23 RFU 22 RFU 21 BAD_VCC_ REQ_DISB R/W 0 20 RFU 19 PCPCI_EN 18 CH_ ASSIGN2 R/W 1 17 CH_ ASSIGN1 R/W 0 16 CH_ ASSIGN0 R/W 0 R/W After reset R 0 R 0 R 0 R/W 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 SUB_ID_ WR_EN R/W 0 2 ASYN_ INT_MODE R/W 1 1 PCI_ CLK_RIN R/W 0 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 Bit 31:22 21 Name RFU BAD_VCC_REQ_DISB Function Reserved. Write 0 to these bits. 0 is returned after a read. Controls the BAD_VCC_REQ bit (see 13.4.3). 1: Invalid 0: Valid Reserved. Write 0 to this bit. 0 is returned after a read. Enables/disables DMA between the PC card and PCI bus. 1: Setting prohibited 0: Disable The CARDU unit does not support DMA. Sets DMA channel between the PC card and PCI bus. The CARDU unit does not support DMA. Set 100 for these bits. Reserved. Write 0 to these bits. 0 is returned after a read. Sets read/write attribute of SUBVID and SUBID registers. 1: Read/writable 0: Read only 20 19 RFU PCPCI_EN 18:16 CH_ASSIGN(2:0) 15:4 3 RFU SUB_ID_WR_EN 212 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 2 Name ASYN_INT_MODE Function Synchronous/asynchronous setting for interrupt request samples from the PC card. 1: Sample interrupt requests other than for card insertion/removal asynchronously relative to the clock 0: Sample interrupt requests synchronously with the clock PCI bus clock run control setting 1: Drive the primary CLKRUN# signal so that the PCICLK driven by CPU does not stop 0: Operate normally according to the clock run protocol Reserved. Write 0 to this bit. 0 is returned after a read. 1 PCI_CLK_RIN 0 RFU Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.33 DEVCNT (offset address: 0x91) Bit Name 7 RFU 6 ZOOM_ VIDEO_EN R/W 0 5 RFU 4 SR_PCI_ INT_SEL1 R/W 0 3 SR_PCI_ INT_SEL0 R/W 0 2 PCI_INT_ MODE R/W 0 1 IRQ_MODE 0 IFG R/W After reset R 0 R 0 R/W 0 R/W 0 Bit 7 6 Name RFU ZOOM_VIDEO_EN Function Reserved. Write 0 to this bit. 0 is returned after a read. Support for ZV (ZOOM Video) card 1: Setting prohibited 0: Disable support The CARDU unit does not support the ZV card. Reserved. Write 0 to this bit. 0 is returned after a read. PCI serial interrupt request channel specification The CARDU unit does not support serial interrupts. Set 00 for these bits. PCI interrupt request output control 1: Setting prohibited 0: Output interrupt requests in parallel The CARDU unit supports only parallel output. IRQ interrupt request output control 1: Setting prohibited 0: Output interrupt requests in parallel The CARDU unit supports only parallel output. PC card function interrupt request detection. Cleared to 0 when 1 is written. 1: Detected 0: Not detected 5 4:3 RFU SR_PCI_INT_SEL(1:0) 2 PCI_INT_MODE 1 IRQ_MODE 0 IFG User's Manual U14579EJ2V0UM 213 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.34 SKDMA0 (offset address: 0x94 to 0x97) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 DMA_PIN_ CONFIG1 R/W 0 0 DMA_PIN_ CONFIG0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit 31:2 1:0 Name RFU DMA_PIN_CONFIG(1:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. DMA request signal allocation control Caution The CARDU of the VRC4173 does not support DMA. Therefore, the default values should be set for this register. 214 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.35 SKDMA1 (offset address: 0x98 to 0x9B) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name 15 DMA_ BADR11 R/W 0 14 DMA_ BADR10 R/W 0 13 DMA_ BADR9 R/W 0 12 DMA_ BADR8 R/W 0 11 DMA_ BADR7 R/W 0 10 DMA_ BADR6 R/W 0 9 DMA_ BADR5 R/W 0 8 DMA_ BADR4 R/W 0 R/W After reset Bit Name 7 DMA_ BADR3 R/W 0 6 DMA_ BADR2 R/W 0 5 DMA_ BADR1 R/W 0 4 DMA_ BADR0 R/W 0 3 RFU 2 1 0 DMA_ DEC_EN R/W 0 DMA_TRANS DMA_TRANS _SIZE1 _SIZE0 R/W 0 R/W 0 R/W After reset R 0 Bit 31:16 15:4 3 2:1 0 Name RFU DMA_BADR(11:0) RFU DMA_TRANS_SIZE(1:0) DMA_DEC_EN Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets DMA register base address in the PCI I/O space. Reserved. Write 0 to this bit. 0 is returned after a read. 16-bit PC card DMA transfer data size Enables DMA base address decoding. Caution The CARDU of the VRC4173 does not support DMA. Therefore, the default values should be set for this register. User's Manual U14579EJ2V0UM 215 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.36 CHIPCNT (offset address: 0x9C) Bit Name 7 RFU 6 RFU 5 RFU 4 S_PREF_ DISB R/W 0 3 RFU 2 RFU 1 RFU 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit 7:5 4 Name RFU S_PREF_DISB Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables prefetch reads from CardBus. 1: Disable 0: Enable Reserved. Write 0 to these bits. 0 is returned after a read. 3:0 RFU Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 13.2.37 SERRDIS (offset address: 0x9F) Bit Name 7 RFU 6 RFU 5 RFU 4 3 2 1 RFU 0 RFU SERR_DIS_ SERR_DIS_ SERR_DIS_ MAB TAB DT_PERR R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 Bit 7:5 4 Name RFU SERR_DIS_MAB Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables SERR# signal output when a master abort occurs during a post write operation. 1: Disable 0: Enable Enables/disables SERR# signal output when a target abort occurs during a post write operation. 1: Disable 0: Enable Enables/disables SERR# signal output when a data parity error occurs during a post write operation. However, when the data parity error occurs on the PC card-side bus, this bit is also valid during operations other than post write operations. 1: Disable 0: Enable Reserved. Write 0 to these bits. 0 is returned after a read. 3 SERR_DIS_TAB 2 SERR_DIS_DT_PERR 1:0 RFU Caution The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). Therefore, the default values should be set for this register. 216 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.38 CAPID (offset address: 0xA0) Bit Name R/W After reset 7 CAPID7 R 0 6 CAPID6 R 0 5 CAPID5 R 0 4 CAPID4 R 0 3 CAPID3 R 0 2 CAPID2 R 0 1 CAPID1 R 0 0 CAPID0 R 1 Bit 7:0 Name CAPID(7:0) Capability ID 0x01: Power management function Function 13.2.39 NIP (offset address: 0xA1) Bit Name R/W After reset 7 NIP7 R 0 6 NIP6 R 0 5 NIP5 R 0 4 NIP4 R 0 3 NIP3 R 0 2 NIP2 R 0 1 NIP1 R 0 0 NIP0 R 0 Bit 7:0 Name NIP(7:0) Function Power management additional function pointer. The CARDU unit does not have additional functions. User's Manual U14579EJ2V0UM 217 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.40 PMC (offset address: 0xA2 to 0xA3) Bit Name 15 PME_ SUPPORT4 R/W 1 14 PME_ SUPPORT3 R 1 13 PME_ SUPPORT2 R 1 12 PME_ SUPPORT1 R 1 11 PME_ SUPPORT0 R 1 10 D2_ SUPPORT R 1 9 D1_ SUPPORT R 1 8 RFU R/W After reset R 0 Bit Name 7 RFU 6 RFU 5 DSI 4 AUX_PWR_ SOURCE R 1 3 PME_CLK 2 VERSION2 1 VERSION1 0 VERSION0 R/W After reset R 0 R 0 R 0 R 1 R 0 R 0 R 1 Bit 15 14:11 10 9 8:6 5 4 Name PME_SUPPORT4 PME_SUPPORT(3:0) D2_SUPPORT D1_SUPPORT RFU DSI AUX_PWR_SOURCE Function Enables the PME# signal (internal signal) to be active during a D3Cold state. PME# signal active condition Supports D2 Supports D1 Reserved. Write 0 to these bits. 0 is returned after a read. Necessity of initial settings other than PCI standard settings Enables the PME# signal to be active during a D3Cold state when an auxiliary power supply is used. Necessity of the PCICLK when the PME# signal (internal signal) is generated Supports the PCI Power Management Interface Specification 1.0. 3 2:0 PME_CLK VERSION(2:0) Remark D3Cold: State name when switching from the D3 state to the D0 state due to a hardware reset. D3Hot: State name when switching from the D3 state to the D0 state due to a software reset. Caution Since the CARDU of the VRC4173 does not support power management functions, this register setting is disabled. Set the default values for this register. 218 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.41 PMCSR (offset address: 0xA4 to 0xA5) Bit Name 15 PME_ STATUS R/W 0 14 DATA_ SCALE1 R 0 13 DATA_ SCALE0 R 0 12 DATA_ SEL3 R 0 11 DATA_ SEL2 R 0 10 DATA_ SEL1 R 0 9 DATA_ SEL0 R 0 8 PME_EN R/W After reset R/W 0 Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 PWR_ STATE1 R/W 0 0 PWR_ STATE0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit 15 14:13 12:9 8 7:2 1:0 Name PME_STATUS DATA_SCALE(1:0) DATA_SEL(3:0) PME_EN RFU PWR_STATE(1:0) Function PME# signal (internal signal) status. Cleared to 0 when 1 is written. Sets the power management DATA register basic time Selects the power management DATA register Enables PME# signal (internal signal) output Reserved. Write 0 to these bits. 0 is returned after a read. Determines the power state Caution Since the CARDU of the VRC4173 does not support power management functions, this register setting is disabled. Set the default values for this register. 13.2.42 PMCSR_BSE (offset address: 0xA6) Bit Name R/W After reset 7 BPCC_EN R 1 6 B2_B3# R 1 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 7 6 5:0 Name BPCC_EN B2_B3# RFU Function Enables bus power supply and clock control Supports B2 and B3 status during a D3Hot state. Reserved. Write 0 to these bits. 0 is returned after a read. Caution Since the CARDU of the VRC4173 does not support power management functions, this register setting is disabled. Set the default values for this register. User's Manual U14579EJ2V0UM 219 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.2.43 DATA (offset address: 0xA7) Bit Name R/W After reset 7 DATA7 R 0 6 DATA6 R 0 5 DATA5 R 0 4 DATA4 R 0 3 DATA3 R 0 2 DATA2 R 0 1 DATA1 R 0 0 DATA0 R 0 Bit 7:0 Name DATA(7:0) Function Write 0 to these bits. 0 is returned after a read. The CARDU unit does not support this function. 13.2.44 TEST (offset address: 0xFC) Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 TEST1 R/W 0 0 TEST2 R/W 0 Bit 7:2 1 Name RFU TEST1 Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the test mode (interlocation test when the PC card is inserted). 1: Test mode 0: Normal operation Sets the test mode (test when supplying power to PC card). 1: Test mode 0: Normal operation 0 TEST2 220 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3 ExCA Register Set There are two methods of accessing these registers. Each access method is explained below. (1) Access according to a memory access from the primary side When all of the following conditions are satisfied, the ExCA registers can be accessed according to a memory access from the primary side. * The higher 20 bits of the address match the higher 20 bits of the CSRBADR register within the configuration registers. * The lower 12 bits of the address are in the range 0x800 to 0xFFF. * The MEM_EN bit of the PCICMD register within the configuration registers is set to 1. Figure 13-1. Access to ExCA Registers (Memory Access from Primary Side) Configuration registers PCI memory space 0xFFF ExCA registers 0x10 CSRBADR CardBus socket registers 0x800 0x7FF 0x000 (2) Access according to an I/O access from the primary side (index method) When all of the following conditions are satisfied, the ExCA registers can be accessed according to an I/O access from the primary side. * The higher 30 bits of the address match the higher 30 bits of the PC16BADR register within the configuration registers. * The IO_EN bit of the PCICMD register within the configuration registers is set to 1. Figure 13-2. Access to ExCA Registers (I/O Access from Primary Side) Configuration registers PCI I/O space ExCA registers 0x3F 0x44 PC16BADR Index Data ExCA registers 0x00 The ExCA registers also contain extended index and extended data registers. User's Manual U14579EJ2V0UM 221 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Figure 13-3. ExCA Extended Registers ExCA registers ExCA registers 0x16 ExCA extended registers 0x00 0x2F 0x2E EXT_DATA EXT_INDX 222 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Tables 13-2 and 13-3 list the ExCA registers. CARDU1 and CARDU2 each have the following ExCA registers. Table 13-2. ExCA Registers (1/2) Offset Address PCI 0x800 0x801 0x802 0x803 0x804 0x805 0x806 0x807 0x808 0x809 0x80A 0x80B 0x80C 0x80D 0x80E 0x80F 0x810 0x811 0x812 0x813 0x814 0x815 0x816 0x817 0x818 0x819 0x81A ExCA 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W ID_REV IF_STATUS PWR_CNT INT_GEN_CNT CARD_SC CARD_SCI ADR_WIN_EN IO_WIN_CNT IO_WIN0_SAL IO_WIN0_SAH IO_WIN0_EAL IO_WIN0_EAH IO_WIN1_SAL IO_WIN1_SAH IO_WIN1_EAL IO_WIN1_EAH MEM_WIN0_SAL MEM_WIN0_SAH MEM_WIN0_EAL MEM_WIN0_EAH MEM_WIN0_OAL MEM_WIN0_OAH GEN_CNT - MEM_WIN1_SAL MEM_WIN1_SAH MEM_WIN1_EAL ID/revision register Interface status register Power control register Interrupt/general-purpose control register Card status change register Card status change interrupt configuration register Address window enable register I/O window control register I/O window 0 start address lower byte register I/O window 0 start address higher byte register I/O window 0 end address lower byte register I/O window 0 end address higher byte register I/O window 1 start address lower byte register I/O window 1 start address higher byte register I/O window 1 end address lower byte register I/O window 1 end address higher byte register Memory window 0 start address lower byte register Memory window 0 start address higher byte register Memory window 0 end address lower byte register Memory window 0 end address higher byte register Memory window 0 offset address lower byte register Memory window 0 offset address higher byte register General control register Reserved Memory window 1 start address lower byte register Memory window 1 start address higher byte register Memory window 1 end address lower byte register R/W Register Symbol Function User's Manual U14579EJ2V0UM 223 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-2. ExCA Registers (2/2) Offset Address PCI 0x81B 0x81C 0x81D 0x81E 0x81F 0x820 0x821 0x822 0x823 0x824 0x825 0x826 to 0x827 0x828 0x829 0x82A 0x82B 0x82C 0x82D - - 0x830 0x831 0x832 0x833 0x834 0x835 0x836 0x837 0x838 0x839 0x83A to 0x83F ExCA 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 to 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A to 0x3F R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W - MEM_WIN1_EAH MEM_WIN1_OAL MEM_WIN1_OAH GLO_CNT - MEM_WIN2_SAL MEM_WIN2_SAH MEM_WIN2_EAL MEM_WIN2_EAH MEM_WIN2_OAL MEM_WIN2_OAH - MEM_WIN3_SAL MEM_WIN3_SAH MEM_WIN3_EAL MEM_WIN3_EAH MEM_WIN3_OAL MEM_WIN3_OAH EXT_INDX EXT_DATA MEM_WIN4_SAL MEM_WIN4_SAH MEM_WIN4_EAL MEM_WIN4_EAH MEM_WIN4_OAL MEM_WIN4_OAH IO_WIN0_OAL IO_WIN0_OAH IO_WIN1_OAL IO_WIN1_OAH - Memory window 1 end address higher byte register Memory window 1 offset address lower byte register Memory window 1 offset address higher byte register Global control register Reserved Memory window 2 start address lower byte register Memory window 2 start address higher byte register Memory window 2 end address lower byte register Memory window 2 end address higher byte register Memory window 2 offset address lower byte register Memory window 2 offset address higher byte register Reserved R/W Register Symbol Function Memory window 3 start address lower byte register Memory window 3 start address higher byte register Memory window 3 end address lower byte register Memory window 3 end address higher byte register Memory window 3 offset address lower byte register Memory window 3 offset address higher byte register Extended index register Extended data register Memory window 4 start address lower byte register Memory window 4 start address higher byte register Memory window 4 end address lower byte register Memory window 4 end address higher byte register Memory window 4 offset address lower byte register Memory window 4 offset address higher byte register I/O window 0 offset address lower byte register I/O window 0 offset address higher byte register I/O window 1 offset address lower byte register I/O window 1 offset address higher byte register Reserved 224 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-3. ExCA Extended Registers Offset Address PCI ExCA Extension 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 to 0x15 0x16 R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W - R/W R/W R/W - R/W R/W - R/W MEM_WIN0_SAU MEM_WIN1_SAU MEM_WIN2_SAU MEM_WIN3_SAU MEM_WIN4_SAU IO_SETUP_TIM IO_CMD_TIM IO_HOLD_TIM - MEM0_SETUP_TIM MEM0_CMD_TIM MEM0_HOLD_TIM - MEM1_SETUP_TIM MEM1_CMD_TIM MEM1_HOLD_TIM - MEM_TIM_SEL1 MEM_TIM_SEL2 - MEM_WIN_PWEN Memory window 0 start address higher byte register Memory window 1 start address higher byte register Memory window 2 start address higher byte register Memory window 3 start address higher byte register Memory window 4 start address higher byte register I/O setup timing register I/O command timing register I/O hold timing register Reserved Memory setup timing 0 register Memory command timing 0 register Memory hold timing 0 register Reserved Memory setup timing 1 register Memory command timing 1 register Memory hold timing 1 register Reserved Memory timing selection 1 register Memory timing selection 2 register Reserved R/W Register Symbol Function 0x840 0x841 0x842 0x843 0x844 0x880 0x881 0x882 0x883 0x884 0x885 0x886 0x887 0x888 0x889 0x88A 0x88B 0x88C 0x88D 0x88E to 0x890 0x891 Memory window post write enable register These registers are described in detail below. User's Manual U14579EJ2V0UM 225 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.1 ID_REV (PCI offset address: 0x800, ExCA offset address: 0x00) Bit Name R/W After reset 7 IF_TYPE1 R 1 6 IF_TYPE0 R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 7:6 Name IF_TYPE(1:0) Interface type 10: Supports 16-bit card Function 5:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. 226 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.2 IF_STATUS (PCI offset address: 0x801, ExCA offset address: 0x01) Bit Name 7 RFU 6 CARD_ PWR R 0 5 READY 4 CARD_WP 3 CARD_ DETECT2 R Undefined 2 CARD_ DETECT1 R Undefined 1 BV_ DETECT1 R Undefined 0 BV_ DETECT0 R Undefined R/W After reset R 0 R Undefined R Undefined Bit 7 6 Name RFU CARD_PWR Function Reserved. Write 0 to these bits. 0 is returned after a read. Supply status of VCC and VPP to the card. 1: Supplied 0: Not supplied Status of slot 1 READY1 signal and slot 2 READY2 signal 1: High level 0: Low level PC card read/write attribute 1: Read only 0: Read/writable Status of slot 1 CD12# signal and slot 2 CD22# signal 1: Low level 0: High level Status of slot 1 CD11# signal and slot 2 CD21# signal 1: Low level 0: High level * For memory card Battery voltage status 11: Good 10: Falling 01: Cannot be supplied 00: Cannot be supplied * For I/O card BV_DETECT1: STSCHG# signal (corresponds to the BVD11# or BVD21# signal of the VRC4173) status 1: Low level 0: High level BV_DETECT0: SPKR# signal (corresponds to the BVD12# or BVD22# signal of the VRC4173) status 1: Low level 0: High level 5 READY 4 CARD_WP 3 CARD_DETECT2 2 CARD_DETECT1 1:0 BV_DETECT(1:0) User's Manual U14579EJ2V0UM 227 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.3 PWR_CNT (PCI offset address: 0x802, ExCA offset address: 0x02) Bit Name 7 CARD_ OUT_EN R/W 0 6 RFU 5 RFU 4 VCC1 3 VCC0 2 RFU 1 VPP1 0 VPP0 R/W After reset R 0 R 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 Bit 7 Name CARD_OUT_EN Function Enables/disables output to a 16-bit card 1: Enable 0: Disable Reserved. Write 0 to these bits. 0 is returned after a read. Sets VCC power supply level 11: 3.3 V 10: 5 V 01: Reserved 00: 0 V Reserved. Write 0 to this bit. 0 is returned after a read. Sets VPP power supply level 11: Reserved 10: 12 V 01: VCC 00: 0 V 6:5 4:3 RFU VCC(1:0) 2 1:0 RFU VPP(1:0) Caution When a read/write to the VCC(1:0) or VPP(1:0) area is performed, the VCC_CNT(2:0) or VPP_CNT(2:0) area of the SKT_CNT register within the CardBus socket registers is actually accessed. 228 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.4 INT_GEN_CNT (PCI offset address: 0x803, ExCA offset address: 0x03) Bit Name 7 RING_IND_ EN R/W 0 6 CARD_ REST0 R/W 0 5 CARD_ TYPE R/W 0 4 RFU 3 FUC_INT_ ROOT3 R/W 0 2 FUC_INT_ ROOT2 R/W 0 1 FUC_INT_ ROOT1 R/W 0 0 FUC_INT_ ROOT0 R/W 0 R/W After reset R 0 Bit 7 Name RING_IND_EN Function Enables/disables Ring Indicate 1: Enable 0: Disable The CARDU unit does not support the Ring Indicate function. Set 0 for this bit. 16-bit PC card reset signal output status 1: Do not output reset 0: Output reset PC card type 1: I/O card 0: Memory card Reserved. Write 0 to this bit. 0 is returned after a read. Function interrupt request routing 1111: IRQ15 1110: IRQ14 1101: IRQ13Note 1100: IRQ12 1011: IRQ11 1010: IRQ10 1001: IRQ9 1000: IRQ8Note 0111: IRQ7 0110: IRQ6Note 0101: IRQ5 0100: IRQ4 0011: IRQ3 0010: SMINote 0001: IRQ1Note 0000: No routing Since the CARDU unit only supports parallel mode for PCI interrupts, the interrupt request routing setting is disabled. Set 0000 for these bits. 6 CARD_REST0 5 CARD_TYPE 4 3:0 RFU FUC_INT_ROOT(3:0) Note Only for Serialized interrupts User's Manual U14579EJ2V0UM 229 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.5 CARD_SC (PCI offset address: 0x804, ExCA offset address: 0x04) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 CARD_DT_ CHG R/W 0 2 RDY_CHG 1 BAT_WAR_ CHG R/W 0 0 BAT_DEAD _ST_CHG R/W 0 R/W After reset R 0 R 0 R 0 R 0 R/W 0 Bit 7:4 3 Name RFU CARD_DT_CHG Function Reserved. Write 0 to these bits. 0 is returned after a read. Detects change in the CDn1# signal and CDn2# signal (n = 1, 2) 1: Change occurred 0: No change occurred * For memory card Detects change in the READY signal (corresponds to the READY1 or READY2 signal of the VRC4173) from 0 to 1. 1: Change occurred 0: No change occurred * For I/O card Always fixed at 0. * For memory card Detects change in the BVD2 signal (corresponds to the BVD12# or BVD22# signal of the VRC4173) from 1 to 0. 1: Change occurred 0: No change occurred * For I/O card Always fixed at 0. * For memory card Detects change in the BVD1 signal (corresponds to the BVD11# or BVD21# signal of the VRC4173) from 1 to 0. * For I/O card Detects change from 1 to 0 in the STSCHG# signal (corresponds to the BVD11# or BVD21# signal of the VRC4173) or in the RI# signal (internal signal) when the RING_IND_EN bit is 1 (However, the CARDU unit does not support the Ring Indicate function). 1: Change occurred 0: No change occurred 2 RDY_CHG 1 BAT_WAR_CHG 0 BAT_DEAD_ST_CHG Caution Each bit of this register can be cleared to 0 either by writing 1 to the corresponding bit or by reading the bit. The method that is used for clearing the bits is selected according to the INT_WB_CLR bit of the GLO_CNT register. 230 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.6 CARD_SCI (PCI offset address: 0x805, ExCA offset address: 0x05) Bit Name 7 CSC_INT_ ROOT3 R/W 0 6 CSC_INT_ ROOT2 R/W 0 5 CSC_INT_ ROOT1 R/W 0 4 CSC_INT_ ROOT0 R/W 0 3 CARD_DT_ EN R/W 0 2 RDY_EN 1 BAT_WAR_ EN R/W 0 0 BAT_DEAD_ EN R/W 0 R/W After reset R/W 0 Bit 7:4 Name CSC_INT_ROOT(3:0) Function Status interrupt request routing 1111: IRQ15 1110: IRQ14 1101: IRQ13Note 1100: IRQ12 1011: IRQ11 1010: IRQ10 1001: IRQ9 1000: IRQ8Note 0111: IRQ7 0110: IRQ6Note 0101: IRQ5 0100: IRQ4 0011: IRQ3 0010: SMINote 0001: IRQ1Note 0000: No routing Since the CARDU unit only supports parallel mode for PCI interrupts, the interrupt request routing setting is disabled. Set 0000 for these bits. Enables/disables interrupt due to change in the CDn1# signal or CDn2# signal (n = 1, 2) 1: Enable 0: Disable Enables/disables interrupt due to change in the READYn signal from 0 to 1 (n = 1, 2) 1: Enable 0: Disable Enables/disables interrupt due to change in the BVDn2# signal from 1 to 0 (n = 1, 2) 1: Enable 0: Disable Enables/disables interrupt due to change in the BVDn1# signal from 1 to 0 (n = 1, 2) 1: Enable 0: Disable 3 CARD_DT_EN 2 RDY_EN 1 BAT_WAR_EN 0 BAT_DEAD_EN Note Only for Serialized interrupts User's Manual U14579EJ2V0UM 231 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.7 ADR_WIN_EN (PCI offset address: 0x806, ExCA offset address: 0x06) Bit Name 7 IO_WIN1_ EN R/W 0 6 IO_WIN0_ EN R/W 0 5 RFU 4 MEM_WIN4 _EN R/W 0 3 MEM_WIN3 _EN R/W 0 2 MEM_WIN2 _EN R/W 0 1 MEM_WIN1 _EN R/W 0 0 MEM_WIN0 _EN R/W 0 R/W After reset R 0 Bit 7 Name IO_WIN1_EN Function Enables/disables I/O window 1 access. 1: Enable 0: Disable Enables/disables I/O window 0 access. 1: Enable 0: Disable Reserved. Write 0 to this bit. 0 is returned after a read. Enables/disables memory window 4 access. 1: Enable 0: Disable Enables/disables memory window 3 access. 1: Enable 0: Disable Enables/disables memory window 2 access. 1: Enable 0: Disable Enables/disables memory window 1 access. 1: Enable 0: Disable Enables/disables memory window 0 access. 1: Enable 0: Disable 6 IO_WIN0_EN 5 4 RFU MEM_WIN4_EN 3 MEM_WIN3_EN 2 MEM_WIN2_EN 1 MEM_WIN1_EN 0 MEM_WIN0_EN 232 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.8 IO_WIN_CNT (PCI offset address: 0x807, ExCA offset address: 0x07) Bit Name 7 RFU 6 RFU 5 IO_WIN1_ DATA_SEL R/W 0 4 IO_WIN1_ DATA_SIZE R/W 0 3 RFU 2 RFU 1 IO_WIN0_ DATA_SEL R/W 0 0 IO_WIN0_ DATA_SIZE R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit 7:6 5 Name RFU IO_WIN1_DATA_SEL Function Reserved. Write 0 to these bits. 0 is returned after a read. Determines the I/O window 1 data size 1: IOIS16# signal (corresponds to WP1 or WP2 signal of the VRC4173) 0: IO_WIN1_DATA_SIZE bit Sets the I/O window 1 data size 1: 16 bits 0: 8 bits Reserved. Write 0 to these bits. 0 is returned after a read. Determines the I/O window 0 data size 1: IOIS16# signal (corresponds to WP1 or WP2 signal of the VRC4173) 0: IO_WIN0_DATA_SIZE bit Sets the I/O window 0 data size 1: 16 bits 0: 8 bits 4 IO_WIN1_DATA_SIZE 3:2 1 RFU IO_WIN0_DATA_SEL 0 IO_WIN0_DATA_SIZE 13.3.9 IO_WIN0_SAL (PCI offset address: 0x808, ExCA offset address: 0x08) Bit Name 7 IO_WIN0_ SAL7 R/W 0 6 IO_WIN0_ SAL6 R/W 0 5 IO_WIN0_ SAL5 R/W 0 4 IO_WIN0_ SAL4 R/W 0 3 IO_WIN0_ SAL3 R/W 0 2 IO_WIN0_ SAL2 R/W 0 1 IO_WIN0_ SAL1 R/W 0 0 IO_WIN0_ SAL0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN0_SAL(7:0) Function Sets the I/O window 0 start address lower byte User's Manual U14579EJ2V0UM 233 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.10 IO_WIN0_SAH (PCI offset address: 0x809, ExCA offset address: 0x09) Bit Name 7 IO_WIN0_ SAH7 R/W 0 6 IO_WIN0_ SAH6 R/W 0 5 IO_WIN0_ SAH5 R/W 0 4 IO_WIN0_ SAH4 R/W 0 3 IO_WIN0_ SAH3 R/W 0 2 IO_WIN0_ SAH2 R/W 0 1 IO_WIN0_ SAH1 R/W 0 0 IO_WIN0_ SAH0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN0_SAH(7:0) Function Sets the I/O window 0 start address higher byte 13.3.11 IO_WIN0_EAL (PCI offset address: 0x80A, ExCA offset address: 0x0A) Bit Name 7 IO_WIN0_ EAL7 R/W 0 6 IO_WIN0_ EAL6 R/W 0 5 IO_WIN0_ EAL5 R/W 0 4 IO_WIN0_ EAL4 R/W 0 3 IO_WIN0_ EAL3 R/W 0 2 IO_WIN0_ EAL2 R/W 0 1 IO_WIN0_ EAL1 R/W 0 0 IO_WIN0_ EAL0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN0_EAL(7:0) Function Sets the I/O window 0 end address lower byte 13.3.12 IO_WIN0_EAH (PCI offset address: 0x80B, ExCA offset address: 0x0B) Bit Name 7 IO_WIN0_ EAH7 R/W 0 6 IO_WIN0_ EAH6 R/W 0 5 IO_WIN0_ EAH5 R/W 0 4 IO_WIN0_ EAH4 R/W 0 3 IO_WIN0_ EAH3 R/W 0 2 IO_WIN0_ EAH2 R/W 0 1 IO_WIN0_ EAH1 R/W 0 0 IO_WIN0_ EAH0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN0_EAH(7:0) Function Sets the I/O window 0 end address higher byte 234 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.13 IO_WIN1_SAL (PCI offset address: 0x80C, ExCA offset address: 0x0C) Bit Name 7 IO_WIN1_ SAL7 R/W 0 6 IO_WIN1_ SAL6 R/W 0 5 IO_WIN1_ SAL5 R/W 0 4 IO_WIN1_ SAL4 R/W 0 3 IO_WIN1_ SAL3 R/W 0 2 IO_WIN1_ SAL2 R/W 0 1 IO_WIN1_ SAL1 R/W 0 0 IO_WIN1_ SAL0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN1_SAL(7:0) Function Sets the I/O window 1 start address lower byte 13.3.14 IO_WIN1_SAH (PCI offset address: 0x80D, ExCA offset address: 0x0D) Bit Name 7 IO_WIN1_ SAH7 R/W 0 6 IO_WIN1_ SAH6 R/W 0 5 IO_WIN1_ SAH5 R/W 0 4 IO_WIN1_ SAH4 R/W 0 3 IO_WIN1_ SAH3 R/W 0 2 IO_WIN1_ SAH2 R/W 0 1 IO_WIN1_ SAH1 R/W 0 0 IO_WIN1_ SAH0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN1_SAH(7:0) Function Sets the I/O window 1 start address higher byte 13.3.15 IO_WIN1_EAL (PCI offset address: 0x80E, ExCA offset address: 0x0E) Bit Name 7 IO_WIN1_ EAL7 R/W 0 6 IO_WIN1_ EAL6 R/W 0 5 IO_WIN1_ EAL5 R/W 0 4 IO_WIN1_ EAL4 R/W 0 3 IO_WIN1_ EAL3 R/W 0 2 IO_WIN1_ EAL2 R/W 0 1 IO_WIN1_ EAL1 R/W 0 0 IO_WIN1_ EAL0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN1_EAL(7:0) Function Sets the I/O window 1 end address lower byte User's Manual U14579EJ2V0UM 235 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.16 IO_WIN1_EAH (PCI offset address: 0x80F, ExCA offset address: 0x0F) Bit Name 7 IO_WIN1_ EAH7 R/W 0 6 IO_WIN1_ EAH6 R/W 0 5 IO_WIN1_ EAH5 R/W 0 4 IO_WIN1_ EAH4 R/W 0 3 IO_WIN1_ EAH3 R/W 0 2 IO_WIN1_ EAH2 R/W 0 1 IO_WIN1_ EAH1 R/W 0 0 IO_WIN1_ EAH0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN1_EAH(7:0) Function Sets the I/O window 1 end address higher byte 13.3.17 MEM_WIN0_SAL (PCI offset address: 0x810, ExCA offset address: 0x10) Bit Name 7 MEM_ WIN0_SAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN0_SAL0 R/W 0 MEM_ MEM_ WIN0_SAL6 WIN0_SAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN0_SAL4 WIN0_SAL3 WIN0_SAL2 WIN0_SAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN0_SAL(7:0) Function Sets the memory window 0 start address lower byte 13.3.18 MEM_WIN0_SAH (PCI offset address: 0x811, ExCA offset address: 0x11) Bit Name 7 MEM_WIN0 _DSIZE R/W 0 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN0_SAH3 WIN0_SAH2 WIN0_SAH1 WIN0_SAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 Bit 7 Name MEM_WIN0_DSIZE Sets the memory window 0 data size 1: 16 bits 0: 8 bits Function 6:4 3:0 RFU MEM_WIN0_SAH(3:0) Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 0 start address higher bits (A(23:20)) 236 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.19 MEM_WIN0_EAL (PCI offset address: 0x812, ExCA offset address: 0x12) Bit Name 7 MEM_ WIN0_EAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN0_EAL0 R/W 0 MEM_ MEM_ WIN0_EAL6 WIN0_EAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN0_EAL4 WIN0_EAL3 WIN0_EAL2 WIN0_EAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN0_EAL(7:0) Function Sets the memory window 0 end address lower byte 13.3.20 MEM_WIN0_EAH (PCI offset address: 0x813, ExCA offset address: 0x13) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN0_EAH3 WIN0_EAH2 WIN0_EAH1 WIN0_EAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit 7:4 3:0 Name RFU MEM_WIN0_EAH(3:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 0 end address higher bits (A(23:20)) 13.3.21 MEM_WIN0_OAL (PCI offset address: 0x814, ExCA offset address: 0x14) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN0_OAL7 WIN0_OAL6 WIN0_OAL5 WIN0_OAL4 WIN0_OAL3 WIN0_OAL2 WIN0_OAL1 WIN0_OAL0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN0_OAL(7:0) Function Sets the memory window 0 offset address lower byte User's Manual U14579EJ2V0UM 237 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.22 MEM_WIN0_OAH (PCI offset address: 0x815, ExCA offset address: 0x15) Bit Name 7 MEM_ WIN0_WP R/W 0 6 MEM_WIN0 _REGSET R/W 0 5 MEM_WIN0 _OAH5 R/W 0 4 MEM_WIN0 _OAH4 R/W 0 3 MEM_WIN0 _OAH3 R/W 0 2 MEM_WIN0 _OAH2 R/W 0 1 MEM_WIN0 _OAH1 R/W 0 0 MEM_WIN0 _OAH0 R/W 0 R/W After reset Bit 7 Name MEM_WIN0_WP Function Enables/disables the memory window 0 write protect setting 1: Enable 0: Disable Sets the memory window 0 mapping destination 1: Attribute memory 0: Common memory Sets the memory window 0 offset address higher bits (A(25:20)) 6 MEM_WIN0_REGSET 5:0 MEM_WIN0_OAH(5:0) 13.3.23 GEN_CNT (PCI offset address: 0x816, ExCA offset address: 0x16) Bit Name 7 VS2_ STATUS R 0 6 VS1_ STATUS R 0 5 RFU 4 RFU 3 RFU 2 RFU 1 ExCA_REG _RST_EN R/W 0 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 Bit 7 Name VS2_STATUS Function 16-bit PC card interface VSn2# signal status (n = 1, 2) 1: High level 0: Low level 16-bit PC card interface VSn1# signal status (n = 1, 2) 1: High level 0: Low level Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables reset to the ExCA registers when the card is removed 1: Enable 0: Disable Reserved. Write 0 to this bit. 0 is returned after a read. 6 VS1_STATUS 5:2 1 RFU ExCA_REG_RST_EN 0 RFU 238 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.24 MEM_WIN1_SAL (PCI offset address: 0x818, ExCA offset address: 0x18) Bit Name 7 MEM_ WIN1_SAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN1_SAL0 R/W 0 MEM_ MEM_ WIN1_SAL6 WIN1_SAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN1_SAL4 WIN1_SAL3 WIN1_SAL2 WIN1_SAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN1_SAL(7:0) Function Sets the memory window 1 start address lower byte 13.3.25 MEM_WIN1_SAH (PCI offset address: 0x819, ExCA offset address: 0x19) Bit Name 7 MEM_WIN1 _DSIZE R/W 0 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN1_SAH3 WIN1_SAH2 WIN1_SAH1 WIN1_SAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 Bit 7 Name MEM_WIN1_DSIZE Sets the memory window 1 data size 1: 16 bits 0: 8 bits Function 6:4 3:0 RFU MEM_WIN1_SAH(3:0) Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 1 start address higher bits (A(23:20)) 13.3.26 MEM_WIN1_EAL (PCI offset address: 0x81A, ExCA offset address: 0x1A) Bit Name 7 MEM_ WIN1_EAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN1_EAL0 R/W 0 MEM_ MEM_ WIN1_EAL6 WIN1_EAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN1_EAL4 WIN1_EAL3 WIN1_EAL2 WIN1_EAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN1_EAL(7:0) Function Sets the memory window 1 end address lower byte User's Manual U14579EJ2V0UM 239 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.27 MEM_WIN1_EAH (PCI offset address: 0x81B, ExCA offset address: 0x1B) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN1_EAH3 WIN1_EAH2 WIN1_EAH1 WIN1_EAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit 7:4 3:0 Name RFU MEM_WIN1_EAH(3:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 1 end address higher bits (A(23:20)) 13.3.28 MEM_WIN1_OAL (PCI offset address: 0x81C, ExCA offset address: 0x1C) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN1_OAL7 WIN1_OAL6 WIN1_OAL5 WIN1_OAL4 WIN1_OAL3 WIN1_OAL2 WIN1_OAL1 WIN1_OAL0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN1_OAL(7:0) Function Sets the memory window 1 offset address lower byte 13.3.29 MEM_WIN1_OAH (PCI offset address: 0x81D, ExCA offset address: 0x1D) Bit Name 7 MEM_ WIN1_WP R/W 0 6 MEM_WIN1 _REGSET R/W 0 5 MEM_WIN1 _OAH5 R/W 0 4 MEM_WIN1 _OAH4 R/W 0 3 MEM_WIN1 _OAH3 R/W 0 2 MEM_WIN1 _OAH2 R/W 0 1 MEM_WIN1 _OAH1 R/W 0 0 MEM_WIN1 _OAH0 R/W 0 R/W After reset Bit 7 Name MEM_WIN1_WP Function Enables/disables the memory window 1 write protect setting 1: Enable 0: Disable Sets the memory window 1 mapping destination 1: Attribute memory 0: Common memory Sets the memory window 1 offset address higher bits (A(25:20)) 6 MEM_WIN1_REGSET 5:0 MEM_WIN1_OAH(5:0) 240 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.30 GLO_CNT (PCI offset address: 0x81E, ExCA offset address: 0x1E) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 FUN_INT_ LEV R/W 0 2 INT_WB_ CLR R/W 0 1 CSC_INT_ LEV R/W 0 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 Bit 7:4 3 Name RFU FUN_INT_LEV Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the trigger for function interrupt requests to the host 1: Level mode 0: Edge mode Since the CARDU unit only supports parallel mode for PCI interrupts, this bit setting is disabled. Set 0 for this bit. Selects the method of clearing CSC interrupt flags 1: Cleared to 0 by writing 1 to the corresponding bit of the CARD_SC register 0: Cleared to 0 by reading the CARD_SC register Sets the trigger for CSC interrupt requests to the host 1: Level mode 0: Edge mode Since the CARDU unit only supports parallel mode for PCI interrupts, this bit setting is disabled. Set 0 for this bit. Reserved. Write 0 to this bit. 0 is returned after a read. 2 INT_WB_CLR 1 CSC_INT_LEV 0 RFU 13.3.31 MEM_WIN2_SAL (PCI offset address: 0x820, ExCA offset address: 0x20) Bit Name 7 MEM_ WIN2_SAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN2_SAL0 R/W 0 MEM_ MEM_ WIN2_SAL6 WIN2_SAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN2_SAL4 WIN2_SAL3 WIN2_SAL2 WIN2_SAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN2_SAL(7:0) Function Sets the memory window 2 start address lower byte User's Manual U14579EJ2V0UM 241 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.32 MEM_WIN2_SAH (PCI offset address: 0x821, ExCA offset address: 0x21) Bit Name 7 MEM_WIN2 _DSIZE R/W 0 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN2_SAH3 WIN2_SAH2 WIN2_SAH1 WIN2_SAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 Bit 7 Name MEM_WIN2_DSIZE Sets the memory window 2 data size 1: 16 bits 0: 8 bits Function 6:4 3:0 RFU MEM_WIN2_SAH(3:0) Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 2 start address higher bits (A(23:20)) 13.3.33 MEM_WIN2_EAL (PCI offset address: 0x822, ExCA offset address: 0x22) Bit Name 7 MEM_WIN2 _EAL7 R/W 0 6 MEM_WIN2 _EAL6 R/W 0 5 MEM_WIN2 _EAL5 R/W 0 4 MEM_WIN2 _EAL4 R/W 0 3 MEM_WIN2 _EAL3 R/W 0 2 MEM_WIN2 _EAL2 R/W 0 1 MEM_WIN2 _EAL1 R/W 0 0 MEM_WIN2 _EAL0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN2_EAL(7:0) Function Sets the memory window 2 end address lower byte 13.3.34 MEM_WIN2_EAH (PCI offset address: 0x823, ExCA offset address: 0x23) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN2_EAH3 WIN2_EAH2 WIN2_EAH1 WIN2_EAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit 7:4 3:0 Name RFU MEM_WIN2_EAH(3:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 2 end address higher bits (A(23:20)) 242 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.35 MEM_WIN2_OAL (PCI offset address: 0x824, ExCA offset address: 0x24) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN2_OAL7 WIN2_OAL6 WIN2_OAL5 WIN2_OAL4 WIN2_OAL3 WIN2_OAL2 WIN2_OAL1 WIN2_OAL0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN2_OAL(7:0) Function Sets the memory window 2 offset address lower byte 13.3.36 MEM_WIN2_OAH (PCI offset address: 0x825, ExCA offset address: 0x25) Bit Name 7 MEM_ WIN2_WP R/W 0 6 MEM_WIN2 _REGSET R/W 0 5 MEM_WIN2 _OAH5 R/W 0 4 MEM_WIN2 _OAH4 R/W 0 3 MEM_WIN2 _OAH3 R/W 0 2 MEM_WIN2 _OAH2 R/W 0 1 MEM_WIN2 _OAH1 R/W 0 0 MEM_WIN2 _OAH0 R/W 0 R/W After reset Bit 7 Name MEM_WIN2_WP Function Enables/disables the memory window 2 write protect setting 1: Enable 0: Disable Sets the memory window 2 mapping destination 1: Attribute memory 0: Common memory Sets the memory window 2 offset address higher bits (A(25:20)) 6 MEM_WIN2_REGSET 5:0 MEM_WIN2_OAH(5:0) 13.3.37 MEM_WIN3_SAL (PCI offset address: 0x828, ExCA offset address: 0x28) Bit Name 7 MEM_ WIN3_SAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN3_SAL0 R/W 0 MEM_ MEM_ WIN3_SAL6 WIN3_SAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN3_SAL4 WIN3_SAL3 WIN3_SAL2 WIN3_SAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN3_SAL(7:0) Function Sets the memory window 3 start address lower byte User's Manual U14579EJ2V0UM 243 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.38 MEM_WIN3_SAH (PCI offset address: 0x829, ExCA offset address: 0x29) Bit Name 7 MEM_WIN3 _DSIZE R/W 0 6 RFU 5 RFU 4 RFU 3 MEM_WIN3 _SAH3 R/W 0 2 MEM_WIN3 _SAH2 R/W 0 1 MEM_WIN3 _SAH1 R/W 0 0 MEM_WIN3 _SAH0 R/W 0 R/W After reset R 0 R 0 R 0 Bit 7 Name MEM_WIN3_DSIZE Sets the memory window 3 data size 1: 16 bits 0: 8 bits Function 6:4 3:0 RFU MEM_WIN3_SAH(3:0) Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 3 start address higher bits (A(23:20)) 13.3.39 MEM_WIN3_EAL (PCI offset address: 0x82A, ExCA offset address: 0x2A) Bit Name 7 MEM_ WIN3_EAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN3_EAL0 R/W 0 MEM_ MEM_ WIN3_EAL6 WIN3_EAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN3_EAL4 WIN3_EAL3 WIN3_EAL2 WIN3_EAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN3_EAL(7:0) Function Sets the memory window 3 end address lower byte 13.3.40 MEM_WIN3_EAH (PCI offset address: 0x82B, ExCA offset address: 0x2B) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN3_EAH3 WIN3_EAH2 WIN3_EAH1 WIN3_EAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit 7:4 3:0 Name RFU MEM_WIN3_EAH(3:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 3 end address higher bits (A(23:20)) 244 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.41 MEM_WIN3_OAL (PCI offset address: 0x82C, ExCA offset address: 0x2C) Bit Name 7 MEM_WIN3 _OAL7 R/W 0 6 MEM_WIN3 _OAL6 R/W 0 5 MEM_WIN3 _OAL5 R/W 0 4 MEM_WIN3 _OAL4 R/W 0 3 MEM_WIN3 _OAL3 R/W 0 2 MEM_WIN3 _OAL2 R/W 0 1 MEM_WIN3 _OAL1 R/W 0 0 MEM_WIN3 _OAL0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN3_OAL(7:0) Function Sets the memory window 3 offset address lower byte 13.3.42 MEM_WIN3_OAH (PCI offset address: 0x82D, ExCA offset address: 0x2D) Bit Name 7 MEM_WIN3 _WP R/W 0 6 MEM_WIN3 _REGSET R/W 0 5 MEM_WIN3 _OAH5 R/W 0 4 MEM_WIN3 _OAH4 R/W 0 3 MEM_WIN3 _OAH3 R/W 0 2 MEM_WIN3 _OAH2 R/W 0 1 MEM_WIN3 _OAH1 R/W 0 0 MEM_WIN3 _OAH0 R/W 0 R/W After reset Bit 7 Name MEM_WIN3_WP Function Enables/disables the memory window 3 write protect setting 1: Enable 0: Disable Sets the memory window 3 mapping destination 1: Attribute memory 0: Common memory Sets the memory window 3 offset address higher bits (A(25:20)) 6 MEM_WIN3_REGSET 5:0 MEM_WIN3_OAH(5:0) 13.3.43 EXT_INDX (ExCA offset address: 0x2E) Bit Name R/W After reset 7 EXT_INDX7 R/W 0 6 EXT_INDX6 R/W 0 5 EXT_INDX5 R/W 0 4 EXT_INDX4 R/W 0 3 EXT_INDX3 R/W 0 2 EXT_INDX2 R/W 0 1 EXT_INDX1 R/W 0 0 EXT_INDX0 R/W 0 Bit 7:0 Name EXT_INDX(7:0) Sets the extended index Function Caution Read/write according to a memory access from the primary side is not supported. User's Manual U14579EJ2V0UM 245 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.44 EXT_DATA (ExCA offset address: 0x2F) Bit Name R/W After reset 7 EXT_DATA7 R/W 0 6 EXT_DATA6 R/W 0 5 EXT_DATA5 R/W 0 4 EXT_DATA4 R/W 0 3 EXT_DATA3 R/W 0 2 EXT_DATA2 R/W 0 1 EXT_DATA1 R/W 0 0 EXT_DATA0 R/W 0 Bit 7:0 Name EXT_DATA(7:0) Sets the extended data Function Caution Read/write according to a memory access from the primary side is not supported. 13.3.45 MEM_WIN4_SAL (PCI offset address: 0x830, ExCA offset address: 0x30) Bit Name 7 MEM_WIN4 _SAL7 R/W 0 6 MEM_WIN4 _SAL6 R/W 0 5 MEM_WIN4 _SAL5 R/W 0 4 MEM_WIN4 _SAL4 R/W 0 3 MEM_WIN4 _SAL3 R/W 0 2 MEM_WIN4 _SAL2 R/W 0 1 MEM_WIN4 _SAL1 R/W 0 0 MEM_WIN4 _SAL0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN4_SAL(7:0) Function Sets the memory window 4 start address lower byte 13.3.46 MEM_WIN4_SAH (PCI offset address: 0x831, ExCA offset address: 0x31) Bit Name 7 MEM_WIN4 _DSIZE R/W 0 6 RFU 5 RFU 4 RFU 3 MEM_WIN4 _SAH3 R/W 0 2 MEM_WIN4 _SAH2 R/W 0 1 MEM_WIN4 _SAH1 R/W 0 0 MEM_WIN4 _SAH0 R/W 0 R/W After reset R 0 R 0 R 0 Bit 7 Name MEM_WIN4_DSIZE Sets the memory window 4 data size 1: 16 bits 0: 8 bits Function 6:4 3:0 RFU MEM_WIN4_SAH(3:0) Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 4 start address higher bits (A(23:20)) 246 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.47 MEM_WIN4_EAL (PCI offset address: 0x832, ExCA offset address: 0x32) Bit Name 7 MEM_ WIN4_EAL7 R/W 0 6 5 4 3 2 1 0 MEM_ WIN4_EAL0 R/W 0 MEM_ MEM_ WIN4_EAL6 WIN4_EAL5 R/W 0 R/W 0 MEM_ MEM_ MEM_ MEM_ WIN4_EAL4 WIN4_EAL3 WIN4_EAL2 WIN4_EAL1 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN4_EAL(7:0) Function Sets the memory window 4 end address lower byte 13.3.48 MEM_WIN4_EAH (PCI offset address: 0x833, ExCA offset address: 0x33) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 2 1 0 MEM_ MEM_ MEM_ MEM_ WIN4_EAH3 WIN4_EAH2 WIN4_EAH1 WIN4_EAH0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit 7:4 3:0 Name RFU MEM_WIN4_EAH(3:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Sets the memory window 4 end address higher bits (A(23:20)) 13.3.49 MEM_WIN4_OAL (PCI offset address: 0x834, ExCA offset address: 0x34) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN4_OAL7 WIN4_OAL6 WIN4_OAL5 WIN4_OAL4 WIN4_OAL3 WIN4_OAL2 WIN4_OAL1 WIN4_OAL0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN4_OAL(7:0) Function Sets the memory window 4 offset address lower byte User's Manual U14579EJ2V0UM 247 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.50 MEM_WIN4_OAH (PCI offset address: 0x835, ExCA offset address: 0x35) Bit Name 7 MEM_ WIN4_WP R/W 0 6 MEM_WIN4 _REGSET R/W 0 5 MEM_WIN4 _OAH5 R/W 0 4 MEM_WIN4 _OAH4 R/W 0 3 MEM_WIN4 _OAH3 R/W 0 2 MEM_WIN4 _OAH2 R/W 0 1 MEM_WIN4 _OAH1 R/W 0 0 MEM_WIN4 _OAH0 R/W 0 R/W After reset Bit 7 Name MEM_WIN4_WP Function Enables/disables the memory window 4 write protect setting 1: Enable 0: Disable Sets the memory window 4 mapping destination 1: Attribute memory 0: Common memory Sets the memory window 4 offset address higher bits (A(25:20)) 6 MEM_WIN4_REGSET 5:0 MEM_WIN4_OAH(5:0) 13.3.51 IO_WIN0_OAL (PCI offset address: 0x836, ExCA offset address: 0x36) Bit Name 7 IO_WIN0_ OAL7 R/W 0 6 IO_WIN0_ OAL6 R/W 0 5 IO_WIN0_ OAL5 R/W 0 4 IO_WIN0_ OAL4 R/W 0 3 IO_WIN0_ OAL3 R/W 0 2 IO_WIN0_ OAL2 R/W 0 1 IO_WIN0_ OAL1 R/W 0 0 IO_WIN0_ OAL0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN0_OAL(7:0) Function Sets the I/O window 0 offset address lower bytes (A(7:0)) 13.3.52 IO_WIN0_OAH (PCI offset address: 0x837, ExCA offset address: 0x37) Bit Name 7 IO_WIN0_ OAH7 R/W 0 6 IO_WIN0_ OAH6 R/W 0 5 IO_WIN0_ OAH5 R/W 0 4 IO_WIN0_ OAH4 R/W 0 3 IO_WIN0_ OAH3 R/W 0 2 IO_WIN0_ OAH2 R/W 0 1 IO_WIN0_ OAH1 R/W 0 0 IO_WIN0_ OAH0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN0_OAH(7:0) Function Sets the I/O window 0 offset address higher bytes (A(15:8)) 248 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.53 IO_WIN1_OAL (PCI offset address: 0x838, ExCA offset address: 0x38) Bit Name 7 IO_WIN1_ OAL7 R/W 0 6 IO_WIN1_ OAL6 R/W 0 5 IO_WIN1_ OAL5 R/W 0 4 IO_WIN1_ OAL4 R/W 0 3 IO_WIN1_ OAL3 R/W 0 2 IO_WIN1_ OAL2 R/W 0 1 IO_WIN1_ OAL1 R/W 0 0 IO_WIN1_ OAL0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN1_OAL(7:0) Function Sets the I/O window 1 offset address lower bytes (A(7:0)) 13.3.54 IO_WIN1_OAH (PCI offset address: 0x839, ExCA offset address: 0x39) Bit Name 7 IO_WIN1_ OAH7 R/W 0 6 IO_WIN1_ OAH6 R/W 0 5 IO_WIN1_ OAH5 R/W 0 4 IO_WIN1_ OAH4 R/W 0 3 IO_WIN1_ OAH3 R/W 0 2 IO_WIN1_ OAH2 R/W 0 1 IO_WIN1_ OAH1 R/W 0 0 IO_WIN1_ OAH0 R/W 0 R/W After reset Bit 7:0 Name IO_WIN1_OAH(7:0) Function Sets the I/O window 1 offset address higher bytes (A(15:8)) 13.3.55 MEM_WIN0_SAU (PCI offset address: 0x840, ExCA extended offset address: 0x00) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN0_SAU7 WIN0_SAU6 WIN0_SAU5 WIN0_SAU4 WIN0_SAU3 WIN0_SAU2 WIN0_SAU1 WIN0_SAU0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN0_SAU(7:0) Function Sets the memory window 0 start address higher bytes (A(31:24)) User's Manual U14579EJ2V0UM 249 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.56 MEM_WIN1_SAU (PCI offset address: 0x841, ExCA extended offset address: 0x01) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN1_SAU7 WIN1_SAU6 WIN1_SAU5 WIN1_SAU4 WIN1_SAU3 WIN1_SAU2 WIN1_SAU1 WIN1_SAU0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN1_SAU(7:0) Function Sets the memory window 1 start address higher bytes (A(31:24)) 13.3.57 MEM_WIN2_SAU (PCI offset address: 0x842, ExCA extended offset address: 0x02) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN2_SAU7 WIN2_SAU6 WIN2_SAU5 WIN2_SAU4 WIN2_SAU3 WIN2_SAU2 WIN2_SAU1 WIN2_SAU0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN2_SAU(7:0) Function Sets the memory window 2 start address higher bytes (A(31:24)) 13.3.58 MEM_WIN3_SAU (PCI offset address: 0x843, ExCA extended offset address: 0x03) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN3_SAU7 WIN3_SAU6 WIN3_SAU5 WIN3_SAU4 WIN3_SAU3 WIN3_SAU2 WIN3_SAU1 WIN3_SAU0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN3_SAU(7:0) Function Sets the memory window 3 start address higher bytes (A(31:24)) 250 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.59 MEM_WIN4_SAU (PCI offset address: 0x844, ExCA extended offset address: 0x04) Bit Name 7 6 5 4 3 2 1 0 MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ MEM_ WIN4_SAU7 WIN4_SAU6 WIN4_SAU5 WIN4_SAU4 WIN4_SAU3 WIN4_SAU2 WIN4_SAU1 WIN4_SAU0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W After reset Bit 7:0 Name MEM_WIN4_SAU(7:0) Function Sets the memory window 4 start address higher bytes (A(31:24)) 13.3.60 IO_SETUP_TIM (PCI offset address: 0x880, ExCA extended offset address: 0x05) Bit Name 7 IO_SETUP_ TIM7 R/W 0 6 5 4 3 2 1 0 IO_SETUP_ TIM0 R/W 0 IO_SETUP_ IO_SETUP_ TIM6 TIM5 R/W 0 R/W 0 IO_SETUP_ IO_SETUP_ IO_SETUP_ IO_SETUP_ TIM4 TIM3 TIM2 TIM1 R/W 0 R/W 0 R/W 1 R/W 1 R/W After reset Bit 7:0 Name IO_SETUP_TIM(7:0) Sets the I/O window setup timing 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x07: 8 clock pulses (240 ns) 0x06: 7 clock pulses (210 ns) 0x05 to 0x00: Setting prohibited Function Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. User's Manual U14579EJ2V0UM 251 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.61 IO_CMD_TIM (PCI offset address: 0x881, ExCA extended offset address: 0x06) Bit Name 7 IO_CMD_ TIM7 R/W 0 6 IO_CMD_ TIM6 R/W 0 5 IO_CMD_ TIM5 R/W 0 4 IO_CMD_ TIM4 R/W 0 3 IO_CMD_ TIM3 R/W 0 2 IO_CMD_ TIM2 R/W 1 1 IO_CMD_ TIM1 R/W 0 0 IO_CMD_ TIM0 R/W 1 R/W After reset Bit 7:0 Name IO_CMD_TIM(7:0) Sets the I/O window command timing 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x04: 5 clock pulses (150 ns) 0x03: 4 clock pulses (120 ns) 0x02 to 0x00: Setting prohibited Function Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. 13.3.62 IO_HOLD_TIM (PCI offset address: 0x882, ExCA extended offset address: 0x07) Bit Name 7 IO_HOLD_ TIM7 R/W 0 6 IO_HOLD_ TIM6 R/W 0 5 IO_HOLD_ TIM5 R/W 0 4 IO_HOLD_ TIM4 R/W 0 3 IO_HOLD_ TIM3 R/W 0 2 IO_HOLD_ TIM2 R/W 0 1 IO_HOLD_ TIM1 R/W 1 0 IO_HOLD_ TIM0 R/W 0 R/W After reset Bit 7:0 Name IO_HOLD_TIM(7:0) Sets the I/O window hold timing 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x01: 2 clock pulses (60 ns) 0x00: 1 clock pulse (30 ns) Function Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. 252 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.63 MEM0_SETUP_TIM (PCI offset address: 0x884, ExCA extended offset address: 0x09) Bit Name 7 MEM0_SET UP_TIM7 R/W 0 6 MEM0_SET UP_TIM6 R/W 0 5 MEM0_SET UP_TIM5 R/W 0 4 MEM0_SET UP_TIM4 R/W 0 3 MEM0_SET UP_TIM3 R/W 0 2 MEM0_SET UP_TIM2 R/W 1 1 MEM0_SET UP_TIM1 R/W 1 0 MEM0_SET UP_TIM0 R/W 0 R/W After reset Bit 7:0 Name MEM0_SETUP_TIM(7:0) Function Sets the memory window setup timing 0 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x01: 2 clock pulses (60 ns) 0x00: 1 clock pulse (30 ns) Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. 13.3.64 MEM0_CMD_TIM (PCI offset address: 0x885, ExCA extended offset address: 0x0A) Bit Name 7 MEM0_ CMD_TIM7 R/W 0 6 MEM0_ CMD_TIM6 R/W 0 5 MEM0_ CMD_TIM5 R/W 0 4 MEM0_ CMD_TIM4 R/W 1 3 MEM0_ CMD_TIM3 R/W 0 2 MEM0_ CMD_TIM2 R/W 0 1 MEM0_ CMD_TIM1 R/W 0 0 MEM0_ CMD_TIM0 R/W 0 R/W After reset Bit 7:0 Name MEM0_CMD_TIM(7:0) Function Sets the memory window command timing 0 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x04: 5 clock pulses (150 ns) 0x03: 4 clock pulses (120 ns) 0x02 to 0x00: Setting prohibited Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. User's Manual U14579EJ2V0UM 253 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.65 MEM0_HOLD_TIM (PCI offset address: 0x886, ExCA extended offset address: 0x0B) Bit Name 7 6 5 4 3 2 1 0 MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ MEM0_ HOLD_TIM7 HOLD_TIM6 HOLD_TIM5 HOLD_TIM4 HOLD_TIM3 HOLD_TIM2 HOLD_TIM1 HOLD_TIM0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 R/W After reset Bit 7:0 Name MEM0_HOLD_TIM(7:0) Function Sets the memory window hold timing 0 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x01: 2 clock pulses (60 ns) 0x00: 1 clock pulse (30 ns) Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. 13.3.66 MEM1_SETUP_TIM (PCI offset address: 0x888, ExCA extended offset address: 0x0D) Bit Name 7 MEM1_SET UP_TIM7 R/W 0 6 MEM1_SET UP_TIM6 R/W 0 5 MEM1_SET UP_TIM5 R/W 0 4 MEM1_SET UP_TIM4 R/W 0 3 MEM1_SET UP_TIM3 R/W 0 2 MEM1_SET UP_TIM2 R/W 0 1 MEM1_SET UP_TIM1 R/W 1 0 MEM1_SET UP_TIM0 R/W 0 R/W After reset Bit 7:0 Name MEM1_SETUP_TIM(7:0) Function Sets the memory window setup timing 1 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x01: 2 clock pulses (60 ns) 0x00: 1 clock pulse (30 ns) Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. 254 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.67 MEM1_CMD_TIM (PCI offset address: 0x889, ExCA extended offset address: 0x0E) Bit Name 7 MEM1_ CMD_TIM7 R/W 0 6 MEM1_ CMD_TIM6 R/W 0 5 MEM1_ CMD_TIM5 R/W 0 4 MEM1_ CMD_TIM4 R/W 0 3 MEM1_ CMD_TIM3 R/W 0 2 MEM1_ CMD_TIM2 R/W 1 1 MEM1_ CMD_TIM1 R/W 1 0 MEM1_ CMD_TIM0 R/W 0 R/W After reset Bit 7:0 Name MEM1_CMD_TIM(7:0) Function Sets the memory window command timing 1 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x04: 5 clock pulses (150 ns) 0x03: 4 clock pulses (120 ns) 0x02 to 0x00: Setting prohibited Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. 13.3.68 MEM1_HOLD_TIM (PCI offset address: 0x88A, ExCA extended offset address: 0x0F) Bit Name 7 6 5 4 3 2 1 0 MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ MEM1_ HOLD_TIM7 HOLD_TIM6 HOLD_TIM5 HOLD_TIM4 HOLD_TIM3 HOLD_TIM2 HOLD_TIM1 HOLD_TIM0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W After reset Bit 7:0 Name MEM1_HOLD_TIM(7:0) Function Sets the memory window hold timing 1 0xFF: 256 clock pulses (7680 ns) 0xFE: 255 clock pulses (7650 ns) : 0x01: 2 clock pulses (60 ns) 0x00: 1 clock pulse (30 ns) Caution Remark Set values that match the device specifications. Values enclosed in parentheses are for PCICLK = 33 MHz. User's Manual U14579EJ2V0UM 255 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.69 MEM_TIM_SEL1 (PCI offset address: 0x88C, ExCA extended offset address: 0x11) Bit Name 7 MEM_WIN3 _TIMSEL1 R/W 0 6 MEM_WIN3 _TIMSEL0 R/W 0 5 MEM_WIN2 _TIMSEL1 R/W 0 4 MEM_WIN2 _TIMSEL0 R/W 0 3 MEM_WIN1 _TIMSEL1 R/W 0 2 MEM_WIN1 _TIMSEL0 R/W 0 1 MEM_WIN0 _TIMSEL1 R/W 0 0 MEM_WIN0 _TIMSEL0 R/W 0 R/W After reset Bit 7:6 Name MEM_WIN3_TIMSEL(1:0) Selects the memory window 3 timing 00: Timing 0 Other: Timing 1 Selects the memory window 2 timing 00: Timing 0 Other: Timing 1 Selects the memory window 1 timing 00: Timing 0 Other: Timing 1 Selects the memory window 0 timing 00: Timing 0 Other: Timing 1 Function 5:4 MEM_WIN2_TIMSEL(1:0) 3:2 MEM_WIN1_TIMSEL(1:0) 1:0 MEM_WIN0_TIMSEL(1:0) 13.3.70 MEM_TIM_SEL2 (PCI offset address: 0x88D, ExCA extended offset address: 0x12) Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 RFU 2 RFU 1 MEM_WIN4 _TIMSEL1 R/W 0 0 MEM_WIN4 _TIMSEL0 R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit 7:2 1:0 Name RFU MEM_WIN4_TIMSEL(1:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Selects the memory window 4 timing 00: Timing 0 Other: Timing 1 256 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.3.71 MEM_WIN_PWEN (PCI offset address: 0x891, ExCA extended offset address: 0x16) Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 POSTWEN R/W 0 Bit 7:1 0 Name RFU POSTWEN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables the memory window post write cycle 1: Enable 0: Disable Caution The setting of POSTWEN bit is common for all windows. User's Manual U14579EJ2V0UM 257 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4 CardBus Socket Register Set When all of the following conditions are satisfied, the CardBus socket registers can be accessed according to a memory access from the primary side. * The higher 20 bits of the address match the higher 20 bits of the CSRBADR register. * The lower 12 bits of the address are in the range 0x000 to 0x7FF. * The MEM_EN bit of the PCICMD register is set to 1. Figure 13-4. CardBus Socket Registers Configuration registers PCI memory space 0xFFF ExCA registers 0x800 0x7FF CardBus socket registers 0x000 0x10 CSRBADR Table 13-4 lists the CardBus socket registers. CARDU1 and CARDU2 each have the following registers. Table 13-4. CardBus Socket Registers Offset Address 0x000 0x004 0x008 0x00C 0x010 0x014 to 0x7FF R/W R/W R/W R R/W R/W - Register Symbol SKT_EV SKT_MASK SKT_PRE_STATE SKT_FORCE_EV SKT_CNT - Socket event register Socket mask register Socket present state register Socket force event register Socket control register Reserved Function 258 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.1 SKT_EV (offset address: 0x000) (1/2) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 POW_ CYC_EV R/W 0 2 CCD2_EV 1 CCD1_EV 0 CSTSCHG_ EV R/W 0 R/W After reset R 0 R 0 R 0 R 0 R/W 0 R/W 0 Bit 31:4 3 Name RFU POW_CYC_EV Function Reserved. Write 0 to these bits. 0 is returned after a read. Whether or not a change to 1 is to be detected in the POW_UP bit of the SKT_PRE_STATE register. Cleared to 0 when 1 is written. 1: Detected 0: Not detected Whether or not a change is to be detected in the CD12# or CD22# signal. Cleared to 0 when 1 is written. 1: Detected 0: Not detected Whether or not a change is to be detected in the CD11# or CD21# signal. Cleared to 0 when 1 is written. 1: Detected 0: Not detected 2 CCD2_EV 1 CCD1_EV User's Manual U14579EJ2V0UM 259 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 0 Name CSTSCHG_EV Function * For a 16-bit memory card Whether or not a change to 0 is to be detected in the BVD1 signal (corresponds to the BVD11# or BVD21# signal of the VRC4173) or BVD2 signal (corresponds to the BVD12# or BVD22# signal of the VRC4173) and a change to 1 is to be detected in the READY signal. * For a 16-bit I/O card Whether or not a change to 0 is to be detected in the STSCHG# signal (corresponds to the BVD11# or BVD21# signal of the VRC4173) and a change to 0 is to be detected in the RI# signal (internal signal) (However, the CARDU unit does not support the Ring Indicate function). 1: Detected 0: Not detected This bit can be cleared to 0 when 1 is written. 260 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.2 SKT_MASK (offset address: 0x004) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 RFU 6 RFU 5 RFU 4 RFU 3 POW_ CYC_MSK R/W 0 2 CCD_MSK1 1 CCD_MSK0 0 CSC_MSK R/W After reset R 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 Bit 31:4 3 Name RFU POW_CYC_MSK Function Reserved. Write 0 to these bits. 0 is returned after a read. Controls interrupt requests according to the POW_CYC_EN bit of the SKT_EV register 1: Do not mask 0: Mask Controls interrupt requests according to the CCD1_EV and CCD2_EV bits of the SKT_EV register 11: Do not mask 00: Mask The settings 01 and 10 are prohibited. If they are set, they will be treated as if 00 were set (mask). Controls interrupt requests according to the CSTSCHG_EV bit of the SKT_EV register 1: Do not mask 0: Mask 2:1 CCD_MSK(1:0) 0 CSC_MSK User's Manual U14579EJ2V0UM 261 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.3 SKT_PRE_STATE (offset address: 0x008) (1/2) Bit Name R/W After reset 31 YV_SKT R 0 30 XV_SKT R 0 29 3V_SKT R 1 28 5V_SKT R 1 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name 15 RFU 14 RFU 13 YV_CARD_ DT R 0 12 XV_CARD_ DT R 0 11 3V_CARD_ DT R 0 10 5V_CARD_ DT R 0 9 BAD_VCC_ REQ R 0 8 DATA_ LOST R 0 R/W After reset R 0 R 0 Bit Name 7 NOT_A_ CARD R 0 6 READY 5 CB_CARD_ DTNote R 0 4 R2_CARD_ DT R 0 3 POW_UP 2 CCD20 1 CCD10 0 CSTSCHGNote R/W After reset R 0 R 0 R 1 R 1 R 0 Bit 31 30 29 28 27:14 13 Name YV_SKT XV_SKT 3V_SKT 5V_SKT RFU YV_CARD_DT Function Supplies YV (arbitrary) voltage. The CARDU unit does not support this function. Supplies XV (arbitrary) voltage. The CARDU unit does not support this function. Controls the 3 V power supply. This bit is fixed at 1 (enabled). Controls the 5 V power supply. This bit is fixed at 1 (enabled). Reserved. Write 0 to these bits. 0 is returned after a read. Detects a YV card 1: Detect a card that is operating at Y.Y V 0: Detect a card that is not operating at Y.Y V Detects a XV card 1: Detect a card that is operating at X.X V 0: Detect a card that is not operating at X.X V 12 XV_CARD_DT Note The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). 262 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 11 Name 3V_CARD_DT Function Detects a 3 V card 1: Detect a card that is operating at 3 V 0: Detect a card that is not operating at 3 V Detects a 5 V card 1: Detect a card that is operating at 5 V 0: Detect a card that is not operating at 5 V Invalid VCC request 1: Software requests an invalid VCC 0: Software requests a valid VCC However, if the BAD_VCC_REQ_DISB bit of the SYSCNT register within the configuration registers is 1, the request will be according to that bit. Determines the possibility of data being lost by removing the card 1: Data may be lost 0: Data is not lost Determines whether a card that can be recognized was inserted 1: A card that cannot be recognized was inserted 0: A card that can be recognized was inserted Status of the READY signal of the memory card or IREQ# signal (corresponds to the READY1 or READY2 signal of the VRC4173) of the I/O card 1: Low level 0: High level Whether or not the CardBus card (32-bit PC card) is to be detected 1: Detected 0: Not detected Whether or not the R2 PC card (16-bit PC card) is to be detected 1: Detected 0: Not detected Status of power to the socket 1: Power up completed 0: Power down Whether or not the PC card is connected (status of CCD2# signal (corresponds to the CD12# or CD22# signal of the VRC4173)) 1: Not connected (high level) 0: Connected (low level) Whether or not the PC card is connected (status of CCD1# signal (corresponds to the CD11# or CD21# signal of the VRC4173)) 1: Not connected (high level) 0: Connected (low level) Status of the CSTSCHG signal (corresponds to the BVD11# or BVD21# signal of the VRC4173) of the CardBus card 1: High level 0: Low level 10 5V_CARD_DT 9 BAD_VCC_REQ 8 DATA_LOST 7 NOT_A_CARD 6 READY 5 CB_CARD_DTNote 4 R2_CARD_DT 3 POW_UP 2 CCD20 1 CCD10 0 CSTSCHGNote Note The CARDU of the VRC4173 does not support a 32-bit PC card (CardBus card). This register indicates the status of the power supply voltage that is supplied to a card connected to the PC card bus. User's Manual U14579EJ2V0UM 263 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.4 SKT_FORCE_EV (offset address: 0x00C) (1/2) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name 15 RFU 14 CVS_TEST 13 YV_CARD 12 XV_CARD 11 3V_CARD 10 5V_CARD 9 BAD_VCC_ REQ W Undefined 8 DATA_LOST R/W After reset R 0 W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined Bit Name 7 NOT_A_ CARD W Undefined 6 RFU 5 CB_CARD 4 R2_CARD 3 POW_UP 2 CCD20 1 CCD10 0 CSTSCHG R/W After reset R 0 W Undefined W Undefined W Undefined W Undefined W Undefined W Undefined Bit 31:15 14 13 Name RFU CVS_TEST YV_CARD Function Reserved. Write 0 to these bits. 0 is returned after a read. When 1 is written to this bit, interlocation is redone. The value written to this bit becomes the value of the YV_CARD_DT bit of the SKT_PRE_STATE register. The value written to this bit becomes the value of the XV_CARD_DT bit of the SKT_PRE_STATE register. The value written to this bit becomes the value of the 3V_CARD_DT bit of the SKT_PRE_STATE register. The value written to this bit becomes the value of the 5V_CARD_DT bit of the SKT_PRE_STATE register. The value written to this bit becomes the value of the BAD_VCC_REQ bit of the SKT_PRE_STATE register. The value written to this bit becomes the value of the DATA_LOST bit of the SKT_PRE_STATE register. The value written to this bit becomes the value of the NOT_A_CARD bit of the SKT_PRE_STATE register. Reserved. Write 0 to this bit. 0 is returned after a read. 12 XV_CARD 11 3V_CARD 10 5V_CARD 9 BAD_VCC_REQ 8 DATA_LOST 7 NOT_A_CARD 6 RFU 264 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 5 Name CB_CARD Function The value written to this bit becomes the value of the CB_CARD_DT bit of the SKT_PRE_STATE register. However, the value is ignored if there is a card. The value written to this bit becomes the value of the R2_CARD_DT bit of the SKT_PRE_STATE register. However, the value is ignored if there is a card. When 1 is written to this bit, the POW_CYC_EV bit of the SKT_EV register is set. The POW_UP bit of the SKT_PRE_STATE register is not affected. When 1 is written to this bit, the CCD2_EV bit of the SKT_EV register is set. The CCD20 bit of the SKT_PRE_STATE register is not affected. When 1 is written to this bit, the CCD1_EV bit of the SKT_EV register is set. The CCD10 bit of the SKT_PRE_STATE register is not affected. When 1 is written to this bit, the CSTSCHG_EV bit of the SKT_EV register is set. The CSTSCHG bit of the SKT_PRE_STATE register is not affected. 4 R2_CARD 3 POW_UP 2 CCD20 1 CCD10 0 CSTSCHG User's Manual U14579EJ2V0UM 265 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.4.5 SKT_CNT (offset address: 0x010) (1/2) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 STP_CLK_ EN R/W 0 6 VCC_CNT2 5 VCC_CNT1 4 VCC_CNT0 3 RFU 2 VPP_CNT2 1 VPP_CNT1 0 VPP_CNT0 R/W After reset R/W 0 R/W 0 R/W 0 R 0 R/W 0 R/W 0 R/W 0 Bit 31:8 7 Name RFU STP_CLK_EN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables clock stopping according to the clock run protocol 1: Enable 0: Disable Controls the VCC power supply 111: Reserved 110: Reserved 101: VCC = Y.Y V 100: VCC = X.X V 011: VCC = 3.3 V 010: VCC = 5 V 001: Reserved 000: VCC = 0 V (power off) Reserved. Write 0 to this bit. 0 is returned after a read. 6:4 VCC_CNT(2:0) 3 RFU 266 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2/2) Bit 2:0 Name VPP_CNT(2:0) Controls the VPP power supply 111: Reserved 110: Reserved 101: VPP = Y.Y V 100: VPP = X.X V 011: VPP = 3.3 V 010: VPP = 5 V 001: VPP = 12 V 000: VPP = 0 V (power off) Function Caution A read/write access to the VCC(1:0) or VPP(1:0) area of the PWR_CNT register within the ExCA registers will also be an access to this register. User's Manual U14579EJ2V0UM 267 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.5 PC Card Unit Operation This section provides supplementary information about PC card unit operation. 13.5.1 16-bit PC card support Each CARDU unit has five memory windows and two I/O windows for 16-bit PC cards. (1) Memory window Memory mapping can map from the 4 GB address space of a PCI system to the 64 MB address space within a card. The size of each memory window is 4 KB to 16 MB. Table 13-5 shows the registers related to memory windows. Table 13-5. Registers Related to Memory Windows Register Name ADR_WIN_EN MEM_WINm_SAL MEM_WINm_SAH MEM_WINm_EAL MEM_WINm_EAH MEM_WINm_SAU Bit Name MEM_WINm_EN MEM_WINm_SAL(7:0) MEM_WINm_SAH(3:0) MEM_WINm_EAL(7:0) MEM_WINm_EAH(3:0) MEM_WINm_SAU(7:0) Higher address (A(31:24)) of each window Determines the 16 MB block of the PCI 4 GB space into which the card's memory area is to be placed. Offset address (A(25:12)) of each window This value is added to the PCI address to obtain the memory address on the card. Common or attribute memory can be selected for each window. Writing can be disabled/enabled for each window. The data size of each window can be set to 8 or 16 bits. The access timing can be selected from two timingsNote for each window. The card's memory area post write cycle can be enabled (common for all windows). End address (A(23:12)) of each window Function Enables each memory window Start address (A(23:12)) of each window MEM_WINm_OAL MEM_WINm_OAH MEM_WINm_OAL(7:0) MEM_WINm_OAH(5:0) MEM_WINm_REGSET MEM_WINm_WP MEM_WINm_SAH MEM_TIM_SEL1 MEM_TIM_SEL2 MEM_WIN_PWEN MEM_WINm_DSIZE MEM_WINn_TIMSEL(2:0) MEM_WIN4_TIMSEL(2:0) POSTWEN Note These are set by using three memory timing registers. The component registers are shown below. * Timing 0: MEM0_SETUP_TIM register, MEM0_CMD_TIM register, and MEM0_HOLD_TIM register * Timing 1: MEM1_SETUP_TIM register, MEM1_CMD_TIM register, and MEM1_HOLD_TIM register Remark m = 0 to 4, n = 0 to 3 268 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) (2) I/O window I/O mapping can map from the first 64 KB address space of the 4 GB address space of a PCI system to the 64 KB address space within a card. The size of each I/O window is 2 KB to 64 KB. Table 13-6 shows the registers related to I/O windows. Table 13-6. Registers Related to I/O Windows Register Name ADR_WIN_EN IO_WINn_SAL IO_WINn_SAH IO_WINn_EAL IO_WINn_EAH IO_WINn_OAL IO_WINn_OAH IO_WIN_CNT Bit Name IO_WINn_EN IO_WINn_SAL(7:0) IO_WINn_SAH(7:0) IO_WINn_EAL(7:0) IO_WINn_EAH(7:0) IO_WINn_OAL(7:0) IO_WINn_OAH(7:0) IO_WINn_DATA_SEL Offset address (A(15:0)) of each window This value is added to the PCI address to obtain the I/O address on the card. Always enter 0 in the A0 bit. Selects whether the data size of each window is to be fixed or determined according to the IOIS16# signal. The data size of each window can be set to 8 or 16 bits. End address (A(15:0)) of each window Enables each I/O window Start address (A(15:0)) of each window Function IO_WINn_DATA_SIZE Remark n = 0, 1 User's Manual U14579EJ2V0UM 269 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.5.2 Interrupts Status interrupt requests of a PC card unit and function interrupt requests from a PC card are reported to the host by using PCI interrupts (parallel). Table 13-7 shows the sources of interrupts and their masking methods. Table 13-7. Interrupt Sources and Corresponding Masks Card Type 16-bit PC card Status/Function Status interrupt Interrupt Source Bit of the CARD_SC register within the ExCA registers is set Interrupt Mask Bit of the CARD_SCI register within the ExCA registers (corresponding to the CARD_SC register bit) is set None Function interrupt The IREQ# signal is active Caution An interrupt due to the CD1# or CD2# signal is masked according to hardware until interlocation ends. The sources of status interrupts other than those due to the detection of a change in the CD1# or CD2# signal can be detected synchronously with the clock or asynchronously. Set this detection mode by using the ASYN_INT_MODE bit of the SYSCNT register. 270 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) 13.5.3 Power supply interface The PC card unit has three serial signals, which are compatible with TI's TPS2202A, for controlling the socket power supplies (VPP and VCC). The VCC_CNT(2:0) and VPP_CNT(2:0) areas of the SKT_CNT register within the CardBus socket registers are monitored, and when there is a change in their values, the power supply control circuit operates and outputs serial signals (PWCDATA, PWCCLK, PWCLATCH). Among the serial data values output from the PWCDATA signal, the higher four bits indicate the CARDU2 (slot 2) supply voltage setting and the lower four bits indicate the CARDU1 (slot 1) supply voltage setting. Table 13-8 shows the relationships between the setting of the VPP_CNT(2:0) area of the CARDU1 (slot 1) SKT_CNT register, the PWCDATA signal, and the supply voltage. Table 13-9 shows the relationships between the setting of the VCC_CNT(2:0) area of the CARDU1 (slot 1) SKT_CNT register, the PWCDATA signal, and the supply voltage. Table 13-10 shows the relationships between the setting of the VPP_CNT(2:0) area of the CARDU2 (slot 2) SKT_CNT register, the PWCDATA signal, and the supply voltage. Table 13-11 shows the relationships between the setting of the VCC_CNT(2:0) area of the CARDU2 (slot 2) SKT_CNT register, the PWCDATA signal, and the supply voltage. Table 13-8. CARDU1 (Slot 1) VPP Settings VPP_CNT(2:0) Bit 0 000 001 010 011 100 101 110 111 0 1 0 0 1 1 1 1 PWCDATA Bit 1 0 0 1 1 1 1 1 1 0 12 5.0 3.3 X.X Y.Y - - 0 12 VCC (slot 1) VCC (slot 1) Hi-Z Hi-Z Hi-Z Hi-Z Request Voltage (V) Supply Voltage (V) Remark Hi-Z: High impedance Table 13-9. CARDU1 (Slot 1) VCC Settings VCC_CNT(2:0) Bit 2 000 001 010 011 100 101 110 111 0 1 0 1 1 1 1 1 PWCDATA Bit 3 0 1 1 0 1 1 1 1 Request Voltage (V) Supply Voltage (V) 0 - 5.0 3.3 X.X Y.Y - - 0 0 5.0 3.3 0 0 0 0 User's Manual U14579EJ2V0UM 271 CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Table 13-10. CARDU2 (Slot 2) VPP Settings VPP_CNT(2:0) Bit 4 000 001 010 011 100 101 110 111 0 1 0 0 1 1 1 1 PWCDATA Bit 5 0 0 1 1 1 1 1 1 0 12 5.0 3.3 X.X Y.Y - - 0 12 VCC (slot 2) VCC (slot 2) Hi-Z Hi-Z Hi-Z Hi-Z Request Voltage (V) Supply Voltage (V) Remark Hi-Z: High impedance Table 13-11. CARDU2 (Slot 2) VCC Settings VCC_CNT(2:0) Bit 6 000 001 010 011 100 101 110 111 0 1 0 1 1 1 1 1 PWCDATA Bit 7 0 1 1 0 1 1 1 1 Request Voltage (V) Supply Voltage (V) 0 - 5.0 3.3 X.X Y.Y - - 0 0 5.0 3.3 0 0 0 0 The setting timing is explained next. The VRC4173 supports two PC card slots. The supply voltages of each slot are set by writing to the VCC_CNT(2:0) and VPP_CNT(2:0) areas of the SKT_CNT register of the CARDU1 and CARDU2. Figure 13-5 shows the timing of the power supply control serial signals (PWCDATA, PWCCLK, and PWCLATCH). Caution When writing to the VCC_CNT(2:0) and VPP_CNT(2:0) areas of the SKT_CNT register, obey the following rules. * When setting the VCC_CNT(2:0) and VPP_CNT(2:0) areas for CARDU1 and CARDU2, set the areas for CARDU2 first and then for CARDU1. * Even if you want to set only one of CARDU1 and CARDU2, always set both units. If only one unit is set, the power supply voltage will not be set correctly. * Wait at least 12 s (395 PCLK) after issuing the CARDU2 setting commands before issuing the CARDU1 supply voltage setting commands. 272 User's Manual U14579EJ2V0UM CHAPTER 13 CARDU1, CARDU2 (PC CARD UNITS) Figure 13-5. Power Supply Control Serial Signal (PWCDATA, PWCCLK, PWCLATCH) Timing (a) Register setting PWCCLK output PCLK (input) VPP_CNT, VCC_CNT PWCCLK (output) Change in CARDU1 setting 0 10 17 20 30 35 (b) Register data latch PWCDATA output 36PCLK CARDU2_clk CARDU2_latch CARDU2_data c2_count(3:0) c2_data_latch shift_data(3:0) CARDU1_clk CARDU1_latch CARDU1_data out_count(3:0) c2_select PWCCLK (output) PWCLATCH (output) PWCDATA (output) 0 1 2 B7 3 B6 4 B5 5 B4 6 B3 7 B2 8 B1 9 B0 0 CARDU1 can be set Valid A7 0 1 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 A0 9 0 B3 B2 B1 B0 A3 A2 A1 A0 User's Manual U14579EJ2V0UM 273 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) The USBU of the VRC4173, which is a USB host controller, is compliant with OPEN HCI Specification Release 1.0. The USBU supports power management functions such as PCI/USB-side clock stopping functions. It is also equipped with two downstream ports. The USBU does not support legacy functions. 14.1 Features USBU features are shown below. Functions * Compliant with OPEN HCI Specification Release 1.0 * Communicates with a USB device asynchronously relative to the host CPU * Supports full-speed (12 Mbps) and low-speed (1.5 Mbps) USB devices * System clock: 48 MHz Interface * USB interface transceiver Compliant with the Universal Serial Bus Specification 1.0 Automatic switching between full speed (12 Mbps) and low speed (1.5 Mbps) Communication with the host CPU * Via the operational registers within the USB host controller * Via the host controller communication area of the system memory space Memory and I/O spaces * Mapping the operational registers to 4 KB blocks within the 4 GB system memory space * Locates a 256-byte host controller communication area within the system memory space On-chip FIFO * PCI side: 16 bytes (4 x 4 double words) * USB side: 64 bytes (64 x 1 byte) Root hub * Equipped with two downstream ports Lower power consumption * Has functions for stopping the PCI clock and USB clock 274 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2 USB Host Control Configuration Registers To set the hardware resources to be used by a device, the device characteristics, and device operations, the PCI local bus (internal PCI bus of the VRC4173) accesses the USB host control configuration registers. Each register is accessed according to the PCI configuration cycle. For more detailed information, refer to the PCI Local bus Specification Revision 2.1. Figure 14-1. USB Host Control Configuration Space 31 24 23 Device ID register Status register 16 15 87 Vendor ID register Command register Revision ID register Latency timer register Cache line size register 0 Offset 0x00 0x04 0x08 0x0C 0x10 0x14 Class code register Built-in self-test register Header type register Base address register Reserved Card bus CIS pointer Subsystem ID register Subsystem vendor ID register 0x28 0x2C 0x30 0x34 0x38 Interrupt line register 0x3C 0x40 Extended ROM base address Reserved Reserved Max_lat register Min_Gnt register Interrupt pin register Reserved Power management register 0xE0 User's Manual U14579EJ2V0UM 275 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.1 Register set Table 14-1 lists the USB host control configuration registers. Table 14-1. USB Host Control Configuration Registers Offset Address 0x00 0x02 0x04 0x06 0x08 Register Name Bits R/W Reset Value Contents Vendor ID register Device ID register Command register Status register Revision ID register 15:0 31:16 15:0 31:16 7:0 R R R/W R/W R 0x1033 0x0035 0x0000 0x0000 0x01 Vendor ID (NEC) Device ID of this macro (USBU) See 14.2.2. See 14.2.3. Indicates that it is compliant with the PCI Local bus Specification Revision 2.1. Indicates that it is a serial bus controller device. Indicates that it is a USB device. Indicates that it is an OpenHCI host controller. A cache cannot be used. Interval that the bus cycle continues to be executed. It is not a PCI-to-PCI bridge. BIST is not supported. See 14.2.4. (This can be written according to the setting of the ID Write Mask bit of the power management register.) (This can be written according to the setting of the ID Write Mask bit of the power management register.) Indicates the route of the interrupt request line (this can be written only when the power management register is used). Indicates that it is equipped with the INTA# signal (internal PCI bus signal). Burst cycle minimum request time 0x09 Class code base address register Class code sub class register Class code programming interface register 31:24 R 0x0C 23:16 15:8 R R 0x03 0x10 0x0C 0x0D Cache line size register Latency timer register 7:0 15:11 10:8 R R/W R R R R/W R(/W) 0x00 00000 000 0x80 0x00 0x0000 0000 0x0000 0x0E 0x0F 0x10 0x2C Header type register Built-in self-test register Base address register Subsystem vendor ID register 23:16 31:24 31:0 15:0 0x2E Subsystem ID register 31:16 R(/W) 0x0000 0x3C Interrupt line register 7:0 R(/W) 0x00 0x3D Interrupt pin register 15:8 R 0x01 0x3E Min_Gnt register (burst cycle minimum request time register) Max_lat register (bus usage right request frequency register) Power management register 23:16 R 0x01 0x3F 31:24 R 0x2A Maximum delay time until a response is returned when the PCI bus usage right is requested. See 14.2.5. 0xE0 31:0 R/W 0x0000 0000 276 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.2 Command register (offset address: 0x04) Bit Name 15 RFU 14 RFU 13 RFU 12 RFU 11 RFU 10 RFU 9 Fast backto-back enable R 0 8 SERR# enable R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R/W 0 Bit Name 7 Wait cycle control 6 Parity Error response 5 VGA palette snoop 4 Memory write and Invalidate enable R 0 3 Special Cycles 2 Bus Master 1 Memory space 0 I/O space R/W After reset R 0 R 0 R 0 R 0 R/W 0 R/W 0 R 0 Bit 15:10 9 8 Name RFU Fast back-to-back enable SERR# enable Function Reserved. Write 0 to these bits. 0 is returned after a read. Fast back-to-back access is not supported. Control of responses to system errors. 1: Do not control 0: Control Address/data stepping is not supported. Parity errors are not checked. The VGA palette snoop function is disabled. The memory write and invalidate function is disabled. 7 6 5 4 Wait cycle control Parity Error response VGA palette snoop Memory write and Invalidate enable Special Cycles Bus Master 3 2 Special cycles are ignored. Control of bus master operation. 1: Do not control 0: Control Control of responses to memory accesses. 1: Do not control 0: Control The USBU does not react to I/O accesses. 1 Memory space 0 I/O space User's Manual U14579EJ2V0UM 277 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.3 Status register (offset address: 0x06) Bit Name 15 Detected parity error 14 Signaled system error R/W 0 13 Received master abort R/W 0 12 Received target abort R/W 0 11 Signal target abort R/W 0 10 DEVSEL timing 9 DEVSEL timing 8 Data Parity Error detected R/W 0 R/W After reset R/W 0 R 0 R 1 Bit Name 7 Fast backto-back capable R 0 6 UDF support 5 66 MHz capable 4 RFU 3 RFU 2 RFU 1 RFU 0 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit 15 Name Detected parity error Function Data and address parity error detection 1: Detected 0: Not detected SERR# signal status 1: Active 0: Inactive When a bus cycle that the USBU had been executing is terminated by a master abort, the master sets this bit to 1. When 0 is written, this bit is cleared. When a bus cycle that the USBU had been executing is terminated by a target abort, the master sets this bit to 1. When 0 is written, this bit is cleared. When a bus cycle that the USBU accessed is terminated by a target abort, the target sets this bit to 1. When 0 is written, this bit is cleared. Active timing of DEVSEL# signal 01: Medium speed This bit is set to 1 when the following three conditions are satisfied. * The USBU is the bus master of the bus cycle in which the data parity error occurred. * Either the USBU set the PERR# signal to active or the USBU detected that the PERR# signal became active due to the target. * The Parity Error response bit of the command register has been set to 1. Since the Parity Error response bit is fixed at 0 for the USBU unit, this bit will not be set to 1. Response to fast Back-to-Back. This is fixed at 0 (disabled). UDF is not supported. 33 MHz operation is set. Reserved. Write 0 to these bits. 0 is returned after a read. 14 Signaled system error 13 Received master abort 12 Received target abort 11 Signal target abort 10:9 DEVSEL timing 8 Data Parity Error detected 7 Fast back-to-back capable 6 5 4:0 UDF support 66 MHz capable RFU 278 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.4 Base address register (offset address: 0x10) Bit Name 31 Base address (MSB) R/W 0 30 Base address (MSB) R/W 0 29 Base address (MSB) R/W 0 28 Base address (MSB) R/W 0 27 Base address (MSB) R/W 0 26 Base address (MSB) R/W 0 25 Base address (MSB) R/W 0 24 Base address (MSB) R/W 0 R/W After reset Bit Name 23 Base address (MSB) R/W 0 22 Base address (MSB) R/W 0 21 Base address (MSB) R/W 0 20 Base address (MSB) R/W 0 19 Base address (MSB) R/W 0 18 Base address (MSB) R/W 0 17 Base address (MSB) R/W 0 16 Base address (MSB) R/W 0 R/W After reset Bit Name 15 Base address (MSB) R/W 0 14 Base address (MSB) R/W 0 13 Base address (MSB) R/W 0 12 Base address (MSB) R/W 0 11 Base address (LSB) R 0 10 Base address (LSB) R 0 9 Base address (LSB) R 0 8 Base address (LSB) R 0 R/W After reset Bit Name 7 Base address (LSB) R 0 6 Base address (LSB) R 0 5 Base address (LSB) R 0 4 Base address (LSB) R 0 3 Prefetchable 2 Type 1 Type 0 Memory space Indicator R 0 R/W After reset R 0 R 0 R 0 Bit 31:12 11:4 3 2:1 Name Base address (MSB) Base address (LSB) Prefetchable Type Function These are the higher 20 bits of the base address of the operational registers. This indicates that the operational registers have a 4 KB address space. Not prefetchable. This indicates that the operational registers can be located anywhere in the 4 GB main memory space. This indicates that the operational registers are mapped to the main memory space. 0 Memory space Indicator User's Manual U14579EJ2V0UM 279 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.2.5 Power management register (offset address: 0xE0) (1/2) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name 23 RFU 22 RFU 21 RFU 20 RFU 19 RFU 18 RFU 17 RFU 16 Wakeup_ Enable R 0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name 15 RFU 14 RFU 13 RFU 12 RFU 11 RFU 10 RFU 9 RFU 8 Wakeup_ Status R/W 0 R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name 7 ID Write Mask 6 PC_mode 5 REQ_ Enable 4 RFU 3 RFU 2 Status Change Standby R 0 1 Power Status 0 Power Status R/W After reset R/W 0 R/W 0 R/W 0 R 0 R 0 R/W 0 R/W 0 Bit 31:17 16 Name RFU Wakeup_Enable Function Reserved. Write 0 to these bits. 0 is returned after a read. Controls WAKE signal (internal signal) output. 1: Enable WAKE signal (internal signal) 0: Disable WAKE signal (internal signal) Reserved. Write 0 to these bits. 0 is returned after a read. Whether or not a Wakeup request was received 1: Wakeup request was received 0: No Wakeup request was received Cleared to 0 when 1 is written. Does not change when 0 is written. Write protection of subsystem ID and subsystem vendor ID. 1: Write enabled 0: Write mask Controls switching between PC/ATTM-compatible and PC-9800 Series modes. 1: PC/AT compatible mode 0: PC-9800 Series mode 15:9 8 RFU Wakeup_Status 7 ID Write Mask 6 PC_mode 280 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 5 Name REQ_Enable Function Controls REQ# signal output timing. 1: PCICLK (internal clock) asynchronous output 0: PCICLK synchronous output Reserved. Write 0 to these bits. 0 is returned after a read. Device status relative to power status transition control. 1: Can correspond 0: Cannot correspond Power status control 11: D3 (PCICLK stopped, device power off) 10: D2 (PCICLK stopped, device power on) 01: Reserved 00: D0 (PCICLK full mode) 4:3 2 RFU Status Change Standby 1:0 Power Status Remarks 1. Always use the default setting (synchronous) for the REQ_Enable bit. If the asynchronous setting is used, the PCI specifications will be violated. 2. When the PC_mode bit = 0, the Power Status area is disabled. The Power Status area can be read or written from the system, but can only be read from the USB host controller (HC). 3. When the PC_mode bit = 0, the Wakeup_Status bit is disabled. When the PC_mode bit = 1 and the Power Status area = 10, the Wakeup_Status bit is set to 1 when a resume from the USB is detected. At this time, if the Wakeup_Enable bit is 1, set the WAKE signal (internal signal) to active. This bit is cleared when 1 is written to it and the WAKE signal is set to inactive at the same time. The above operations occur only when the RHSC bit of the HcInterruptEnable register is set. 4. When the PC_mode bit = 0, the Wakeup_Enable bit is disabled. 5. After 10 or 11 is set in the Power Status area, 0 is displayed in the Status Change Standby bit until the status change can actually occur, and 1 is displayed when the change can occur. Once the Status Change Standby bit becomes 1 after 10 or 11 is set in the Power Status area, it cannot return to 0. User's Manual U14579EJ2V0UM 281 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3 Operational Registers The USBU (USB host controller, HC) has on-chip operational registers, which are windows for communicating with the host CPU. These registers, which are mapped to a 4 KB range of the system's 4 GB main memory space, are used by the host controller driver (HCD). All of these registers are read/written in units of words. The CPU is accessed according to a PC memory cycle via the internal PCI bus. The base address is indicated by the base address register of the USB host control configuration space. For more detailed information, refer to the OPEN HCI Specification Release 1.0. 14.3.1 Register set Table 14-2 lists the host control operational registers. Table 14-2. Host Control Operational Registers Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 R/W (HCD) R R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (HC) R R/W R/W R/W R R R R/W R R/W R R/W R/W R R/W R/W R R R R R/W R/W R/W Register Symbol Function HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcFmInterval HcFmRemaining HcFmNumber HcPeriodicStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 HC revision register HC control register HC command register HC interrupt request detection register HC interrupt request enable register HC interrupt request disable register HC base address register HC period current ED register HC control list 1st ED register HC control list current ED register HC bulk list 1st ED register HC bulk list current ED register HC last TD register HC frame interval register HC frame bit time remaining register HC frame counter register HC list processing start register HC low speed transfer diagnosis register HC power supply status register A HC power supply status register B HC status register HC port status register 1 HC port status register 2 These registers are described in detail below. 282 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.2 HcRevision (offset address: 0x00) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R R Undefined 30 RFU R R Undefined 29 RFU R R Undefined 28 RFU R R Undefined 27 RFU R R Undefined 26 RFU R R Undefined 25 RFU R R Undefined 24 RFU R R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R R Undefined 22 RFU R R Undefined 21 RFU R R Undefined 20 RFU R R Undefined 19 RFU R R Undefined 18 RFU R R Undefined 17 RFU R R Undefined 16 RFU R R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R R Undefined 14 RFU R R Undefined 13 RFU R R Undefined 12 RFU R R Undefined 11 RFU R R Undefined 10 RFU R R Undefined 9 RFU R R Undefined 8 RFU R R Undefined Bit Name R/W (HCD) R/W (HC) After reset 7 Revision R R 0 6 Revision R R 0 5 Revision R R 0 4 Revision R R 1 3 Revision R R 0 2 Revision R R 0 1 Revision R R 0 0 Revision R R 0 Bit 31:8 Name RFU Function Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Indicates that the USBU is compliant with the OPEN HCI Specification Release 1.0. 7:0 Revision User's Manual U14579EJ2V0UM 283 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.3 HcControl (offset address: 0x04) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R/W R Undefined 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 RFU R/W R Undefined 10 RWE R/W R 0 0 9 RWC R/W R Note 1 8 IR R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 HCFS R/W R/W Note 2 6 HCFS R/W R/W Note 2 5 BLE R/W R 0 4 CLE R/W R 0 3 IE R/W R 0 2 PLE R/W R 0 1 CBSR R/W R 0 0 CBSR R/W R 0 Bit 31:11 Name RFU Function Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Remote Wakeup Enable Enables/disables remote wakeup when an upstream resume signal is detected. 1: Enable 0: Disable Remote Wakeup Connected Remote wakeup signal support. 1: Supported 0: Not supported 10 RWE 9 RWC Notes 1. Only a hardware reset is possible. 2. When a hardware reset occurs: 0, when a software reset occurs: 1 284 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 8 Name IR Function Interrupt Routing Route of interrupt request generated due to an event registered in the HcInterruptStatus register 1: SMI# signal (internal signal) output 0: USBINT# signal (internal signal) output Host Controller Functional Status for USB USB operation mode 11: UsbSuspend 10: UsbOperational 01: UsbResume 00: UsbReset Bulk List Enable Validity of bulk list processing of next frame 1: Valid 0: Invalid Control List Enable Validity of control list processing of next frame 1: Valid 0: Invalid Isochronous Enable Validity of IsochronousED (Endpoint Descriptor) processing of next frame 1: Valid 0: Invalid Periodic List Enable Validity of periodic list processing of next frame 1: Valid 0: Invalid Control Bulk Service Ratio Control/bulk ED service ratio 11: 4:1 10: 3:1 01: 2:1 00: 1:1 7:6 HCFS 5 BLE 4 CLE 3 IE 2 PLE 1:0 CBSR User's Manual U14579EJ2V0UM 285 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.4 HcCommandStatus (offset address: 0x08) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R/W R Undefined 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 SOC R R/W 0 16 SOC R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 RFU R/W R Undefined 10 RFU R/W R Undefined 9 RFU R/W R Undefined 8 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 7 RFU R/W R Undefined 6 RFU R/W R Undefined 5 RFU R/W R Undefined 4 RFU R/W R Undefined 3 OCR R/W R/W 0 2 BLF R/W R/W 0 1 CLF R/W R/W 0 0 HCR R/W R/W 0 Bit 31:18 Name RFU Function Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Scheduling Overrun Count Scheduling overrun error count. Incremented as follows when an error occurs. 00 (initialization) 01 10 11 00 Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Ownership Change Request Whether or not an HC control change request was received. This bit is reset by the HCD. 1: Received 0: Not received Bulk List Filled Whether or not a TD (Transfer Descriptor) exists within the bulk list. 1: Exists 0: Does not exist 17:16 SOC 15:4 RFU 3 OCR 2 BLF 286 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 1 Name CLF Function Control List Filled Whether or not a TD exists within the control list. 1: Exists 0: Does not exist Host Controller Reset HC software reset Set (1) by the HCD and cleared (0) by the HC. 0 HCR User's Manual U14579EJ2V0UM 287 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.5 HcInterruptStatus (offset address: 0x0C) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R R 0 30 OC R/W R/W 0 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 RFU R/W R Undefined 10 RFU R/W R Undefined 9 RFU R/W R Undefined 8 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 7 RFU R/W R Undefined 6 RHSC R/W R/W 0 5 FNO R/W R/W 0 4 UE R/W R/W 0 3 RD R/W R/W 0 2 SF R/W R/W 0 1 WDH R/W R/W 0 0 SO R/W R/W 0 Bit 31 30 Name RFU OC Function Reserved. Write 0 to these bits. 0 is returned after a read. Ownership Change This bit is set (1) by the HC when the HCD sets the OCR bit of the HcCommandStatus register. When it is not masked, this event immediately generates a system monitor interrupt request (SMI). This bit is cleared when 0 is written. Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Root Hub Status Change This bit is set (1) when the contents of the HcRhStatus register or HcRhPortStatusN (N = 1, 2) register are changed. This bit is cleared (0) when 0 is written. Frame Number Overflow Change in the value of bit 15 of the HcFmNumber register 1: Change 0: No change 29:7 RFU 6 RHSC 5 FNO 288 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 4 Name UE Function Unrecoverable Error Detection of system error not related to the USB 1: Detected 0: Normal Resume Detected Detection of resume signal 1: Detected 0: Normal Start of Frame This bit is set at the start of a frame. This bit is cleared (0) when 0 is written. Writeback Done Head This bit is set (1) when the contents of the HcDoneHead register are written to the HccaDoneHead areaNote. This bit is cleared (0) by the HCD after the contents of the HccaDoneHead area are saved. Scheduling overrun Occurrence of an overrun due to the USB schedule of the current frame 1: Occurred 0: Normal 3 RD 2 SF 1 WDH 0 SO Note The HccaDoneHead area is in the HCCA (Host Controller Communication Area). The HCCA is a 256-byte system memory area that is used when the HCD and HC communicate. For details, see 14.4.11 HCCA (Host Controller Communication Area). User's Manual U14579EJ2V0UM 289 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.6 HcInterruptEnable (offset address: 0x10) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 MIE R R 0 30 OC R/W R 0 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 RFU R/W R Undefined 10 RFU R/W R Undefined 9 RFU R/W R Undefined 8 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 7 RFU R/W R Undefined 6 RHSC R/W R 0 5 FNO R/W R 0 4 UE R/W R 0 3 RD R/W R 0 2 SF R/W R 0 1 WDH R/W R 0 0 SO R/W R 0 Bit 31 Name MIE Function Master Interrupt Enable Validity of enabling of interrupts due to events indicated by other bits of this register 1: Valid 0: Invalid Ownership Change Interrupt request due to Ownership Change 1: Enable 0: Disable Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Root Hub Status Change Interrupt request due to Root Hub Status Change 1: Enable 0: Disable 30 OC 29:7 RFU 6 RHSC 290 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 5 Name FNO Function Frame Number Overflow Interrupt request due to Frame Number Overflow 1: Enable 0: Disable Unrecoverable Error Interrupt request due to Unrecoverable Error 1: Enable 0: Disable Resume Detected Interrupt request due to Resume Detected 1: Enable 0: Disable Start of Frame Interrupt request due to Start of Frame 1: Enable 0: Disable Writeback Done Head Interrupt request due to HcDoneHead Writeback 1: Enable 0: Disable Scheduling Overrun Interrupt request due to Scheduling Overrun 1: Enable 0: Disable 4 UE 3 RD 2 SF 1 WDH 0 SO This register controls the sources that generate hardware interrupt requests. Although a bit is set when 1 is written, even if 0 is written to a bit, it will be ignored. To clear (0) the value, write 1 to the corresponding bit of the HcInterruptDisable register. Each bit of this register corresponds to a bit of the HcInterruptStatus register. A hardware interrupt request is generated when all of the following conditions are satisfied. * The interrupt source occurred and any bit of the HcInterruptStatus register was set. * The corresponding bit of the HcInterruptEnable register is set. * The MIE bit of the HcInterruptEnable register is set. User's Manual U14579EJ2V0UM 291 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.7 HcInterruptDisable (offset address: 0x14) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 MIE R R 0 30 OC R/W R 0 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 RFU R/W R Undefined 10 RFU R/W R Undefined 9 RFU R/W R Undefined 8 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 7 RFU R/W R Undefined 6 RHSC R/W R 0 5 FNO R/W R 0 4 UE R/W R 0 3 RD R/W R 0 2 SF R/W R 0 1 WDH R/W R 0 0 SO R/W R 0 Bit 31 Name MIE Function Master Interrupt Enable Validity of enabling of interrupts due to events indicated by other bits of this register 1: Invalid Ownership Change Interrupt request due to Ownership Change 1: Disable Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Root Hub Status Change Interrupt request due to Root Hub Status Change 1: Disable Frame Number Overflow Interrupt request due to Frame Number Overflow 1: Disable 30 OC 29:7 RFU 6 RHSC 5 FNO 292 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 4 Name UE Function Unrecoverable Error Interrupt request due to Unrecoverable Error 1: Disable Resume Detected Interrupt request due to Resume Detected 1: Disable Start of Frame Interrupt request due to Start of Frame 1: Disable Writeback Done Head Interrupt request due to HcDoneHead Writeback 1: Disable Scheduling Overrun Interrupt request due to Scheduling Overrun 1: Disable 3 RD 2 SF 1 WDH 0 SO This register is used to clear (0) the corresponding bit of the HcInterruptEnable register. When 1 is written to a bit of this register, the corresponding bit of the HcInterruptEnable register is cleared (0). Even if 0 is written to a bit of this register, it will be ignored. When this register is read, the value of the HcInterruptEnable register is returned. User's Manual U14579EJ2V0UM 293 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.8 HcHCCA (offset address: 0x18) Bit Name R/W (HCD) R/W (HC) After reset 31 HCCA R/W R 0 30 HCCA R/W R 0 29 HCCA R/W R 0 28 HCCA R/W R 0 27 HCCA R/W R 0 26 HCCA R/W R 0 25 HCCA R/W R 0 24 HCCA R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 23 HCCA R/W R 0 22 HCCA R/W R 0 21 HCCA R/W R 0 20 HCCA R/W R 0 19 HCCA R/W R 0 18 HCCA R/W R 0 17 HCCA R/W R 0 16 HCCA R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 15 HCCA R/W R 0 14 HCCA R/W R 0 13 HCCA R/W R 0 12 HCCA R/W R 0 11 HCCA R/W R 0 10 HCCA R/W R 0 9 HCCA R/W R 0 8 HCCA R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 HCCA R R 0 6 HCCA R R 0 5 HCCA R R 0 4 HCCA R R 0 3 HCCA R R 0 2 HCCA R R 0 1 HCCA R R 0 0 HCCA R R 0 Bit 31:0 Name HCCA Function Host Controller Communication Area Base address of the host controller communication area. Since this area is located in 256-byte units, bits 7 to 0 are fixed at 0. 294 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.9 HcPeriodCurrentED (offset address: 0x1C) Bit Name R/W (HCD) R/W (HC) After reset 31 PCED R R/W 0 30 PCED R R/W 0 29 PCED R R/W 0 28 PCED R R/W 0 27 PCED R R/W 0 26 PCED R R/W 0 25 PCED R R/W 0 24 PCED R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 23 PCED R R/W 0 22 PCED R R/W 0 21 PCED R R/W 0 20 PCED R R/W 0 19 PCED R R/W 0 18 PCED R R/W 0 17 PCED R R/W 0 16 PCED R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 15 PCED R R/W 0 14 PCED R R/W 0 13 PCED R R/W 0 12 PCED R R/W 0 11 PCED R R/W 0 10 PCED R R/W 0 9 PCED R R/W 0 8 PCED R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 7 PCED R R/W 0 6 PCED R R/W 0 5 PCED R R/W 0 4 PCED R R/W 0 3 PCED R R 0 2 PCED R R 0 1 PCED R R 0 0 PCED R R 0 Bit 31:0 Name PCED Function Period Current ED Physical address of the Isochronous/InterruptED of the periodic list processed by the current frame. Since the ED (Endpoint Descriptor) is located in 16-byte units, bits 3 to 0 are fixed at 0. User's Manual U14579EJ2V0UM 295 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.10 HcControlHeadED (offset address: 0x20) Bit Name R/W (HCD) R/W (HC) After reset 31 CHED R/W R 0 30 CHED R/W R 0 29 CHED R/W R 0 28 CHED R/W R 0 27 CHED R/W R 0 26 CHED R/W R 0 25 CHED R/W R 0 24 CHED R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 23 CHED R/W R 0 22 CHED R/W R 0 21 CHED R/W R 0 20 CHED R/W R 0 19 CHED R/W R 0 18 CHED R/W R 0 17 CHED R/W R 0 16 CHED R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 15 CHED R/W R 0 14 CHED R/W R 0 13 CHED R/W R 0 12 CHED R/W R 0 11 CHED R/W R 0 10 CHED R/W R 0 9 CHED R/W R 0 8 CHED R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 CHED R/W R 0 6 CHED R/W R 0 5 CHED R/W R 0 4 CHED R/W R 0 3 CHED R R 0 2 CHED R R 0 1 CHED R R 0 0 CHED R R 0 Bit 31:0 Name CHED Function Control Head ED Physical address of the control list 1st ED. For details about the ED (Endpoint Descriptor), see 14.4.3 ED (Endpoint Descriptor). 296 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.11 HcControlCurrentED (offset address: 0x24) Bit Name R/W (HCD) R/W (HC) After reset 31 CCED R/W R/W 0 30 CCED R/W R/W 0 29 CCED R/W R/W 0 28 CCED R/W R/W 0 27 CCED R/W R/W 0 26 CCED R/W R/W 0 25 CCED R/W R/W 0 24 CCED R/W R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 23 CCED R/W R/W 0 22 CCED R/W R/W 0 21 CCED R/W R/W 0 20 CCED R/W R/W 0 19 CCED R/W R/W 0 18 CCED R/W R/W 0 17 CCED R/W R/W 0 16 CCED R/W R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 15 CCED R/W R/W 0 14 CCED R/W R/W 0 13 CCED R/W R/W 0 12 CCED R/W R/W 0 11 CCED R/W R/W 0 10 CCED R/W R/W 0 9 CCED R/W R/W 0 8 CCED R/W R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 7 CCED R/W R/W 0 6 CCED R/W R/W 0 5 CCED R/W R/W 0 4 CCED R/W R/W 0 3 CCED R R 0 2 CCED R R 0 1 CCED R R 0 0 CCED R R 0 Bit 31:0 Name CCED Function Control Current ED Physical address of the control list current ED. For details about the ED (Endpoint Descriptor), see 14.4.3 ED (Endpoint Descriptor). User's Manual U14579EJ2V0UM 297 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.12 HcBulkHeadED (offset address: 0x28) Bit Name R/W (HCD) R/W (HC) After reset 31 BHED R/W R 0 30 BHED R/W R 0 29 BHED R/W R 0 28 BHED R/W R 0 27 BHED R/W R 0 26 BHED R/W R 0 25 BHED R/W R 0 24 BHED R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 23 BHED R/W R 0 22 BHED R/W R 0 21 BHED R/W R 0 20 BHED R/W R 0 19 BHED R/W R 0 18 BHED R/W R 0 17 BHED R/W R 0 16 BHED R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 15 BHED R/W R 0 14 BHED R/W R 0 13 BHED R/W R 0 12 BHED R/W R 0 11 BHED R/W R 0 10 BHED R/W R 0 9 BHED R/W R 0 8 BHED R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 BHED R/W R 0 6 BHED R/W R 0 5 BHED R/W R 0 4 BHED R/W R 0 3 BHED R R 0 2 BHED R R 0 1 BHED R R 0 0 BHED R R 0 Bit 31:0 Name BHED Function Bulk Head ED Physical address of the bulk list 1st ED. For details about the ED (Endpoint Descriptor), see 14.4.3 ED (Endpoint Descriptor). 298 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.13 HcBulkCurrentED (offset address: 0x2C) Bit Name R/W (HCD) R/W (HC) After reset 31 BCED R/W R/W 0 30 BCED R/W R/W 0 29 BCED R/W R/W 0 28 BCED R/W R/W 0 27 BCED R/W R/W 0 26 BCED R/W R/W 0 25 BCED R/W R/W 0 24 BCED R/W R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 23 BCED R/W R/W 0 22 BCED R/W R/W 0 21 BCED R/W R/W 0 20 BCED R/W R/W 0 19 BCED R/W R/W 0 18 BCED R/W R/W 0 17 BCED R/W R/W 0 16 BCED R/W R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 15 BCED R/W R/W 0 14 BCED R/W R/W 0 13 BCED R/W R/W 0 12 BCED R/W R/W 0 11 BCED R/W R/W 0 10 BCED R/W R/W 0 9 BCED R/W R/W 0 8 BCED R/W R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 7 BCED R/W R/W 0 6 BCED R/W R/W 0 5 BCED R/W R/W 0 4 BCED R/W R/W 0 3 BCED R R 0 2 BCED R R 0 1 BCED R R 0 0 BCED R R 0 Bit 31:0 Name BCED Function Bulk Current ED Physical address of the bulk list current ED. For details about the ED (Endpoint Descriptor), see 14.4.3 ED (Endpoint Descriptor). User's Manual U14579EJ2V0UM 299 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.14 HcDoneHead (offset address: 0x30) Bit Name R/W (HCD) R/W (HC) After reset 31 DH R R/W 0 30 DH R R/W 0 29 DH R R/W 0 28 DH R R/W 0 27 DH R R/W 0 26 DH R R/W 0 25 DH R R/W 0 24 DH R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 23 DH R R/W 0 22 DH R R/W 0 21 DH R R/W 0 20 DH R R/W 0 19 DH R R/W 0 18 DH R R/W 0 17 DH R R/W 0 16 DH R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 15 DH R R/W 0 14 DH R R/W 0 13 DH R R/W 0 12 DH R R/W 0 11 DH R R/W 0 10 DH R R/W 0 9 DH R R/W 0 8 DH R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 7 DH R R/W 0 6 DH R R/W 0 5 DH R R/W 0 4 DH R R/W 0 3 DH R R 0 2 DH R R 0 1 DH R R 0 0 DH R R 0 Bit 31:0 Name DH Function Done Head Physical address of the last TD that was added to the Done queue (transfer completed queue). For details about the TD (Transfer Descriptor), see 14.4.6 TD (Transfer Descriptor). 300 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.15 HcFmInterval (offset address: 0x34) Bit Name R/W (HCD) R/W (HC) After reset 31 FIT R/W R 0 30 FSMPS R/W R 0 29 FSMPS R/W R 0 28 FSMPS R/W R 0 27 FSMPS R/W R 0 26 FSMPS R/W R 0 25 FSMPS R/W R 0 24 FSMPS R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 23 FSMPS R/W R 0 22 FSMPS R/W R 0 21 FSMPS R/W R 0 20 FSMPS R/W R 0 19 FSMPS R/W R 0 18 FSMPS R/W R 0 17 FSMPS R/W R 0 16 FSMPS R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 FI R/W R 1 12 FI R/W R 0 11 FI R/W R 1 10 FI R/W R 1 9 FI R/W R 1 8 FI R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 FI R/W R 1 6 FI R/W R 0 5 FI R/W R 1 4 FI R/W R 1 3 FI R/W R 1 2 FI R/W R 1 1 FI R/W R 1 0 FI R/W R 1 Bit 31 Name FIT Function Frame Interval Toggle This bit is inverted when a value is loaded into the FI area. FS Large Data Packet This is the maximum number of data bits that can be transmitted/received by a single process. Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Frame Interval This is the bit time per frame. 30:16 FSMPS 15:14 RFU 13:0 FI User's Manual U14579EJ2V0UM 301 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.16 HcFmRemaining (offset address: 0x38) Bit Name R/W (HCD) R/W (HC) After reset 31 FRT R R/W 0 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 FR R R/W 0 12 FR R R/W 0 11 FR R R/W 0 10 FR R R/W 0 9 FR R R/W 0 8 FR R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 7 FR R R/W 0 6 FR R R/W 0 5 FR R R/W 0 4 FR R R/W 0 3 FR R R/W 0 2 FR R R/W 0 1 FR R R/W 0 0 FR R R/W 0 Bit 31 Name FRT Function Frame Remaining Toggle When the FR area becomes 0, the value of the FIT area of the HcFmInterval register is loaded in this bit. Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Frame Remaining This is a down counter that indicates the remaining bit time of the current frame. 30:14 RFU 13:0 FR 302 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.17 HcFmNumber (offset address: 0x3C) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R/W R Undefined 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 FN R R/W 0 14 FN R R/W 0 13 FN R R/W 0 12 FN R R/W 0 11 FN R R/W 0 10 FN R R/W 0 9 FN R R/W 0 8 FN R R/W 0 Bit Name R/W (HCD) R/W (HC) After reset 7 FN R R/W 0 6 FN R R/W 0 5 FN R R/W 0 4 FN R R/W 0 3 FN R R/W 0 2 FN R R/W 0 1 FN R R/W 0 0 FN R R/W 0 Bit 31:16 Name RFU Function Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Frame Number This is a counter that is incremented when the HcFmRemaining register is reloaded. 15:0 FN User's Manual U14579EJ2V0UM 303 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.18 HcPeriodicStart (offset address: 0x40) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R/W R Undefined 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 PS R/W R 0 12 PS R/W R 0 11 PS R/W R 0 10 PS R/W R 0 9 PS R/W R 0 8 PS R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 PS R/W R 0 6 PS R/W R 0 5 PS R/W R 0 4 PS R/W R 0 3 PS R/W R 0 2 PS R/W R 0 1 PS R/W R 0 0 PS R/W R 0 Bit 31:14 Name RFU Function Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Periodic Start This area indicates when periodic list processing started. The standard value is 0x3E67 counts (1 count is 0.1 ms). 13:0 PS 304 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.19 HcLSThreshold (offset address: 0x44) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R/W R Undefined 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 LST R/W R 0 10 LST R/W R 1 9 LST R/W R 1 8 LST R/W R 0 Bit Name R/W (HCD) R/W (HC) After reset 7 LST R/W R 0 6 LST R/W R 0 5 LST R/W R 1 4 LST R/W R 0 3 LST R/W R 1 2 LST R/W R 0 1 LST R/W R 0 0 LST R/W R 0 Bit 31:12 Name RFU Function Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Low-Speed Threshold This value is compared with the FR area of the HcFmRemaining register to determine whether a low-speed transfer can be performed before the EOF (End of Frame). 11:0 LST User's Manual U14579EJ2V0UM 305 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.20 HcRhDescriptorA (offset address: 0x48) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 POTPGT R/W R 1 Note 30 POTPGT R/W R 1 Note 29 POTPGT R/W R 1 Note 28 POTPGT R/W R 1 Note 27 POTPGT R/W R 1 Note 26 POTPGT R/W R 1 Note 25 POTPGT R/W R 1 Note 24 POTPGT R/W R 1Note Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 RFU R/W R Undefined 16 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R/W R Undefined 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 NOCP R/W R 0 Note 11 OCPM R/W R 1 Note 10 DT R R 0 Note 9 NPS R/W R 0 Note 8 PSM R/W R 1Note Bit Name R/W (HCD) R/W (HC) After reset 7 NDP R R 0 Note 6 NDP R R 0 Note 5 NDP R R 0 Note 4 NDP R R 0 Note 3 NDP R R 0 Note 2 NDP R R 0 Note 1 NDP R R 1 Note 0 NDP R R 1Note Bit 31:24 Name POTPGT Function Poweron To Power Good Time Indicates the time that the HCD must support before accessing a port of the root hub to which power was applied. Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. No Over Current Protection Whether or not to report an over current state 1: Over current protection is not supported 0: Report an over current state Over Current Protection Mode Over current state report mode 1: Reported for each port 0: Reported for all downstream ports in a batch 23:13 RFU 12 NOCP 11 OCPM Note Only a hardware reset is possible for bits 31 to 24 and bits 12 to 0. 306 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 10 Name DT Function Device Type Indicates that the root hub is not a compound device. No Power Switching Denial of power application switching 1: If the HC is on, the port power is also always applied. 0: The port power can be on or off. Power Switching Mode Power application mode 1: The power is applied separately at each port. 0: The power is applied at all ports simultaneously. Number of Downstream Ports Number of downstream ports that are supported by the root hub 9 NPS 8 PSM 7:0 NDP User's Manual U14579EJ2V0UM 307 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.21 HcRhDescriptorB (offset address: 0x4C) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 31 PPCM R/W R 1 Note 30 PPCM R/W R 1 Note 29 PPCM R/W R 1 Note 28 PPCM R/W R 1 Note 27 PPCM R/W R 1 Note 26 PPCM R/W R 1 Note 25 PPCM R/W R 1 Note 24 PPCM R/W R 1Note Bit Name R/W (HCD) R/W (HC) After reset 23 PPCM R/W R 1Note 22 PPCM R/W R 1Note 21 PPCM R/W R 1Note 20 PPCM R/W R 1Note 19 PPCM R/W R 1Note 18 PPCM R/W R 1Note 17 PPCM R/W R 1Note 16 PPCM R/W R 0Note Bit Name R/W (HCD) R/W (HC) After reset 15 DR R/W R 0 Note 14 DR R/W R 0 Note 13 DR R/W R 0 Note 12 DR R/W R 0 Note 11 DR R/W R 0 Note 10 DR R/W R 0 Note 9 DR R/W R 0 Note 8 DR R/W R 0Note Bit Name R/W (HCD) R/W (HC) After reset 7 DR R/W R 0 Note 6 DR R/W R 0 Note 5 DR R/W R 0 Note 4 DR R/W R 0 Note 3 DR R/W R 0 Note 2 DR R/W R 0 Note 1 DR R/W R 0 Note 0 DR R/W R 0Note Bit 31:19 18 Name PPCM Function Reserved. Write 1 to these bits. 1 is returned after a read. Port Power Control Mask Masking of one set of power supplies of port 2 1: Mask 0: Do not mask Port Power Control Mask Masking of one set of power supplies of port 1 1: Mask 0: Do not mask Reserved. Write 0 to this bit. 0 is returned after a read. 17 16 Note Only a hardware reset is possible. 308 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 15:3 2 Name DR Function Reserved. Write 0 to these bits. 0 is returned after a read. Device Removable Connection of device to port 2 1: Connected 0: Not connected Device Removable Connection of device to port 1 1: Connected 0: Not connected Reserved. Write 0 to this bit. 0 is returned after a read. 1 0 User's Manual U14579EJ2V0UM 309 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.22 HcRhStatus (offset address: 0x50) (1/2) Bit Name R/W (HCD) R/W (HC) After reset 1 31 CRWE W R Note 1 30 RFU R/W R Undefined 29 RFU R/W R Undefined 28 RFU R/W R Undefined 27 RFU R/W R Undefined 26 RFU R/W R Undefined 25 RFU R/W R Undefined 24 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R/W R Undefined 22 RFU R/W R Undefined 21 RFU R/W R Undefined 20 RFU R/W R Undefined 19 RFU R/W R Undefined 18 RFU R/W R Undefined 17 OCIC R/W R/W 1Note 1 16 Note 2 R/W R 0Note 1 Bit Name R/W (HCD) R/W (HC) After reset 15 Note 2 R/W R 0 Note 1 14 RFU R/W R Undefined 13 RFU R/W R Undefined 12 RFU R/W R Undefined 11 RFU R/W R Undefined 10 RFU R/W R Undefined 9 RFU R/W R Undefined 8 RFU R/W R Undefined Bit Name R/W (HCD) R/W (HC) After reset 7 RFU R/W R Undefined 6 RFU R/W R Undefined 5 RFU R/W R Undefined 4 RFU R/W R Undefined 3 RFU R/W R Undefined 2 RFU R/W R Undefined 1 OCI R R/W 0 Note 1 0 Note 2 R/W R 0 Note 1 Notes 1. Only a hardware reset is possible for bit 31, bits 17 to 15, and bits 1 and 0. 2. The bit names for these bits differ for an HCD read and HCD write. The bit names in each case are as follows. Bit Name For HCD Read 16 15 0 LPSC DRWE LPS For HCD Write SGP SRWE CGP 310 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/2) Bit 31 Name CRWE Function Clean Remote Wakeup Enable 1: Clear the RWE bit of the HcControl register to 0. 0: No change Reserved. Write 0 to these bits. Since the values of these bits are undefined after a reset, initialize them by using software. Over Current Indicator Change The HC sets 1 in this bit when a change occurs in the OCI bit. This bit is cleared to 0 when 1 is written by the HCD. It does not change when 0 is written by the HCD. 30:18 RFU 17 OCIC 16 SGPNote LPSC 15 SRWENote DRWE 14:2 RFU 1 OCI 0 CGPNote LPS Note These bits can be only written by the HCD. They cannot be read/written by the HC. User's Manual U14579EJ2V0UM 311 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.3.23 HcRhPortStatus1, 2 (offset address: 0x54, 0x58) (1/4) Bit Name R/W (HCD) R/W (HC) After reset 31 RFU R R 0 30 RFU R R 0 29 RFU R R 0 28 RFU R R 0 27 RFU R R 0 26 RFU R R 0 25 RFU R R 0 24 RFU R R 0 Bit Name R/W (HCD) R/W (HC) After reset 23 RFU R R 0 22 RFU R R 0 21 RFU R R 0 20 PRSC R/W R/W 0Note 1 19 POCIC R/W R/W 0Note 1 18 PSSC R/W R/W 0Note 1 17 PESC R/W R/W 0Note 1 16 CSC R/W R/W 0Note 1 Bit Name R/W (HCD) R/W (HC) After reset 15 RFU R R 0 14 RFU R R 0 13 RFU R R 0 12 RFU R R 0 11 RFU R R 0 10 RFU R R 0 9 Note 2 R/W R/W Undefined Note 1 8 Note 2 R/W R/W 0Note 1 Bit Name R/W (HCD) R/W (HC) After reset 7 RFU R R 0 6 RFU R R 0 5 RFU R R 0 4 Note 2 R/W R/W 0 Note 1 3 Note 2 R/W R/W 0 Note 1 2 Note 2 R/W R/W 0 Note 1 1 Note 2 R/W R/W 0 Note 1 0 Note 2 R/W R/W 0Note 1 Notes 1. Only a hardware reset is possible for bits 20 to 16, bits 9 and 8, and bits 4 to 0. 2. The bit names for these bits differ for an HCD or HC read and HCD or HC write. The bit names in each case are as follows. Bit Name For Reading 9 8 4 3 2 1 0 LSDA PPS PRS POCI PSS PES CCS For Writing CPP SPP SPR CSS SPS SPE CPE 312 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (2/4) Bit 31: 21 20 Name RFU PRSC Function Reserved. Write 0 to these bits. 0 is returned after a read. Port Reset Status Change This bit is set (1) due to the completion of a reset. It is cleared (0) when 1 is written by the HCD. Port Over Current Indicator Change This bit is set (1) due to a change in the POCI bit. It is cleared (0) when 1 is written by the HCD. Port Suspend Status Change This bit is set (1) due to the completion of a resume. It is cleared (0) when either 1 is written by the HCD or the PRSC bit is set (1). Port Enable Status Change This bit is set (1) due to the occurrence of an over current, a port power off state due to a device disconnection, or the occurrence of an operational error such as the bubble detection. It is cleared (0) when 1 is written by the HCD. Connect Status Change This bit is set (1) due to a change in the CCS bit, the setting of the corresponding bit in the DR area of the HcRhDescriptorB register, or the writing of 1 to the SPR bit, SPE bit, or SPS bit when the CCS bit is 0. It is cleared (0) when 1 is written by the HCD. Reserved. Write 0 to these bits. 0 is returned after a read. 19 POCIC 18 PSSC 17 PESC 16 CSC 15:10 9 RFU CPP LSDA User's Manual U14579EJ2V0UM 313 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (3/4) Bit 8 Name SPP Function PPS 7:5 4 RFU SPR PRS 3 CSS POCI 314 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) (4/4) Bit 2 Name SPS Function PSS 1 SPE PES 0 CPE CCS User's Manual U14579EJ2V0UM 315 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4 USB Specifications This section describes communication functions and operations using the USB and the structure of the interface data that is used. For details, see Open HCI Specification Release 1.0. 14.4.1 General The Universal Serial Bus (USB) is a serial bus for exchanging data between a host computer and various types of peripheral devices. The USB host and USB devices are connected by point-to-point connections using a scheme called a tiered star topology. A device called a hub is at the center of each star. Figure 14-2 shows the USB bus topology. At most 127 devices can be connected by using this tiered star topology on a USB. In addition, a device can be removed during operation. Figure 14-2. Bus Topology Host Host Hub 1 Hub 2 Hub 3 Tier 1 Tier 2 Node Node Node Tier 3 Tier 4 Node Hub 4 Node Node Node USB signals are sent point-to-point as differential signals using two signal lines. The two signal rates are full speed (12 Mbps) and low speed (1.5 Mbps). Low speed is used by a device that can have weak EMI protection, such as a mouse, in order to lower the cost of the device. Full-speed and low-speed devices are differentiated by the position of termination resistors, which are connected at both ends of the cable as shown in Figures 14-3 and 14-4. These termination resistors are also used for disconnection detection at each port. Figure 14-3. Full-Speed Device Cable and Resistor Connections D+ Full-speed or lowspeed USB transceiver D- Host or hub port R1 R1 Twisted pair shielded cable Maximum cable length is 5 meters Z0 = 90 15% R1 = 15 k 5% R2 = 1.5 k 5% R2 D+ Full-speed USB transceiver D- Hub upstream port or full-speed function 316 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-4. Low-Speed Device Cable and Resistor Connections D+ Full-speed or lowspeed USB transceiver D- Host or hub port R1 R1 Non-twisted unshielded cable Maximum cable length is 3 meters R1 = 15 k 5% R2 = 1.5 k 5% D+ Low-speed USB transceiver R2 D- Low-speed function Data transfers are scheduled and managed by the host. Therefore, transfers are always initiated by the host. All transfers consist of at most three packets (token, data, and handshake). The token packet sends information such as the type and direction of processing, the address, and endpoint to the USB device. The USB device decodes the address field and determines whether or not it is being accessed itself. A data packet transmits data in the data transfer direction (either from the host to the device or from the device to the host) indicated by the token packet. Finally, the receiving side returns a handshake packet to the transmitting side to indicate whether the transfer was successful. The USB has the following four types of data transfers. * Interrupt transfers: Small-scale data transfers used to convey information from a USB device to client software. The HCD executes USB data transfers by issuing tokens to devices periodically, with a period that satisfies device requests. * Isochronous transfers: * Control transfers: * Bulk transfers: Periodic data transfers having a fixed data transfer rate. Asynchronous data transfers, which are used to convey configuration, command, or status information between client software and USB devices. Asynchronous data transfers, which are used to convey large quantities of information between client software and USB devices. With OpenHCI, the data transfer types are further divided into the two categories of periodic and asynchronous. Interrupt and isochronous transfers are classified as periodic transfers, which are executed at a certain fixed period. Control and bulk transfers are classified as asynchronous transfers, which are not executed periodically. To implement this kind of operation, the system must be equipped with a device called the USB host controller and software called the USB host controller driver (USBHCD). OpenHCI are specifications that define the relationship between the host controller and HCD. The USBU unit is compliant with the Open HCI Specification Release 1.0 and Open HCI Legacy Support Interface Specification Release Version 1.01. User's Manual U14579EJ2V0UM 317 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.2 Host controller communication methods The host controller (HC) and host controller driver (HCD) communicate by using the following two routes. 1. Operational registers 2. HCCA (Host Controller Communication Area) For communication that is performed by using the operational registers contained in the HC, the HC is the PCI target device. The operational registers, which are a set of control, status, list pointer, and other registers, also maintain a pointer that indicates the HCCA position within the system memory. For communication that is performed via the HCCA, the HC is the PCI device master. The HCCA is a 256-byte system memory area that maintains a header pointer for the InterruptED list, header pointer for the Done queue (transfer completed queue), and status information related to frames. By using this system memory, software can directly control HC functions without reading from the HC during normal conditions (for example, when there is no error). These two routes are used to control the HC and to exchange data transfer results on the USB. Communication between the HC and a USB device is performed based on Endpoint Descriptors (ED) and Transfer Descriptors (TD), which are enqueued by the HCD. An ED maintains information (maximum packet size, endpoint address, endpoint speed, and data flow direction) that is required by the HC to communicate with an endpoint. An ED is also used as an anchor of the TD queue. The HCD generates EDs, assigns them to endpoints, and links them to the list. A TD maintains information (data toggle information, buffer position in system memory, and completion status code) that is required for data packets that are transferred. Each TD stores information that is related to one or more data packets. The TD data buffer size is from 0 to 8192 bytes. However, only 1024 bytes can be transferred by a single data packet. TDs are processed sequentially beginning with the first one that was entered in the queue. A TD queue is linked with the ED of a given endpoint, and TDs are linked with the TD queue. The HCD creates the data of these structures and passes it to the HC for processing. Figure 14-5 shows the relationship between EDs and TDs. Figure 14-5. Relationship Between EDs and TDs Head Ptr ED ED ED ED TD TD TD TD TD TD TD 318 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Although ED lists are classified into four types (bulk, control, interrupt, and isochronous), three ED list header pointers are maintained (the isochronous type is excluded). The IsochronousED list is simply linked after the InterruptEDs. The header pointers of the BulkED and ControlED lists are maintained in the operational registers, and the header pointer of the InterruptED list is maintained in the HCCA. There are 32 interrupt header pointers, and the header pointer that is used by a given frame is determined by using the lower 5 bits of the frame counter. The InterruptED list structure is a tree structure like the one shown in Figure 14-6. The execution interval is determined by the depth of the intersections of multiple paths. That is, an InterruptED that is linked to the root of the tree structure is executed at a rate of once per 1 ms. Figure 14-6. InterruptED List Interrupt header pointer 0 16 8 24 4 20 12 28 2 18 10 26 6 22 14 30 1 17 9 25 5 21 13 29 3 19 11 27 7 23 15 31 32 16 8 4 : Interrupt endpoint descriptor place holder 2 1 Endpoint polling interval (ms) User's Manual U14579EJ2V0UM 319 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-7 shows how OpenHCI allocates bandwidth. The HC selects the list to process based on a priority order algorithm. Control/bulk list processing has priority until the value of the FR area of the HcFmRemaining register from the beginning of the frame is the same as the value of the PS area of the HcPeriodicStart register. When the value of the FR area is the same as the value of the PS area, periodic list processing has priority. The periodic list processing priority will be greater than or equal to the control/bulk list processing priority until the periodic list processing is completed or the frame time has elapsed. After the periodic list processing is completed, the control/bulk list processing is restarted. Figure 14-7. Bandwidth Allocation Method 1.0 ms SOF NP Periodic NP Time Remark SOF: Start of Frame, NP: Non-Periodic Transfer During interrupt/isochronous list processing, processing is performed from the InterruptED header pointer that is processed by the current frame. Since the isochronous list is linked after the interrupt list, the interrupt list always has a higher priority than the isochronous list. During bulk/control list processing, processing is restarted from the location where it was previously interrupted in each list. When the end of the list is reached, a value is loaded from the header pointer and processing is resumed. The control end pointer is compared with the bulk end pointer and an equivalent or higher access right to the bus is assigned. The ratio of the access rights is set in the CBSR area of the HcControl register. Figure 14-8 shows an example of a 4:1 control bulk service ratio. While control and bulk transfers have priority, the HC switches the ED processing of each list according to the value in the CBSR area. Figure 14-8. 4:1 Control Bulk Service Ratio Control ED Control ED Control ED Control ED Bulk ED The control bulk service ratio is maintained across multiple frames. When the processing of one data packet of a TD included in a given ED is serviced, the HC processes the next ED. 320 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.3 ED (Endpoint Descriptor) An ED is always located in system memory in units of 16 bytes. When the HC checks an ED list and finds a linked TD, it executes the transfers indicated there. When the HCD must change the value of the HeadP area of an ED, the HCD sets (1) the K bit of the ED to disable all ED list processing having the same transfer type as the ED to be deleted so that the HC will not access the ED. 14.4.4 ED format Figure 14-9 shows the ED format. For details about each field, see Table 14-3. Figure 14-9. ED Format 31 Dword0 Dword1 Dword2 Dword3 RFU 27 26 MPS 16 15 14 13 12 11 10 FKS TailP HeadP NextED D EN 76 43 2 1 FA RFU 0 0 CH RFU User's Manual U14579EJ2V0UM 321 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.5 ED fields Table 14-3 shows details about the ED fields. Table 14-3. ED Fields (1/2) Field Name FA R/W R Function Function Address USB address of the function that includes the endpoint controlled by this ED Endpoint Number Endpoint address within the function Direction Indicates the data flow direction (in or out). If values other than 10 or 01 are set, the transfer direction is defined by the DP area of the TD. 11: Defined by the DP area of the TD 10: In 01: Out 00: Defined by the DP area of the TD Speed Indicates the endpoint speed. 1: Low speed 0: Full speed Skip When this bit is set, the HC skips to the next ED without accessing the TD queue and without issuing a USB token to the endpoint. Format Indicates the format of the TDs linked to this ED. 1: IsochronousTD format (for an isochronous endpoint) 0: GeneralTD format (for a control, bulk, or interrupt endpoint) Maximum Packet Size Indicates the maximum number of bytes (maximum: 1024 bytes) that can be transmitted to or received from the endpoint in one data packet. The data packet size that is sent to the endpoint by a write (OUT and SETUP) from the HC to the endpoint always is the smaller of the value of this area and the size of the data in the buffer. The data packet size sent by a read (IN) from the endpoint to the HC is determined by the endpoint. TD Queue Tail Pointer When the values of this area and the HeadP area are the same, it indicates that the list contains no TDs that can be processed by the HC. When the values of this area and the HeadP area differ, the list contains TDs. Halted This bit usually indicates that the endpoint TD queue processing was halted due to a TD processing error. This bit is set (1) by the HC. EN R D R S R K R F R MPS R TailP R H R/W 322 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Table 14-3. ED Fields (2/2) Field Name C R/W R/W Function Toggle Carry This bit is a data toggle carry bit. When a TD is retired, this bit is always written using the final data toggle value (LSB of the T area) that was used by the retired TD. This field is not used by an isochronous endpoint. TD Queue Head Pointer Indicates the TD that is to be processed next by this endpointer. NextED Indicates the next ED (excluding 0x000 0000). Reserved for Future Use Reserved. Write 0 to these bits. 0 is returned after a read. HeadP R/W NextED R RFU R 14.4.6 TD (Transfer Descriptor) TDs (Transfer Descriptors) are used by the HC to indicate a buffer for the data that is transmitted to or received from an endpoint. The two types of TDs are General and Isochronous. A GeneralTD is used by an interrupt, control, or bulk endpointer. An IsochronousTD is used by an isochronous transfer. Both a GeneralTD and an IsochronousTD can indicate a buffer from 0 to 8192 bytes. In addition, the data buffer described by a single TD can be divided into two pages. This eliminates problems such as forcibly placing buffers so they are physically contiguous and moving excess data. When the HCD adds a TD, it links the new TD to the TD indicated by the TailP area and updates the TailP area so that it points to the added TD. Therefore, the added TD must be added at the end of the TD queue. The HC processes TDs asynchronously relative to processing by the host CPU. Therefore, when the TD queue must be switched to another queue, the HC's endpoint TD queue processing must be halted so the queue can be changed. The HCD halts TD processing by setting (1) the K bit of the ED to be deleted. 14.4.7 GeneralTD format A GeneralTD is a TD for control, bulk, or interrupt transfers. It is always located in system memory in units of 16 bytes. Figure 14-10 shows the GeneralTD format. For details about each field, see Table 14-4. Figure 14-10. GeneralTD Format 31 Dword0 Dword1 Dword2 Dword3 CC 28 27 26 25 24 23 EC T DI 21 20 19 18 17 DP R RFU 43 0 CBP Next TD BE 0 User's Manual U14579EJ2V0UM 323 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.8 GeneralTD fields Table 14-4 shows details about the GeneralTD fields. Table 14-4. GeneralTD Fields (1/2) Field Name R R/W R Function Buffer Rounding 1: The final data packet will not fill the defined buffer even if no error occurs. 0: The defined data buffer must be completely filled by the final data packet from the endpoint indicated by the TD. Direction/PID (Process ID) Indicates the data flow direction and PID used by the token. If the D area of the ED was set to 00 or 11, this area is meaningful for the HC. 11: Reserved 10: In (from endpoint) 01: Out (to endpoint) 00: Setup (to endpoint) Delay Interrupt Indicates the time until an interrupt request is generated for reporting that TD processing is completed. When TD processing is completed, the HC delays the generation of the interrupt request until the frame indicated by this area. When the value of this area is 111, no interrupt request related to the completion of this TD processing will be generated. Data Toggle This area is used for comparing/generating the data PID value (DATA0 or DATA1). It is updated each time a data packet is successfully transmitted or received. When the MSB of this area is 0, the data toggle is obtained from the C bit of the ED and the LSB of this area is ignored. When the MSB of this area is 1, the LSB of this area indicates the data toggle. Error Count This area is incremented by each transmission error. When the value of this area is 2 and an error occurred, the error type is recorded in the CC area and the data is moved to the Done queue (transfer completed queue). When processing is completed without an error, this area is reset to 0. Condition Code This area is updated after processing is executed, regardless of whether or not processing is successful. When processing is successful, this area is set to NoError (0000). Otherwise, it is set according to the error type. 1111: NotAccessed 1110: NotAccessed 1101: BufferUnderrun 1100: BufferOverrun 1011: Reserved 1010: Reserved 1001: DataUnderrun 1000: DataOverrun 0111: UnexpectedPID 0110: PIDCheckFailure 0101: DeviceNotResponding 0100: STALL PID 0011: DataToggleMismatch 0010: BitStuffing Violation 0001: CRC Error 0000: NoError DP R DI R T R/W EC R/W CC R/W 324 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Table 14-4. GeneralTD Fields (2/2) Field Name CBP R/W R/W Function Current Buffer Pointer Indicates the next physical address in memory to be accessed by a transmission/reception for the endpoint. When this area is 0, it indicates either a data packet of length zero or that all bytes were transferred. Next TD This area points to the next TD of the TD list that is linked with this endpointer. Buffer End Indicates the physical address of the final byte within this TD buffer. Reserved for Future Use Reserved. Write 0 to these bits. 0 is returned after a read. NextTD R/W BE R RFU R The CBP area of a GeneralTD indicates the address of the data packet that is used in a data packet transfer for the endpoint addressed by the ED. If the transfer is completed without any error occurring, the HC advances the value of the CBP area by the number of bytes that were transferred. If the buffer address indicated by the CBP area exceeds the 4 KB boundary during a data packet transfer, the higher 20 bits of the BE area are copied to the working value (software-determined location for temporarily saving the pointer value) of the CBP area, and the next buffer address will be byte 0 of the same 4 KB page space as the one where the last byte is maintained. Figure 14-11. Current Buffer Pointer, Buffer End, and 4 KB Boundary Current buffer pointer 4 KB boundary 1 data packet 4 KB boundary 4 KB Buffer end 4 KB boundary User's Manual U14579EJ2V0UM 325 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.9 IsochronousTD format An IsochronousTD is used only for isochronous endpoint. When the F bit of an ED is 1, all TDs that are linked to the ED always use this format, and the TDs are always located in system memory in units of 32 bytes. Figure 14-12. IsochronousTD Format 31 Dword0 Dword1 Dword2 Dword3 Dword4 Dword5 Dword6 Dword6 CC 28 27 26 RFU 24 23 DI BP0 21 20 RFU 16 15 12 11 SF 54 0 FC RFU NextTD BE 0 Offset1/PSW1 Offset3/PSW3 Offset5/PSW5 Offset7/PSW7 Offset0/PSW0 Offset2/PSW2 Offset4/PSW4 Offset6/PSW6 326 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.10 IsochronousTD fields Table 14-5 shows details about the IsochronousTD fields. Table 14-5. IsochronousTD Fields Field Name SF R/W R Function Starting Frame Lower 16 bits of the frame number that is sent by the first data packet of the IsochronousTD Delay Interrupt Time until an interrupt request is issued after this IsochronousTD processing is completed Frame Count Number of data packets indicated by this IsochronousTD. When this area is 0, it indicates that one data packet is included. When it is 7, it indicates that eight data packets are included. Condition Code When an IsochronousTD is moved to the Done queue (transfer completed queue), this area contains the completion code. Buffer Page 0 This area displays the physical page number of the first byte of the data buffer used by this IsochronousTD. Next TD This area indicates the next IsochronousTD in the IsochronousTD queue that is liked with the ED. Buffer End This area contains the physical address of the last byte of the buffer. Offset N (N = 0 to 7) This area is used for determining the size and starting address of the isochronous data packet. Packet Status Word N (N = 0 to 7) This area contains the completion code and the data size that was received by the isochronous data packet. Reserved for Future Use Reserved. Write 0 to these bits. 0 is returned after a read. DI R FC R CC R/W BP0 R NextTD R/W BE R OffsetN R PSWN W RFU R An IsochronousTD has (FC area value + 1) frame buffers, within the range from 1 to 8. The first data packet is sent by the frame for which the lower 16 bits of the HcFmNumber register matches the SF area of the IsochronousTD. If the buffer address exceeds the 4 KB boundary during a data packet transfer, the higher 20 bits of the BE area are used as the physical address of the next buffer. Therefore, the next buffer address will be byte 0 of the same 4 KB page space as the one where the last byte is maintained. 14.4.11 HCCA (Host Controller Communication Area) The HCCA (Host Controller Communication Area) is a 256-byte area of system memory, which is used by system software for transmitting specific control/status information to or receiving this information from the HC. The system software always writes this area address in the HcHCCA register of the HC. User's Manual U14579EJ2V0UM 327 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.12 HCCA format Table 14-6 shows the HCCA format. Table 14-6. HCCA Format Offset Address 0 0x80 Size (Bytes) 128 2 Field Name R/W Function HccaInterruptTable HccaFrameNumber R W Pointer to an InterruptED Displays the current frame number. This value is updated by the HC before periodic list processing begins in the frame. When the HC updates the HccaFrameNumber area, the HC sets this area to 0. When the HC reaches the end of frame and the decrement value of the value indicated by the DI area of the TD is 0, the HC writes the current value of HcDoneHead to this area. If interrupts are enabled, an interrupt request is generated. This area will not be written to again by the HC until the WDH bit of the HcInterruptStatus register is cleared by software. When this area is zero, an interrupt request is caused by a reason other than an update of this area, and the HcInterruptStatus register must be accessed to determine the source of the interrupt request. When this area is not zero, the interrupt request is a Done queue update interrupt request. When LSB of this area is not zero, an addition separate interrupt source has occurred. Therefore, check the HcInterruptStatus register to determine that source. Reserved for use by the HC. 0x82 2 HccaPad1 W 0x84 4 HccaDoneHead W 0x88 116 reserved R/W 14.4.13 HCCA overview The HccaInterruptTable area, which consists of 32 Dword entry tables, points to pointers to each interrupt list of the ED list. The execution rate is higher for EDs having more linked lists. An ED that exists in only 1 list is executed every 32 ms, and an ED that exists in 2 lists is executed once every 6 ms. When an ED is linked to all 32 lists, it is executed once for each frame. The last entry of each of the 32 interrupt lists must point to an isochronous list. After the SOF is sent, the HccaFrameNumber area is rewritten with the value of the FN area of the HcFmNumber register before the HC reads the ED to be processed in the new frame. 328 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.14 HC state transitions The HC has four states. These states are UsbOperational, UsbReset, UsbSuspend, and UsbResume. The current state is indicated in the HCFS area of the HcControl register. The HCD can execute the transitions between the USB states shown in Figure 14-13. The HC can only execute the state transition from UsbSuspend to UsbResume during a remote wakeup event. Figure 14-13. HC State Transitions UsbReset Write Usb Operational Hardware Reset UsbOperational Write UsbSuspend Write UsbOperational Write Usb Resume UsbReset Write Usb Reset UsbResume Write or Remote Wakeup Usb Suspend UsbReset Write In the UsbOperational state, the HC processes a list and issues an SOF token. At the same time that the HC transitions to the UsbOperational state, the value of the FI area of the HcFmInterval register is loaded in the FR area of the HcFmRemaining register. The first SOF token that is sent after the HC enters the UsbOperational state is sent at the frame boundary for which the FR area changed from 0 to the value of the FI area. In the UsbReset state, the HC forcibly sends a reset signal to the bus. After a hardware reset, the HC is always in the UsbReset state. The UsbSuspend state indicates a state in which the USB is temporarily stopped. At this time, the HC monitors USB wakeup actions. The HC is forced to transition to the UsbResume state by a remote wakeup condition. This transition may conflict with a transition to the UsbReset state performed by the HCD. If this conflict occurs, the transition to the UsbReset state that was performed by the HCD has priority. The HC cannot transition to the UsbResume state for 5 ms after a transition to the UsbSuspend State. In the UsbResume state, the HC forcibly sends a resume signal to the bus. During the UsbResume state, the root hub always transmits USB resume signals to the downstream ports. A transition to the UsbResume state is started by a remote wakeup signal from the HCD or root hub. User's Manual U14579EJ2V0UM 329 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) 14.4.15 List service flow Figure 14-14 shows the list service flow. Figure 14-14. List Service Flow Start Is list enabled? yes no End Synchronous list? yes no no Hc_Current ED = 0 ? yes Read head pointer no HeadP = 0 ? yes Isochronous ED ? yes Is isochronous list enabled? yes no BLF, CLF = 1 ? yes no no End Set Hc_Current ED and Hc_Head ED no BLF, CLF 0 Hc_Current ED = 0 ? yes End ED service (see Figure 14-15) no Bulk list? yes Control list? yes no no Next ED =0? yes Isochronous ED ? yes no no Is isochronous list enabled? yes End Does control/bulk ratio match? yes no End 330 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) The list service flow is executed after the HC determines the kind of list that must be serviced. A list is periodically disabled by the HCD to switch the ED. Therefore, when processing lists, the HC first checks whether or not the target list is enabled according to the BLE, CLE, and PLE bits of the HcControl register. If the list is enabled, the HC services the list. If it is disabled, the HC skips that list and proceeds to the next list. When a list is enabled, the HC confirms the position of the first ED for which service is requested. If the head pointer is 0 during periodic list processing, no ED exists in the list, and the HC proceeds to the next list. However during asynchronous list processing, if the CurrentED of a list is 0, the HC checks the BLF and CLF bits of the HcCommandStatus register. If these bits had been set to 1, at least one ED for which service is required exists in the target list. Therefore, the HC copies the HeadED to the CurrentED, clears the BLF and CLF bits to 0, and processes the ED that is indicated by the CurrentED. If the BLF and CLF bits are 0 when the HC checks them, the HC proceeds to the next list. After ED service, for a periodic list, the HC checks the NextED area of the ED for which the service was just completed and continues processing the next ED. If the NextED area is 0x000 0000 at this time, the HC proceeds to an asynchronous list. For a bulk list, the HC only advances to the next list. For a control list, the next action differs according to whether or not the number of ControlEDs indicated by the control/bulk service ratio have been serviced. Figure 14-15 shows the ED service flow. Figure 14-15. ED Service Flow Start H = 1 or K=1? yes no HeadP = TailP ? yes no Periodic list? yes no CLF 0 TD service (see Figure 14-16) End First, the HC reads the ED to be processed from system memory via the PCI bus. Next, the HC determines whether or not this ED should be processed. If either the K bit or the H bit of the ED is 1, the ED is skipped and the HC proceeds to the next list. When the HC determines that the ED should be processed, it determines whether or not any TDs that can be processed are in the queue. The HC compares the TailP area and HeadP area of the ED. When the values of these areas are equal, no enabled TD exists in the list, and the HC proceeds to the next ED or the next list. If the two values differ, the HC services that TD. User's Manual U14579EJ2V0UM 331 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-16 shows the TD service flow. When processing an IsochronousTD, the HC first calculates the relative frame number to decide whether to send a packet in the current frame. This relative frame number is used to select Offset(R) and Offset(R+1) (R = 0, 2, 4, 6). When the relative frame number is equal to the value of the FC area of the TD, Offset(R+1) becomes (BE area value + 1). The data buffer size for each transfer is calculated by subtracting Offset(R) from Offset(R+1), and its address is determined from Offset(R). When bit 12 of Offset(R) is 0, buffer page 0 of the IsochronousTD is used as the higher 20 bits of the address. When bit 12 of Offset(R) is 1, the higher 20 bits of the BR area are used as the higher 20 bits of the address. 332 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-16. TD Service Flow Start Isochronous TD? yes Compare Number with Frame in ED no Frame Number > BE area value? yes no FrameNumber < 0? yes Retire TD no Calculate Packet Addr and Size PID = OUT? yes Read Packet from memory no Perform SOF check Perform SOF check Time available? yes Execute USB Transaction no no Time available? yes Execute USB Transaction Write Packet to memory Status Writeback no To Complete? yes Retire TD End User's Manual U14579EJ2V0UM 333 CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) When processing a GeneralTD, the HC obtains the next memory address from the CBP area. For a transmission to or reception from the CurrentBufferPointer address of the data, the data many not fit in a single physical page and may span multiple pages. In this case, the higher 20 bits of the BE area are used as the higher 20 bits of the address instead of the higher 20 bits of the CBP area. The maximum amount of data to be transmitted to or received from a device is the smaller of the value of the MPS area of the ED and the remaining buffer size. After the HC decides the packet size, it always checks whether or not packets can be transferred until the end of frame. If the bit time request of the packets that are transferred is greater than the remaining bit time of the frame, processing is not performed. After GeneralTD processing, the HC updates the CC, T, EC, and CBP areas of the GeneralTD. Also, after IsochronousTD processing, the HC updates Offset(R) to the value of the PSWN area (R = N = 0 to 7). When a TD succeeded (all data was transmitted or received) or an error occurred, the HC moves the TD to the Done queue, updates the transfer completed queue interrupt counter (internal Done Queue Interrupt Counter), and updates the ED to change the HeadP, C, and H areas. To enqueue a TD in the Done queue, first the HC copies the value of the NextTD area of the current TD to the HeadP area of the ED. Next, it writes the value of the HcDoneHead register to the NextTD area of the TD that was enqueued. Finally, it writes the address of the TD that was enqueued in the HcDoneHead register. At this time, the HC uses the value of the C area of the ED and the value of the final T area of the TD for updating. When the TD is retired because of an error, the HC also updates the H area of the ED. After performing these various kinds of processing, the HC writes the value of the HcDoneHead register to the HCCA and updates the transfer completed queue interrupt counter by using the DI area (base for number of SOFs issued), which defines the time until the interrupt request is generated. This counter is not updated if the value of the DI area of the TD is greater than the counter value. The transfer completed queue interrupt counter is decremented by each SOF, and when it becomes 0, the HC immediately writes the current value of the HcDoneHead register to the HccaDoneHead area at the next frame boundary. After writing the value of the HcDoneHead register to the HCCA, the HC generates an interrupt request by resetting the HcDoneHead register to 0 and setting the WDH bit of the HcInterruptStatus register to 1. In this way, the transfer completed queue is transferred from the HC to the HCD via the HCCA. The HCD processes the Done queue and provides completion information to the software that requested the transfer. While the WDH bit of the HcInterruptStatus register is set, the HC does not write to the HCCA of the HcDoneHead register. In preparation for receiving another transfer completed queue from the HC, the WDH bit of the HcInterruptStatus register is cleared (0) by the HCD. Figure 14-17 shows the transfer completed queue operation. 334 User's Manual U14579EJ2V0UM CHAPTER 14 USBU (UNIVERSAL SERIAL BUS UNIT) Figure 14-17. Transfer Completed Queue Operation 1 ED HeadP 3 2 HcDoneHead HeadP TD NextTD TD NextTD TD NextTD TD NextTD Remark 1 to 3: Operation sequence : Writing of data User's Manual U14579EJ2V0UM 335 CHAPTER 15 AC97U (AC97 UNIT) 15.1 General The AC97U is a digital controller that is compliant with the Audio Codec '97 Revision 2.1. It is used for connecting with an external Codec through an AC-Link. 15.2 Configuration Register Set Table 15-1 lists the AC97U PCI configuration registers. Table 15-1. AC97U PCI Configuration Registers Offset Address 0x00 to 0x01 0x02 to 0x03 0x04 to 0x05 0x06 to 0x07 0x08 0x09 to 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 to 0x13 0x14 to 0x2B 0x2C to 0x2D 0x2E to 0x2F 0x30 to 0x33 0x34 to 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 to 0xFF R/W R R R/W R/W R R R R/W R R R/W - R R R - R/W R R R - Register Symbol VID DID PCICMD PCISTS RID CLASSC CACHELS MLT HEDT BIST BASEADR - SVID SUBID EXROMADR - INTL INTP MIN_GNT MAX_LAT - Vendor ID register Device ID register PCI command register PCI device status register Revision ID register Class code register Cache line size register Master latency timer register Header type register Built-in self-test register Base address register Reserved Subsystem vendor ID register Subsystem ID register Extended ROM base address register Reserved Interrupt line register Interrupt pin register Burst cycle minimum request time register Bus usage right request frequency register Reserved Function These registers are described in detail below. 336 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.2.1 VID (offset address: 0x00 to 0x01) Bit Name R/W After reset 15 VID15 R 0 14 VID14 R 0 13 VID13 R 0 12 VID12 R 1 11 VID11 R 0 10 VID10 R 0 9 VID9 R 0 8 VID8 R 0 Bit Name R/W After reset 7 VID7 R 0 6 VID6 R 0 5 VID5 R 1 4 VID4 R 1 3 VID3 R 0 2 VID2 R 0 1 VID1 R 1 0 VID0 R 1 Bit 15:0 Name VID(15:0) Vendor ID 0x1033: NEC Function 15.2.2 DID (offset address: 0x02 to 0x03) Bit Name R/W After reset 15 DID15 R 0 14 DID14 R 0 13 DID13 R 0 12 DID12 R 0 11 DID11 R 0 10 DID10 R 0 9 DID9 R 0 8 DID8 R 0 Bit Name R/W After reset 7 DID7 R 1 6 DID6 R 0 5 DID5 R 1 4 DID4 R 0 3 DID3 R 0 2 DID2 R 1 1 DID1 R 1 0 DID0 R 0 Bit 15:0 Name DID(15:0) Device ID 0x00A6: AC97U Function User's Manual U14579EJ2V0UM 337 CHAPTER 15 AC97U (AC97 UNIT) 15.2.3 PCICMD (offset address: 0x04 to 0x05) Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 FBTB_EN R 0 8 SERREN R/W 0 Bit Name 7 AD_STEP 6 PERREN 5 VGA_P_ SNOOP R 0 4 MEMW_ INV_EN R 0 3 SP_CYC 2 MASTER_ EN R/W 0 1 MEM_EN 0 IO_EN R/W After reset R 0 R/W 0 R 0 R 0 R/W 0 Bit 15:10 9 Name RFU FBTB_EN Function Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables fast Back to Back. This function is not supported by the AC97U. Enables/disables SERR# signal output. 1: Enable The SERR# signal is set to active if an address parity error is detected and the PERREN bit is 1. 0: Disable Enables/disables address/data stepping. This function is not supported by the AC97U. Enables/disables parity error. 1: Enable output of the PERR# signal The PERR# signal is set to active if a data parity error is detected. The SERR# signal is set to active if an address parity error is detected and the SERREN bit is 1. 0: Disable output of the PERR# signal VGA palette snoop. This function is not supported by the AC97U. Enables/disables memory write and invalidate. This function is not supported by the AC97U. Special cycle. This function is not supported by the AC97U. Controls bus master operation. 1: Operate as bus master on the PCI bus. 0: Do not operate as bus master on the PCI bus. Controls memory space. This function is not supported by the AC97U. Controls the response to an I/O space access. 1: Respond to an I/O access to the AC97. 0: Do not respond to an I/O access to the AC97. 8 SERREN 7 AD_STEP 6 PERREN 5 VGA_P_SNOOP 4 MEMW_INV_EN 3 SP_CYC 2 MASTER_EN 1 MEM_EN 0 IO_EN 338 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.2.4 PCISTS (offset address: 0x06 to 0x07) Bit Name 15 DETECT_ PERR R/W 0 14 SIG_SERR 13 RV_ MABORT R/W 0 12 RV_ TABORT R/W 0 11 SIG_TABOT 10 DEVSEL1 9 DEVSEL0 8 DETECT_ D_PERR R/W 0 R/W After reset R/W 0 R/W 0 R 0 R 1 Bit Name R/W After reset 7 FBTB_CAP R 0 6 UDF_SPT R 0 5 66M_CAP R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 15 Name DETECT_PERR Function Data and address parity error detection. Cleared to 0 when 1 is written. 1: Detected 0: Normal SERR# signal status. Cleared to 0 when 1 is written. 1: Active 0: Inactive Master abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reception. Cleared to 0 when 1 is written. 1: Received 0: Not received Target abort reporting. Cleared to 0 when 1 is written. 1: Reported 0: Not reported DEVSEL# timing 01: Medium speed Set to 1 when the following three conditions are satisfied. Cleared to 0 when 1 is written. * The AC97U is the master of the bus cycle in which the data parity error occurred. * Either the AC97U set the PERR# signal to active or the AC97U detected that the PERR# signal became active due to the target. * The PERREN bit of the PCICMD register has been set to 1. Response to fast Back to Back. This is fixed at 0 (disabled). Indicates that the AC97U does not support the UDF. Indicates 33 MHz operation. Reserved. Write 0 to these bits. 0 is returned after a read. 14 SIG_SERR 13 RV_MABORT 12 RV_TABORT 11 SIG_TABOT 10:9 DEVSEL(1:0) 8 DETECT_D_PERR 7 FBTB_CAP 6 5 4:0 UDF_SPT 66M_CAP RFU User's Manual U14579EJ2V0UM 339 CHAPTER 15 AC97U (AC97 UNIT) 15.2.5 RID (offset address: 0x08) Bit Name R/W After reset 7 RID7 R 0 6 RID6 R 0 5 RID5 R 0 4 RID4 R 0 3 RID3 R 0 2 RID2 R 0 1 RID1 R 0 0 RID0 R 1 Bit 7:0 Name RID(7:0) Revision ID Function 15.2.6 CLASSC (offset address: 0x09 to 0x0B) Bit Name R/W After reset 23 CLASSC23 R 0 22 CLASSC22 R 0 21 CLASSC21 R 0 20 CLASSC20 R 0 19 CLASSC19 R 0 18 CLASSC18 R 1 17 CLASSC17 R 0 16 CLASSC16 R 0 Bit Name R/W After reset 15 CLASSC15 R 0 14 CLASSC14 R 0 13 CLASSC13 R 0 12 CLASSC12 R 0 11 CLASSC11 R 0 10 CLASSC10 R 0 9 CLASSC9 R 0 8 CLASSC8 R 1 Bit Name R/W After reset 7 CLASSC7 R 0 6 CLASSC6 R 0 5 CLASSC5 R 0 4 CLASSC4 R 0 3 CLASSC3 R 0 2 CLASSC2 R 0 1 CLASSC1 R 0 0 CLASSC0 R 0 Bit 23:0 Name CLASSC(23:0) Class code 0x040100: Multimedia device Function 15.2.7 CACHELS (offset address: 0x0C) Bit Name R/W After reset 7 CACHELS7 R 0 6 CACHELS6 R 0 5 CACHELS5 R 0 4 CACHELS4 R 0 3 CACHELS3 R 0 2 CACHELS2 R 0 1 CACHELS1 R 0 0 CACHELS0 R 0 Bit 7:0 Name CACHELS(7:0) Function Sets the cache line size. This function is not supported by the AC97U. 340 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.2.8 MLT (offset address: 0x0D) Bit Name R/W After reset 7 MLT7 R/W 0 6 MLT6 R/W 0 5 MLT5 R/W 0 4 MLT4 R/W 0 3 MLT3 R 0 2 MLT2 R 0 1 MLT1 R 0 0 MLT0 R 0 Bit 7:4 Name MLT(7:4) Sets the latency timer. 1111: 30 PCLK (900 ns) : 0010: 17 PCLK (510 ns) 0001: 16 PCLK (480 ns) 0000: 0 PCLK (0 ns) Function 3:0 MLT(3:0) Write 0 to these bits. 0 is returned after a read. Remark Values enclosed in parentheses are for PCICLK = 33 MHz. 15.2.9 HEDT (offset address: 0x0E) Bit Name R/W After reset 7 HEDT7 R 1 6 HEDT6 R 0 5 HEDT5 R 0 4 HEDT4 R 0 3 HEDT3 R 0 2 HEDT2 R 0 1 HEDT1 R 0 0 HEDT0 R 0 Bit 7:0 Name HEDT(7:0) Function Header type 0x80: This is a multifunction device and is not a PCI-to-PCI bridge. 15.2.10 BIST (offset address: 0x0F) Bit Name R/W After reset 7 BIST7 R 0 6 BIST6 R 0 5 BIST5 R 0 4 BIST4 R 0 3 BIST3 R 0 2 BIST2 R 0 1 BIST1 R 0 0 BIST0 R 0 Bit 7:0 Name BIST(7:0) Function Built-in self-test. This function is not supported by the AC97U. User's Manual U14579EJ2V0UM 341 CHAPTER 15 AC97U (AC97 UNIT) 15.2.11 BASEADR (offset address: 0x10 to 0x13) Bit Name 31 BASEADR 31 R/W 0 30 BASEADR 30 R/W 0 29 BASEADR 29 R/W 0 28 BASEADR 28 R/W 0 27 BASEADR 27 R/W 0 26 BASEADR 26 R/W 0 25 BASEADR 25 R/W 0 24 BASEADR 24 R/W 0 R/W After reset Bit Name 23 BASEADR 23 R/W 0 22 BASEADR 22 R/W 0 21 BASEADR 21 R/W 0 20 BASEADR 20 R/W 0 19 BASEADR 19 R/W 0 18 BASEADR 18 R/W 0 17 BASEADR 17 R/W 0 16 BASEADR 16 R/W 0 R/W After reset Bit Name 15 BASEADR 15 R/W 0 14 BASEADR 14 R/W 0 13 BASEADR 13 R/W 0 12 BASEADR 12 R/W 0 11 BASEADR 11 R 0 10 BASEADR 10 R 0 9 BASEADR9 8 BASEADR8 R/W After reset R 0 R 0 Bit Name R/W After reset 7 BASEADR7 R 0 6 BASEADR6 R 0 5 BASEADR5 R 0 4 BASEADR4 R 0 3 BASEADR3 R 0 2 BASEADR2 R 0 1 RFU R 0 0 I/OSpace R 1 Bit 31:12 11:2 1 0 Name BASEADR(31:12) BASEADR(11:2) RFU I/OSpace Function Sets the higher 20 bits of the operational register base address. Write 0 to these bits. 0 is returned after a read. Reserved. Write 0 to this bit. 0 is returned after a read. Indicates that the operational registers are mapped to the I/O space. 342 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.2.12 SVID (offset address: 0x2C to 0x2D) Bit Name R/W After reset 15 SVID15 R 0 14 SVID14 R 0 13 SVID13 R 0 12 SVID12 R 0 11 SVID11 R 0 10 SVID10 R 0 9 SVID9 R 0 8 SVID8 R 0 Bit Name R/W After reset 7 SVID7 R 0 6 SVID6 R 0 5 SVID5 R 0 4 SVID4 R 0 3 SVID3 R 0 2 SVID2 R 0 1 SVID1 R 0 0 SVID0 R 0 Bit 15:0 Name SVID(15:0) Function Subsystem vendor ID This is a vendor identification number to be used for recognizing the system or option card. The operating system writes and uses this ID. 15.2.13 SUBID (offset address: 0x2E to 0x2F) Bit Name R/W After reset 15 SUBID15 R 0 14 SUBID14 R 0 13 SUBID13 R 0 12 SUBID12 R 0 11 SUBID11 R 0 10 SUBID10 R 0 9 SUBID9 R 0 8 SUBID8 R 0 Bit Name R/W After reset 7 SUBID7 R 0 6 SUBID6 R 0 5 SUBID5 R 0 4 SUBID4 R 0 3 SUBID3 R 0 2 SUBID2 R 0 1 SUBID1 R 0 0 SUBID0 R 0 Bit 15:0 Name SUBID(15:0) Function Subsystem ID This is a controller identification number to be used for recognizing the system or option card. The operating system writes and uses this ID. User's Manual U14579EJ2V0UM 343 CHAPTER 15 AC97U (AC97 UNIT) 15.2.14 EXROMADR (offset address: 0x30 to 0x33) Bit Name 31 30 29 28 27 26 25 24 EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR 31 30 29 28 27 26 25 24 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W After reset Bit Name 23 22 21 20 19 18 17 16 EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR 23 22 21 20 19 18 17 16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W After reset Bit Name 15 14 13 12 11 10 9 8 EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR 15 14 13 12 11 10 9 8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W After reset Bit Name 7 6 5 4 3 2 1 0 EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR EXROMADR 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R/W After reset Bit 31:0 Name EXROMADR(31:0) Extended ROM base address Fixed at 0x0000 0000. Function 15.2.15 INTL (offset address: 0x3C) Bit Name R/W After reset 7 INTL7 R/W 0 6 INTL6 R/W 0 5 INTL5 R/W 0 4 INTL4 R/W 0 3 INTL3 R/W 0 2 INTL2 R/W 0 1 INTL1 R/W 0 0 INTL0 R/W 0 Bit 7:0 Name INTL(7:0) Function Sets the interrupt request line. Since this function is not supported by the AC97U, settings for these bits are invalid. 344 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.2.16 INTP (offset address: 0x3D) Bit Name R/W After reset 7 INTP7 R 0 6 INTP6 R 0 5 INTP5 R 0 4 INTP4 R 0 3 INTP3 R 0 2 INTP2 R 0 1 INTP1 R 0 0 INTP0 R 1 Bit 7:0 Name INTP(7:0) Function PCI interrupt pin 0x01: Serial (equipped with INTA# signal) 15.2.17 MIN_GNT (offset address: 0x3E) Bit Name R/W After reset 7 MIN_GNT7 R 0 6 MIN_GNT6 R 0 5 MIN_GNT5 R 0 4 MIN_GNT4 R 0 3 MIN_GNT3 R 0 2 MIN_GNT2 R 0 1 MIN_GNT1 R 0 0 MIN_GNT0 R 1 Bit 7:0 Name MIN_GNT(7:0) Burst cycle minimum request time. These bits are fixed at 0x01. Function 15.2.18 MAX_LAT (offset address: 0x3F) Bit Name R/W After reset 7 MAX_LAT7 R 0 6 MAX_LAT6 R 1 5 MAX_LAT5 R 1 4 MAX_LAT4 R 1 3 MAX_LAT3 R 0 2 MAX_LAT2 R 0 1 MAX_LAT1 R 0 0 MAX_LAT0 R 0 Bit 7:0 Name MAX_LAT(7:0) Function Maximum delay time until a response is returned when the PCI bus usage right is requested. These bits are fixed at 0x70. User's Manual U14579EJ2V0UM 345 CHAPTER 15 AC97U (AC97 UNIT) 15.3 Operational Register Set Table 15-2 lists the AC97U operational registers. The AC97U operational registers are mapped to the I/O space. Table 15-2. AC97U Operational Registers Offset Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 to 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 R/W R/W R/W R R R/W R R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Register Symbol INT_CLR/INT_STATUS CODEC_WR CODEC_RD CODEC_REQ SLOT12_WR SLOT12_RD CTRL ACLINK_CTRL SRC_RAM_DATA INT_MASK - DAC1_CTRL DAC1L DAC1_BADDR DAC2_CTRL DAC2L DAC2_BADDR DAC3_CTRL DAC3L DAC3_BADDR ADC1_CTRL ADC1L ADC1_BADDR ADC2_CTRL ADC2L ADC2_BADDR ADC3_CTRL ADC3L ADC3_BADDR Function Interrupt clear/status register Codec write register Codec read register Codec slot request register Slot 12 write register Slot 12 read register Codec/SRC control register AC-Link control register Sample rate converter RAM data register Interrupt mask register Reserved DAC1 DMA control register DAC1 DMA length register DAC1 DMA base address register DAC2 DMA control register DAC2 DMA length register DAC2 DMA base address register DAC3 DMA control register DAC3 DMA length register DAC3 DMA base address register ADC1 DMA control register ADC1 DMA length register ADC1 DMA base address register ADC2 DMA control register ADC2 DMA length register ADC2 DMA base address register ADC3 DMA control register ADC3 DMA length register ADC3 DMA base address register 346 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.1 INT_CLR/INT_STATUS (offset address: 0x00) (1/2) Bit Name R/W After reset 31 INTR R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 IOSTS R/W 0 10 STSDAT R/W 0 9 STSADR R/W 0 8 ACLINK_CK R/W 0 Bit Name R/W After reset 7 CODECGPI R/W 0 6 ACLINK R/W 0 5 DAC1END R/W 0 4 DAC2END R/W 0 3 DAC3END R/W 0 2 ADC1END R/W 0 1 ADC2END R/W 0 0 ADC3END R/W 0 Bit 31 Name INTR Function Master interrupt request status 1: Any of bits 11 to 9 and bits 7 to 0 of this register are 1 0: All of bits 11 to 9 and bits 7 to 0 of this register are 0 Reserved. Write 0 to these bits. 0 is returned after a read. AC97 input data slot 12 valid data input interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. AC97 input data slot 2 valid data input interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. AC97 input data slot 1 valid data input interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. 30:12 11 RFU IOSTS 10 STSDAT 9 STSADR User's Manual U14579EJ2V0UM 347 CHAPTER 15 AC97U (AC97 UNIT) (2/2) Bit 8 Name ACLINK_CK Function AC-Link clock request interrupt request, or clock request interrupt request from Codec side during a suspend state 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. Interrupt request when 1 was set for the AC97 input data slot 12 bit 0 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. Interrupt request when a loopback transfer is performed and an error occurred 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. DAC1 DMA end interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. DAC2 DMA end interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. DAC3 DMA end interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. ADC1 DMA end interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. ADC2 DMA end interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. ADC3 DMA end interrupt request 1: Interrupt requested 0: No interrupt requested Writing 1 for this bit clears to 0 the interrupt request signal that was set. 7 CODECGPI 6 ACLINK 5 DAC1END 4 DAC2END 3 DAC3END 2 ADC1END 1 ADC2END 0 ADC3END 348 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.2 CODEC_WR (offset address: 0x04) Bit Name R/W After reset 31 WRDY R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RWC R/W 0 22 WADDR6 R/W 0 21 WADDR5 R/W 0 20 WADDR4 R/W 0 19 WADDR3 R/W 0 18 WADDR2 R/W 0 17 WADDR1 R/W 0 16 WADDR0 R/W 0 Bit Name R/W After reset 15 WDAT15 R/W 0 14 WDAT14 R/W 0 13 WDAT13 R/W 0 12 WDAT12 R/W 0 11 WDAT11 R/W 0 10 WDAT10 R/W 0 9 WDAT9 R/W 0 8 WDAT8 R/W 0 Bit Name R/W After reset 7 WDAT7 R/W 0 6 WDAT6 R/W 0 5 WDAT5 R/W 0 4 WDAT4 R/W 0 3 WDAT3 R/W 0 2 WDAT2 R/W 0 1 WDAT1 R/W 0 0 WDAT0 R/W 0 Bit 31 Name WRDY Function CODEC register (register within external Codec) access status 1: Writing to Codec prohibited 0: Writing to Codec allowed Reserved. Write 0 to these bits. 0 is returned after a read. Sets a read/write command for the CODEC register 1: Read command 0: Write command CODEC register access address For writing: Set the address when accessing the CODEC register. For reading: The address can be read according to the response from the Codec. CODEC register access data For writing: Set the data when accessing the CODEC register. For reading: The data can be read according to the response from the Codec. 30:24 23 RFU RWC 22:16 WADDR(6:0) 15:0 WDAT(15:0) User's Manual U14579EJ2V0UM 349 CHAPTER 15 AC97U (AC97 UNIT) 15.3.3 CODEC_RD (offset address: 0x08) Bit Name R/W After reset 31 RRDYA R 0 30 RRDYD R 0 29 WIP R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RADDR6 R 0 21 RADDR5 R 0 20 RADDR4 R 0 19 RADDR3 R 0 18 RADDR2 R 0 17 RADDR1 R 0 16 RADDR0 R 0 Bit Name R/W After reset 15 RDAT15 R 0 14 RDAT14 R 0 13 RDAT13 R 0 12 RDAT12 R 0 11 RDAT11 R 0 10 RDAT10 R 0 9 RDAT9 R 0 8 RDAT8 R 0 Bit Name R/W After reset 7 RDAT7 R 0 6 RDAT6 R 0 5 RDAT5 R 0 4 RDAT4 R 0 3 RDAT3 R 0 2 RDAT2 R 0 1 RDAT1 R 0 0 RDAT0 R 0 Bit 31 Name RRDYA Function CODEC register access status 1: The RADDR(6:0) area contains valid data from the Codec 0: The RADDR(6:0) area contains no valid data from the Codec This bit is cleared to 0 when read processing ends. CODEC register access status 1: The RDAT(15:0) area contains valid data from the Codec 0: The RDAT(15:0) area contains no valid data from the Codec This bit is cleared to 0 when read processing ends. Code read processing status 1: Read processing for the Codec remains 0: There is no read processing for the Codec Reserved. Write 0 to these bits. 0 is returned after a read. CODEC register access address The address can be read according to the response from the Codec. CODEC register access data The data can be read according to the response from the Codec. 30 RRDYD 29 WIP 28:23 22:16 RFU RADDR(6:0) 15:0 RDAT(15:0) 350 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.4 CODEC_REQ (offset address: 0x0C) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 8 SLOT3_REQ SLOT4_REQ R 0 R 0 Bit Name R/W After reset 7 6 5 4 3 2 1 0 SLOT5_REQ SLOT6_REQ SLOT7_REQ SLOT8_REQ SLOT9_REQ SLOT10_REQ SLOT11_REQ SLOT12_REQ R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit 31:10 9 8 7 6 5 4 3 2 1 0 Name RFU SLOT3_REQ SLOT4_REQ SLOT5_REQ SLOT6_REQ SLOT7_REQ SLOT8_REQ SLOT9_REQ SLOT10_REQ SLOT11_REQ SLOT12_REQ Function Reserved. Write 0 to these bits. 0 is returned after a read. Codec input data slot 1 bit 11 (slot 3 request) Codec input data slot 1 bit 10 (slot 4 request) Codec input data slot 1 bit 9 (slot 5 request) Codec input data slot 1 bit 8 (slot 6 request) Codec input data slot 1 bit 7 (slot 7 request) Codec input data slot 1 bit 6 (slot 8 request) Codec input data slot 1 bit 5 (slot 9 request) Codec input data slot 1 bit 4 (slot 10 request) Codec input data slot 1 bit 3 (slot 11 request) Codec input data slot 1 bit 2 (slot 12 request) User's Manual U14579EJ2V0UM 351 CHAPTER 15 AC97U (AC97 UNIT) 15.3.5 SLOT12_WR (offset address: 0x10) Bit Name R/W After reset 31 WRDY_SLOT R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 LOOP R/W 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 18 17 16 WSLOT1219 WSLOT1218 WSLOT1217 WSLOT1216 R/W 0 R/W 0 R/W 0 R/W 0 Bit Name R/W After reset 15 14 13 12 11 10 9 WSLOT129 R/W 0 8 WSLOT128 R/W 0 WSLOT1215 WSLOT1214 WSLOT1213 WSLOT1212 WSLOT1211 WSLOT1210 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit Name R/W After reset 7 WSLOT127 R/W 0 6 WSLOT126 R/W 0 5 WSLOT125 R/W 0 4 WSLOT124 R/W 0 3 WSLOT123 R/W 0 2 WSLOT122 R/W 0 1 WSLOT121 R/W 0 0 WSLOT120 R/W 0 Bit 31 Name WRDY_SLOT Slot 12 write status 1: Writing to Codec prohibited 0: Writing to Codec allowed Function 30:24 23 RFU LOOP Reserved. Write 0 to these bits. 0 is returned after a read. Slot 12 control 1: LoopbackNote of SLOT12_WR and SLOT12_RD registers 0: Normal Reserved. Write 0 to these bits. 0 is returned after a read. Sets write data for slot 12 22:20 19:0 RFU WSLOT12(19:0) Note This is a VRC4173 standalone debug function. The value written to the SLOT12_WR register can be read by using the SLOT12_RD register. 352 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.6 SLOT12_RD (offset address: 0x14) Bit Name 31 RRDY_ SLOT R 0 30 RFU 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 18 17 16 RSLOT1216 R 0 RSLOT1219 RSLOT1218 RSLOT1217 R 0 R 0 R 0 Bit Name R/W After reset 15 RSLOT1215 R 0 14 13 12 11 10 9 RSLOT129 R 0 8 RSLOT128 R 0 RSLOT1214 RSLOT1213 R 0 R 0 RSLOT1212 RSLOT1211 RSLOT1210 R 0 R 0 R 0 Bit Name R/W After reset 7 RSLOT127 R 0 6 RSLOT126 R 0 5 RSLOT125 R 0 4 RSLOT124 R 0 3 RSLOT123 R 0 2 RSLOT122 R 0 1 RSLOT121 R 0 0 RSLOT120 R 0 Bit 31 Name RRDY_SLOT Function Slot 12 read status 1: The RSLOT12(19:0) area contains valid data from the Codec 0: The RSLOT12(19:0) area contains no valid data from the Codec This bit is cleared to 0 when read processing ends. Reserved. Write 0 to these bits. 0 is returned after a read. Slot 12 data from the Codec can be read. 30:20 19:0 RFU RSLOT12(19:0) User's Manual U14579EJ2V0UM 353 CHAPTER 15 AC97U (AC97 UNIT) 15.3.7 CTRL (offset address: 0x18) (1/2) Bit Name 31 SRC_RAM_ ADR R/W 0 30 SRC_CNVT _ON R/W 0 29 SRC_ FILTER_ON R/W 0 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 MICENB R/W 0 Note 17 DAC3ENB R/W 0 16 ADC3ENB R/W 0 Bit Name R/W After reset 15 DAC2ENB R/W 0 14 ADC2ENB R/W 0 13 DAC1ENB R/W 0 12 ADC1ENB R/W 0 Note 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 4 3 2 1 0 DAC1FORM2 DAC1FORM1 DAC1FORM0 ADC1FORM2 ADC1FORM1 ADC1FORM0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit 31 Name SRC_RAM_ADR Selects sample rate converter RAM 1: ADC RAM or MIC RAM 0: DAC RAM Controls sample rate converter 1: Operate converter 0: Stop converter Controls sample rate filter 1: Setting prohibited 0: Stop filter Function 30 SRC_CNVT_ON 29 SRC_FILTER_ON 28:19 18 RFU MICENBNote Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables MIC slot 1: Enable 0: Disable Enables/disables DAC3 (LINE1) slot 1: Enable 0: Disable 17 DAC3ENB Note As the DMAs of the slots 3 (PCML) and 6 (MIC) cannot be operated simultaneously, do not set the MICENB bit and the ADC1ENB bit to 1 at the same time. 354 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) (2/2) Bit 16 Name ADC3ENB Enables/disables ADC3 (LINE1) slot 1: Enable 0: Disable Enables/disables DAC2 (PCMR) slot 1: Enable 0: Disable Enables/disables ADC2 (PCMR) slot 1: Enable 0: Disable Enables/disables DAC1 (PCML) slot 1: Enable 0: Disable Enables/disables ADC1 (PCML) slot 1: Enable 0: Disable Reserved. Write 0 to these bits. 0 is returned after a read. DAC1 format 111: Setting prohibited 110: Input 44 Kss data from cache buffer 101: Input 22 Kss data from cache buffer 100: Input 11 Kss data from cache buffer 011: Input 32 Kss data from cache buffer 010: Input 16 Kss data from cache buffer 001: Input 8 Kss data from cache buffer 000: Input 48 Kss data from cache buffer ADC1 format 111: Setting prohibited 110: Output 44 Kss data to cache buffer 101: Output 22 Kss data to cache buffer 100: Output 11 Kss data to cache buffer 011: Output 32 Kss data to cache buffer 010: Output 16 Kss data to cache buffer 001: Output 8 Kss data to cache buffer 000: Output 48 Kss data to cache buffer Function 15 DAC2ENB 14 ADC2ENB 13 DAC1ENB 12 ADC1ENBNote 11:6 5:3 RFU DAC1FORM(2:0) 2:0 ADC1FORM(2:0) Note As the DMAs of the slots 3 (PCML) and 6 (MIC) cannot be operated simultaneously, do not set the MICENB bit and the ADC1ENB bit to 1 at the same time. Remark Kss: Kilo Sampling per Second User's Manual U14579EJ2V0UM 355 CHAPTER 15 AC97U (AC97 UNIT) 15.3.8 ACLINK_CTRL (offset address: 0x1C) Bit Name R/W After reset 31 ck_stop_on R/W 0 30 sync_on R/W 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 sync_time7 R/W 1 22 sync_time6 R/W 1 21 sync_time5 R/W 1 20 sync_time4 R/W 1 19 sync_time3 R/W 1 18 sync_time2 R/W 1 17 sync_time1 R/W 1 16 sync_time0 R/W 1 Bit Name R/W After reset 15 aclink_rst_on R/W 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name 7 aclink_rst_ time7 R/W 1 6 aclink_rst_ time6 R/W 1 5 aclink_rst_ time5 R/W 1 4 aclink_rst_ time4 R/W 1 3 aclink_rst_ time3 R/W 1 2 aclink_rst_ time2 R/W 1 1 aclink_rst_ time1 R/W 1 0 aclink_rst_ time0 R/W 1 R/W After reset Bit 31 Name ck_stop_on Function Set this bit to 1 when a power save mode or power down mode command is issued for the Codec. This bit is cleared (0) when a clock pulse is supplied from the Codec. Set this bit to 1 when you want to start the Codec again after the ck_stop_on bit was set to 1 or when a clock request interrupt request was issued from the Codec. A SYNC signal will be automatically output for the Codec. This bit is automatically cleared to 0 after the SYNC signal is output. Reserved. Write 0 to these bits. 0 is returned after a read. Sets the active period of the SYNC signal that is output when 1 was set for the sync_on bit (count clock = 33 MHz). Set this bit to 1 when you want to output a reset_b signal (internal signal) for the Codec. A reset_b signal will be automatically output for the Codec. This bit is automatically cleared to 0 after the reset_b signal is output. Sets the active period of the reset_b signal that is output when 1 was set for the aclink_rst_on bit (count clock = 33 MHz). 30 sync_on 29:24 23:16 RFU sync_time(7:0) 15 aclink_rst_on 7:0 aclink_rst_time(7:0) 356 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) Figure 15-1. SYNC Signal Set 1 in the sync_on bit The sync_on bit is automatically cleared SYNC (sync_time (7:0) + 2) x 33 MHz Figure 15-2. reset_b Signal (Internal Signal) Set 1 in the aclink_rst_on bit The aclink_rst_on bit is automatically cleared reset_b (aclink_rst_time (7:0) + 2) x 33 MHz User's Manual U14579EJ2V0UM 357 CHAPTER 15 AC97U (AC97 UNIT) 15.3.9 SRC_RAM_DATA (offset address: 0x20) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name 15 SRC_RAM_ DATA15 R/W 0 14 SRC_RAM_ DATA14 R/W 0 13 SRC_RAM_ DATA13 R/W 0 12 SRC_RAM_ DATA12 R/W 0 11 SRC_RAM_ DATA11 R/W 0 10 SRC_RAM_ DATA10 R/W 0 9 SRC_RAM_ DATA9 R/W 0 8 SRC_RAM_ DATA8 R/W 0 R/W After reset Bit Name 7 SRC_RAM_ DATA7 R/W 0 6 SRC_RAM_ DATA6 R/W 0 5 SRC_RAM_ DATA5 R/W 0 4 SRC_RAM_ DATA4 R/W 0 3 SRC_RAM_ DATA3 R/W 0 2 SRC_RAM_ DATA2 R/W 0 1 SRC_RAM_ DATA1 R/W 0 0 SRC_RAM_ DATA0 R/W 0 R/W After reset Bit 31:16 15:0 Name RFU SRC_RAM_DATA(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. Sample rate converter RAM data The RAM that was specified by the SRC_RAM_ADR bit of the CTRL register can be accessed by reading from or writing to this register. However, this register cannot be written to during a DMA operation. The RAM that is selected by the SRC_RAM_ADR bit is 16 bits x 32 levels. The 32-level RAM can be accessed by continuously reading from or writing to this register. 358 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.10 INT_MASK (offset address: 0x24) (1/2) Bit Name R/W After reset 31 MMASK R/W 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name 15 RFU 14 RFU 13 RFU 12 RFU 11 MASK_ IOSTS R/W 0 10 MASK_ STSDAT R/W 0 9 MASK_ STSADR R/W 0 8 MASK_ ACLINK_CK R/W 0 R/W After reset R 0 R 0 R 0 R 0 Bit Name 7 MASK_ CODECGPI R/W 0 6 MASK_ ACLINK R/W 0 5 MASK_ DAC1END R/W 0 4 MASK_ DAC2END R/W 0 3 MASK_ DAC3END R/W 0 2 MASK_ ADC1END R/W 0 1 MASK_ ADC2END R/W 0 0 MASK_ ADC3END R/W 0 R/W After reset Bit 31 Name MMASK Enables/disables mask interrupt 1: Enable 0: Disable Function 30:12 11 RFU MASK_IOSTS Reserved. Write 0 to these bits. 0 is returned after a read. Enables/disables AC97 input data slot 12 valid data input interrupt 1: Enable 0: Disable Enables/disables AC97 input data slot 2 valid data input interrupt 1: Enable 0: Disable Enables/disables AC97 input data slot 1 valid data input interrupt 1: Enable 0: Disable 10 MASK_STSDAT 9 MASK_STSADR User's Manual U14579EJ2V0UM 359 CHAPTER 15 AC97U (AC97 UNIT) (2/2) Bit 8 Name MASK_ACLINK_CK Function Enables/disables AC-Link clock request interrupt or enables/disables clock request interrupt from Codec side during a suspend state 1: Enable 0: Disable Enables/disables interrupt when 1 was set for the AC97 input data slot 12 bit 0 1: Enable 0: Disable Enables/disables interrupt when a loopback transfer is performed and an error occurred 1: Enable 0: Disable Enables/disables DAC1 DMA end interrupt 1: Enable 0: Disable Enables/disables DAC2 DMA end interrupt 1: Enable 0: Disable Enables/disables DAC3 DMA end interrupt 1: Enable 0: Disable Enables/disables ADC1 DMA end interrupt 1: Enable 0: Disable Enables/disables ADC2 DMA end interrupt 1: Enable 0: Disable Enables/disables ADC3 DMA end interrupt 1: Enable 0: Disable 7 MASK_CODECGPI 6 MASK_ACLINK 5 MASK_DAC1END 4 MASK_DAC2END 3 MASK_DAC3END 2 MASK_ADC1END 1 MASK_ADC2END 0 MASK_ADC3END When an interrupt is set to disabled (the relevant bit is set to 0) in this register and an interrupt request is generated internally, the interrupt request is masked. When the relevant bit is set to 1, the interrupt request is reported to the external component. 360 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.11 DAC1_CTRL (offset address: 0x30) Bit Name 31 DAC1_ ENABLE R/W 0 30 DAC1_ STATUS R 0 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 31 Name DAC1_ENABLE DAC1 DMA control 1: Enable 0: Disable DAC1 AC-Link transfer status 1: Transfer in progress 0: Transfer ended Function 30 DAC1_STATUS 29:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. User's Manual U14579EJ2V0UM 361 CHAPTER 15 AC97U (AC97 UNIT) 15.3.12 DAC1L (offset address: 0x34) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 DAC1L15 R/W 0 14 DAC1L14 R/W 0 13 DAC1L13 R/W 0 12 DAC1L12 R/W 0 11 DAC1L11 R/W 0 10 DAC1L10 R/W 0 9 DAC1L9 R/W 0 8 DAC1L8 R/W 0 Bit Name R/W After reset 7 DAC1L7 R/W 0 6 DAC1L6 R/W 0 5 DAC1L5 R/W 0 4 DAC1L4 R/W 0 3 DAC1L3 R/W 0 2 DAC1L2 R/W 0 1 DAC1L1 R/W 0 0 DAC1L0 R/W 0 Bit 31:16 15:0 Name RFU DAC1L(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. DAC1 DMA transfer count * DMA transfer count For a single DMA transfer, 32 bits x 4 data are input from memory. Also, the data size that is output at one time to the Codec is 16 bits of the data that was input from memory. Therefore, when 1 is set in the DAC1L(15:0) area, 32 bits x 4 data are input from memory and data is output 8 times to the Codec. 362 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.13 DAC1_BADDR (offset address: 0x38) Bit Name 31 DAC1_ BADDR31 R/W 0 30 DAC1_ BADDR30 R/W 0 29 DAC1_ BADDR29 R/W 0 28 DAC1_ BADDR28 R/W 0 27 DAC1_ BADDR27 R/W 0 26 DAC1_ BADDR26 R/W 0 25 DAC1_ BADDR25 R/W 0 24 DAC1_ BADDR24 R/W 0 R/W After reset Bit Name 23 DAC1_ BADDR23 R/W 0 22 DAC1_ BADDR22 R/W 0 21 DAC1_ BADDR21 R/W 0 20 DAC1_ BADDR20 R/W 0 19 DAC1_ BADDR19 R/W 0 18 DAC1_ BADDR18 R/W 0 17 DAC1_ BADDR17 R/W 0 16 DAC1_ BADDR16 R/W 0 R/W After reset Bit Name 15 DAC1_ BADDR15 R/W 0 14 DAC1_ BADDR14 R/W 0 13 DAC1_ BADDR13 R/W 0 12 DAC1_ BADDR12 R/W 0 11 DAC1_ BADDR11 R/W 0 10 DAC1_ BADDR10 R/W 0 9 DAC1_ BADDR9 R/W 0 8 DAC1_ BADDR8 R/W 0 R/W After reset Bit Name 7 DAC1_ BADDR7 R/W 0 6 DAC1_ BADDR6 R/W 0 5 DAC1_ BADDR5 R/W 0 4 DAC1_ BADDR4 R/W 0 3 DAC1_ BADDR3 R/W 0 2 DAC1_ BADDR2 R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 Bit 31:2 1:0 Name DAC1_BADDR(31:2) RFU Sets the DAC1 DMA base address Function Reserved. Write 0 to these bits. 0 is returned after a read. User's Manual U14579EJ2V0UM 363 CHAPTER 15 AC97U (AC97 UNIT) 15.3.14 DAC2_CTRL (offset address: 0x3C) Bit Name 31 DAC2_ ENABLE R/W 0 30 DAC2_ STATUS R 0 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 31 Name DAC2_ENABLE DAC2 DMA control 1: Enable 0: Disable DAC2 AC-Link transfer status 1: Transfer in progress 0: Transfer ended Function 30 DAC2_STATUS 29:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. 364 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.15 DAC2L (offset address: 0x40) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 DAC2L15 R/W 0 14 DAC2L14 R/W 0 13 DAC2L13 R/W 0 12 DAC2L12 R/W 0 11 DAC2L11 R/W 0 10 DAC2L10 R/W 0 9 DAC2L9 R/W 0 8 DAC2L8 R/W 0 Bit Name R/W After reset 7 DAC2L7 R/W 0 6 DAC2L6 R/W 0 5 DAC2L5 R/W 0 4 DAC2L4 R/W 0 3 DAC2L3 R/W 0 2 DAC2L2 R/W 0 1 DAC2L1 R/W 0 0 DAC2L0 R/W 0 Bit 31:16 15:0 Name RFU DAC2L(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. DAC2 DMA transfer count * DMA transfer count For a single DMA transfer, 32 bits x 4 data are input from memory. Also, the data size that is output at one time to the Codec is 16 bits of the data that was input from memory. Therefore, when 1 is set in the DAC2L(15:0) area, 32 bits x 4 data are input from memory and data is output 8 times to the Codec. User's Manual U14579EJ2V0UM 365 CHAPTER 15 AC97U (AC97 UNIT) 15.3.16 DAC2_BADDR (offset address: 0x44) Bit Name 31 DAC2_ BADDR31 R/W 0 30 DAC2_ BADDR30 R/W 0 29 DAC2_ BADDR29 R/W 0 28 DAC2_ BADDR28 R/W 0 27 DAC2_ BADDR27 R/W 0 26 DAC2_ BADDR26 R/W 0 25 DAC2_ BADDR25 R/W 0 24 DAC2_ BADDR24 R/W 0 R/W After reset Bit Name 23 DAC2_ BADDR23 R/W 0 22 DAC2_ BADDR22 R/W 0 21 DAC2_ BADDR21 R/W 0 20 DAC2_ BADDR20 R/W 0 19 DAC2_ BADDR19 R/W 0 18 DAC2_ BADDR18 R/W 0 17 DAC2_ BADDR17 R/W 0 16 DAC2_ BADDR16 R/W 0 R/W After reset Bit Name 15 DAC2_ BADDR15 R/W 0 14 DAC2_ BADDR14 R/W 0 13 DAC2_ BADDR13 R/W 0 12 DAC2_ BADDR12 R/W 0 11 DAC2_ BADDR11 R/W 0 10 DAC2_ BADDR10 R/W 0 9 DAC2_ BADDR9 R/W 0 8 DAC2_ BADDR8 R/W 0 R/W After reset Bit Name 7 DAC2_ BADDR7 R/W 0 6 DAC2_ BADDR6 R/W 0 5 DAC2_ BADDR5 R/W 0 4 DAC2_ BADDR4 R/W 0 3 DAC2_ BADDR3 R/W 0 2 DAC2_ BADDR2 R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 Bit 31:2 1:0 Name DAC2_BADDR(31:2) RFU Sets the DAC2 DMA base address Function Reserved. Write 0 to these bits. 0 is returned after a read. 366 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.17 DAC3_CTRL (offset address: 0x48) Bit Name 31 DAC3_ ENABLE R/W 0 30 DAC3_ STATUS R 0 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 31 Name DAC3_ENABLE DAC3 DMA control 1: Enable 0: Disable DAC3 AC-Link transfer status 1: Transfer in progress 0: Transfer ended Function 30 DAC3_STATUS 29:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. User's Manual U14579EJ2V0UM 367 CHAPTER 15 AC97U (AC97 UNIT) 15.3.18 DAC3L (offset address: 0x4C) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 DAC3L15 R/W 0 14 DAC3L14 R/W 0 13 DAC3L13 R/W 0 12 DAC3L12 R/W 0 11 DAC3L11 R/W 0 10 DAC3L10 R/W 0 9 DAC3L9 R/W 0 8 DAC3L8 R/W 0 Bit Name R/W After reset 7 DAC3L7 R/W 0 6 DAC3L6 R/W 0 5 DAC3L5 R/W 0 4 DAC3L4 R/W 0 3 DAC3L3 R/W 0 2 DAC3L2 R/W 0 1 DAC3L1 R/W 0 0 DAC3L0 R/W 0 Bit 31:16 15:0 Name RFU DAC3L(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. DAC3 DMA transfer count * DMA transfer count For a single DMA transfer, 32 bits x 4 data are input from memory. Also, the data size that is output at one time to the Codec is 16 bits of the data that was input from memory. Therefore, when 1 is set in the DAC3L(15:0) area, 32 bits x 4 data are input from memory and data is output 8 times to the Codec. 368 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.19 DAC3_BADDR (offset address: 0x50) Bit Name 31 DAC3_ BADDR31 R/W 0 30 DAC3_ BADDR30 R/W 0 29 DAC3_ BADDR29 R/W 0 28 DAC3_ BADDR28 R/W 0 27 DAC3_ BADDR27 R/W 0 26 DAC3_ BADDR26 R/W 0 25 DAC3_ BADDR25 R/W 0 24 DAC3_ BADDR24 R/W 0 R/W After reset Bit Name 23 DAC3_ BADDR23 R/W 0 22 DAC3_ BADDR22 R/W 0 21 DAC3_ BADDR21 R/W 0 20 DAC3_ BADDR20 R/W 0 19 DAC3_ BADDR19 R/W 0 18 DAC3_ BADDR18 R/W 0 17 DAC3_ BADDR17 R/W 0 16 DAC3_ BADDR16 R/W 0 R/W After reset Bit Name 15 DAC3_ BADDR15 R/W 0 14 DAC3_ BADDR14 R/W 0 13 DAC3_ BADDR13 R/W 0 12 DAC3_ BADDR12 R/W 0 11 DAC3_ BADDR11 R/W 0 10 DAC3_ BADDR10 R/W 0 9 DAC3_ BADDR9 R/W 0 8 DAC3_ BADDR8 R/W 0 R/W After reset Bit Name 7 DAC3_ BADDR7 R/W 0 6 DAC3_ BADDR6 R/W 0 5 DAC3_ BADDR5 R/W 0 4 DAC3_ BADDR4 R/W 0 3 DAC3_ BADDR3 R/W 0 2 DAC3_ BADDR2 R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 Bit 31:2 1:0 Name DAC3_BADDR(31:2) RFU Sets the DAC3 DMA base address Function Reserved. Write 0 to these bits. 0 is returned after a read. User's Manual U14579EJ2V0UM 369 CHAPTER 15 AC97U (AC97 UNIT) 15.3.20 ADC1_CTRL (offset address: 0x54) Bit Name 31 ADC1_ ENABLE R/W 0 30 RFU 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 31 Name ADC1_ENABLE ADC1 DMA control 1: Enable 0: Disable Function 30:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. 370 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.21 ADC1L (offset address: 0x58) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 ADC1L15 R/W 0 14 ADC1L14 R/W 0 13 ADC1L13 R/W 0 12 ADC1L12 R/W 0 11 ADC1L11 R/W 0 10 ADC1L10 R/W 0 9 ADC1L9 R/W 0 8 ADC1L8 R/W 0 Bit Name R/W After reset 7 ADC1L7 R/W 0 6 ADC1L6 R/W 0 5 ADC1L5 R/W 0 4 ADC1L4 R/W 0 3 ADC1L3 R/W 0 2 ADC1L2 R/W 0 1 ADC1L1 R/W 0 0 ADC1L0 R/W 0 Bit 31:16 15:0 Name RFU ADC1L(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. ADC1 DMA transfer count * DMA transfer count For a single DMA transfer, 32 bits x 4 data are output to memory. Also, the data size that is input at one time from the Codec is 16 bits of the data that is output to memory. Therefore, when 1 is set in the ADC1L(15:0) area, data is input 8 times from the Codec and 32 bits x 4 data are output to memory. User's Manual U14579EJ2V0UM 371 CHAPTER 15 AC97U (AC97 UNIT) 15.3.22 ADC1_BADDR (offset address: 0x5C) Bit Name 31 ADC1_ BADDR31 R/W 0 30 ADC1_ BADDR30 R/W 0 29 ADC1_ BADDR29 R/W 0 28 ADC1_ BADDR28 R/W 0 27 ADC1_ BADDR27 R/W 0 26 ADC1_ BADDR26 R/W 0 25 ADC1_ BADDR25 R/W 0 24 ADC1_ BADDR24 R/W 0 R/W After reset Bit Name 23 ADC1_ BADDR23 R/W 0 22 ADC1_ BADDR22 R/W 0 21 ADC1_ BADDR21 R/W 0 20 ADC1_ BADDR20 R/W 0 19 ADC1_ BADDR19 R/W 0 18 ADC1_ BADDR18 R/W 0 17 ADC1_ BADDR17 R/W 0 16 ADC1_ BADDR16 R/W 0 R/W After reset Bit Name 15 ADC1_ BADDR15 R/W 0 14 ADC1_ BADDR14 R/W 0 13 ADC1_ BADDR13 R/W 0 12 ADC1_ BADDR12 R/W 0 11 ADC1_ BADDR11 R/W 0 10 ADC1_ BADDR10 R/W 0 9 ADC1_ BADDR9 R/W 0 8 ADC1_ BADDR8 R/W 0 R/W After reset Bit Name 7 ADC1_ BADDR7 R/W 0 6 ADC1_ BADDR6 R/W 0 5 ADC1_ BADDR5 R/W 0 4 ADC1_ BADDR4 R/W 0 3 ADC1_ BADDR3 R/W 0 2 ADC1_ BADDR2 R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 Bit 31:2 1:0 Name ADC1_BADDR(31:2) RFU Sets the ADC1 DMA base address Function Reserved. Write 0 to these bits. 0 is returned after a read. 372 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.23 ADC2_CTRL (offset address: 0x60) Bit Name 31 ADC2_ ENABLE R/W 0 30 RFU 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 31 Name ADC2_ENABLE ADC2 DMA control 1: Enable 0: Disable Function 30:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. User's Manual U14579EJ2V0UM 373 CHAPTER 15 AC97U (AC97 UNIT) 15.3.24 ADC2L (offset address: 0x64) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 ADC2L15 R/W 0 14 ADC2L14 R/W 0 13 ADC2L13 R/W 0 12 ADC2L12 R/W 0 11 ADC2L11 R/W 0 10 ADC2L10 R/W 0 9 ADC2L9 R/W 0 8 ADC2L8 R/W 0 Bit Name R/W After reset 7 ADC2L7 R/W 0 6 ADC2L6 R/W 0 5 ADC2L5 R/W 0 4 ADC2L4 R/W 0 3 ADC2L3 R/W 0 2 ADC2L2 R/W 0 1 ADC2L1 R/W 0 0 ADC2L0 R/W 0 Bit 31:16 15:0 Name RFU ADC2L(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. ADC2 DMA transfer count * DMA transfer count For a single DMA transfer, 32 bits x 4 data are output to memory. Also, the data size that is input at one time from the Codec is 16 bits of the data that is output to memory. Therefore, when 1 is set in the ADC2L(15:0) area, data is input 8 times from the Codec and 32 bits x 4 data are output to memory. 374 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.25 ADC2_BADDR (offset address: 0x68) Bit Name 31 ADC2_ BADDR31 R/W 0 30 ADC2_ BADDR30 R/W 0 29 ADC2_ BADDR29 R/W 0 28 ADC2_ BADDR28 R/W 0 27 ADC2_ BADDR27 R/W 0 26 ADC2_ BADDR26 R/W 0 25 ADC2_ BADDR25 R/W 0 24 ADC2_ BADDR24 R/W 0 R/W After reset Bit Name 23 ADC2_ BADDR23 R/W 0 22 ADC2_ BADDR22 R/W 0 21 ADC2_ BADDR21 R/W 0 20 ADC2_ BADDR20 R/W 0 19 ADC2_ BADDR19 R/W 0 18 ADC2_ BADDR18 R/W 0 17 ADC2_ BADDR17 R/W 0 16 ADC2_ BADDR16 R/W 0 R/W After reset Bit Name 15 ADC2_ BADDR15 R/W 0 14 ADC2_ BADDR14 R/W 0 13 ADC2_ BADDR13 R/W 0 12 ADC2_ BADDR12 R/W 0 11 ADC2_ BADDR11 R/W 0 10 ADC2_ BADDR10 R/W 0 9 ADC2_ BADDR9 R/W 0 8 ADC2_ BADDR8 R/W 0 R/W After reset Bit Name 7 ADC2_ BADDR7 R/W 0 6 ADC2_ BADDR6 R/W 0 5 ADC2_ BADDR5 R/W 0 4 ADC2_ BADDR4 R/W 0 3 ADC2_ BADDR3 R/W 0 2 ADC2_ BADDR2 R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 Bit 31:2 1:0 Name ADC2_BADDR(31:2) RFU Sets the ADC2 DMA base address Function Reserved. Write 0 to these bits. 0 is returned after a read. User's Manual U14579EJ2V0UM 375 CHAPTER 15 AC97U (AC97 UNIT) 15.3.26 ADC3_CTRL (offset address: 0x6C) Bit Name 31 ADC3_ ENABLE R/W 0 30 RFU 29 RFU 28 RFU 27 RFU 26 RFU 25 RFU 24 RFU R/W After reset R 0 R 0 R 0 R 0 R 0 R 0 R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 RFU R 0 14 RFU R 0 13 RFU R 0 12 RFU R 0 11 RFU R 0 10 RFU R 0 9 RFU R 0 8 RFU R 0 Bit Name R/W After reset 7 RFU R 0 6 RFU R 0 5 RFU R 0 4 RFU R 0 3 RFU R 0 2 RFU R 0 1 RFU R 0 0 RFU R 0 Bit 31 Name ADC3_ENABLE ADC3 DMA control 1: Enable 0: Disable Function 30:0 RFU Reserved. Write 0 to these bits. 0 is returned after a read. 376 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.3.27 ADC3L (offset address: 0x70) Bit Name R/W After reset 31 RFU R 0 30 RFU R 0 29 RFU R 0 28 RFU R 0 27 RFU R 0 26 RFU R 0 25 RFU R 0 24 RFU R 0 Bit Name R/W After reset 23 RFU R 0 22 RFU R 0 21 RFU R 0 20 RFU R 0 19 RFU R 0 18 RFU R 0 17 RFU R 0 16 RFU R 0 Bit Name R/W After reset 15 ADC3L15 R/W 0 14 ADC3L14 R/W 0 13 ADC3L13 R/W 0 12 ADC3L12 R/W 0 11 ADC3L11 R/W 0 10 ADC3L10 R/W 0 9 ADC3L9 R/W 0 8 ADC3L8 R/W 0 Bit Name R/W After reset 7 ADC3L7 R/W 0 6 ADC3L6 R/W 0 5 ADC3L5 R/W 0 4 ADC3L4 R/W 0 3 ADC3L3 R/W 0 2 ADC3L2 R/W 0 1 ADC3L1 R/W 0 0 ADC3L0 R/W 0 Bit 31:16 15:0 Name RFU ADC3L(15:0) Function Reserved. Write 0 to these bits. 0 is returned after a read. ADC3 DMA transfer count * DMA transfer count For a single DMA transfer, 32 bits x 4 data are output to memory. Also, the data size that is input at one time from the Codec is 16 bits of the data that is output to memory. Therefore, when 1 is set in the ADC3L(15:0) area, data is input 8 times from the Codec and 32 bits x 4 data are output to memory. User's Manual U14579EJ2V0UM 377 CHAPTER 15 AC97U (AC97 UNIT) 15.3.28 ADC3_BADDR (offset address: 0x74) Bit Name 31 ADC3_ BADDR31 R/W 0 30 ADC3_ BADDR30 R/W 0 29 ADC3_ BADDR29 R/W 0 28 ADC3_ BADDR28 R/W 0 27 ADC3_ BADDR27 R/W 0 26 ADC3_ BADDR26 R/W 0 25 ADC3_ BADDR25 R/W 0 24 ADC3_ BADDR24 R/W 0 R/W After reset Bit Name 23 ADC3_ BADDR23 R/W 0 22 ADC3_ BADDR22 R/W 0 21 ADC3_ BADDR21 R/W 0 20 ADC3_ BADDR20 R/W 0 19 ADC3_ BADDR19 R/W 0 18 ADC3_ BADDR18 R/W 0 17 ADC3_ BADDR17 R/W 0 16 ADC3_ BADDR16 R/W 0 R/W After reset Bit Name 15 ADC3_ BADDR15 R/W 0 14 ADC3_ BADDR14 R/W 0 13 ADC3_ BADDR13 R/W 0 12 ADC3_ BADDR12 R/W 0 11 ADC3_ BADDR11 R/W 0 10 ADC3_ BADDR10 R/W 0 9 ADC3_ BADDR9 R/W 0 8 ADC3_ BADDR8 R/W 0 R/W After reset Bit Name 7 ADC3_ BADDR7 R/W 0 6 ADC3_ BADDR6 R/W 0 5 ADC3_ BADDR5 R/W 0 4 ADC3_ BADDR4 R/W 0 3 ADC3_ BADDR3 R/W 0 2 ADC3_ BADDR2 R/W 0 1 RFU 0 RFU R/W After reset R 0 R 0 Bit 31:2 1:0 Name ADC3_BADDR(31:2) RFU Sets the ADC3 DMA base address Function Reserved. Write 0 to these bits. 0 is returned after a read. 378 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.4 AC97 Interface Configuration Figure 15-3 shows the AC97 interface configuration. Figure 15-3. AC97 Interface Configuration PCI bus VRC4173 PCI bridge Flip bus AC97U AC-Link AC97 Codec User's Manual U14579EJ2V0UM 379 CHAPTER 15 AC97U (AC97 UNIT) 15.5 AC97U Function Overview 15.5.1 Block diagram Figure 15-4 shows a block diagram of the AC97U. Figure 15-4. AC97U Block Diagram VRC4173 Flip bus AC97U Host interface Interrupt control DMA control Cache buffer SRC control AC-Link SDATAOUT BCLK (12.228 MHz) Codec interface SDATAIN SYNC ACLINKRST# AC97 Codec 380 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.5.2 AC-Link interface support format The AC97U only supports the slots shown in Figure 15-5 among those in the AC97 guidelines. Figure 15-5. AC97U-Supported Slots 48 kHz (20.8 s) Slot number SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 SDATAOUT TAG CMD CMD PCM PCM LINE1 RFU RFU RFU RFU RFU RFU IO ADDR DATA L R DAC CTRL STATUS STATUS PCM PCM LINE1 MIC RFU RFU RFU RFU RFU IO ADDR DATA L R ADC ADC STATUS SDATAIN TAG For details about the data transfer format, see 15.6 AC-Link Interface Data Transfer Format. 15.5.3 Cache buffer The AC97U has a cache buffer for transferring audio data or modem data. This buffer has a total of six blocks. The DAC1, DAC2, and DAC3 blocks are for output, and the ADC1, ADC2, and ADC3 blocks are for input. Name DAC1 DAC2 DAC3 ADC1 ADC2 ADC3 Function PCM L (16 bytes) PCM R (16 bytes) Line 1 (16 bytes) PCM L or MIC (16 bytes) PCM R (16 bytes) Line 1 (16 bytes) (1) Buffer format Two 16-byte buffers (buffer 1 and buffer 2) are allocated for each block. Figure 15-6. Buffer Format Buffer 1 (16 bytes) 31 1 3 5 7 16 15 0 2 4 6 0 31 Buffer 2 (16 bytes) 16 15 1 3 5 7 0 2 4 6 0 User's Manual U14579EJ2V0UM 381 CHAPTER 15 AC97U (AC97 UNIT) (2) Data transfer On the PCI bus, 32-bit (word) data transfers are performed in units of 4 words. The first transfer after transfers are enabled is a 4-word burst transfer performed two times consecutively to fill the double buffer. Subsequently, the buffers are filled alternately by requesting the next data whenever one buffer becomes empty. Figure 15-7. Data Transfer (Buffer AC-Link) PCI bus Request Cache buffer block Buffer 1 Transfer Buffer 2 Transfer AC-Link Figure 15-8. Data Transfer (AC-Link Buffer) PCI bus Request Cache buffer block Buffer 1 Transfer Buffer 2 Transfer AC-Link 15.5.4 DMA control The following control registers are used for DMA transfers in terms of individual DAC1, DAC2, DAC3, ADC1, ADC2, and ADC3 cache buffers. * Memory base address/data length register * Transfer control register (enable, status) 382 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.5.5 Interrupt control Figure 15-9 shows interrupt control. Figure 15-9. Interrupt Control Interrupt source S FF AND OR INTR R Set 1 in INT_CLR/INT_STATUS register Interrupt request mask (INT_MSK register) Various types of interrupt requests 15.5.6 SRC (sample rate converter) This section explains the converter and filter functions. Since the AC97U handles all audio I/O data by using 48 kHz samples, rate conversion must be performed for data having various sample conditions. The converter function performs this rate conversion. However, when a rate conversion is simply performed from PCM data, distortion occurs in the output analog waveform. Therefore, the filter function is used to restore the waveform. (1) Input data format * 16-bit data * Bit 15 is a sign bit * When the sign bit is 1, set two's-complement data for the data part (bits 14 to 0). * The decimal point position can be selected. However, the same position is set for all data (fixed decimal point). Figure 15-10. Input Data Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Decimal point position A Sign bit Decimal point position B Remark Coefficient range when the decimal point position is A: -1 < X < 1 Coefficient range when the decimal point position is B: -32767 < X < 32767 User's Manual U14579EJ2V0UM 383 CHAPTER 15 AC97U (AC97 UNIT) (2) Converter function Figure 15-11 shows the converter function when data is output. When data is input, 48 Kss data is input from the AC-Link and converted to data of various rates in the reverse of the process shown for data output. Figure 15-11. Converter Function (for Output) 11 Kss 11.025 -> 22.05 (1:2) 22 Kss 22.25 -> 44.1 (1:2) 44 Kss 44.1 -> 48.0 (147:160) to AC-Link 48 Kss 8 Kss 8.0 -> 16.0 (1:2) 16 Kss 16.0 -> 32.0 (1:2) 32 Kss 32.0 -> 48.0 (2:3) (a) Output data conversion * For 1:2 data Data B, A B, (B+A)/2, A * For 2:3 data Data C, B, A C, (C+B)/2, (B+A)/2, A * For 147:160 data Prepare 147 counters and insert on average 13 values by taking the averages of 13 pairs of consecutive data among them. (b) Input data conversion * For 1:2 data Data C, B, A C, A * For 2:3 data Data D, C, B, A D, C, A * For 147:160 data Prepare 160 counters and delete on average 13 values among them. 384 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) (3) Filter function A 32-order FIR filter is used as the filter function. Figure 15-12. Filter Function Codec 48k Waveform data 4k to 48k Converter Filter Record data 4k to 48k Codec 48k The output equation is as follows. y(x_0) = (a_-31 x x_-31) + (a_-30 x x_-30) +...+ (a_0 x x_0) Remarks 1. y: Output signal x: Input signal a: Coefficient 2. The "_-31" of x_-31 indicates the input signal that appeared 31 signals prior to the input signal (x_0) to be input next. The prior position (how many signals earlier) of the signal to be used differs according to the sample rate (8k, 16k, 32k, 11k, 22k, or 44k). For input-signal 8 kHz sample data (system Codec direction), to convert to a 48 kHz sample, the signal with an 8 kHz period (input signal) is converted to 6 times the sample rate (48 kHz) (signal expansion) and output. For input-signal 48 kHz sample data (system Codec direction), to convert to an 8 kHz sample, the signal with a 48 kHz period (input signal) is converted to 1/6 times the sample rate (8 kHz) (signal compression) and output. However, when the filter function is used together with the converter function, this processing is not performed because the input signal has been converted to the sample rate. To use the filter function for a DMA transfer, the coefficients for the calculation must be set in the filter RAM in advance. For details about the filter RAM, see 15.12 Filter RAM. User's Manual U14579EJ2V0UM 385 CHAPTER 15 AC97U (AC97 UNIT) 15.6 AC-Link Interface Data Transfer Format Figure 15-13 shows the AC-Link interface data transfer format. Figure 15-13. AC-Link Interface Data Transfer Format 48 kHz (20.8 s) Slot number SYNC 0 1 2 3 4 5 6 7 8 9 10 11 12 SDATAOUT TAG CMD CMD PCM PCM LINE1 RFU RFU RFU RFU RFU RFU IO ADDR DATA L R DAC CTRL STATUSSTATUS PCM PCM LINE1 MIC SDATAIN TAG ADDR DATA L R ADC ADC RFU RFU RFU RFU RFU IO STATUS * SDATAOUT For slots 1, 2, and 12, data is output by performing write processing in the operational registers. For slots 3, 4, and 5, data is output by starting DMAs for DAC1, DAC2, and DAC3, respectively. * SDATAIN For slots 1, 2, and 12, data is input by generating an interrupt request when a valid data is input and performing read processing for the operational registers. For slots 3, 4, 5, and 6, data is input by starting DMAs for ADC1, ADC2, ADC3, and ADC1 respectively. 386 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) (1) SDATAOUT slot 0: TAG Bit 15 Function Valid Frame When any of bits 14 to 10 or bit 3 is 1, 1 is set for this bit. Slot1 Valid bit When a write operation is performed for the CODEC_WR register, 1 is set for this bit. Slot2 Valid bit When a write operation is performed for the CODEC_WR register, 1 is set for this bit. Slot3 Valid bit When a DMA is started for DAC1, 1 is set for this bit. Slot4 Valid bit When a DMA is started for DAC2, 1 is set for this bit. Slot5 Valid bit When a DMA is started for DAC3, 1 is set for this bit. Slot6 Valid bit (fixed at 0). Slot7 Valid bit (fixed at 0). Slot8 Valid bit (fixed at 0). Slot9 Valid bit (fixed at 0). Slot10 Valid bit (fixed at 0). Slot11 Valid bit (fixed at 0). Slot12 Valid bit When a write operation is performed for the CODEC_RD register, 1 is set for this bit. These bits are fixed at 0. 14 13 12 11 10 9 8 7 6 5 4 3 2:0 (2) SDATAOUT slot 1: CMDADDR (Command Address Port) Bit 19 Function Read/Write Command (1: Read, 0: Write) Outputs the value that was set in the RWC bit of the CODEC_WR register. Control Register Index Outputs the value that was set in the WADDR(6:0) area of the CODEC_WR register. These bits are fixed at 0. 18:12 11:0 (3) SDATAOUT slot 2: CMDDATA (Command Data Port) Bit 19:4 Function Control Register Write Data Outputs the value that was set in the WDAT(15:0) area of the CODEC_WR register. These bits are fixed at 0. 3:0 User's Manual U14579EJ2V0UM 387 CHAPTER 15 AC97U (AC97 UNIT) (4) SDATAOUT slot 3: PCML (PCM Playback Left Channel) Bit 19:4 Function PCM Playback Left Data Outputs the result of the calculation (filter or rate conversion) that was performed on the data that was input from memory due to a DMA for DAC1. These bits are fixed at 0. 3:0 (5) SDATAOUT slot 4: PCMR (PCM Playback Right Channel) Bit 19:4 Function PCM Playback Right Data Outputs the result of the calculation (filter or rate conversion) that was performed on the data that was input from memory due to a DMA for DAC2. These bits are fixed at 0. 3:0 (6) SDATAOUT slot 5: LINE1DAC (Optional Modem Line1 DAC) Bit 19:4 Function Optional Modem Line1 DAC Data Outputs the data that was input from memory due to a DMA for DAC3. These bits are fixed at 0. 3:0 (7) SDATAOUT slot 12: IOCTRL (Optional Modem GPIO Control) Bit 19:0 Function up to 16 GPIO pins Outputs the value that was set in the WSLOT12(19:0) bits of the SLOT12_WR register. 388 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) (8) SDATAIN slot 0: TAG Bit 15 Function Valid Frame When any of bits 14 to 10 or bit 3 is 1, this bit becomes 1. Slot1 Valid bit When 1 is entered for this bit, an interrupt request is generated. Slot2 Valid bit When 1 is entered for this bit, an interrupt request is generated. Slot3 Valid bit When 1 is entered for this bit, a DMA is started for ADC1. Slot4 Valid bit When 1 is entered for this bit, a DMA is started for ADC2. Slot5 Valid bit When 1 is entered for this bit, a DMA is started for ADC3. Slot6 Valid bit When 1 is entered for this bit, a DMA is started for ADC1. Unused Slot12 Valid bit When 1 is entered for this bit, an interrupt request is generated. Unused 14 13 12 11 10 9 8:4 3 2:0 User's Manual U14579EJ2V0UM 389 CHAPTER 15 AC97U (AC97 UNIT) (9) SDATAIN slot 1: STATUSADDR (Status Address Port) Bit 19 18:12 Unused Control Register Index The value of this area is displayed in the RADDR(6:0) area of the CODEC_RD register. Slot3 Request: PCM Left Channel The value of this bit is displayed in the SLOT3_REQ bit of the CODEC_REQ register. Slot4 Request: PCM Right Channel The value of this bit is displayed in the SLOT4_REQ bit of the CODEC_REQ register. Slot5 Request: Modem Line1 The value of this bit is displayed in the SLOT5_REQ bit of the CODEC_REQ register. Slot6 Request: PCM Center The value of this bit is displayed in the SLOT6_REQ bit of the CODEC_REQ register. Slot7 Request: PCM Left surround The value of this bit is displayed in the SLOT7_REQ bit of the CODEC_REQ register. Slot8 Request: PCM Right surround The value of this bit is displayed in the SLOT8_REQ bit of the CODEC_REQ register. Slot9 Request: PCM LFE The value of this bit is displayed in the SLOT9_REQ bit of the CODEC_REQ register. Slot10 Request: Modem Line2 or PCM Left(n+1) The value of this bit is displayed in the SLOT10_REQ bit of the CODEC_REQ register. Slot11 Request: Handset or PCM Right(n+1) The value of this bit is displayed in the SLOT11_REQ bit of the CODEC_REQ register. Slot12 Request: PCM Center(n+1) The value of this bit is displayed in the SLOT12_REQ bit of the CODEC_REQ register. Unused Function 11 10 9 8 7 6 5 4 3 2 1:0 (10) SDATAIN slot 2: STATUSDATA (Status Data Port) Bit 19:4 Function Control Register Read Data The value of this area is displayed in the RDAT(15:0) area of the CODEC_RD register. Unused 3:0 (11) SDATAIN slot 3: PCML (PCM Record Left Channel) Bit 19:4 Function PCM Record Left Data This area is output to memory due to a DMA for ADC1. Unused 3:0 390 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) (12) SDATAIN slot 4: PCMR (PCM Record Right Channel) Bit 19:4 Function PCM Record Right Data This area is output to memory due to a DMA for ADC2. Unused 3:0 (13) SDATAIN slot 5: LINE1ADC (Optional Modem Line1 ADC) Bit 19:4 Function Optional Modem Line1 ADC Data This area is output to memory due to a DMA for ADC3. Unused 3:0 (14) SDATAIN slot 6: MICADC (Optional Dedicated Microphone Record Data) Bit 19:4 Function Optional Dedicated Microphone Record Data This area is output to memory due to a DMA for ADC1. Unused 3:0 (15) SDATAIN slot 12: IOSTATUS (Optional Modem GPIO Status) Bit 19:0 Function up to 16 GPIO pins The value of this area is displayed in the RSLOT12(19:0) area of the SLOT12_RD register. When 1 is entered in bit 0 (GPIO_INT enabled input pin event interrupt), an interrupt request is generated. User's Manual U14579EJ2V0UM 391 CHAPTER 15 AC97U (AC97 UNIT) 15.7 Data Output to Codec (1) Data output to slot 1 or 2 The following steps <1> and <2> are repeated due to data output to slot 1 or 2. <1> Confirm that the WRDY bit of the CODEC_WR register in the operational registers is 0 (When it is 1, writing is enabled for slots 1 and 2). <2> Write the data to be output by using slot 1 or 2 to the WDAT(15:0) area of the CODEC_WR register in the operational registers. (2) Data output to slot 12 The following steps <1> and <2> are repeated due to data output to slot 12. <1> Confirm that the WRDY_SLOT bit of the SLOT12_WR register in the operational registers is 0 (When it is 1, writing is enabled for slot 12). <2> Write the data to be output by using slot 12 to the WSLOT12(19:0) area of the SLOT12_WR register in the operational registers. (3) Data output to slot 3, 4, or 5 A DMA to the following cache buffers is started for data output to slot 3, 4, or 5. * Slot 3: DAC1 * Slot 4: DAC2 * Slot 5: DAC3 392 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.8 Data Input from Codec (1) Slot 1 data input Data is read due to slot 1 data input by repeating the following steps (a) and (b). (a) Read data according to an interrupt request <1> Valid data is input in slot 1 and an interrupt request is generated (the STSADR bit of the INT_CLR/INT_STATUS register in the operational registers becomes 1). <2> Read the RADDR(6:0) area of the CODEC_RD register in the operational registers. <3> Read bits 9 to 0 of the CODEC_REQ register in the operational registers. (b) Read periodic data <1> Periodically read the CODEC_RD register in the operational registers (when the RRDYA bit is 1, the RADDR(6:0) area is valid). <2> Read bits 9 to 0 of the CODEC_REQ register in the operational registers. (2) Slot 2 data input Data is read due to slot 2 data input by repeating the following steps (a) and (b). (a) Read data according to an interrupt request <1> Valid data is input in slot 2 and an interrupt request is generated (the STSDAT bit of the INT_CLR/INT_STATUS register in the operational registers becomes 1). <2> Read the RDAT(15:0) area of the CODEC_RD register in the operational registers. (b) Read periodic data <1> Periodically read the CODEC_RD register in the operational registers (when the RRDYD bit is 1, the RDAT(15:0) area is valid). Remark The WIP bit of the CODEC_RD register in the operational registers counts the number of times 1 is set (status read) in the RWC bit of the CODEC_WR register in the operational registers. When valid data is input in the CODEC_RD register, this count value is set to -1. When this count value is not zero, the WIP bit becomes 1 (read processing for the CODEC remains). When the count value is 0, the WIP bit becomes 0 (no read processing for the CODEC remains). (3) Slot 12 data input Data is read due to slot 12 data input by repeating the following steps (a) and (b). (a) Read data according to an interrupt request <1> Valid data is input in slot 12 and an interrupt request is generated (the IOSTS bit of the INT_CLR/INT_STATUS register in the operational registers becomes 1). <2> Read the RSLOT12(19:0) area of the SLOT12_RD register in the operational registers. (b) Read periodic data <1> Periodically read the SLOT12_RD register in the operational registers (when the RRDY_SLOT bit is 1, the RSLOT12(19:0) area is valid). User's Manual U14579EJ2V0UM 393 CHAPTER 15 AC97U (AC97 UNIT) (4) Slot 3, 4, 5, or 6 data input A DMA to the following cache buffers is started for slot 3, 4, 5, or 6 data input. * Slot 3: ADC1 * Slot 4: ADC2 * Slot 5: ADC3 * Slot 6: ADC1 Note Note Note The DMAs of the slots 3 and 6 cannot be operated at the same time. 15.9 DMA Transfer (1) Data output to the Codec (slot 3, 4, or 5) The method of outputting data to the Codec (slot 3, 4, or 5) is shown below. <1> Set the base address of the memory to be accessed and the transfer count ((32 bits x 4)/transfer) in the operational registers. Slot Base Address Setting Register DAC1_BADDR DAC2_BADDR DAC3_BADDR Transfer Count Register DAC1L DAC2L DAC3L Area DAC1L(15:0) DAC2L(15:0) DAC3L(15:0) 3 4 5 <2> The DMA operation is started by setting 1 in the DMA start bit in the operational registers. Slot Register 3 4 5 DAC1_CTRL DAC2_CTRL DAC3_CTRL Start Bit Bit DAC1_ENABLE DAC2_ENABLE DAC3_ENABLE <3> Set the following items in the CTRL register in the operational registers to start the transfers with the Codec. * Whether or not to perform converter or filter operation * Conversion rate of data to be output * Enabling of transfers with the Codec Slot Converter Operation Filter Operation Conversion Rate Enabling of Codec Transfer DAC1ENB bit DAC2ENB bit - - - DAC3ENB bit 3 4 5 SRC_CNVT_ON bit SRC_FILTER_ON bit DAC1FORM(2:0) area 394 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) <4> To continue to perform DMA operations, set the next transfer base address and transfer count. <5> When the DMAs have executed the specified number of transfers, an interrupt request is generated and the DMA start bit is automatically cleared to 0. Slot Interrupt Status Bit Register 3 4 5 INT_CLR/INT_STATUS Bit DAC1END DAC2END DAC3END The DMA automatically loads the base address and transfer count and executes the transfer. To end the DMA transfers forcibly, set 0 in the start bit in step <2>. Also, if the next status bit becomes 0, set the Codec transfer enable bit in step <3> to 0. Slot Register 3 4 5 DAC1_CTRL DAC2_CTRL DAC3_CTRL Status Bit Bit DAC1_STATUS DAC2_STATUS DAC3_STATUS * The counters for the base address and transfer count are separate from the registers. The register values are loaded in the counters only when the start bit is set to 1 and the DMA end interrupt request is generated. Therefore, if the next base address and transfer count are set in advance after the start bit was set to 1 or the DMA end interrupt request was generated, DMA operations can be performed continuously by loading the setting values after the DMA that is currently being processed ends. * The correspondence between the DMA transfer count and the Codec transfer count differs according to the following bit settings of the CTRL register in the operational registers. * SRC_CNVT_ON bit: Whether or not to perform converter operation * SRC_FILTER_ON bit: Whether or not to perform filter operation * DAC1FORM(2:0) area: Conversion rate of data to be output User's Manual U14579EJ2V0UM 395 CHAPTER 15 AC97U (AC97 UNIT) The data length that is transferred to the buffer within the AC97U by a single DMA is 32 bits x 4 (= 16 bits x 8). The data that is used in a single transfer with the Codec is 16 bits among these bits. The following table shows the relationship between the CTRL register settings and data transfer counts. SRC_CNVT_ON bit, SRC_FILTER_ON bit SRC_CNVT_ON = 0 and SRC_FILTER_ON = 0 Other combination than above DAC1FORM (2:0) - 000 001 010 011 100 101 110 DMA Transfer Count A (Arbitrary) DAC1 or DAC2 Codec Transfer Count Ax8 Ax8 (A x 48) - 5 (A x 24) - 2 (A x 12) - 1 ((A x 32) - 3) x 147/160 ((A x 16) - 1) x 147/160 (A x 8) x 147/160 DAC3 Codec Transfer Count Ax8 * The address shown below is output as the DMA address. DMA address = (Address set in the operational register) + (0x10 x N) N: DMA transfer count (0, 1, 2, 3,...) The higher 12 bits (bits 31 to 20) are fixed, and the lower 18 bits (bits 19 to 2) vary. Therefore, if a carry occurs in the lower 18 bits, 1 is not added to the higher 12 bits. (2) Data input from the Codec (slot 3, 4, 5, or 6) The method of inputting data from the Codec (slot 3, 4, 5, or 6) is shown below. <1> Set the base address of the memory to be accessed and the transfer count ((32 bits x 4)/transfer) in the operational registers. Slot Base Address Setting Register ADC1_BADDR ADC2_BADDR ADC3_BADDR Transfer Count Register ADC1L ADC2L ADC3L Area ADC1L(15:0) ADC2L(15:0) ADC3L(15:0) 3, 6 4 5 396 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) <2> The DMA operation is started by setting 1 in the DMA start bit in the operational registers. Slot Register 3, 6 4 5 ADC1_CTRL ADC2_CTRL ADC3_CTRL Start Bit Bit ADC1_ENABLE ADC2_ENABLE ADC3_ENABLE <3> Set the following items in the CTRL register in the operational registers. * Whether or not to perform converter or filter operation * Conversion rate of data to be input * Enabling of transfers with the Codec Slot Converter Operation Filter Operation Conversion Rate Enabling of Codec Transfer ADC1ENB bitNote ADC2ENB bit - SRC_CNVT_ON bit - SRC_FILTER_ON bit - ADC1FORM(2:0) area ADC3ENB bit MICENB bitNote 3 4 5 6 SRC_CNVT_ON bit SRC_FILTER_ON bit ADC1FORM(2:0) area Note As the DMAs of the slots 3 and 6 cannot be operated simultaneously, do not set these bits to 1 at the same time. <4> To continue to perform DMA operations, set the next transfer base address and transfer count. <5> When the DMAs end, an interrupt request is generated and the DMA start bit is automatically cleared to 0. Slot Register 3, 6 4 5 INT_CLR/INT_STATUS Interrupt Bit Bit ADC1END ADC2END ADC3END The DMA automatically loads the base address and transfer count and executes the transfer. To end the DMA transfers forcibly, set 0 in the start bit in step <2>. Also, set the Codec transfer enable bit in step <3> to 0. User's Manual U14579EJ2V0UM 397 CHAPTER 15 AC97U (AC97 UNIT) * The counters for the base address and transfer count are separate from the registers. The register values are loaded in the counters only when the start bit is set to 1 and the DMA end interrupt request is generated. Therefore, if the next base address and transfer count are set in advance after the start bit was set to 1 or the DMA end interrupt request was generated, DMA operations can be performed continuously by loading the setting values after the DMA that is currently being processed ends. * The correspondence between the DMA transfer count and the Codec transfer count differs according to the following bit settings of the CTRL register in the operational registers. * SRC_CNVT_ON bit: Whether or not to perform converter operation * SRC_FILTER_ON bit: Whether or not to perform filter operation * ADC1FORM(2:0) area: Conversion rate of data to be input The data length that is transferred from the buffer within the AC97U by a single DMA is 32 bits x 4 (= 16 bits x 8). The data that is used in a single transfer with the Codec is 16 bits among these bits. The following table shows the relationship between the CTRL register settings and data transfer counts. SRC_CNVT_ON bit, SRC_FILTER_ON bit SRC_CNVT_ON = 0 and SRC_FILTER_ON = 0 Other combination than above ADC1FORM (2:0) - 000 001 010 011 100 101 110 DMA Transfer Count A (Arbitrary) ADC1 or ADC2 Codec Transfer Count Ax8 Ax8 (A x 48) - 5 (A x 24) - 2 (A x 12) - 1 ((A x 32) - 3) x 147/160 ((A x 16) - 1) x 147/160 (A x 8) x 147/160 ADC3 Codec Transfer Count Ax8 * The address shown below is output as the DMA address. DMA address = (Address set in the operational register) + (0x10 x N) N: DMA transfer count (0, 1, 2, 3,...) The higher 12 bits (bits 31 to 20) are fixed, and the lower 18 bits (bits 19 to 2) vary. Therefore, if a carry occurs in the lower 18 bits, 1 is not added to the higher 12 bits. 398 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.10 Special Interrupts This section explains bits 8 to 6 of the INT_CLR/INT_STATUS register in the operational registers. (1) Bit 8: ACLINK_CK An interrupt request is generated when there is a clock request from the Codec side during a suspend state. (2) Bit 7: CODECGPI An interrupt request is generated when valid data is input to AC97 input data slot 12 and bit 0 of slot 12 is 1. (3) Bit 6: ACLINK An interrupt request is generated when a loopback transfer is performed and an error occurred. * Loopback transfer Set output data in the SLOT12_WR register in the operational registers and set the LOOP bit to 1 at the same time. The next valid data that is input to the SLOT12_RD register in the operational registers is compared with the output data and an error occurs if they differ. User's Manual U14579EJ2V0UM 399 CHAPTER 15 AC97U (AC97 UNIT) 15.11 AC97U Suspend Transition Procedure The procedure for setting the AC97U to suspend mode is shown below. <1> Issue a power down mode/power save mode command for the Codec. <2> Set the ck_stop_on bit of the ACLINK_CTRL register in the operational registers to 1. <3> Transition to suspend mode. The procedure for canceling the AC97U suspend mode is shown below. The AC97U suspend mode can be canceled from the CPU or canceled due to a request from the Codec. (1) Cancellation from the CPU <1> 1 is set in either the sync_on bit or aclink_rst_on bit of the ACLINK_CTRL register in the operational registers. The SYNC signal or reset_b signal (internal signal) is output and the suspend mode of the ACLink interface is canceled. <2> After confirming that the bit that was set in step <1> has become 0, the next processing is performed for the AC97U. (2) Cancellation due to a request from the Codec <1> An interrupt request is generated (the ACLINK_CK bit of the INT_CLR/INT_STATUS register in the operational registers is set). <2> 1 is set in either the sync_on bit or aclink_rst_on bit of the ACLINK_CTRL register in the operational registers. The SYNC signal or reset_b signal is output and the suspend mode of the AC-Link interface is canceled. <3> After confirming that the bit that was set in step <2> has become 0, the interrupt request of step <1> is cleared (0), and next processing is performed. 400 User's Manual U14579EJ2V0UM CHAPTER 15 AC97U (AC97 UNIT) 15.12 Filter RAM To use the filter function with DMA transfers, the coefficients for the calculation must be set in advance in the filter RAM. The method of setting this RAM is described below. The RAM has two blocks. One is for data output (DAC) and the other is for data input (ADC). One block is 16 bits x 32 levels. (1) Method of setting the data output (DAC) RAM <1> Confirm that the DAC1_ENABLE and DAC1_STATUS bits of the DAC1_CTRL register, the DAC2_ENABLE and DAC2_STATUS bits of the DAC2_CTRL register, and the DAC3_ENABLE and DAC3_STATUS bits of the DAC3_CTRL register in the operational registers are 0. <2> Set 0 in the SRC_RAM_ADR bit of the CTRL register in the operational registers. <3> Write data 32 times in the SRC_RAM_DATA register in the operational registers (internally, the address is automatically incremented and the data is expanded in the 32-level register). (2) Method of setting the data input (ADC) RAM <1> Confirm that the ADC1_ENABLE bit of the ADC1_CTRL register, the ADC2_ENABLE bit of the ADC2_CTRL register, and the ADC3_ENABLE bit of the ADC3_CTRL register in the operational registers are 0. <2> Set 1 in the SRC_RAM_ADR bit of the CTRL register in the operational registers. <3> Write data 32 times in the SRC_RAM_DATA register in the operational registers (internally, the address is automatically incremented and the data is expanded in the 32-level register). (3) RAM data format The RAM data format is shown below. * Bit 15 is a sign bit * The decimal point position is the same position that is used for audio data. Figure 15-14. RAM Data Format Bit number 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Decimal point position A Sign bit Decimal point position B Remark Coefficient range when the decimal point position is A: -1 < X < 1 Coefficient range when the decimal point position is B: -32767 < X < 32767 User's Manual U14579EJ2V0UM 401 APPENDIX A CAUTIONS A.1 Adjusting Skew of PCI Clock If the hold time of the PCLK signal of the VRC4173 (4 ns, refer to PD31173 (VRC4173) Data Sheet) cannot be satisfied, bring forward the rising edge of the PCI clock as illustrated in Figure A-1. Evaluate the PCI clock block. If necessary, insert a circuit that adjusts the skew of PCLK to the PCLK pin of the VRC4173. Figure A-1. Adjusting Skew of PCI Clock (a) Clock skew PCLK (Output from VR4122, etc.) PCLK (Input to VRC4173) Clock brought forward (b) Adjusting skew VRC4173 VR4122 Skew adjustment circuit PCLK Delay PCLK 402 User's Manual U14579EJ2V0UM APPENDIX B RESTRICTIONS Version 3.1 of the VRC4173 has the following restrictions. Consult NEC for the restrictions on products other than version 3.1. B.1 B.1.1 Noise During Operation of AC97 Phenomenon If playback or recording is performed with the AC97U, noise is superimposed on the sound. The AC97U uses an external AC97 Codec via an AC-Link. Because the AC-Link handles audio data at a rate of 48 kHz, the rate must be converted during recording or playback. In the case of playback, for example, the frequency of the AC-Link is 48 kHz where the sampling rate is 8, 16, 32, 11, 22, or 44 kHz, so the rate must be converted as shown in Figure B-1. Figure B-1. Rate Conversion VRC4173 AC-Link AC97 Codec 11 kHz 22 kHz 44 kHz 48 kHz 48 kHz 8/16/32/11/22/44 kHz DAC 8 kHz 16 kHz 32 kHz The VRC4173 simply converts this rate (i.e., simply arranges 44 kHz data when the rate is converted into 48 kHz and interpolates the insufficient part with the adjacent data by means of linear approximation). If the frequency component of the data string changes, therefore, the waveform is distorted by the interpolating data newly created, and thus noise is generated. B.1.2 Preventive measures Modify the hardware and software as follows. * Hardware: Slightly lower the frequency of the oscillator connected to the AC97 Codec so that the transfer frequency of the AC-Link is 44.1 kHz. By this method, however, the AC97 Codec may be used out of its specifications. * Software: Modify the driver software of the AC97 block of the VRC4173 to implement rate conversion between the sampling frequency (8, 16, 32, 11, 22, or 44 kHz) and AC-Link transfer rate, and FIR filtering during recording, using software. User's Manual U14579EJ2V0UM 403 APPENDIX B RESTRICTIONS B.2 B.2.1 Erroneous Recognition of PC Card Phenomenon The CEn1#, CEn2#, and OEn# pins output a low level for about 10 ms after the power supply to the card has been turned on (the supply voltage is set by the VCC(1:0) and VPP(1:0) areas of the PWR_CNT register). Some CF cards that quickly clear a power-on reset recognize this as a request for IDE mode by mistake, and enter the IDE mode. As a result, the VRC4173 cannot recognize the card. Figure B-2 shows the statuses of the CEn1#, CEn2#, and OEn# signals when the PC card is initialized. Remark n = 1, 2 Figure B-2. Initializing PC Card Card power supply rise time Vcc Card power supply 0V Approx. 10 ms CEn1#, CEn2#, OEn# (Output) <1> Wait 1 <2> Wait 2 <3> Note Note The VRC4173 outputs a high-impedance state which is pulled up in the PC card to the high level. Remarks 1. The numbers in the figure indicate the following operations. <1> Clear the CARD_OUT_EN bit of the PWR_CNT register to 0. <2> Set the VCC(1:0) area of the PWR_CNT register (on power application). <3> Clear the CARD_REST0 bit of the INT_GEN_CNT register to 0 and set the CARD_OUT_EN bit of the PWR_CNT register to 1. 2. The dotted line indicates the high-impedance state. 3. n = 1, 2 404 User's Manual U14579EJ2V0UM APPENDIX B RESTRICTIONS B.2.2 Preventive measures The CF card can be prevented from entering the IDE mode by adding the external circuit shown in Figure B-3. Figure B-3. Example of Circuit Preventing Shift to IDE Mode GPIO VRC4173 Note Card power supply CF card Note CEn1#, CEn2#, and OEn# pins (n = 1, 2) Insert a buffer with a high-impedance control pin between the CEn1#, CEn2#, and OEn# pins, and the card socket, and pull up the buffer output to the card power supply (n = 1, 2). Connect the high-impedance control pin to the GPIO pin of the VR4122 or VRC4173. The GPIO pin controls the buffer so that it goes into a high-impedance state from when pull-out of the card is detected until driving the card control signal is started (by the CARD_OUT_EN bit of the PWR_CNT register). User's Manual U14579EJ2V0UM 405 APPENDIX B RESTRICTIONS B.3 B.3.1 Pulling up PC Card Pins Phenomenon The C1A(22:20), C1A(15:14), WP1, C2A(22:20), C2A(15:14), and WP2 pins are always high when the power supply to the card is off. This is because the C1A(22:20), C1A(15:14), WP1, C2A(22:20), C2A(15:14), and WP2 pins are pulled up by an internal 50 k pull-up resistor of the VRC4173. B.3.2 Preventive measures Although only a tiny amount of current flows into these pins when the power supply to the card is off, if any adverse influence is expected, insert a diode between these pins and the card power supply to drop the level of the card pins to close to 0 V. Figure B-4 shows an example of inserting a diode. Figure B-4. Example of Inserting Diode Card power supply VRC4173 Note CF card Note C1A(22:20), C1A(15:14), WP1, C2A(22:20), C2A(15:14), and WP2 pins 406 User's Manual U14579EJ2V0UM APPENDIX B RESTRICTIONS B.4 B.4.1 Incorrect Playback with AIU Phenomenon If recording and playback are simultaneously performed with the AIU, illegal data may be output during playback and thus playback may not be correctly executed. B.4.2 Preventive measures (1) Do not set the AIUMEN and AIUSEN bits of the SEQREG register to 1 at the same time. (2) Recording and playback can be performed simultaneously by using an interrupt and I/O read by the CPU as a substitute for DMA, without using recording DMA. The sequence used to set the registers for performing recording and playback simultaneously is shown below. <1> Set a DMA address. <2> DMAMSKREG register of DCU = 0x0004 Recording DMA = Disabled, Playback DMA = Enabled <3> Unmask interrupts. <4> Set registers related to AIU recording. <5> Set registers related to AIU playback. <6> SEQREG register of AIU = 0x0011 Start the recording/playback sequencer. <7> The MIC input receive complete interrupt request occurs (MSTINTR bit of the INTREG register of AIU = 1). <8> Read the DVALIDREG register of AIU. Check to see whether valid data is stored in the MDMADATREG register of AIU. <9> Read the MDMADATREG register of AIU. Receive the recording data. <10> Write data to the DVALIDREG register and clear the MDMAV bit to 0. <11> Clear the MIC input receive complete interrupt request. Other processing can be performed until the next MIC input receive complete interrupt request occurs. User's Manual U14579EJ2V0UM 407 APPENDIX C INDEX A A/D converter unit .................................................... 27 A/D port scan ......................................................... 149 AC97U ............................................................. 27, 336 AC97U operational registers ............................ 43, 346 AC97U PCI configuration registers .................. 42, 336 AC97 unit ......................................................... 27, 336 AC-Link interface data transfer format ................... 386 ACLINK_CTRL....................................................... 356 ADC1_BADDR ....................................................... 372 ADC1_CTRL .......................................................... 370 ADC1L ................................................................... 371 ADC2_BADDR ....................................................... 375 ADC2_CTRL .......................................................... 373 ADC2L ................................................................... 374 ADC3_BADDR ....................................................... 378 ADC3_CTRL .......................................................... 376 ADC3L ................................................................... 377 Adjusting skew of PCI clock................................... 402 ADR_WIN_EN........................................................ 232 ADU ......................................................................... 27 AIU ................................................................... 27, 152 AIU IN DMA address registers ................................. 78 AIU IN DMA base address registers ........................ 77 AIU OUT DMA address registers ............................. 80 AIU OUT DMA base address registers .................... 79 AIU registers .................................................... 33, 152 AIUIAHREG ............................................................. 78 AIUIALREG .............................................................. 78 AIUIBAHREG ........................................................... 77 AIUIBALREG............................................................ 77 AIUINTREG.............................................................. 97 AIUOAHREG............................................................ 80 AIUOALREG ............................................................ 80 AIUOBAHREG ......................................................... 79 AIUOBALREG.......................................................... 79 Audio interface unit .......................................... 27, 152 BIST......................................................... 69, 195, 341 BRGCNT ............................................................... 208 Bulk transfers......................................................... 317 Bus control unit.................................................. 26, 64 Bus topology.......................................................... 316 BUSCNT.................................................................. 73 C CACHELS................................................ 68, 194, 340 CAP ....................................................................... 196 CAPID.................................................................... 217 CARD_SC ............................................................. 230 CARD_SCI ............................................................ 231 CardBus socket registers ................................ 39, 258 CARDNUM ............................................................ 198 CARDU configuration registers ....................... 35, 188 CARDU1.......................................................... 27, 187 CARDU2.......................................................... 27, 187 CHIPCNT............................................................... 216 CLASSC .................................................. 68, 194, 340 Clock mask unit ................................................. 27, 86 Clock oscillator ........................................................ 62 CLT........................................................................ 199 CMU .................................................................. 27, 86 CMU registers.................................................... 30, 87 CMUCLKMSK.......................................................... 87 CMUSRST ............................................................... 89 CODEC_RD........................................................... 350 CODEC_REQ ........................................................ 351 CODEC_WR.......................................................... 349 Command register ................................................. 277 Control transfers .................................................... 317 Coordinate detection ............................................. 127 CSRBADR ............................................................. 196 CTRL ..................................................................... 354 D DAC1_BADDR....................................................... 363 DAC1_CTRL.......................................................... 361 DAC1L ................................................................... 362 DAC2_BADDR....................................................... 366 DAC2_CTRL.......................................................... 364 DAC2L ................................................................... 365 DAC3_BADDR....................................................... 369 DAC3_CTRL.......................................................... 367 B BADR ....................................................................... 70 Base address register ............................................ 279 BASEADR .............................................................. 342 BCU ................................................................... 26, 64 BCU configuration registers ............................... 29, 64 408 User's Manual U14579EJ2V0UM APPENDIX C INDEX DAC3L ................................................................... 368 DATA ..................................................................... 220 Data lost................................................................. 150 DCU ................................................................... 27, 81 DCU registers .................................................... 30, 81 DEVCNT ................................................................ 213 DID........................................................... 65, 190, 337 DMA address unit .............................................. 27, 75 DMA control unit ................................................ 27, 81 DMA priority ............................................................. 81 DMA space .............................................................. 75 DMA transfer.......................................................... 394 DMAAU .............................................................. 27, 75 DMAAU registers ............................................... 30, 76 DMAIDLEREG ......................................................... 82 DMAMSKREG ......................................................... 84 DMAREQREG ......................................................... 85 DMARSTREG .......................................................... 82 DMASENREG.......................................................... 83 DVALIDREG .......................................................... 160 GIUINTSTATL ........................................................113 GIUINTTYPH..........................................................117 GIUINTTYPL ..........................................................116 GIULINTREG ...........................................................99 GIUPIODH..............................................................112 GIUPIODL ..............................................................111 GLO_CNT ..............................................................241 H HC state transitions ................................................329 HcBulkCurrentED ...................................................299 HcBulkHeadED ......................................................298 HCCA .....................................................................327 HcCommandStatus ................................................286 HcControl ...............................................................284 HcControlCurrentED ..............................................297 HcControlHeadED..................................................296 HcDoneHead..........................................................300 HcFmInterval ..........................................................301 HcFmNumber .........................................................303 HcFmRemaining.....................................................302 HcHCCA.................................................................294 HcInterruptDisable..................................................292 HcInterruptEnable ..................................................290 HcInterruptStatus ...................................................288 HcLSThreshold.......................................................305 HcPeriodCurrentED................................................295 HcPeriodicStart ......................................................304 HcRevision .............................................................283 HcRhDescriptorA....................................................306 HcRhDescriptorB....................................................308 HcRhPortStatus1, 2................................................312 HcRhStatus ............................................................310 HEDT........................................................69, 195, 341 Host control operational registers ....................41, 282 Host controller ........................................................318 Host Controller Communication Area.....................327 E ED.......................................................................... 321 Endpoint Descriptor ............................................... 321 ExCA extended registers ................................. 39, 225 ExCA registers......................................... 37, 221, 223 EXROMADR .......................................................... 344 EXT_DATA ............................................................ 246 EXT_INDX ............................................................. 245 F Filter RAM.............................................................. 401 G GEN_CNT.............................................................. 238 General-purpose I/O unit ................................. 27, 107 GIU .................................................................. 27, 107 GIU registers.................................................... 31, 108 GIUDIRH................................................................ 110 GIUDIRL ................................................................ 109 GIUHINTREG .......................................................... 99 GIUINTALSELH ..................................................... 119 GIUINTALSELL...................................................... 118 GIUINTENH ........................................................... 115 GIUINTENL............................................................ 115 GIUINTHTSELH..................................................... 121 GIUINTHTSELL ..................................................... 120 GIUINTSTATH ....................................................... 114 I ICU .....................................................................27, 90 ICU registers ......................................................31, 93 ID_REV ..................................................................226 IDSELNUM...............................................................74 IF_STATUS ............................................................227 INT_CLR/INT_STATUS..........................................347 INT_GEN_CNT ......................................................229 INT_MASK .............................................................359 Internal block configuration ......................................26 User's Manual U14579EJ2V0UM 409 APPENDIX C INDEX Interrupt control outline diagram .............................. 91 Interrupt control unit ........................................... 27, 90 Interrupt source........................................................ 92 Interrupt transfers................................................... 317 INTL ......................................................... 72, 207, 344 INTP......................................................... 72, 208, 345 INTREG.................................................................. 162 IO_CMD_TIM ......................................................... 252 IO_HOLD_TIM ....................................................... 252 IO_SETUP_TIM ..................................................... 251 IO_WIN_CNT ......................................................... 233 IO_WIN0_EAH ....................................................... 234 IO_WIN0_EAL........................................................ 234 IO_WIN0_OAH....................................................... 248 IO_WIN0_OAL ....................................................... 248 IO_WIN0_SAH ....................................................... 234 IO_WIN0_SAL........................................................ 233 IO_WIN1_EAH ....................................................... 236 IO_WIN1_EAL........................................................ 235 IO_WIN1_OAH....................................................... 249 IO_WIN1_OAL ....................................................... 249 IO_WIN1_SAH ....................................................... 235 IO_WIN1_SAL........................................................ 235 IOB0....................................................................... 204 IOB1....................................................................... 206 IOL0 ....................................................................... 205 IOL1 ....................................................................... 207 Isochronous transfers ............................................ 317 MEM_TIM_SEL1 ................................................... 256 MEM_TIM_SEL2 ................................................... 256 MEM_WIN_PWEN................................................. 257 MEM_WIN0_EAH .................................................. 237 MEM_WIN0_EAL................................................... 237 MEM_WIN0_OAH.................................................. 238 MEM_WIN0_OAL .................................................. 237 MEM_WIN0_SAH .................................................. 236 MEM_WIN0_SAL................................................... 236 MEM_WIN0_SAU .................................................. 249 MEM_WIN1_EAH .................................................. 240 MEM_WIN1_EAL................................................... 239 MEM_WIN1_OAH.................................................. 240 MEM_WIN1_OAL .................................................. 240 MEM_WIN1_SAH .................................................. 239 MEM_WIN1_SAL................................................... 239 MEM_WIN1_SAU .................................................. 250 MEM_WIN2_EAH .................................................. 242 MEM_WIN2_EAL................................................... 242 MEM_WIN2_OAH.................................................. 243 MEM_WIN2_OAL .................................................. 243 MEM_WIN2_SAH .................................................. 242 MEM_WIN2_SAL................................................... 241 MEM_WIN2_SAU .................................................. 250 MEM_WIN3_EAH .................................................. 244 MEM_WIN3_EAL................................................... 244 MEM_WIN3_OAH.................................................. 245 MEM_WIN3_OAL .................................................. 245 MEM_WIN3_SAH .................................................. 244 MEM_WIN3_SAL................................................... 243 MEM_WIN3_SAU .................................................. 250 MEM_WIN4_EAH .................................................. 247 MEM_WIN4_EAL................................................... 247 MEM_WIN4_OAH.................................................. 248 MEM_WIN4_OAL .................................................. 247 MEM_WIN4_SAH .................................................. 246 MEM_WIN4_SAL................................................... 246 MEM_WIN4_SAU .................................................. 251 MEM0_CMD_TIM .................................................. 253 MEM0_HOLD_TIM ................................................ 254 MEM0_SETUP_TIM .............................................. 253 MEM1_CMD_TIM .................................................. 255 MEM1_HOLD_TIM ................................................ 255 MEM1_SETUP_TIM .............................................. 254 MEMB0.................................................................. 200 MEMB1.................................................................. 202 MEML0 .................................................................. 201 MEML1 .................................................................. 203 K Keyboard interface unit .................................... 27, 166 KIU ................................................................... 27, 166 KIU registers .................................................... 33, 166 KIUDATn ................................................................ 167 KIUINT ................................................................... 176 KIUINTREG.............................................................. 98 KIURST .................................................................. 177 KIUSCANREP........................................................ 169 KIUSCANS............................................................. 171 KIUWKI .................................................................. 175 KIUWKS ................................................................. 173 M MAIUINTREG......................................................... 103 MAX_LAT......................................................... 73, 345 MCNTREG ............................................................. 158 MCNVRREG .......................................................... 159 MDMADATREG ..................................................... 153 410 User's Manual U14579EJ2V0UM APPENDIX C INDEX MGIUHINTREG ..................................................... 105 MGIULINTREG ...................................................... 105 MIC ........................................................................ 165 MIDATREG ............................................................ 157 MIN_GNT......................................................... 72, 345 MKIUINTREG ........................................................ 104 MLT.......................................................... 69, 195, 341 MPIUINTREG ........................................................ 102 MSYSINT1REG ..................................................... 100 PS2CH1RST ..........................................................185 PS2CH2 registers.............................................34, 182 PS2CH2CTRL ........................................................184 PS2CH2DATA........................................................183 PS2CH2RST ..........................................................185 PS2U ................................................................27, 182 PWR_CNT..............................................................228 R RID ...........................................................68, 194, 340 N NIP......................................................................... 217 S Sample rate converter ............................................383 Scan sequencer .............................................128, 129 SCANLINE .............................................................178 SCNTREG..............................................................155 SCNVRREG ...........................................................156 SDMADATREG ......................................................153 SECSTS .................................................................197 SELECTREG..........................................................123 SEQREG ................................................................161 SERRDIS ...............................................................216 SKDMA0.................................................................214 SKDMA1.................................................................215 SKT_CNT ...............................................................266 SKT_EV..................................................................259 SKT_FORCE_EV ...................................................264 SKT_MASK ............................................................261 SKT_PRE_STATE .................................................262 SLOT12_RD...........................................................353 SLOT12_WR ..........................................................352 SODATREG ...........................................................154 Speaker ..................................................................163 Special interrupts ...................................................399 SRC........................................................................383 SRC_RAM_DATA ..................................................358 Status register ........................................................278 SUBBNUM .............................................................198 SUBID ......................................................71, 210, 343 SUBVID ............................................................71, 210 SVID .......................................................................343 SYSCNT.................................................................212 SYSINT1REG...........................................................94 O Operational registers ............................................. 282 P PC card units ................................................... 27, 187 PC16BADR ............................................................ 211 PCI bridge................................................................ 26 PCI device configuration.......................................... 28 PCIBNUM .............................................................. 198 PCICMD................................................... 66, 191, 338 PCISTS.................................................... 67, 193, 339 PIB bridge ................................................................ 26 Pin configuration ...................................................... 44 Pin functions ............................................................ 44 Pin status ................................................................. 58 PIU................................................................... 27, 125 PIU registers .................................................... 32, 131 PIUABnREG .......................................................... 144 PIUAMSKREG ....................................................... 141 PIUASCNREG ....................................................... 139 PIUCIVLREG ......................................................... 142 PIUCMDREG ......................................................... 138 PIUCNTREG.......................................................... 132 PIUINTREG ..................................................... 96, 135 PIUPBnmREG ....................................................... 143 PIUSIVLREG ......................................................... 136 PIUSTBLREG ........................................................ 137 PMC....................................................................... 218 PMCSR .................................................................. 219 PMCSR_BSE......................................................... 219 Power management register.................................. 280 PS/2 unit .......................................................... 27, 182 PS2CH1 registers ............................................ 34, 182 PS2CH1CTRL........................................................ 184 PS2CH1DATA ....................................................... 183 T TD...........................................................................323 TEST ......................................................................220 Touch panel ...........................................................127 User's Manual U14579EJ2V0UM 411 APPENDIX C INDEX Touch panel interface controller............................. 128 Touch panel interface unit................................ 27, 125 Touch/release detection......................................... 149 Transfer Descriptor ................................................ 323 U Universal serial bus unit................................... 27, 274 USB host control configuration registers................................................ 40, 275, 276 USB host control configuration space.................... 275 USBU ............................................................... 27, 274 V VID ........................................................... 65, 190, 337 412 User's Manual U14579EJ2V0UM Facsimile Message From: Name Company Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. Tel. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: +1-800-729-9288 +1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Market Communication Dept. Fax: +82-2-528-4411 Fax: +49-211-6503-274 South America NEC do Brasil S.A. Fax: +55-11-6462-6829 Taiwan NEC Electronics Taiwan Ltd. Fax: +886-2-2719-5951 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-250-3583 Japan NEC Semiconductor Technical Hotline Fax: +81- 44-435-9608 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Clarity Technical Accuracy Organization CS 01.11 Excellent Good Acceptable Poor |
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