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High Voltage, Differential 18-Bit ADC Driver ADA4922-1
FEATURES
Single-ended-to-differential conversion Low distortion (VO, dm = 40 V p-p) -99 dBc HD at 100 kHz Low differential output referred noise: 12 nV/Hz High input impedance: 11 M Fixed gain of 2 No external gain components required Low output-referred offset voltage: 1.1 mV max Low input bias current: 3.5 A max Wide supply range 5 V to 26 V Can produce differential output signals in excess of 40 V p-p High speed 38 MHz, -3 dB bandwidth @ 0.2 V p-p differential output Fast settling time 200 ns to 0.01% for 12 V step on 5 V supplies Disable feature Available in space-saving, thermally enhanced packages 3 mm x 3 mm LFCSP 8-lead SOIC_EP Low supply current: IS = 10 mA on 12 V supplies
FUNCTIONAL BLOCK DIAGRAM
ADA4922-1
NC
1 8
IN
REF
2
7
DIS
VS+
3
6
VS-
OUT+
4
5
OUT-
05681-001
NC = NO CONNECT
Figure 1.
-84 -87 -90 -93 RL = 2k SECOND HARMONIC THIRD HARMONIC
DISTORTION (dBc)
-96 -99 -102 -105 -108 -111
VS = 5V, VO, dm = 12V p-p
High voltage data acquisition systems Industrial instrumentation Spectrum analysis ATE Medical instruments
-117 -120 1 10
VS = 12V, VO, dm = 40V p-p 100
FREQUENCY (kHz)
Figure 2. Harmonic Distortion for Various Power Supplies
GENERAL DESCRIPTION
The ADA4922-1 is a differential driver for 16-bit to 18-bit ADCs that have differential input ranges up to 20 V. Configured as an easy-to-use, single-ended-to-differential amplifier, the ADA4922-1 requires no external components to drive ADCs. The ADA4922-1 provides essential benefits such as low distortion and high SNR that are required for driving ADCs with resolutions up to 18 bits. With a wide supply voltage range (5 V to 26 V), high input impedance, and fixed differential gain of 2, the ADA4922-1 is designed to drive ADCs found to in a variety of applications, including industrial instrumentation. The ADA4922-1 is manufactured on ADI's proprietary secondgeneration XFCB process that enables the amplifier to achieve excellent noise and distortion performance on high supply voltages. The ADA4922-1 is available in an 8-lead 3 mm x 3 mm LFCSP as well as an 8-lead SOIC package. Both packages are equipped with an exposed paddle for more efficient heat transfer. The ADA4922-1 is rated to work over the extended industrial temperature range, -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05681-012
APPLICATIONS
-114
ADA4922-1 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 14 Applications..................................................................................... 16 ADA4922-1 Differential Output Noise Model .......................... 16 Using the REF Pin ...................................................................... 16 Internal Feedback Network Power Dissipation...................... 17 Disable Feature ........................................................................... 17 Driving a Differential Input ADC............................................ 17 Printed Circuit Board Layout Considerations ....................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20
REVISION HISTORY
10/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADA4922-1 SPECIFICATIONS
VS = 12 V, TA = 25C, RL = 1 k, DIS = HIGH, CL = 3 pF, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Overdrive Recovery Time Slew Rate Settling Time to 0.01% NOISE/DISTORTION PERFORMANCE Harmonic Distortion Differential Output Voltage Noise Input Current Noise DC PERFORMANCE Differential Output Offset Voltage Differential Output Offset Voltage Drift Input Bias Current Gain Gain Error Gain Error Drift INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing DC Output Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Power Supply Rejection Ratio (PSRR) -PSRR +PSRR DISABLE DIS Input Voltage Threshold Turn-Off Time Turn-On Time DIS Bias Current Enabled Disabled Conditions G = +2, VO = 0.2 V p-p, differential G = +2, VO = 40 V p-p, differential VS+ + 0.5 V to VS- - 0.5 V; +Recovery/-Recovery VO, dm = 2 V step VO, dm = 40 V step VO, dm = 40 V step fC = 5 kHz, VO = 40 V p-p, RL = 2 k, HD2/HD3 fC = 100 kHz, VO = 40 V p-p, RL = 2 k, HD2/HD3 f = 100 kHz f = 100 kHz Min 34 6.5 Typ 38 7.2 180/330 260 730 580 -116/-109 -99/-100 12 1.4 0.35 14 1.8 2 -0.05 0.0002 11 1 10.7 Each single-ended output, RL = 1 k 30% overshoot 5 9.4 1.5 -89 -91 Disabled Enabled -11 -9 160 78 114 -125 10.65 10.7 40 20 26 10.1 2.0 -80 -83 1.1 3.5 Max Unit MHz MHz ns V/s V/s ns dBc dBc nV/Hz pA/Hz mV V/C A V/V % %/C M pF V V mA pF V mA mA dB dB V V s ns A A
DIS = -9 V DIS = -11 V
Rev. 0 | Page 3 of 20
ADA4922-1
VS = 5 V, TA = 25C, RL = 1 k, DIS = HIGH, CL = 3 pF, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Overdrive Recovery Time Slew Rate Settling Time to 0.01% NOISE/DISTORTION PERFORMANCE Harmonic Distortion Differential Output Voltage Noise Input Current Noise DC PERFORMANCE Differential Output Offset Voltage Differential Output Offset Voltage Drift Input Bias Current Gain Gain Error Gain Error Drift INPUT CHARACTERISTICS Input Resistance Input Capacitance Input Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing DC Output Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Quiescent Current (Disabled) Power Supply Rejection Ratio (PSRR) -PSRR +PSRR DISABLE DIS Input Voltage Turn-Off Time Turn-On Time DIS Bias Current Enabled Disabled Conditions G = +2, VO = 0.2 V p-p, differential G = +2, VO = 12 V p-p, differential +Recovery/-Recovery VO, dm = 2 V step VO, dm = 12 V step VO, dm = 12 V step fC = 5 kHz, VO = 12 V p-p, RL = 2 k, HD2/HD3 fC = 100 kHz, VO = 12 V p-p, RL = 2 k, HD2/HD3 f = 100 kHz f = 100 kHz Min 36 6.5 Typ 40.5 13.5 200/670 220 350 200 -102/-108 -101/-98 12 1.4 0.4 12 2.0 2 -0.05 0.0002 11 1 3.6 Each single-ended output, RL = 1 k 30% overshoot 5 7.0 0.7 -93 -91 Disabled Enabled -4 -2 160 78 41 49 3.55 3.6 40 20 26 7.6 1.6 -82 -83 1.2 3.5 Max Unit MHz MHz ns V/s V/s ns dBc dBc nV/Hz pA/Hz mV V/C A V/V % %/C M pF V V mA pF V mA mA dB dB V V s ns A A
DIS = -2 V DIS = -4 V
Rev. 0 | Page 4 of 20
ADA4922-1 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 26 V See Figure 3 -65C to +125C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. The power dissipated due to all of the loads is equal to the sum of the power dissipation due to each individual load. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface that is thermally connected to a copper plane to achieve the specified JA. Figure 3 shows the maximum safe power dissipation in the packages vs. the ambient temperature for the 8-lead SOIC (79C/W) and for the 8-lead LFCSP (81C/W) on a JEDEC standard 4-layer board, each with its underside paddle soldered to a pad that is thermally connected to a PCB plane. JA values are approximations.
3.0
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the PCB surface that is thermally connected to a copper plane, with zero airflow. Table 4. Thermal Resistance
Package Type 8-Lead SOIC with EP on 4-layer board 8-Lead LFCSP with EP on 4-layer board JA 79 81 JC 25 17 Unit C/W C/W
MAXIMUM POWER DISSIPATION (W)
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4922-1 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4922-1. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices potentially causing failure.
2.5 SOIC 2.0 LFCSP 1.5
1.0
0.5
05681-041
0 -40
-20
0
20
40
60
80
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADA4922-1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADA4922-1
NC
1 8
IN
REF
2
7
DIS
VS+
3
6
VS-
OUT+
4
5
OUT-
05681-001
NC = NO CONNECT
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic NC REF VS+ OUT+ OUT- VS- DIS IN Description No Internal Connection Reference Voltage for Single-Ended Input Signal Positive Power Supply Noninverting Side of Differential Output Inverting Side of Differential Output Negative Power Supply Disable Single-Ended Signal Input
Rev. 0 | Page 6 of 20
ADA4922-1 TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, VS = 12 V, RL, dm = 1 k, REF = 0 V, DIS = HIGH, TA = 25C.
3 VO, dm = 0.2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB) NORMALIZED CLOSED-LOOP GAIN (dB)
3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 10 FREQUENCY (MHz) 100
05681-016
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 10 100 FREQUENCY (MHz)
05681-013
VS = 5V, VO, dm = 12V p-p
VS = 5V
VS = 12V
VS = 12V, VO, dm = 40V p-p
1000
Figure 5. Small Signal Frequency Response for Various Power Supplies
3 VO, dm = 0.2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 8. Large Signal Frequency Response for Various Power Supplies
3
NORMALIZED CLOSED-LOOP GAIN (dB)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 VS = 12V @ +85C VS = 5V @ +85C VS = 12V @ +25C VS = 5V @ +25C VS = 12V @ -40C VS = 5V @ -40C 10 100
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 (ALL VOLTAGES ARE VO, dm) 40V p-p +85C 40V p-p +25C 40V p-p -40C 12V p-p +85C 12V p-p +25C 12V p-p -40C 10 FREQUENCY (MHz) VO, dm = 12V p-p (VS = 5V) VO, dm = 40V p-p (VS = 12V)
05681-014
1000
100
FREQUENCY (MHz)
Figure 6. Small Signal Frequency Response for Various Temperatures and Supplies
3
NORMALIZED CLOSED-LOOP GAIN (dB)
Figure 9. Large Signal Frequency Response at Various Temperatures and Supplies
3
NORMALIZED CLOSED-LOOP GAIN (dB)
VO, dm = 0.2V p-p
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 10 100 FREQUENCY (MHz) VS = 12V RL, dm = 1k VS = 5V RL, dm = 1k VS = 12V RL, dm = 500 VS = 5V RL, dm = 500
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 VS = 12V, RL, dm = 1k VS = 5V, RL, dm = 1k VS = 12V, RL, dm = 500 VS = 5V, RL, dm = 500 10 FREQUENCY (MHz) VO, dm = 12V p-p (VS = 5V) VO, dm = 40V p-p (VS = 12V)
05681-015
1000
100
Figure 7. Small Signal Frequency Response for Various Resistive Loads and Supplies
Figure 10. Large Signal Frequency Response for Various Resistive Loads and Supplies
Rev. 0 | Page 7 of 20
05681-018
05681-017
ADA4922-1
3
NORMALIZED CLOSED-LOOP GAIN (dB)
VO, dm = 0.2V p-p
NORMALIZED CLOSED-LOOP GAIN (dB)
3 0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 VS = 5V, VIN = 12V p-p, CL, dm = 0pF VS = 12V, VIN = 40V p-p, CL, dm = 0pF VS = 5V, VIN = 12V p-p, CL, dm = 20pF VS = 12V, VIN = 40V p-p, CL, dm = 20pF 10 FREQUENCY (MHz)
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 VS = 5V, CL, dm = 10pF VS = 5V, CL, dm = 20pF VS = 12V, CL, dm = 0pF VS = 12V, CL, dm = 20pF 10 100
05681-019
1000
100
FREQUENCY (MHz)
Figure 11. Small Signal Frequency Response for Various Capacitive Loads
3 0 -3
NORMALIZED GAIN (dB)
Figure 14. Large Signal Frequency Response for Various Capacitive Loads
3 0 -3
NORMALIZED GAIN (dB)
-6 -9 -12 -15 -18 -21 -24 10V p-p -27 12V p-p 16V p-p 2V p-p
0.2V p-p
-6 -9 10V p-p -12 -15 -18 -21 40V p-p -24 -27 2V p-p
05681-023
0.2V p-p
20V p-p
-30 -33 1 10 100 FREQUENCY (MHz)
05681-020
-30 -33 1 10 100 FREQUENCY (MHz)
1000
1000
Figure 12. Frequency Response for Various Output Amplitudes, VS = 5 V
-50 -60 -70
ISOLATION (dB)
Figure 15. Frequency Response for Various Output Amplitudes, VS = 12 V
3
NORMALIZED CLOSED-LOOP GAIN (dB)
VIN = 0.1V p-p DIS = LOW
VREF = 0.1V p-p
0 -3 -6 -9 -12 -15 -18 -21 -24 -27 -30 1 10 100 FREQUENCY (MHz)
05681-024
VS = 5V
VS = 12V -80 -90 -100 -110 -120 1 10 FREQUENCY (MHz) 100
VS = 12V
VS 5V
05681-011
1000
1000
Figure 13. Isolation vs. Frequency--Disabled
Figure 16. REF Small Signal Frequency Response for Various Power Supplies
Rev. 0 | Page 8 of 20
05681-050
ADA4922-1
-84 -87 -90 -93
DISTORTION (dBc) DISTORTION (dBc)
-84 RL = 2k SECOND HARMONIC THIRD HARMONIC -87 -90 -93 VS = 5V, VO, dm = 12V p-p -96 -99 -102 -105 -108 -111 -114
05681-012 05681-022
VS = 12V VO, dm = 40V p-p
SECOND HARMONIC THIRD HARMONIC
-96 -99 -102 -105 -108 -111 -114 -117 -120
RL = 600
RL = 1k
VS = 12V, VO, dm = 40V p-p 1 10 FREQUENCY (kHz) 100
-117 -120
RL = 2k 1 10 FREQUENCY (kHz) 100
Figure 17. Harmonic Distortion for Various Power Supplies
-60 RL = 2k -70 -80
DISTORTION (dBc)
Figure 20. Harmonic Distortion for Various Loads
100
SECOND HARMONIC THIRD HARMONIC 10
-90 -100 -110 -120
VS = 5V
IMPEDANCE ()
VON VS = 5V 1 VON VS = 12V
0.1
05681-021
VOP VS = 5V VOP VS = 12V
05681-030
-130 VS = 12V -140 2 7 12 17 22 27 32 37 42 47 OUTPUT AMPLITUDE (V p-p)
0.01 0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Output Amplitude and Supply Voltage (f =10 kHz)
0 -10 -20 -30
PSRR (dB)
Figure 21. Single-Ended Output Impedance vs. Frequency and Supplies
-40 -50 -60 -PSRR -70 -80 -90 -100 0.001 0.01 0.1 1 10
05681-025
+PSRR
100
FREQUENCY (MHz)
Figure 19. PSRR vs. Frequency
Rev. 0 | Page 9 of 20
ADA4922-1
DIFFERENTIAL VOLTAGE NOISE (RTO) (nV/ Hz)
100 90 80 70 60 50 40 30 20
05681-032
50 45
INPUT CURRENT NOISE (pA/Hz)
40 35 30 25 20 15 10 5 0 1 10 100 1k 10k 100k 1M FREQUENCY (Hz)
05681-026
10 0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
100M
Figure 22. Differential Output Noise vs. Frequency
22
20ns/DIV
Figure 25. Input Current Noise vs. Frequency
0.12 0.10 0.08
VS = 5V VS = 12V
18 14
OUTPUT VOLTAGE (V)
CL = 20pF VOUT = 40V p-p
OUTPUT VOLTAGE (V)
0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08
05681-033
10 6 2 -2 -6 -10 -14 -18 -22 TIME (s)
05681-027 05681-040
100ns/DIV
-0.10 -0.12
Figure 23. Small Signal Transient Response for Various Power Supplies
Figure 26. Large Signal Transient Response for Various Power Supplies
0.125 0.100 0.075 CL = 0pF CL = 10pF CL = 20pF
22 18 14 CL = 0pF CL = 20pF
OUTPUT VOLTAGE (V)
0.050 0.025 0 -0.025 -0.050 -0.075 -0.100 5ns/DIV -0.125
05681-037
OUTPUT VOLTAGE (V)
10 6 2 -2 -6 -10 -14 -18
20ns/DIV -22
Figure 24. Small Signal Transient Response for Various Capacitive Loads
Figure 27. Large Signal Transient Response for Various Capacitive Loads
Rev. 0 | Page 10 of 20
ADA4922-1
8 6 4 VOUT, dm 4.8 3.6 2.4 28 21 14 VOUT, dm 16 12 8
VIN
VIN
AMPLITUDE (V)
ERROR (mV) 1 DIV = 0.01%
0 ERROR -2 -4 1s/DIV -6 -8 VS = 5V VO, dm = 12V p-p
0 -1.2 -2.4 -3.6 -4.8
0 ERROR -7 -14 1s/DIV -21 -28 VS = 12V VO, dm = 40V p-p
0 -4 -8 -12 -16
05681-028
Figure 28. Settling Time, VS = 5 V
Figure 31. Settling Time, VS = 12 V
12 INPUT x 2 8
26 22 18 14
INPUT x 2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4
10 6 2 -2 -6 -10 -14 OUTPUT
05681-035
0
-4
-8
05681-029
OUTPUT 1s/DIV
-18 -22 -26 1s/DIV
-12
Figure 29. Input Overdrive Recovery, VS = 5 V
Figure 32. Input Overdrive Recovery, VS = 12 V
DIFFERENTIAL OUTPUT OFFSET VOLTAGE (mV)
1.2 1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
05681-036
50 45 40
VS = 5V MEAN = 0.25mV STD. DEV. = 0.19mV VS = 12V MEAN = -0.07mV STD. DEV. = 0.17mV NUMBER OF UNITS = 590
VS = 5V
35
FREQUENCY
30 25 20 15 10 5 0
VS = 12V
-1.0 -1.2 -40 -20 0 20 40 60 80
0.125
0.250
0.375
0.500
0.625
0.750
0.875
-1.000
-0.875
-0.750
-0.625
-0.500
-0.375
-0.250
-0.125
TEMPERATURE (C)
DIFFERENTIAL OUTPUT OFFSET VOLTAGE (mV)
Figure 30. Differential Output Offset Voltage vs. Temperature
Figure 33. Differential Output Offset Voltage Distribution
Rev. 0 | Page 11 of 20
1.000
0
05681-043
05681-031
ERROR (mV) 1 DIV = 0.01%
2
1.2
AMPLITUDE (V)
7
4
ADA4922-1
12.0 11.5
10 9 ISUPPLY = 12V
POWER SUPPLY CURRENT (mA)
POWER SUPPLY CURRENT (mA)
11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 7.0 6.5 6.0 -40 -20 0 20 40 60 80 VS = 5V
05681-038
8 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIS INPUT VOLTAGE WITH RESPECT TO VS- (V)
05681-044
ISUPPLY = 5V
VS = 12V
TEMPERATURE (C)
Figure 34. Power Supply Current vs. Temperature
Figure 37. Power Supply Current vs. Disable Input Voltage
3.0
5 4 3
2.5
INPUT BIAS CURRENT (A)
INPUT BIAS CURRENT (A)
2 1 0 -1 -2 -3 IB = 5V
IB = 12V
2.0
1.5
05681-039
-4 -5 0 2 4 6 8 10 12 14 16 18 20 22 24 INPUT VOLTAGE WITH RESPECT TO VS- (V)
1.0 -40
-20
0
20
40
60
80
TEMPERATURE (C)
Figure 35. Input Bias Current vs. Temperature
Figure 38. Input Bias Current vs. Input Voltage
VO, dm = 2V p-p DIS INPUT VDIS = -8.5V VDIS = -8.5V
VO, dm = 2V p-p
VO, dm
500mV/DIV 500mV/DIV
DIS INPUT
VDIS = -10.5V
05681-046
VDIS = -10.5V 40s/DIV 40s/DIV
05681-048
VO, dm
Figure 36. Disable Turn-On Time
Figure 39. Disable Turn-Off Time
Rev. 0 | Page 12 of 20
05681-045
INPUT BIAS CURRENT, VS = 5V REFERENCE BIAS CURRENT, VS = 5V INPUT BIAS CURRENT, VS = 12V REFERENCE BIAS CURRENT, VS = 12V
ADA4922-1
300 250
PART OFF
DIS INPUT CURRENT (A)
200 150 100
PART ON
IDIS = 5V 50 0 -50 -100 -150 0 5 10 15 20 DIS VOLTAGE WITH RESPECT TO VS- (V) IDIS = 12V
05681-047
Figure 40. Disable Current vs. Disable Voltage
Rev. 0 | Page 13 of 20
ADA4922-1 THEORY OF OPERATION
The ADA4922-1 is dual amplifier that has been optimized to drive a differential ADC from a single-ended input source with a minimum number of external components (see Figure 41).
IN OUT+ R R OUT- REF
05681-002
If an application uses an input midswing voltage other than midsupply, the REF pin needs to be offset to the input midswing level to obtain outputs that do not exhibit a differential offset (see Figure 43). If the voltage applied to the REF pin is different from the midswing level of the input signal, a dc offset is created between outputs VOUT+ and VOUT-. Figure 44 illustrates this condition when the input signal is referenced to a positive level, and the REF pin is connected to 0 V.
10 5 0 VIN
Figure 41. Functional Diagram
The differential output voltage is defined as
VOLTAGE (V)
REF
VO, dm = VOUT+ - VOUT-
(1)
-5 -10 10
Each amplifier in Figure 41 is identical, and the value of Resistor R is set at 600 , yielding an optimal trade-off between output differential noise, internal power dissipation, and overall system linearity. For basic operation, the REF input is tied to the midswing level of the input signal, which is often midsupply. The input signal (referenced to REF) produces a differential output signal with an overall gain of +2. Figure 42 shows typical operation on 12 V supplies with the source referenced to 0 V and the REF pin tied to 0 V.
20 VIN 10 0 REF -10
5
OUT+
0 -2.5 0 5
OUT-
10
15
20
25 TIME (s)
30
35
40
45
50
Figure 43. Typical Input/Output Response--Equal Input/Reference
20 15 10 5 VIN
VOLTAGE (V)
VOLTAGE (V)
0 REF -5 10 5 OUT+
-20 10 5 0 OUT+
0 -5 -10 0 5 10 15 20 25 TIME (s) 30 35 40 45 50 OUT-
05681-005
-5 -10 0 5
OUT-
10
15
20
25 TIME (s)
30
35
40
45
50
Figure 42. Typical Input/Output Response--Centered Reference
05681-003
Figure 44. Typical Input/Output Response--Unequal Input/Reference
Rev. 0 | Page 14 of 20
05681-004
ADA4922-1
A more detailed view of the amplifier is shown in Figure 45. Each amplifier is a 2-stage design that uses an input H-Bridge followed by a rail-to-rail output stage (see Figure 46).
MIRROR I I C
The architecture used in the ADA4922-1 results in excellent SNR and distortion performance when compared to other differential amplifiers. One of the more subtle points of operation arises when the two amplifiers are used to generate the differential outputs. Because the differential outputs are derived from a follower amplifier and an inverting amplifier, they have different noise gains and, therefore, different closed-loop bandwidths. For frequencies up to 1 MHz, the bandwidth difference between outputs causes little difference in the overall differential output performance. However, because the bandwidth is the sum of both amplifiers, the 3 dB point of the inverting amplifier defines the overall differential 3 dB corner (see Figure 48).
0 OUT+
INP
RIN
INN
OUTPUT STAGE
OUT
I
I MIRROR
05681-006
Figure 45. Internal Amplifier Architecture
MIRROR I I
CLOSED-LOOP GAIN
-2
-4 OUT- -6 7 DIFFERENTIAL OUTPUT
IN
ROUT
INTERNAL REF
OUT
5
I MIRROR
I
05681-007 05681-010
3 1 10k
Figure 46. Output Stage Architecture
100k
1M FREQUENCY (Hz)
10M
100M
Figure 47 illustrates the open-loop gain and phase relationships of each amplifier in the ADA4922-1.
125 100
MAGNITUDE/PHASE (dB/Degrees)
Figure 48. Closed-Loop AC Gain (Differential Outputs)
75 50 25 0 -25 -50 -75 -100 -125 100 1k
GAIN
PHASE
05681-008
Small delay and gain errors exist between the two outputs because the inverting output is derived from the noninverting output through an inverting amplifier. The gain error is due to imperfect matching of the inverting amplifier gain and feedback resistors, as well as differences in the transfer functions of the two amplifiers, as illustrated in Figure 48. The delay error is due to the delay through the inverting amplifier relative to the noninverting amplifier output. The delay produces a reduction in differential gain because the two outputs are not exactly 180 out of phase. Both of these errors combine to produce an overall gain error because the outputs are completely balanced. This error is very small at the frequencies involved in most ADA4922-1 applications.
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 47. Amplifier Gain/Phase Relationship
Rev. 0 | Page 15 of 20
ADA4922-1 APPLICATIONS
The ADA4922-1 is a fixed-gain, single-ended-to-differential voltage amplifier, optimized for driving high resolution ADCs in high voltage applications. There are no gain adjustments available to the user.
Voltage Noise @ OUT- due to VnRf: VnRF
Rf Voltage Noise @ OUT- due toVn2: Vn2 1 + Rg = 2V n2
(8)
(9)
ADA4922-1 DIFFERENTIAL OUTPUT NOISE MODEL
The principal noise sources in a typical ADA4922-1 application circuit are shown in Figure 49.
VnRf Vn1 VnRg Rs Vn2 VnRs In1
05681-042
Rf
Rg OUT-
REF OUT+
When looking at OUT- by itself, the contributing noise sources are uncorrelated, and therefore, the total output noise is calculated as the root-sum-square (rss) of the individual contributors. When looking at the differential output noise, the noise contributors are uncorrelated except for three, Vn1, RS(In1), and VnRs, which are common noise sources for both outputs. It can be seen from the previous results that the output noise due to Vn1, RS(In1), and VnRs each appear at OUT+ with a gain of +1 and at OUT- with a gain of -1. This produces a gain of 2 for each of these three sources at the differential output. The total differential output noise density is calculated as Von, dm =
Figure 49. ADA4922-1 Differential Output Noise Model
Using the traditional approach, a noise source is applied in series with one of the inputs of each op amp to model inputreferred voltage noise. The input current noise that matters the most is present at the input pin. The output voltage noise due to this noise current depends on the source resistance feeding the input, as well as the downstream gain in the amplifier. Resistor noise is modeled by placing a noise voltage source in series with a noiseless resistor. Rf and Rg are both 600 and therefore have the same noise voltage density. At room temperature,
(2(V
n
+ Rs (1.4 pA/ Hz ) + VnRs
)) + 2(3.2 nV/
2
Hz + 4Vn2 (10)
)
2
where Vn1 = Vn2 Vn = 3.9 nV/Hz; the input referred voltage noise of each amplifier is the same. The output noise due to the amplifier alone is calculated by setting RS and VnRs equal to zero. In this case: Von, dm = 12 nV/Hz (11)
VnRg = VnRf = 4 kT(600 ) 3.2 nV/ Hz
(2)
Clearly, the output noise is not balanced between the outputs, but this is not an issue in most applications.
The noise at OUT+ is due to the input-referred current and voltage noise sources of the noninverting amplifier and the noise of the source resistance, all reflected to the output with a noise gain of 1, and is equal to: Voltage Noise @ OUT+: Vn1 + RS(In1) + VnRs (3)
USING THE REF PIN
The REF pin sets the output baseline in the inverting path and is used as a reference for the input signal. In most applications, the REF pin is set to the input signal midswing level, which in many cases is also midsupply. For bipolar signals and power supplies, REF is generally set to ground. In single-supply applications, setting REF to the input signal midswing level provides optimal output dynamic range performance with minimum differential offset. Note that the REF input only affects the inverting signal path, or OUT-. Most applications require a differential output signal with the same dc common-mode level on each output. It is possible for the signal measured across OUT+ and OUT- to have a commonmode voltage that is of the desired level but has different dc levels at both outputs. Typically, this situation is avoided, because it wastes the amplifier's output dynamic range.
where RS is the source resistance feeding the input, and VnRs is the source resistance noise. The noise at OUT- originates from a number of sources:
- Rf Voltage Noise @ OUT- due to Vn1: Vn1 Rg = - Vn1
(4)
- Rf Voltage Noise @ OUT- due to In1: RS (I n1 ) Rg - Rf Voltage Noise @ OUT- due to RS: VnRs Rg - Rf Voltage Noise @ OUT- due to VnRg: VnRg Rg
= - R (I n1 ) (5) S
(6)
= - VnRs = - VnRg
(7)
Rev. 0 | Page 16 of 20
ADA4922-1
Defining VIN as the voltage applied to the input pin, the equations that govern the two signal paths are given in Equation 12 and Equation 13. VOUT+ = +VIN VOUT- = -VIN + 2(REF) (12) (13)
DISABLE FEATURE
The ADA4922-1 includes a disable feature that can be asserted to minimize power consumption in a device that is not needed at a particular time. When asserted, the disable feature does not place the device output in a high impedance or three-state condition. The disable feature is asserted by applying a control voltage to the DIS pin and is active low. See the Specifications section for the high and low level voltage specifications.
When the REF voltage is set to the midswing level of the input signal, the two output signals fall directly on top of each other with minimal offset. Setting the REF voltage elsewhere results in an offset between the two outputs. This effect is illustrated in the Theory of Operation section. The best use of the REF pin can be further illustrated by considering a single-supply example that uses a 10 V dc power supply and has an input signal that varies between 2 V and 7 V. This is a case where the midswing level of the input signal is not at midsupply but is at 4.5 V. By setting the REF input to 4.5 V and neglecting offsets, Equation 12 and Equation 13 are used to calculate the results. When the input signal is at its midpoint of 4.5 V, VOUT+ is at 4.5 V, as is VOUT-. This can be considered as a type of baseline state where the differential output voltage is zero. When the input increases to 7 V, VOUT+ tracks the input to 7 V and VOUT- decreases to 2 V. This can be viewed as a positive peak signal where the differential output voltage equals 5 V. When the input signal decreases to 2 V, VOUT+ again tracks to 2 V, and VOUT- increases to 7 V. This can be viewed as a negative peak signal where the differential output voltage equals -5 V. The resulting differential output voltage is 10 V p-p. The previous discussion exposes how the single-ended-todifferential gain of 2 is achieved.
DRIVING A DIFFERENTIAL INPUT ADC
The ADA4922-1 provides the single-ended-to-differential conversion that is required to drive most high resolution ADCs. Figure 50 shows how the ADA4922-1 simplifies ADC driving.
+12V +12V
0.1F 7 DIS 8 IN VIN 10V R OUT- 5 2 REF VS- 6 0.1F -12V R 3 VS+
0.1F
ADA4922-1
OUT+ 4 R R C C HIGH VOLTAGE HIGH RESOLUTION ADC
0.1F
05681-049
-12V
Figure 50. Driving a Differential Input ADC
INTERNAL FEEDBACK NETWORK POWER DISSIPATION
While traditional op amps do not have on-chip feedback elements, the ADA4922-1 contains two on-chip 600 resistors that comprise an internal feedback loop. The power dissipated in these resistors must be included in the overall power dissipation calculations for the device. Under certain circumstances, the power dissipated in these resistors could be considerably more than the device's quiescent current. For example, on 12 V supplies with the REF pin tied to ground and OUT- at 9 V dc, each 600 resistor carries 15 mA and dissipates 135 mW. This is a significant amount of power and must therefore be included in the overall device power dissipation calculations. For ac signals, rms analysis is required.
For example, consider the case where the input signal bandwidth is 100 KHz and R = 41.2 and C = 3.9 nF, as is shown in Figure 50, to form a single-pole filter with -3 dB bandwidth of approximately 1 MHz. The ADA4922-1 output noise (with zero source resistance) integrated over this bandwidth appears at the ADC input and is calculated as
Vn, ADC , dm (rms) = 12 nV/ Hz
(
)
(1MHz ) = 15V rms 2
(14)
The rms value of a 20 V p-p signal at the ADC input is 7 V rms, yielding a SNR of 113 dB at the ADC input.
Rev. 0 | Page 17 of 20
ADA4922-1
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
Although the ADA4922-1 is used in many applications involving frequencies that are well below 1 MHz, some general high speed layout practices must be adhered to because it is a high speed amplifier. Controlled impedance transmission lines are not required for low frequency signals, provided the signal rise times are longer than approximately 5 times the electrical delay of the interconnections. For reference, typical 50 transmission lines on FR-4 material exhibit approximately 140 ps/in delay on outer layers and 180 ps/in for inner layers. Most connections between the ADA4922-1 and the ADC can be kept very short. Broadband power supply decoupling networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling.
Rev. 0 | Page 18 of 20
ADA4922-1 OUTLINE DIMENSIONS
5.00 (0.197) 4.90 (0.193) 4.80 (0.189)
8 1 5 4
4.00 (0.157) 3.90 (0.154) 3.80 (0.150)
2.29 (0.092) 6.20 (0.244) 6.00 (0.236) 5.80 (0.228) BOTTOM VIEW 2.29 (0.092)
TOP VIEW
1.27 (0.05) BSC 1.75 (0.069) 1.35 (0.053) 0.25 (0.0098) 0.10 (0.0039) COPLANARITY SEATING 0.10 PLANE 0.51 (0.020) 0.31 (0.012)
(PINS UP)
0.50 (0.020) x 45 0.25 (0.010)
8 0.25 (0.0098) 0 1.27 (0.050) 0.40 (0.016) 0.17 (0.0068)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 51. 8-Lead Standard Small Outline Package with Exposed Pad [SOIC_N_EP] Narrow Body (RD-8-1) Dimensions shown in millimeters and (inches
3.00 BSC SQ
0.60 MAX
0.50 0.40 0.30
PIN 1 INDICATOR
8
1
PIN 1 INDICATOR
TOP VIEW
2.75 BSC SQ 0.50 BSC
5 4
1.50 REF
1.89 1.74 1.59
0.90 MAX 0.85 NOM
12 MAX
0.70 MAX 0.65 TYP 0.05 MAX 0.01 NOM
1.60 1.45 1.30
SEATING PLANE
0.30 0.23 0.18
0.20 REF
Figure 52. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters
Rev. 0 | Page 19 of 20
ADA4922-1
ORDERING GUIDE
Model ADA4922-1ARDZ 1 ADA4922-1ARDZ-RL1 ADA4922-1ARDZ-R71 ADA4922-1ACPZ-R21 ADA4922-1ACPZ-RL1 ADA4922-1ACPZ-RL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead Small Outline Package (SOIC_N_EP) 8-Lead Small Outline Package (SOIC_N_EP) 8-Lead Small Outline Package (SOIC_N_EP) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
Package Option RD-8-1 RD-8-1 RD-8-1 CP-8-2 CP-8-2 CP-8-2
Branding
HUB HUB HUB
Z = Pb-free part.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05681-0-10/05(0)
Rev. 0 | Page 20 of 20

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