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1CY 7C42 25
fax id: 5410
CY7C4425/4205/4215 CY7C4225/4235/4245
64, 256, 512, 1K, 2K, 4K x 18 Synchronous FIFOs
Features
* High-speed, low-power, first-in first-out (FIFO) memories * 64 x 18 (CY7C4425) * 256 x 18 (CY7C4205) * 512 x 18 (CY7C4215) * 1K x 18 (CY7C4225) * 2K x 18 (CY7C4235) * 4K x 18 (CY7C4245) * High-speed 100-MHz operation (10 ns read/write cycle time) * Low power (ICC =45 mA) * Fully asynchronous and simultaneous read and write operation * Empty, Full, Half Full, and Programmable Almost Empty/Almost Full status flags * TTL-compatible * Retransmit function * Output Enable (OE) pin * Independent read and write enable pins * Center power and ground for reduced noise * Supports free-running 50% duty cycle clock inputs * Width Expansion Capability * Depth Expansion Capability * Space saving 64-pin 10x10 TQFP, and 14x14 TQFP * 68-pin PLCC controlled by a free-running clock (WCLK) and a write enable pin (WEN). When WEN is asserted, data is written into the FIFO on the rising edge of the WCLK signal. While WEN is held active, data is continually written into the FIFO on each cycle. The output port is controlled in a similar manner by a free-running read clock (RCLK) and a read enable pin (REN). In addition, the CY7C42X5 have an output enable pin (OE). The read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. Clock frequencies up to 100 MHz are achievable. Retransmit and Synchronous Almost Full/Almost Empty flag features are available on these devices. Depth expansion is possible using the cascade input (WXI, RXI), cascade output (WXO, RXO), and First Load (FL) pins. The WXO and RXO pins are connected to the WXI and RXI pins of the next device, and the WXO and RXO pins of the last device should be connected to the WXI and RXI pins of the first device. The FL pin of the first device is tied to VSS and the FL pin of all the remaining devices should be tied to VCC. The CY7C42X5 provides five status pins. These pins are decoded to determine one of five states: Empty, Almost Empty, Half Full, Almost Full, and Full (see Table 2). The Half Full flag shares the WXO pin. This flag is valid in the standalone and width-expansion configurations. In the depth expansion, this pin provides the expansion out (WXO) information that is used to signal the next FIFO when it will be activated. The Empty and Full flags are synchronous, i.e., they change state relative to either the read clock (RCLK) or the write clock (WCLK). When entering or exiting the Empty states, the flag is updated exclusively by the RCLK. The flag denoting Full states is updated exclusively by WCLK. The synchronous flag architecture guarantees that the flags will remain valid from one clock cycle to the next. As mentioned previously, the Almost Empty/Almost Full flags become synchronous if the VCC/SMODE is tied to VSS. All configurations are fabricated using an advanced 0.65 N-Well CMOS technology. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings.
Functional Description The CY7C42X5 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All are 18 bits wide and are pin/functionally compatible to IDT722x5. The CY7C42X5 can be cascaded to increase FIFO depth. Programmable features include Almost Full/Almost Empty flags. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. These FIFOs have 18-bit input and output ports that are controlled by separate clock and enable signals. The input port is
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
* CA 95134 * 408-943-2600 April 1995 - Revised August 18, 1997
CY7C4425/4205/4215 CY7C4225/4235/4245
Logic Block Diagram
D0
- 17
INPUT REGISTER
WCLK
WEN
WRITE CONTROL DUAL PORT RAM ARRAY 64 x 18 256 x 18 512 x 18 1K x 18 2K x 18 4K x 18
FLAG PROGRAM REGISTER
FLAG LOGIC
FF EF PAE PAF SMODE
WRITE POINTER
READ POINTER
RS
RESET LOGIC
FL/RT WXI WXO/HF RXI RXO EXPANSION LOGIC
THREE-STATE OUTPUT REGISTER
READ CONTROL OE 42X5-1
Q0
- 17
RCLK
REN
Pin Configurations
REN LD OE RS VCC GND EF Q17 Q16 GND Q15 VCC/SMODE
PLCC Top View
RCLK REN LD OE RS GND GND GND Q15 VCC VCC Q17 D16 D17 GND RCLK
TQFP Top View
987 D14 D13 D12 D11 D10 D9 VCC D8 GND D7 D6 D5 D4 D3 D2 D1 D0 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
65
4
3
2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VCC/SMODE Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 VCC Q6 Q5 GND Q4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 D15 D14 D13 D12 D 11 D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q14 Q13 GND Q12 Q11 VCC Q10 Q9 GND Q8 Q7 Q6 Q5 GND Q4 VCC
Q16
D15
D16
D17
EF
CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245
CY7C4425 CY7C4205 CY7C4215 CY7C4225 CY7C4235 CY7C4245
2728 2930 3132 33 34 35 36 37 38 3940 4142 43 PAE FL/RT WEN WXI PAF RXI FF WXO/HF RXO WCLK GND VCC VCC Q0 Q1 Q2 Q3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
FL/RT WCLK WEN WXI VCC PAF RXI FF WXO/HF RXO
PAE
Q0 Q1 GND Q2
42x5-2
2
Q3
42X5-3
CY7C4425/4205/4215 CY7C4225/4235/4245
Selection Guide
7C42X5-10 Maximum Frequency (MHz) Maximum Access Time (ns) Minimum Cycle Time (ns) Minimum Data or Enable Set-Up (ns) Minimum Data or Enable Hold (ns) Maximum Flag Delay (ns) Operating Current (ICC2) (mA) @ freq=20MHz Commercial Industrial CY7C4205 256 x 18 68-pin PLCC 64-pin TQFP (10x10/14x14) 100 8 10 3 0.5 8 45 50 CY7C4215 512 x 18 68-pin PLCC 64-pin TQFP (10x10/14x14) 7C42X5-15 66.7 10 15 4 1 10 45 50 CY7C4225 1K x 18 68-pin PLCC 64-pin TQFP (10x10/14x14) 7C42X5-25 40 15 25 6 1 15 45 50 CY7C4235 2K x 18 68-pin PLCC 64-pin TQFP (10x10/14x14) 7C42X5-35 28.6 20 35 7 2 20 45 50 CY7C4245 4K x 18 68-pin PLCC 64-pin TQFP (10x10/14x14)
CY7C4425 Density Packages 64 x 18 68-pin PLCC 64-pin TQFP (10x10/14x14)
Pin Definitions
Signal Name D0-17 Q 0-17 WEN REN WCLK Description Data Inputs Data Outputs Write Enable Read Enable Write Clock I/O I O I I I Data inputs for an 18-bit bus Data outputs for an 18-bit bus Enables the WCLK input Enables the RCLK input The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-offset register. The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset register. Dual-Mode Pin: Single device or width expansion - Half Full status flag. Cascaded - Write Expansion Out signal, connected to WXI of next device. When EF is LOW, the FIFO is empty. EF is synchronized to RCLK. When FF is LOW, the FIFO is full. FF is synchronized to WCLK. When PAE is LOW, the FIFO is almost empty based on the almost-empty offset value programmed into the FIFO. PAE is asynchronous when V CC/SMODE is tied to V CC; it is synchronized to RCLK when V CC/SMODE is tied to V SS. When PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the FIFO. PAF is asynchronous when V CC/SMODE is tied to V CC; it is synchronized to WCLK when V CC/SMODE is tied to VSS. When LD is LOW, D 0 - 17 (O 0 - 17) are written (read) into (from) the programmable-flag-offset register. Dual-Mode Pin: Cascaded - The first device in the daisy chain will have FL tied to V SS; all other devices will have FL tied to V CC. In standard mode of width expansion, FL is tied to V SS on all devices. Not Cascaded - Tied to VSS. Retransmit function is also available in standalone mode by strobing RT. Cascaded - Connected to WXO of previous device. Not Cascaded - Tied to VSS. Function
RCLK
Read Clock
I
WXO/HF
Write Expansion Out/Half Full Flag Empty Flag Full Flag Programmable Almost Empty Programmable Almost Full Load First Load/ Retransmit
O
EF FF PAE
O O O
PAF
O
LD FL/RT
I I
WXI
Write Expansion Input
I
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Pin Definitions (continued)
Signal Name RXI RXO RS OE VCC/SMODE Description Read Expansion Input Read Expansion Output Reset Output Enable Synchronous Almost Empty/ Almost Full Flags I/O I O I I I Function Cascaded - Connected to RXO of previous device. Not Cascaded - Tied to VSS. Cascaded - Connected to RXI of next device. Resets device to empty condition. A reset is required before an initial read or write operation after power-up. When OE is LOW, the FIFO's data outputs drive the bus to which they are connected. If OE is HIGH, the FIFO's outputs are in High Z (high-impedance) state. Dual-Mode Pin Asynchronous Almost Empty/Almost Full flags - tied to VCC. Synchronous Almost Empty/Almost Full flags - tied to V SS. (Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.) Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ....................................-65C to +150C Ambient Temperature with Power Applied.................................................-55C to +125C Supply Voltage to Ground Potential .................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-3.0V to +7.0V
Operating Range
Range Commercial Industrial[1] Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range[2]
7C42X5-10 Parameter VOH VOL VIH [3] VIL IIX IOS[4] IOZL I OZH ICC2[5] ISB
[6] [3]
7C42X5-15 Min. 2.4 Max.
7C42X5-25 Min. 2.4 Max.
7C42X5-35 Min. 2.4 Max. Unit V 0.4 2.2 -3.0 -10 -90 VCC 0.8 +10 V V V A mA +10 45 50 10 15 A mA mA mA mA
Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Short Circuit Current Output OFF, High Z Current Operating Current Standby Current
Test Conditions VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA
Min. 2.4
Max.
0.4 2.2 -3.0 VCC 0.8 +10 2.2 -3.0 -10 -90 +10 45 50 10 15 -10
0.4 VCC 0.8 +10 2.2 -3.0 -10 -90 +10 45 50 10 15 -10
0.4 VCC 0.8 +10
VCC = Max. VCC = Max., V OUT = GND OE > VIH, VSS < VO < VCC VCC = Max., IOUT = 0 mA VCC = Max., IOUT = 0 mA Com'l Ind Com'l Ind
-10 -90 -10
+10 45 50 10 15
-10
Notes: 1. TA is the "instant on" case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. The V IH and VIL specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the previous device or V SS. 4. Test no more than one output at a time for not more than one second. 5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz. Outputs are unloaded. 6. All input signals are connected to VCC . All outputs are unloaded.
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Capacitance[7]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 5 7 Unit pF pF
AC Test Loads and Waveforms[8, 9]
R11.1K 5V OUTPUT CL INCLUDING JIG AND SCOPE Equivalent to: THE EVENIN OUTPUT EQUIVALENT 410 1.91V R2 680 3.0V GND < 3 ns
ALL INPUT PULSES
90% 10% 90% 10% < 3 ns
42X5-5
42X5-4
Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. CL = 30 pF for all AC parameters except for tOHZ. 9. CL = 5 pF for t OHZ .
Switching Characteristics Over the Operating Range
7C42X5-10 Parameter tS tA tCLK tCLKH tCLKL tDS tDH tENS tENH tRS tRSR tRSF tPRT tRTR tOLZ tOE tOHZ tWFF tREF tPAFasynch Description Clock Cycle Frequency Data Access Time Clock Cycle Time Clock HIGH Time Clock LOW Time Data Set-Up Time Data Hold Time Enable Set-Up Time Enable Hold Time Reset Pulse Width[10] Reset Recovery Time Reset to Flag and Output Time Retransmit Pulse Width Retransmit Recovery Time Output Enable to Output in Low Output Enable to Output Valid Output Enable to Output in High Z[12] Write Clock to Full Flag Read Clock to Empty Flag Clock to Programmable Almost-Full Flag[12] (Asynchronous mode, VCC/SMODE tied to VCC) Z[11] 12 12 0 3 3 7 7 8 8 12 2 10 4.5 4.5 3 0.5 3 0.5 10 8 10 15 15 0 3 3 8 8 10 10 16 Min. Max. 100 8 2 15 6 6 4 1 4 1 15 10 15 25 25 0 3 3 12 12 15 15 20 7C42X5-15 Min. Max. 66.7 10 2 25 10 10 6 1 6 1 25 15 25 35 35 0 3 3 15 15 20 20 25 7C42X5-25 Min. Max. 40 15 2 35 14 14 7 2 7 2 35 20 35 7C42X5-35 Min. Max. Unit 28.6 20 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Switching Characteristics Over the Operating Range (continued)
7C42X5-10 Parameter tPAFsynch tPAEasynch tPAEsynch tHF tXO tXI tXIS tSKEW1 tSKEW2 tSKEW3 Description Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) Clock to Programmable Almost-Empty Flag[12] (Asynchronous mode, VCC/SMODE tied to VCC) Clock to Programmable Almost-Full Flag (Synchronous mode, VCC/SMODE tied to VSS) Clock to Half-Full Flag Clock to Expansion Out Expansion in Pulse Width Expansion in Set-Up Time Skew Time between Read Clock and Write Clock for Full Flag Skew Time between Read Clock and Write Clock for Empty Flag Skew Time between Read Clock and Write Clock for Programmable Almost Empty and Programmable Almost Full Flags. 3 4.5 5 5 10 Min. Max. 8 12 8 12 7 6.5 5 6 6 15 7C42X5-15 Min. Max. 10 16 10 16 10 10 10 10 10 18 7C42X5-25 Min. Max. 15 20 15 20 15 14 15 12 12 20 7C42X5-35 Min. Max. Unit 20 25 20 25 20 ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Write Cycle Timing
tCLK tCLKH WCLK tDS D0 -D17 tENS WEN tWFF FF tSKEW1[13] RCLK tWFF tENH
NO OPERATION
tCLKL
tDH
REN
42X5-6
Notes: 10. Pulse widths less than minimum values are not allowed. 11. Values guaranteed by design, not currently tested. 12. PAFasynch, tPAEasynch, after program register write will not be valid until 5 ns + tPAF(E). 13. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
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Switching Waveforms (continued)
Read Cycle Timing
tCLK tCLKH RCLK tENS REN tREF EF tA Q0 -Q17 tOLZ tOE OE
[14] tSKEW2
VALID DATA
tCLKL
tENH
NO OPERATION
tREF
tOHZ
WCLK
WEN
42X5-7
Reset Timing[15]
tRS RS tRSR REN, WEN, LD tRSF EF,PAE tRSF FF,PAF, HF tRSF Q0 - Q17 OE=0
42X5-8
OE=1[16]
Notes: 14. .tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge. 15. The clocks (RCLK, WCLK) can be free-running during reset. 16. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
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Switching Waveforms (continued)
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK tDS D0 -D17 tENS WEN tSKEW2 RCLK tREF EF tFRL
[17]
D0 (FIRSTVALID WRITE)
D1
D2
D3
D4
REN tA Q0 -Q17 tOLZ tOE OE
42X5-9
tA D0
[18]
D1
Empty Flag Timing
WCLK tDS D0 -D17 tENS WEN tFRL[17] RCLK tSKEW2 EF tREF tREF tSKEW2 tREF
[17] tFRL
tDS D0 tENH tENS D1 tENH
REN OE tA Q0 -Q17 D0
42X5-10
Notes: 17. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW). 18. The first word is available the cycle after EF goes HIGH, always.
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Switching Waveforms (continued)
Full Flag Timing
NO WRITE WCLK tSKEW1 [13] D0 -D17 tWFF FF tDS tSKEW1 DATA WRITE tWFF tWFF
[13]
NO WRITE
DATA WRITE
WEN
RCLK tENH tENS REN tENS tENH
OE
LOW tA tA DATAREAD NEXT DATA READ
42X5-11
Q0 -Q17
DATA IN OUTPUT REGISTER
Half-Full Flag Timing
tCLKH WCLK tENS tENH WEN tHF HF HALF FULL OR LESS tCLKL
HALF FULL+1 OR MORE tHF
HALF FULL OR LESS
RCLK tENS REN
42X5-12
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Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKH WCLK tENS tENH WEN tPAE PAE]
[19]
tCLKL
n+1 WORDS IN FIFO tPAE
n WORDS IN FIFO
RCLK tENS REN
42X5-13
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW)
tCLKH WCLK tENS tENH WEN tCLKL
WEN2 tENS tENH PAE tSKEW3 [21] RCLK tENS REN
42X5-14
Note 20 tPAEsynch
N + 1 WORDS INFIFO
Note 22
tPAEsynch
tENS tENH
Notes: 19. PAE offset - n. Number of data words into FIFO already = n. 20. PAE offset - n. 21. tSKEW3 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising RCLK is less than tSKEW3, then PAE may not change state until the next RCLK. 22. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
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Switching Waveforms (continued)
Programmable Almost Full Flag Timing
tCLKH Note 23 WCLK tENS tENH WEN tPAF PAF
[24]
tCLKL
FULL - M WORDS IN FIFO [25] tPAF
FULL - M + 1 WORDS IN FIFO [26]
RCLK tENS REN
42X5-15
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE in LOW))
tCLKH WCLK tENS tENH WEN tCLKL Note 27
WEN2 tENS tENH PAF FULL- M+1 ORDS INFIFO
Note 28 tPAF FULL - M WORDS [29] IN FIFO
[30] tSKEW3
tPAFsynch
RCLK tENS REN
42X5-16
tENS tENH
Notes: 23. PAF offset = m. Number of data words written into FIFO already = 64 - m + 1 for the CY7C4425, 256 - m + 1 for the CY7C4205, 512 - m + 1 for the CY7C4215. 1024 - m + 1 for the CY7C4225, 2048 - m + 1 for the CY7C4235, and 4096 - m + 1 for the CY7C4245. 24. PAF is offset = m. 25. 64 - m words in CY7C4425, 256 - m words inCY7C4205, 512 - m word in CY7C4215. 1024 - m words in CY7C4225, 2048 - m words in CY7C4235, and 4096 - m words in CY7C4245. 26. 64 - m + 1 words in CY7C4425, 256 - m + 1 words in CY7C4205, 512 - m +1 words in CY7C4215, 1024 - m + 1 CY7C4225, 2048 - m + 1 in CY74235, and 4096 - m + 1 words in CY7C4245. 27. If a write is performed on this rising edge of the write clock, there will be Full - (m - 1) words of the FIFO when PAF goes LOW. 28. PAF offset = m. 29. 64 - m words in CY7C4425, 256 - m words in FIFO for CY7C4205, 512 - m word in CY7C4215. 1024 - m words in CY7C4225, 2048 - m words in CY7C4235, and 4096 - m words in CY7C4245. 30. tSKEW3 is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and the rising edge of WCLK is less than tSKEW3, then PAF may not change state until the next WCLK rising edge.
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Switching Waveforms (continued)
Write Programmable Registers
tCLK tCLKH WCLK tENS LD tENS WEN tDS D0 -D17 PAE OFFSET PAF OFFSET D0 -D11
42X5-17
tCLKL
tENH
tDH
PAE OFFSET
Read Programmable Registers
tCLK tCLKH RCLK tENS LD tENS WEN tA Q0 -Q17 UNKNOWN PAE OFFSET PAF OFFSET PAE OFFSET
42X5-18
tCLKL
tENH
Write Expansion Out Timing
tCLKH WCLK Note 31 tXO WXO tENS WEN
42X5-19
tXO
Note: 31. Write to Last Physical Location.
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Switching Waveforms (continued)
Read Expansion Out Timing
tCLKH WCLK Note 32 tXO RXO tENS REN
42X5-20
tXO
Write Expansion In Timing
tXI WXI
WCLK
tXIS
42X5-21
Read Expansion In Timing
tXI RXI
tXIS RCLK
42X5-22
Retransmit Timing[33, 34, 35]
FL/RT tPRT tRTR REN/WEN
EF/FF and all async flags HF/PAE/PAF
Notes: 32. Read from Last Physical Location. 33. Clocks are free running in this case. 34. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags.
42X5-23
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Architecture
The CY7C42X5 consists of an array of 64 to 4K words of 18 bits each (implemented by a dual-port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The CY7C42X5 also includes the control signals WXI, RXI, WXO, RXO for depth expansion. Table 1. Write Offset Register LD 0 WEN 0 WCLK[36] Selection Writing to offset registers: Empty Offset Full Offset No Operation Write Into FIFO No Operation
0 1
1 0 1
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS) cycle. This causes the FIFO to enter the Empty condition signified by EF being LOW. All data outputs go LOW after the falling edge of RS only if OE is asserted. In order for the FIFO to reset to its default state, a falling edge must occur on RS and the user must not read or write while RS is LOW.
1
FIFO Operation
When the WEN signal is active (LOW), data present on the D0-17 pins is written into the FIFO on each rising edge of the WCLK signal. Similarly, when the REN signal is active LOW, data in the FIFO memory will be presented on the Q0-17 outputs. New data will be presented on each rising edge of RCLK while REN is active LOW and OE is LOW. REN must set up tENS before RCLK for it to be a valid read function. WEN must occur tENS before WCLK for it to be a valid write function. An output enable (OE) pin is provided to three-state the Q0-17 outputs when OE is deasserted. When OE is enabled (LOW), data in the output register will be available to the Q0-17 outputs after tOE. If devices are cascaded, the OE function will only output data on the FIFO that is read enabled. The FIFO contains overflow circuitry to disallow additional writes when the FIFO is full, and underflow circuitry to disallow additional reads when the FIFO is empty. An empty FIFO maintains the data of the last valid read on its Q0-17 outputs even after additional reads occur.
Note: 36. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Flag Operation
The CY7C42X5 devices provide five flag pins to indicate the condition of the FIFO contents. Empty and Full are synchronous. PAE and PAF are synchronous if VCC/SMODE is tied to VSS. Full Flag The Full Flag (FF) will go LOW when device is Full. Write operations are inhibited whenever FF is LOW regardless of the state of WEN. FF is synchronized to WCLK, i.e., it is exclusively updated by each rising edge of WCLK. Empty Flag The Empty Flag (EF) will go LOW when the device is empty. Read operations are inhibited whenever EF is LOW, regardless of the state of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by each rising edge of RCLK. Programmable Almost Empty/Almost Full Flag The CY7C42X5 features programmable Almost Empty and Almost Full Flags. Each flag can be programmed (described in the Programming section) a specific distance from the corresponding boundary flags (Empty or Full). When the FIFO contains the number of words or fewer for which the flags have been programmed, the PAF or PAE will be asserted, signifying that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. When the SMODE pin is tied LOW, the PAF flag signal transition is caused by the rising edge of the write clock and the PAE flag transition is caused by the rising edge of the read clock.
Programming
The CY7C42X5 devices contain two 12-bit offset registers. Data present on D0-11 during a program write will determine the distance from Empty (Full) that the Almost Empty (Almost Full) flags become active. If the user elects not to program the FIFO's flags, the default offset values are used (see Table 2). When the Load LD pin is set LOW and WEN is set LOW, data on the inputs D0-11 is written into the Empty offset register on the first LOW-to-HIGH transition of the write clock (WCLK). When the LD pin and WEN are held LOW then data is written into the Full offset register on the second LOW-to-HIGH transition of the write clock (WCLK). The third transition of the write clock (WCLK) again writes to the Empty offset register (see Table 1). Writing all offset registers does not have to occur at one time. One or two offset registers can be written and then, by bringing the LD pin HIGH, the FIFO is returned to normal read/write operation. When the LD pin is set LOW, and WEN is LOW, the next offset register in sequence is written. The contents of the offset registers can be read on the output lines when the LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-to-HIGH transition of the read clock (RCLK).
Retransmit
The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The Retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred since the last RS cycle. A HIGH pulse on RT resets the internal read pointer to the first physical location of the FIFO. WCLK and RCLK may be free running but must be disabled during and tRTR after the retransmit pulse. With
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CY7C4425/4205/4215 CY7C4225/4235/4245
every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a Table 2. Flag Truth Table. Number of Words in FIFO 7C4425 - 64 x 18 0 1 to n
[37
retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted.
7C4205 - 256 x 18 0 1 to n
[37]
7C4215 - 512 x 18 0 1 to n
[37]
FF H H H H H L
PAF H H H H L L
HF H H H L L L
PAE L L H H H H
EF L H H H H H
(n+1) to 32 33 to (64 - (m+1)) (64 - m)[38] to 63 64
(n+1) to 128 129 to (256 - (m+1)) (256 - m)[38] to 255 256 Number of Words in FIFO
(n+1) to 256 257 to (512 - (m+1)) (512 - m)[38] to 511 512
7C4225 - 1K x 18 0 1 to n[37] (n+1) to 512 513 to (1024 - (m+1)) (1024 - m)[38] to 1023 1024 0
7C4235 - 2K x 18 0 1 to n[37] (n+1) to 1024 1025 to (2048 - (m+1)) (2048 - m)[38] to 2047 2048
7C4245 - 4K x 18 1 to n[37] (n+1) to 2048 2049 to (4096 - (m+1)) (4096 - m)[38] to 4095 4096
FF H H H H H L
PAF H H H H L L
HF H H H L L L
PAE L L H H H H
EF L H H H H H
Notes: 37. n = Empty Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127). 38. m = Full Offset (Default Values: CY7C4425 n = 7, CY7C4205 n = 31, CY7C4215 n = 63, CY7C4225/7C4235/7C4245 n = 127).
Width Expansion Configuration
The CY7C42X5 can be expanded in width to provide word widths greater than 18 in increments of 18. During width expansion mode all control line inputs are common and all flags
are available. Empty (Full) flags should be created by ANDing the Empty (Full) flags of every FIFO. This technique will avoid ready data from the FIFO that is "staggered" by one clock cycle due to the variations in skew between RCLK and WCLK. Figure 1 demonstrates a 36-word width by using two CY7C42X5.
RESET (RS) DATA IN (D) 36
18 18
RESET (RS)
WRITECLOCK (WCLK) WRITEENABLE (WEN) LOAD (LD) PROGRAMMABLE(PAE) HALF FULL FLAG (HF) FF FULL FLAG (FF)
18
7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUTENABLE (OE) PROGRAMMABLE(PAF)
EMPTYFLAG (EF) EF
18
EF
FF
DATA OUT (Q)
36
FIRST LOAD (FL) WRITE EXPANSION IN (WXI) READ EXPANSION IN (RXI)
42X5-24
Figure 1. Block Diagram of 64x36/256 x 36/512 x 36/1024 x 36/2048 x 36/4096 x 36 Synchronous FIFO Memory Used in a Width Expansion Configuration.
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CY7C4425/4205/4215 CY7C4225/4235/4245
Depth Expansion Configuration (with Programmable Flags)
The CY7C42X5 can easily be adapted to applications requiring more than 64/256/512/1024/2048/4096 words of buffering. Figure 2 shows Depth Expansion using three CY7C42X5s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input. 2. All other devices must have FL in the HIGH state. 3. The Write Expansion Out (WXO) pin of each device must be tied to the Write Expansion In (WXI) pin of the next device. 4. The Read Expansion Out (RXO) pin of each device must be tied to the Read Expansion In (RXI) pin of the next device. 5. All Load (LD) pins are tied together. 6. The Half-Full Flag (HF) is not available in the Depth Expansion Configuration. 7. EF, FF, PAE, and PAF are created with composite flags by ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise.
WXO RXO 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 FF EF PAE PAF WXI RXI
VCC FIRSTLOAD (FL)
WXO RXO 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 FF EF PAE PAF WXI RXI
DATAIN (D) VCC FIRSTLOAD (FL)
DATAOUT (Q)
WRITECLOCK (WCLK) WRITE ENABLE (WEN) RESET(RS)
WXO RXO 7C4425 7C4205 7C4215 7C4225 7C4235 7C4235 FF EF
READ CLOCK (RCLK) READ ENABLE (REN) OUTPUT ENABLE (OE)
LOAD (LD) FF PAF
EF PAE
42X5-23
PAFWXI RXIPAE FIRSTLOAD (FL)
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration.
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CY7C4425/4205/4215 CY7C4225/4235/4245
Typical AC and DC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC NORMALIZED ICC 1.2 1.0 0.8 0.6 4 4.5 5 5.5 6 VIN =3.0V TA =25C f=100 MHz 1.2 NORMALIZED ICC 1.1 1.0 0.9 0.8 -55 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (C) VIN =3.0V VCC =5.0V f=100 MHz NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.1 1.0 0.9 0.8 0.7 0.6 0 25 50 75 100
VCC =5.0V TA =25C VIN =3.0V
FREQUENCY (MHz)
NORMALIZED tA vs.SUPPLY VOLTAGE 1.2 NORMALIZED tA TA =25C NORMALIZED tA 1.1 1.0 0.9 0.8 4 4.5 5 5.5 6 1.50 1.25 1.0 .75 0.5 -55
NORMALIZED tA vs. AMBIENT TEMPERATURE 40 NORMALIZED tA
TYPICAL tA CHANGE vs. OUTPUT LOADING
25
VCC =5.0V
10 VCC =5.0V TA =25C 275 550 825 1000
25
125
-5.0 .50
SUPPLY VOLTAGE (V) OUTPUT SOURCECURRENT vs. OUTPUT VOLTAGE OUTPUT SINK CURENT (mA) 55 TA =25C VCC =5.0V
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 120 140 120 100 80 60 40 20 0 0 1 2 3 4 TA =25C VCC =5.0V
CAPACITANCE (pF)
OUTPUTS OURCE CURRENT (mA)
45 35 25 0 1 2
3
4
5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
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CY7C4425/4205/4215 CY7C4225/4235/4245
Ordering Information
64 x 18 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4425-10AC CY7C4425-10ASC CY7C4425-10JC CY7C4425-10AI CY7C4425-10ASI CY7C4425-10JI 15 CY7C4425-15AC CY7C4425-15ASC CY7C4425-15JC CY7C4425-15AI CY7C4425-15ASI CY7C4425-15JI 25 CY7C4425-25AC CY7C4425-25ASC CY7C4425-25JC CY7C4425-25AI CY7C4425-25ASI CY7C4425-25JI 35 CY7C4425-35AC CY7C4425-35ASC CY7C4425-35JC CY7C4425-35AI CY7C4425-35ASI CY7C4425-35JI Package Name A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 Package Type 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
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CY7C4425/4205/4215 CY7C4225/4235/4245
256 x 18 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4205-10AC CY7C4205-10ASC CY7C4205-10JC CY7C4205-10AI CY7C4205-10ASI CY7C4205-10JI 15 CY7C4205-15AC CY7C4205-15ASC CY7C4205-15JC CY7C4205-15AI CY7C4205-15ASI CY7C4205-15JI 25 CY7C4205-25AC CY7C4205-25ASC CY7C4205-25JC CY7C4205-25AI CY7C4205-25ASI CY7C4205-25JI 35 CY7C4205-35AC CY7C4205-35ASC CY7C4205-35JC CY7C4205-35AI CY7C4205-35ASI CY7C4205-35JI Package Name A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 Package Type 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
19
CY7C4425/4205/4215 CY7C4225/4235/4245
512 x 18 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4215-10AC CY7C4215-10ASC CY7C4215-10JC CY7C4215-10AI CY7C4215-10ASI CY7C4215-10JI 15 CY7C4215-15AC CY7C4215-15ASC CY7C4215-15JC CY7C4215-15AI CY7C4215-15ASI CY7C4215-15JI 25 CY7C4215-25AC CY7C4215-25ASC CY7C4215-25JC CY7C4215-25AI CY7C4215-25ASI CY7C4215-25JI 35 CY7C4215-35AC CY7C4215-35ASC CY7C4215-35JC CY7C4215-35AI CY7C4215-35ASI CY7C4215-35JI Package Name A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 Package Type 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
20
CY7C4425/4205/4215 CY7C4225/4235/4245
1K x 18 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4225-10AC CY7C4225-10ASC CY7C4225-10JC CY7C4225-10AI CY7C4225-10ASI CY7C4225-10JI 15 CY7C4225-15AC CY7C4225-15ASC CY7C4225-15JC CY7C4225-15AI CY7C4225-15ASI CY7C4225-15JI 25 CY7C4225-25AC CY7C4225-25ASC CY7C4225-25JC CY7C4225-25AI CY7C4225-25ASI CY7C4225-25JI 35 CY7C4225-35AC CY7C4225-35ASC CY7C4225-35JC CY7C4225-35AI CY7C4225-35ASI CY7C4225-35JI Package Name A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 Package Type 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
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CY7C4425/4205/4215 CY7C4225/4235/4245
2K x 18 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4235-10AC CY7C4235-10ASC CY7C4235-10JC CY7C4235-10AI CY7C4235-10ASI CY7C4235-10JI 15 CY7C4235-15AC CY7C4235-15ASC CY7C4235-15JC CY7C4235-15AI CY7C4235-15ASI CY7C4235-15JI 25 CY7C4235-25AC CY7C4235-25ASC CY7C4235-25JC CY7C4235-25AI CY7C4235-25ASI CY7C4235-25JI 35 CY7C4235-35AC CY7C4235-35ASC CY7C4235-35JC CY7C4235-35AI CY7C4235-35ASI CY7C4235-35JI Package Name A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 Package Type 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
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CY7C4425/4205/4215 CY7C4225/4235/4245
4K x 18 Synchronous FIFO Speed (ns) 10 Ordering Code CY7C4245-10AC CY7C4245-10ASC CY7C4245-10JC CY7C4245-10AI CY7C4245-10ASI CY7C4245-10JI 15 CY7C4245-15AC CY7C4245-15ASC CY7C4245-15JC CY7C4245-15AI CY7C4245-15ASI CY7C4245-15JI 25 CY7C4245-25AC CY7C4245-25ASC CY7C4245-25JC CY7C4245-25AI CY7C4245-25ASI CY7C4245-25JI 35 CY7C4245-35AC CY7C4245-35ASC CY7C4245-35JC CY7C4245-35AI CY7C4245-35ASI CY7C4245-35JI Package Name A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 A65 A64 J81 Package Type 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier 64-Lead 14x14 Thin Quad Flatpack 64-Lead 10x10 Thin Quad Flatpack 68-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial
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CY7C4425/4205/4215 CY7C4225/4235/4245
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack A65
64-Pin Thin Quad Flat Pack A64
24
CY7C4425/4205/4215 CY7C4225/4235/4245
Package Diagrams (continued)
68-Lead Plastic Leaded Chip Carrier J81
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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