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14-Bit, 160 MSPS TxDAC+ with 2 Interpolation Filter AD9772A
(R)
FEATURES Single 3.1 V to 3.5 V Supply 14-Bit DAC Resolution and Input Data Width 160 MSPS Input Data Rate 67.5 MHz Reconstruction Pass Band @ 160 MSPS 74 dBc SFDR @ 25 MHz 2 Interpolation Filter with High- or Low-Pass Response 73 dB Image Rejection with 0.005 dB Pass-band Ripple Zero-Stuffing Option for Enhanced Direct IF Performance Internal 2/4 Clock Multiplier 250 mW Power Dissipation; 13 mW with Power-Down Mode 48-Lead LQFP Package APPLICATIONS Communication Transmit Channel W-CDMA Base Stations, Multicarrier Base Stations, Direct IF Synthesis, Wideband Cable Systems Instrumentation GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 CLK+ CLK- 1 1/2
AD9772A
CLOCK DISTRIBUTION AND MODE SELECT FILTER MUX CONTROL CONTROL PLL CLOCK MULTIPLIER 2/4
PLLCOM LPF PLLVDD
DATA INPUTS (DB13... DB0) SLEEP
EDGETRIGGERED LATCHES
2 FIR INTERPOLATION FILTER
ZEROSTUFF MUX
14-BIT DAC
IOUTA IOUTB REFIO FSADJ
+1.2V REFERENCE AND CONTROL AMP DCOM DVDD ACOM AVDD REFLO
The AD9772A is a single-supply, oversampling, 14-bit digital-to-analog converter (DAC) optimized for baseband or IF waveform reconstruction applications requiring exceptional dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 2 digital interpolation filter and clock multiplier. The onchip PLL clock multiplier provides all the necessary clocks for the digital filter and the 14-bit DAC. A flexible differential clock input allows for a single-ended or differential clock driver for optimum jitter performance. For baseband applications, the 2 digital interpolation filter provides a low-pass response, thus providing as much as a threefold reduction in the complexity of the analog reconstruction filter. It does so by multiplying the input data rate by a factor of 2 while suppressing the original upper in-band image by more than 73 dB. For direct IF applications, the 2 digital interpolation filter response can be reconfigured to select the upper in-band image (i.e., high-pass response) while suppressing the original baseband image. To increase the signal level of the higher IF images and their pass-band flatness in direct IF applications, the AD9772A also features a zero-stuffing option in which the data following the 2 interpolation filter is upsampled by a factor of 2 by inserting midscale data samples. The AD9772A can reconstruct full-scale waveforms with bandwidths as high as 67.5 MHz while operating at an input data rate of 160 MSPS. The 14-bit DAC provides differential current outputs to support differential or single-ended applications. REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The differential current outputs may be fed into a transformer or a differential op amp topology to obtain a single-ended output voltage using an appropriate resistive load. The on-chip band gap reference and control amplifier are configured for maximum accuracy and flexibility. The AD9772A can be driven by the on-chip reference or by a variety of external reference voltages. The full-scale current of the AD9772A can be adjusted over a 2 mA to 20 mA range, thus providing additional gain ranging capabilities. The AD9772A is available in a 48-lead LQFP package and is specified for operation over the industrial temperature range of -40C to +85C.
PRODUCT HIGHLIGHTS
1. A flexible, low power 2 interpolation filter supporting reconstruction bandwidths of up to 67.5 MHz can be configured for a low- or high-pass response with 73 dB of image rejection for traditional baseband or direct IF applications. 2. A zero-stuffing option enhances direct IF applications. 3. A low glitch, fast settling 14-bit DAC provides exceptional dynamic range for both baseband and direct IF waveform reconstruction applications. 4. The AD9772A digital interface, consisting of edge-triggered latches and a flexible differential or single-ended clock input, can support input data rates up to 160 MSPS. 5. On-chip PLL clock multiplier generates all of the internal high speed clocks required by the interpolation filter and DAC. 6. The current output(s) of the AD9772A can easily be configured for various single-ended or differential circuit topologies.
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A. .O. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD9772A-SPECIFICATIONS
DC SPECIFICATIONS
Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) Monotonicity (12-Bit) ANALOG OUTPUT Offset Error Gain Error (without Internal Reference) Gain Error (with Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance (REFLO = 3 V) Small Signal Bandwidth TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (without Internal Reference) Gain Drift (with Internal Reference) Reference Voltage Drift POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD) Analog Supply Current in SLEEP Mode (IAVDD) DVDD1, DVDD2 Voltage Range Digital Supply Current (IDVDD1 + IDVDD2) CLKVDD, PLLVDD4 (PLLVDD = 3.3 V) Voltage Range Clock Supply Current (ICLKVDD + IPLLVDD) CLKVDD (PLLVDD = 0 V) Voltage Range Clock Supply Current (ICLKVDD) Nominal Power Dissipation5 Power Supply Rejection Ratio (PSRR)6 - AVDD Power Supply Rejection Ratio (PSRR)6 - DVDD OPERATING RANGE
NOTES 1Measured at I OUTA driving a virtual ground. 2Nominal full-scale current, I OUTFS, is 32 the IREF current. 3Use an external amplifier to drive any external load. 4Measured at f DATA = 100 MSPS and fOUT = 1 MHz, DIV1, DIV0 = 0 V. 5Measured with PLL enabled at f DATA = 50 MSPS and fOUT = 1 MHz. 6Measured over a 3.0 V to 3.6 V range. Specifications subject to change without notice.
1
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Min 14 3.5 2.0 Guaranteed over Specified Temperature Range -0.025 -2 -5 -1.0 +0.025 +2 +5 +1.25 Typ Max Unit Bits LSB LSB
0.5 1.5 20 200 3 1.20 1
% of FSR % of FSR % of FSR mA V kW pF V A V MW MHz ppm of FSR/C ppm of FSR/C ppm of FSR/C ppm/C
1.14
1.26
0.1
10 0.5 0 50 100 50
1.25
3.1
3.3 34 4.3 3.3 37 3.3 25 3.3 6.0 253
3.5 37 6 3.5 40 3.5 30 3.5 272 +0.6 +0.025 +85
V mA mA V mA V mA V mA mW % of FSR/V % of FSR/V C
3.1 3.1 3.1 -0.6 -0.025 -40
-2-
REV. B
AD9772A DYNAMIC SPECIFICATIONS
Parameter DYNAMIC PERFORMANCE Maximum DAC Output Update Rate (fDAC) Output Settling Time (tST) (to 0.025%) Output Propagation Delay1 (tPD) Output Rise Time (10% to 90%)2 Output Fall Time (10% to 90%)2 Output Noise (IOUTFS = 20 mA) AC LINEARITY--BASEBAND MODE Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS) fDATA = 65 MSPS; fOUT = 1.01 MHz fDATA = 65 MSPS; fOUT = 10.01 MHz fDATA = 65 MSPS; fOUT = 25.01 MHz fDATA = 160 MSPS; fOUT = 5.02 MHz fDATA = 160 MSPS; fOUT = 20.02 MHz fDATA = 160 MSPS; fOUT = 50.02 MHz Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = -6 dBFS) fDATA = 65 MSPS; fOUT1 = 5.01 MHz; fOUT2 = 6.01 MHz fDATA = 65 MSPS; fOUT1 = 15.01 MHz; fOUT2 = 17.51 MHz fDATA = 65 MSPS; fOUT1 = 24.1 MHz; fOUT2 = 26.2 MHz fDATA = 160 MSPS; fOUT1 = 10.02 MHz; fOUT2 = 12.02 MHz fDATA = 160 MSPS; fOUT1 = 30.02 MHz; fOUT2 = 35.02 MHz fDATA = 160 MSPS; fOUT1 = 48.2 MHz; fOUT2 = 52.4 MHz Total Harmonic Distortion (THD) fDATA = 65 MSPS; fOUT = 1.0 MHz; 0 dBFS fDATA = 78 MSPS; fOUT = 10.01 MHz; 0 dBFS Signal-to-Noise Ratio (SNR) fDATA = 65 MSPS; fOUT = 16.26 MHz; 0 dBFS fDATA = 100 MSPS; fOUT = 25.1 MHz; 0 dBFS Adjacent Channel Power Ratio (ACPR) WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing IF = 16 MHz, fDATA = 65.536 MSPS IF = 32 MHz, fDATA = 131.072 MSPS Four-Tone Intermodulation 15.6 MHz, 15.8 MHz, 16.2 MHz, and 16.4 MHz at -12 dBFS fDATA = 65 MSPS, Missing Center AC LINEARITY--IF MODE Four-Tone Intermodulation at IF = 70 MHz 68.1 MHz, 69.3 MHz, 71.2 MHz, and 72.0 MHz at -20 dBFS fDATA = 52 MSPS, fDAC = 208 MHz
NOTES 1Propagation delay is delay from CLK input to DAC update. 2Measured single-ended into 50 W load. Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 doubly terminated, unless otherwise noted.)
Min 400
Typ
Max
Unit MSPS ns ns ns ns pAHz
11 17 0.8 0.8 50
82 75 73 82 75 65 85 75 68 85 70 65 -80 -74 71 71 78 68 88
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dB dB dB dB dBc dBc dBFS
77
dBFS
REV. B
-3-
AD9772A DIGITAL SPECIFICATIONS
Parameter DIGITAL INPUTS Logic 1 Voltage Logic 0 Voltage Logic 1 Current* Logic 0 Current Input Capacitance CLOCK INPUTS Input Voltage Range Common-Mode Voltage Differential Voltage PLL CLOCK ENABLED--FIGURE 1a Input Setup Time (tS), TA = 25C Input Hold Time (tH), TA = 25C Latch Pulsewidth (tLPW), TA = 25C PLL CLOCK DISABLED--FIGURE 1b Input Setup Time (tS), TA = 25C Input Hold Time (tH), TA = 25C Latch Pulsewidth (tLPW), TA = 25C CLK/PLLLOCK Delay (tOD), TA = 25C PLLLOCK (VOH), TA = 25C PLLLOCK (VOL), TA = 25C
Specifications subject to change without notice.
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Min 2.1 -10 -10 Typ 3 0 5 Max Unit V V A A pF V V V ns ns ns ns ns ns ns V V
0.9 +10 +10
0 0.75 0.5 0.5 1.0 1.5 -1.2 3.2 1.5 2.8 3.0
1.5 1.5
3 2.25
3.2 0.3
*MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 A.
DB0-DB13
DB0-DB13
tS
PLLLOCK
tH tOD
tS
CLK+ - CLK-
tH tLPW
CLK+ - CLK-
tLPW
tPD
IOUTA OR IOUTB
tST
0.025% IOUTA OR IOUTB
tPD
tST
0.025%
0.025%
0.025%
Figure 1a. Timing Diagram--PLL Clock Multiplier Enabled
Figure 1b. Timing Diagram--PLL Clock Multiplier Disabled
-4-
REV. B
AD9772A DIGITAL FILTER SPECIFICATIONS
Parameter MAXIMUM INPUT DATA RATE (fDATA) DIGITAL FILTER CHARACTERISTICS Pass-Bandwidth1: 0.005 dB Pass-Bandwidth: 0.01 dB Pass-Bandwidth: 0.1 dB Pass-Bandwidth: -3 dB LINEAR PHASE (FIR IMPLEMENTATION) STOP BAND REJECTION 0.606 fCLOCK to 1.394 fCLOCK GROUP DELAY
2
(TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 doubly terminated, unless otherwise noted.)
Min 150 0.401 0.404 0.422 0.479 Typ Max Unit MSPS fOUT/fDATA fOUT/fDATA fOUT/fDATA fOUT/fDATA
73 11 36 42
dB Input Clocks Input Clocks Input Clocks
IMPULSE RESPONSE DURATION -40 dB -60 dB
NOTES 1Excludes sin(x)/x characteristic of DAC. 2Defined as the number of data clock cycles between impulse input and peak of output response. Specifications subject to change without notice.
0 -20 -40 OUTPUT (dB) -60 -80
Table I. Integer Filter Coefficients for Interpolation Filter (43-Tap Half-Band FIR Filter)
Lower Coefficient H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22)
Upper Coefficient H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23)
Integer Value 10 0 -31 0 69 0 -138 0 248 0 -419 0 678 0 -1083 0 1776 0 -3282 0 10364 16384
-100 -120 -140
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7 FREQUENCY (DC TO fDATA)
0.8
0.9
1.0
Figure 2a. FIR Filter Frequency Response--Baseband Mode
1.0 0.8 NORMALIZED OUTPUT 0.6 0.4 0.2 0 -0.2 -0.4
0
5
10
15
20 25 30 TIME (Samples)
35
40
45
Figure 2b. FIR Filter Impulse Response--Baseband Mode
REV. B
-5-
AD9772A
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD, DVDD1-2, CLKVDD, PLLVDD AVDD, DVDD1-2, CLKVDD, PLLVDD ACOM, DCOM1-2, CLKCOM, PLLCOM REFIO, REFLO, FSADJ, SLEEP IOUTA, IOUTB DB0-DB13, MOD0, MOD1, PLLLOCK CLK+, CLK- DIV0, DIV1, RESET LPF Junction Temperature Storage Temperature Lead Temperature (10 sec)
With Respect to
ACOM, DCOM, CLKCOM, PLLCOM AVDD, DVDD1-2, CLKVDD, PLLVDD ACOM, DCOM1-2, CLKCOM, PLLCOM ACOM ACOM DCOM1-2 CLKCOM CLKCOM PLLCOM
Min
-0.3 -4.0 -0.3 -0.3 -1.0 -0.3 -0.3 -0.3 -0.3 -65
Max
+4.0 +4.0 +0.3 AVDD + 0.3 AVDD + 0.3 DVDD + 0.3 CLKVDD + 0.3 CLKVDD + 0.3 PLLVDD + 0.3 125 +150 300
Unit
V V V V V V V V V C C C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
THERMAL CHARACTERISTIC
Temperature Model Range AD9772AAST -40C to +85C AD9772AASTRL -40C to +85C AD9772A-EB
*ST = Thin Plastic Quad Flatpack.
Package Description 48-Lead LQFP 48-Lead LQFP Evaluation Board
Package Option* ST-48 ST-48
Thermal Resistance
48-Lead LQFP qJA = 91C/W qJC = 28C/W
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9772A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-6-
REV. B
AD9772A
PIN CONFIGURATION
REFLO ACOM IOUTA IOUTB ACOM FSADJ REFIO AVDD ACOM DVDD DCOM 1 DCOM 2 (MSB) DB13 3 DB12 4 DB11 5 DB10 6 DB9 7 DB8 8 DB7 9 DB6 10 DB5 11 DB4 12
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
DVDD AVDD
PIN 1 IDENTIFIER
SLEEP
AD9772A
TOP VIEW (Not to Scale)
LPF PLLVDD 33 PLLCOM 32 CLKVDD
31 30 29 28 27 26 25
CLKCOM CLK- CLK+ DIV0 DIV1 RESET PLLLOCK
(LSB) DB0 MOD0
MOD1 DCOM DCOM DVDD DVDD
DB3
DB2 DB1
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. 1, 2, 19, 20 3 4-15 16 17 18 23, 24 21, 22, 47, 48 25 26 27, 28 29 30 31 32 33 34 35 Mnemonic DCOM DB13 DB12-DB1 DB0 MOD0 MOD1 NC DVDD PLLLOCK RESET DIV1, DIV0 CLK+ CLK- CLKCOM CLKVDD PLLCOM PLLVDD LPF Description Digital Common. Most Significant Data Bit (MSB). Data Bits 1-12. Least Significant Data Bit (LSB). Invokes digital high-pass filter response (i. e., half-wave digital mixing mode). Active high. Invokes Zero-Stuffing Mode. Active high. Note, quarter-wave digital mixing occurs with MOD0 also set high. No Connect, Leave Open. Digital Supply Voltage (3.1 V to 3.5 V). Phase-Lock Loop Lock Signal when PLL clock multiplier is enabled. High indicates PLL is locked to input clock. Provides 1 clock output when PLL clock multiplier is disabled. Maximum fanout is 1 (i.e., <10 pF). Resets internal divider by bringing momentarily high when PLL is disabled to synchronize internal 1 clock to the input data and/or multiple AD9772A devices. DIV1 along with DIV0 sets the PLL's prescaler divide ratio (refer to Table III). Noninverting Input to Differential Clock. Bias to midsupply (i.e., CLKVDD/2). Inverting Input to Differential Clock. Bias to midsupply (i.e., CLKVDD/2). Clock Input Common. Clock Input Supply Voltage (3.1 V to 3.5 V). Phase-Lock Loop Common. Phase-Lock Loop (PLL) Supply Voltage (3.1 V to 3.5 V). To disable PLL clock multiplier, connect PLLVDD to PLLCOM. PLL Loop Filter Node. This pin should be left as a no connect (open) unless the DAC update rate is less than 10 MSPS, in which case a series RC should be connected from LPF to PLLVDD as indicated on the evaluation board schematic. Power-Down Control Input. Active high. Connect to ACOM if not used. Analog Common. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 F capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Analog Supply Voltage (3.1 V to 3.5 V).
36 37, 41, 44 38 39
SLEEP ACOM REFLO REFIO
40 42 43 45, 46
FSADJ IOUTB IOUTA AVDD
REV. B
-7-
NC NC
AD9772A
DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Settling Time
Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition.
Glitch Impulse
DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
A D/A converter is monotonic if the output either increases or remains constant as the digital input increases.
Offset Error
The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s.
Gain Error
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)
The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s.
Output Compliance Range
S/N is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels.
Pass Band
The range of allowable voltage at the output of a currentoutput DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Frequency band in which any input applied therein passes unattenuated to the DAC output.
Stop-band Rejection
Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per C. For reference drift, the drift is reported in ppm per C.
Power Supply Rejection
The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band.
Group Delay
Number of input clocks between an impulse applied at the device input and peak DAC output current.
Impulse Response
Response of the device to an impulse applied to the input.
Adjacent Channel Power Ratio (ACPR)
The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages.
A ratio in dBc between the measured power within a channel relative to its adjacent channel.
CH1 FROM HP8644A SIGNAL GENERATOR CH2
HP8130 PULSE GENERATOR EXT. INPUT
3.3V 1k PLLLOCK MOD0 MOD1 DIV0 RESET DIV1 1k CLKVDD CLKCOM CLK+ CLK- AWG2021 OR DG2020 EXT. CLOCK
AD9772A
PLLCOM LPF PLLVDD IOUTA TO FSEA30 SPECTRUM MINI-CIRCUITS ANALYZER T1-1T 100 IOUTB 0.1F REFIO FSADJ 1.91k
1
1/2
CLOCK DISTRIBUTION AND MODE SELECT FILTER MUX CONTROL CONTROL
PLLCLOCK MULTIPLIER 2/4
DIGITAL DATA
EDGETRIGGERED LATCHES
2 FIR INTERPOLATION FILTER
ZERO STUFF MUX
14-BIT DAC
SLEEP DCOM DVDD 3.3V ACOM AVDD 3.3V
+1.2V REFERENCE AND CONTROL AMP REFLO
50
50 20pF
20pF
Figure 3. Basic AC Characterization Test Setup
-8-
REV. B
Typical Performance Characteristics-AD9772A
(AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA. PLL disabled.)
90 0 IN-BAND OUT-OFBAND 85 80 SFDR (dBc) SFDR (dBc) 75 70 65 60 -80 55 0 20 40 60 80 100 120 50 0 5 10 15 20 25 30 -12dBFS 0dBFS -6dBFS 70 65 60 55 50 45 40 35 30 0 5 10 15 20 25 30 0dBFS -12dBFS -6dBFS
AMPLITUDE (dBm)
-20
-40
-60
-100
fOUT (MHz)
fOUT (MHz)
fOUT (MHz)
TPC 1. Single-Tone Spectral Plot @ fDATA = 65 MSPS with fOUT = fDATA/3
90 0 IN-BAND OUT-OFBAND AMPLITUDE (dBm) -20 SFDR (dBc) 85 80
TPC 2. In-Band SFDR vs. fOUT @ fDATA = 65 MSPS
TPC 3. Out-of-Band SFDR vs. fOUT @ fDATA = 65 MSPS
-6dBFS
70 65 60 AMPLITUDE (dBm) 55 50 45 40 35 30 0dBFS
-6dBFS
75 70 65 60 -12dBFS 0dBFS
-12dBFS
-40
-60
-80
55 50 0 50 100 FREQUENCY (MHz) 150 0 5 10 15 20 25 30 35
-100
0
5
10
15
20
25
30
35
fOUT (MHz)
fOUT (MHz)
TPC 4. Single-Tone Spectral Plot @ fDATA = 78 MSPS with fOUT = fDATA/3
0
TPC 5. In-Band SFDR vs. fOUT @ fDATA = 78 MSPS
TPC 6. Out-of-Band SFDR vs. fOUT @ fDATA = 78 MSPS
90 IN-BAND OUT-OFBAND AMPLITUDE (dBm) 85 80 75 70 65 60 -80 55 -100 0 50 100 150 200 250 FREQUENCY (MHz) 300 50 0 10 20 30 40 50 60 -12dBFS 0dBFS -6dBFS
70 65 60 AMPLITUDE (dBm) 55 50 45 40 35 30 0 10 20 30 40 50 60 70 -12dBFS -6dBFS 0dBFS
AMPLITUDE (dBm)
-20
-40
-60
fOUT (MHz)
fOUT (MHz)
TPC 7. Single-Tone Spectral Plot @ fDATA = 160 MSPS with fOUT = fDATA/3
TPC 8. In-Band SFDR vs. fOUT @ fDATA = 160 MSPS
TPC 9. Out-of-Band SFDR vs. fOUT @ fDATA = 160 MSPS
REV. B
-9-
AD9772A
90 85 80 IMD (dBc) IMD (dBc) 75 70 65 60 55 50 0 5 10 15 20 25 30 -3dBFS -6dBFS 90 85 80 75 70 65 60 55 50 0 5 10 15 20 25 30 35 0dBFS -6dBFS 90 85 -3dBFS IMD (dBc) 80 75 70 65 60 55 50 0 10 20 30 40 50 60 70 0dBFS -6dBFS
-3dBFS
0dBFS
fOUT (MHz)
fOUT (MHz)
fOUT (MHz)
TPC 10. Third Order IMD Products vs. fOUT @ fDATA = 65 MSPS
TPC 11. Third Order IMD Products vs. fOUT @ fDATA = 78 MSPS
TPC 12. Third Order IMD Products vs. fOUT @ fDATA = 160 MSPS
90 85
90
90
fDATA = 65MSPS
80 IMD (dBc)
fDATA = 160MSPS
85 80
fDATA = 78MSPS
85 80 SFDR (dBc) 75 0dBFS 70 65 60 55 50 3.0
-3dBFS
IMD (dBc)
75 70 65 60
75 70 65 60 -20
fDATA = 78MSPS
fDATA = 160MSPS
-6dBFS
fDATA = 65MSPS
55 50 -20
-15
-10 AOUT (dBFS)
-5
0
-15
-10 AOUT (dBFS)
-5
0
3.1
3.2 3.3 3.4 AVDD (Volts)
3.5
3.6
TPC 13. Third Order IMD Products vs. AOUT @ fOUT = fDAC/11
TPC 14. Third Order IMD Products vs. AOUT @ fOUT = fDAC/5
TPC 15. SFDR vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS
90 0dBFS 85 80 IMD (dBc) -6dBFS SNR (dBc) 75 70 65 60 55 50 3.0 -3dBFS
90 85 80 PLL OFF SFDR (dBc) 75 70 65 60 55 50 25 75
90 85 80 75 70 65 60 55 50 -40
fDATA = 78MSPS
fDATA = 65MSPS
fDATA = 160MSPS
PLL ON, OPTIMUM DIV0/1 SETTINGS
3.1
3.2 3.3 3.4 AVDD (Volts)
3.5
3.6
125
175
-20
0
20
40
60
80
fDAC (MHz)
TEMPERATURE (C)
TPC 16. Third Order IMD Products vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS
TPC 17. SNR vs. fDAC @ fOUT = 10 MHz
TPC 18. In-Band SFDR vs. Temperature @ fOUT = fDATA/11
-10-
REV. B
AD9772A
FUNCTIONAL DESCRIPTION Table II. Digital Modes Digital Mode MOD0 MOD1 Digital Filter ZeroStuffing
Figure 4 shows a simplified block diagram of the AD9772A. The AD9772A is a complete, 2 oversampling, 14-bit DAC that includes a 2 interpolation filter, a phase-locked loop (PLL) clock multiplier, and a 1.20 V band gap voltage reference. While the AD9772A's digital interface can support input data rates as high as 160 MSPS, its internal DAC can operate up to 400 MSPS, thus providing direct IF conversion capabilities. The 14-bit DAC provides two complementary current outputs whose full-scale current is determined by an external resistor. The AD9772A features a flexible, low jitter, differential clock input, providing excellent noise rejection while accepting a sine wave input. An on-chip PLL clock multiplier produces all of the necessary synchronized clocks from an external reference clock source. Separate supply inputs are provided for each functional block to ensure optimum noise and distortion performance. A SLEEP mode is also included for power savings.
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1 CLK+ CLK- 1 1/2
Baseband Baseband Direct IF Direct IF
0 0 1 1
0 1 0 1
Low Low High High
No Yes No Yes
AD9772A
CLOCK DISTRIBUTION AND MODE SELECT FILTER MUX CONTROL CONTROL PLL CLOCK MULTIPLIER 2/4
PLLCOM LPF PLLVDD
Applications requiring the highest dynamic range over a wide bandwidth should consider operating the AD9772A in a baseband mode. Note, the zero-stuffing option can also be used in this mode, however, the ratio of signal to image power will be reduced. Applications requiring the synthesis of IF signals should consider operating the AD9772A in a Direct IF mode. In this case, the zero-stuffing option should be considered when synthesizing and selecting IFs beyond the input data rate, fDATA. If the reconstructed IF falls below fDATA, the zero-stuffing option may or may not be beneficial. Note, the dynamic range (i.e., SNR/ SFDR) is also optimized by disabling the PLL clock multiplier (i.e., PLLVDD to PLLCOM) and by using an external low jitter clock source operating at the DAC update rate, fDAC.
2 Interpolation Filter Description
DATA INPUTS (DB13... DB0) SLEEP
EDGETRIGGERED LATCHES
2 FIR INTERPOLATION FILTER
ZERO STUFF MUX
14-BIT DAC
IOUTA IOUTB REFIO FSADJ
+1.2V REFERENCE AND CONTROL AMP DCOM DVDD ACOM AVDD REFLO
Figure 4. Functional Block Diagram
Preceding the 14-bit DAC is a 2 digital interpolation filter that can be configured for a low-pass (i.e., baseband mode) or highpass (i.e., direct IF mode) response. The input data is latched into the edge-triggered input latches on the rising edge of the differential input clock as shown in Figure 1a and then interpolated by a factor of 2 by the digital filter. For traditional baseband applications, the 2 interpolation filter has a low-pass response. For direct IF applications, the filter's response can be converted into a high-pass response to extract the higher image. The output data of the 2 interpolation filter can update the 14-bit DAC directly or undergo a zero-stuffing process to increase the DAC update rate by another factor of 2. This action enhances the relative signal level and pass-band flatness of the higher images.
DIGITAL MODES OF OPERATION
The 2 interpolation filter is based on a 43-tap half-band symmetric FIR topology that can be configured for a low- or high-pass response, depending on the state of the MOD0 control input. The low-pass response is selected with MOD0 low while the high-pass response is selected with MOD0 high. The low-pass frequency and impulse response of the halfband interpolation filter are shown in Figures 2a and 2b, while Table I lists the idealized filter coefficients. Note that a FIR filter's impulse response is also represented by its idealized filter coefficients. The 2 interpolation filter essentially multiplies the input data rate to the DAC by a factor of 2, relative to its original input data rate, while reducing the magnitude of the first image associated with the original input data rate occurring at fDATA - fFUNDAMENTAL. Note, as a result of the 2 interpolation, the digital filter's frequency response is uniquely defined over its Nyquist zone of dc to fDATA, with mirror images occurring in adjacent Nyquist zones. The benefits of an interpolation filter are clearly seen in Figure 5, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to the 2 digital interpolation filter in a low-pass configuration. Images of the sine wave signal appear around multiples of the DAC's input data rate (i.e., fDATA) as predicted by sampling theory. These undesirable images will also appear at the output of a reconstruction DAC, although attenuated by the DAC's sin(x)/x roll-off response. In many band-limited applications, the images from the reconstruction process must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. Adding to the complexity of this analog filter may be the requirement of compensating for the DAC's sin(x)/x response.
The AD9772A features four different digital modes of operation controlled by the digital inputs, MOD0 and MOD1. MOD0 controls the 2 digital filter's response (i.e., low-pass or highpass), while MOD1 controls the zero-stuffing option. The selected mode as shown in Table II will depend on whether the application requires the reconstruction of a baseband or IF signal.
REV. B
-11-
AD9772A
Referring to Figure 5, the new first image associated with the DAC's higher data rate after interpolation is pushed out further relative to the input signal, since it now occurs at 2 fDATA - fFUNDAMENTAL. The old first image associated with the lower DAC data rate before interpolation is suppressed by the digital filter. As a result, the transition band for the analog reconstruction filter is increased, thus reducing the complexity of the analog filter. Furthermore, the sin(x)/x roll-off over the original input data pass band (i.e., dc to fDATA/2) is significantly reduced. As previously mentioned, the 2 interpolation filter can be converted into a high-pass response, thus suppressing the fundamental while passing the original first image occurring at fDATA - fFUNDAMENTAL. Figure 6 shows the time and frequency representation for a high-pass response of a discrete time sine wave. This action can also be modeled as a 1/2 wave digital mixing process in which the impulse response of the low-pass filter is digitally mixed with a square wave having a frequency of exactly fDATA/2. Since the even coefficients have a zero value (refer to Table I), this process simplifies into inverting the center coefficient of the low-pass filter (i.e., invert H(18)). Note that this also corresponds to inverting the peak of the impulse response shown in Figure 2a. The resulting high-pass frequency response becomes the frequency inverted mirror image of the low-pass filter response shown in Figure 2b. It is worth noting that the new first image now occurs at fDATA + fFUNDAMENTAL. A reduced transition region of 2 fFUNDAMENTAL exists for image selection, thus mandating that the fFUNDAMENTAL be placed sufficiently high for practical filtering purposes in direct IF applications. Also, the lower side-band images occurring at fDATA - fFUNDAMENTAL and its multiples (i.e., N fDATA - fFUNDAMENTAL) experience a frequency inversion while the upper sideband images occurring at fDATA + fFUNDAMENTAL and its multiples (i.e., N fDATA + fFUNDAMENTAL) do not.
TIME DOMAIN 1/ f DATA
1/ 2 fDATA
fFUNDAMENTAL
1ST IMAGE
fFUNDAMENTAL DIGITAL
FILTER RESPONSE
NEW 1ST IMAGE
DAC'S SIN (X)/X RESPONSE
FREQUENCY DOMAIN
fDATA
2fDATA fDATA SUPPRESSED 1ST IMAGE
2fDATA
fDATA
2fDATA
INPUT DATA LATCH
2 INTERPOLATION FILTER 2 2 fDATA
DAC
fDATA
Figure 5. Time and Frequency Domain Example of Low-Pass 2 Digital Interpolation Filter
1/ 2 fDATA
TIME DOMAIN 1/ f DATA
fFUNDAMENTAL
1ST IMAGE
UPPER AND LOWER IMAGE
DIGITAL FILTER RESPONSE
DAC'S SIN (X)/X RESPONSE
FREQUENCY DOMAIN
fDATA
2fDATA SUPPRESSED
fDATA
2fDATA
fDATA
2fDATA
fFUNDAMENTAL
INPUT DATA LATCH
2 INTERPOLATION FILTER 2 2 fDATA
DAC
fDATA
Figure 6. Time and Frequency Domain Example of High-Pass 2 Digital Interpolation Filter
-12-
REV. B
AD9772A
Zero-Stuffing Option Description
As shown in Figure 7, a zero or null in the frequency responses (after interpolation and DAC reconstruction) occurs at the final DAC update rate (i.e., 2 fDATA) due to the DAC's inherent sin(x)/x roll-off response. In baseband applications, this roll-off in the frequency response may not be as problematic since much of the desired signal energy remains below fDATA/2 and the amplitude variation is not as severe. However, in direct IF applications interested in extracting an image above fDATA/2, this roll-off may be problematic due to the increased pass-band amplitude variation as well as the reduced signal level of the higher images.
0
in Figure 7. Note that if the 2 interpolation filter's high-pass response is also selected, this action can be modeled as a 1/4 wave digital mixing process, since this is equivalent to digitally mixing the impulse response of the low-pass filter with a square wave having a frequency of exactly fDATA (i.e., fDAC/4). It is important to realize that the zero-stuffing option by itself does not change the location of the images but rather their signal level, amplitude flatness, and relative weighting. For instance, in the previous example, the pass-band amplitude flatness of the lower and upper side-band images centered around fDATA are improved to 0.14 dB and 0.24 dB, respectively, while the signal level has changed to -6.5 dBFS and -7.5 dBFS. The lower or upper side-band image centered around 3 fDATA will exhibit an amplitude flatness of 0.77 dB and 1.29 dB with signal levels of approximately -14.3 dBFS and -19.2 dBFS.
PLL CLOCK MULTIPLIER OPERATION
-10
WITH ZERO-STUFFING
dBFS
WITHOUT ZERO-STUFFING -20
-30
-40
0
0.5
1.0
BASEBAND REGION
1.5 2.0 2.5 FREQUENCY (fDATA)
3.0
3.5
4.0
Figure 7. Effects of Zero-Stuffing on DAC's Sin(x)/x Response
For instance, if the digital data into the AD9772A represented a baseband signal centered around fDATA/4 with a pass band of fDATA/10, the reconstructed baseband signal out of the AD9772A would experience only a 0.18 dB amplitude variation over its pass band with the first image occurring at 7/4 fDATA with 17 dB of attenuation relative to the fundamental. However, if the high-pass filter response was selected, the AD9772A would now produce pairs of images at [(2N + 1) fDATA] fDATA/4 where N = 0, 1. . . Note, due to the DAC's sin(x)/x response, only the lower or upper side-band images centered around fDATA may be useful, although they would be attenuated by -2.1 dB and -6.54 dB, respectively, as well as experience a pass-band amplitude roll-off of 0.6 dB and 1.3 dB. To improve upon the pass-band flatness of the desired image and/or to extract higher images (i.e., 3 fDATA fFUNDAMENTAL) the zero-stuffing option should be employed by bringing the MOD1 pin high. This option increases the effective DAC update rate by another factor of 2 since a midscale sample (i.e., 10 0000 0000 0000) is inserted after every data sample originating from the 2 interpolation filter. A digital multiplexer switching at a rate of 4 fDATA between the interpolation filter's output and a data register containing the midscale data sample is used to implement this option as shown in Figure 6. Therefore, the DAC output is now forced to return to its differential midscale current value (i.e., IOUTA - IOUTB @ 0 mA) after reconstructing each data sample from the digital filter. The net effect is to increase the DAC update rate such that the zero in the sin(x)/x frequency response now occurs at 4 fDATA along with a corresponding reduction in output power as shown REV. B
The phase-lock loop (PLL) clock multiplier circuitry, along with the clock distribution circuitry, can produce the necessary internally synchronized 1, 2, and 4 clocks for the edge triggered latches, 2 interpolation filter, zero-stuffing multiplier, and DAC. Figure 8 shows a functional block diagram of the PLL clock multiplier, which consists of a phase detector, a charge pump, a voltage controlled oscillator (VCO), a prescaler, and digital control inputs/outputs. The clock distribution circuitry generates all the internal clocks for a given mode of operation. The charge pump and VCO are powered from PLLVDD, while the differential clock input buffer, phase detector, prescaler, and clock distribution circuitry are powered from CLKVDD. To ensure optimum phase noise performance from the PLL clock multiplier and clock distribution circuitry, PLLVDD and CLKVDD must originate from the same clean analog supply.
CLK+ CLK- CLKVDD PLLLOCK + -
AD9772A
PHASE DETECTOR EXT/INT CLOCK CONTROL CLOCK DISTRIBUTION
CHARGE PUMP
LPF PLL VDD
DNC
OUT1
2.7V TO 3.6V
PRESCALER
VCO
PLL COM
RESET
MOD1
MOD0
DIV1
CLKCOM
Figure 8. Clock Multiplier with PLL Clock Multiplier Enabled
The PLL clock multiplier has two modes of operation. It can be enabled for less demanding applications, providing a reference clock meeting the minimum specified input data rate of 6 MSPS. It can be disabled for applications below this data rate or for applications requiring higher phase noise performance. In this case, a reference clock at twice the input data rate (i.e., 2 fDATA) must be provided without the zero-stuffing option selected and four -13-
DIV0
AD9772A
times the input data rate (i.e., 4 fDATA) with the zero-stuffing option selected. Note, multiple AD9772A devices can be synchronized in either mode if driven by the same reference clock, since the PLL clock multiplier when enabled ensures synchronization. RESET can be used for synchronization if the PLL clock multiplier is disabled. Figure 8 shows the proper configuration used to enable the PLL clock multiplier. In this case, the external clock source is applied to CLK+ (and/or CLK-) and the PLL clock multiplier is fully enabled by connecting PLLVDD to CLKVDD. The settling/acquisition time characteristics of the PLL are also dependent on the divide-by-N ratio as well as the input data rate. In general, the acquisition time increases with increasing data rate (for fixed divide-by-N ratio) or increasing divide-by-N ratio (for fixed input data rate). Since the VCO can operate over a 96 MHz to 400 MHz range, the prescaler divide-by-ratio following the VCO must be set according to Table III for a given input data rate (i.e., fDATA) to ensure optimum phase noise and successful locking. In general, the best phase noise performance for any prescaler setting is achieved with the VCO operating near its maximum output frequency of 400 MHz. Note, the divide-by-N ratio also depends on whether the zero-stuffing option is enabled since this option requires the DAC to operate at 4 the input data rate. The divide-by-N ratio is set by DIV1 and DIV0. With the PLL clock multiplier enabled, PLLLOCK serves as an active high control output that may be monitored upon system power-up to indicate that the PLL is successfully locked to the input clock. Note, when the PLL clock multiplier is not locked, PLLLOCK will toggle between logic high and low in an asynchronous manner until locking is finally achieved. As a result, it is recommended that PLLLOCK, if monitored, be sampled several times to detect proper locking 100 ms after power-up.
Table III. Recommended Prescaler Divide-by-N Ratio Settings
The effects of phase noise on the AD9772A's SNR performance become more noticeable at higher reconstructed output frequencies and signal levels. Figure 9 compares the phase noise of a full-scale sine wave at exactly fDATA/4 at different data rates (therefore carrier frequency) with the optimum DIV1, DIV0 setting. The effects of phase noise, and its effect on a signal's CNR performance, become even more evident at higher IF frequencies as shown in Figure 10. In both instances, it is the narrow-band phase noise that limits the CNR performance.
0 -10 -20
NOISE DENSITY (dBm/Hz)
-30 -40 -50 -60 -70 -80 -90 -100 -110
PLL ON, fDATA = 160MSPS PLL ON, fDATA = 100MSPS PLL ON, fDATA = 75MSPS PLL ON, fDATA = 50MSPS
PLL OFF, fDATA = 50MSPS
0
1
2 3 FREQUENCY OFFSET (MHz)
4
5
Figure 9. Phase Noise of PLL Clock Multiplier at Exact fOUT = fDATA/4 at Different fDATA Settings with Optimum DIV0/DIV1 Settings Using R & S FSEA30, RBW = 30 kHz
10
-10
AMPLITUDE (dBm)
-30
-50
fDATA (MSPS) 48-160 24-100 12-50 6-25 24-100 12-50 6-25 3-12.5
MOD1 0 0 0 0 1 1 1 1
DIV1 0 0 1 1 0 0 1 1
DIV0 0 1 0 1 0 1 0 1
Divide-by-N Ratio 1 2 4 8 1 2 4 8
-70
-90
-110 120
122
124 126 FREQUENCY (MHz)
128
130
Figure 10. Direct IF Mode Reveals Phase Noise Degradation with and without PLL Clock Multiplier (IF = 125 MHz and fDATA = 100 MSPS)
As stated earlier, applications requiring input data rates below 6 MSPS must disable the PLL clock multiplier and provide an external reference clock. However, applications already containing a low phase noise (i.e., jitter) reference clock that is twice (or four times) the input data rate should consider disabling the PLL clock multiplier to achieve the best SNR performance from the AD9772A. Note that the SFDR performance and wideband noise performance of the AD9772A remain unaffected with or without the PLL clock multiplier enabled.
To disable the PLL clock multiplier, connect PLLVDD to PLLCOM as shown in Figure 11. LPF may remain open since this portion of the PLL circuitry is now disabled. The differential clock input should be driven with a reference clock twice the data input rate in baseband applications and four times the data input rate in direct IF applications in which the 1/4 wave mixing option is employed (i.e., MOD1 and MOD0 active high). The clock distribution circuitry remains enabled providing a 1 internal clock at PLLLOCK. Digital input data is latched into the AD9772 on every other rising edge of the differential clock input. The rising
-14-
REV. B
AD9772A
edge that corresponds to the input latch immediately precedes the rising edge of the 1 clock at PLLLOCK. Adequate setup and hold time for the input data as shown in Figure 1b should be allowed. Note that enough delay is present between CLK+/ CLK- and the data input latch to cause the minimum setup time for input data to be negative. This is noted in the Digital Specifications section. PLLLOCK contains a relatively weak driver output, with its output delay (tOD) sensitive to output capacitance loading. Thus PLLLOCK should be buffered for fanouts greater than 1, and/or load capacitance greater than 10 pF. If a data timing issue exists between the AD9772A and its external driver device, the 1 clock appearing at PLLLOCK can be inverted via an external gate to ensure proper setup and hold time.
CLK+ CLK- CLKVDD PLLLOCK + - DIGITAL DATA IN EXTERNAL 2 CLK DELAYED INTERNAL 1 CLK LOAD DEPENDENT DELAYED 1 CLK AT PLLLOCK IOUTA OR IOUTB DATA
t LPW
t PD
t PD
tD
DATA ENTERS INPUT LATCHES ON THIS EDGE
Figure 12. Internal Timing of AD9772A with PLL Disabled
AD9772A
PHASE DETECTOR EXT/INT CLOCK CONTROL CLOCK DISTRIBUTION
CHARGE PUMP
LPF
OUT1
PLL VDD
PRESCALER
VCO
PLL COM
Figures 13a and 13b illustrate the details of the RESET function timing. RESET going from a high to a low logic level enables the 1 clock output, generated by the PLLLOCK pin. If RESET goes low at a time well before the rising edge of the 2 clock as shown in Figure 13a, then PLLLOCK will go high on the following edge of the 2 clock. If RESET goes from a high to a low logic level 600 ps or later following the rising edge of the 2 clock as shown in Figure 13b, there will be a delay of one 2 clock cycle before PLLLOCK goes high. In either case, as long as RESET remains low, PLLLOCK will change state on every rising edge of the 2 clock. As stated before, it is the rising edge of the 2 clock that immediately precedes the rising edge of PLLLOCK that latches data into the AD9772A input latches.
[T ] EXTERNAL 2 CLOCK 1 T
CLKCOM MOD1 MOD0 RESET DIV1 DIV0
Figure 11. Clock Multiplier with PLL Clock Multiplier Disabled SYNCHRONIZATION OF CLK/DATA USING RESET WITH PLL DISABLED
2
T T
PLLLOCK
The relationship between the internal and external clocks in this mode is shown in Figure 12. A clock at the output update data rate (2 the input data rate) must be applied to the CLK inputs. Internal dividers create the internal 1 clock necessary for the input latches. With the PLL disabled, a delayed version of the 1 clock is present at the PLLLOCK pin. The DAC latch is updated on the particular rising edge of the external 2 clock, which corresponds to the rising edge of the 1 clock. Updates to the input data should be synchronized to this specific rising edge as shown in Figure 12. To ensure this synchronization, a Logic 1 should be momentarily applied to the RESET pin on power-up, before CLK is applied. Applying a momentary Logic 1 to RESET brings the 1 clock at PLLLOCK to a Logic 1. On the next rising edge of the 2 clock, the 1 clock will go to Logic 0. The following rising edge of the 2 clock will cause the 1 clock to go to Logic 1 again, as well as update the data in both of the input latches.
3 CH1 2.00V CH2 2.00V M 10.0ns CH3 2.00V
RESET
Figure 13a. RESET Timing with PLL Disabled
[T ] EXTERNAL 2 CLOCK 1 T PLLLOCK 2 T T
3 CH1 2.00V CH2 2.00V M 10.0ns CH4 CH3 2.00V 1.20V
RESET
Figure 13b. RESET Timing with PLL Disabled and Insufficient Set-Up Time
REV. B
-15-
AD9772A
DAC OPERATION
The 14-bit DAC along with the 1.2 V reference and reference control amplifier is shown in Figure 14. The DAC consists of a large PMOS current source array capable of providing up to 20 mA of full-scale current, IOUTFS. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits, or middle bits, consist of 15 equal current sources whose values are 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits' current sources. All of these current sources are switched to one or the other of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC's high output impedance.
2.7V TO 3.6V
As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO, and external resistor, RSET. It can be expressed as IOUTFS = 32 x IREF where: IREF = VREFIO /RSET (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note that RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 W or 75 W cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply VOUTA = IOUTA x RLOAD VOUTB = IOUTB x RLOAD (5) (6) (3)
REFLO +1.2V REF REFIO 0.1F RSET 2k FSADJ IREF SEGMENTED SWITCHES 250pF
AVDD
ACOM
CURRENT SOURCE ARRAY IOUTA LSB SWITCHES IOUTB IOUTA VDIFF = VOUTA - VOUTB RLOAD RLOAD
Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range of 1.25 V to prevent signal compression. To maintain optimum distortion and linearity performance, the maximum voltages at VOUTA and VOUTB should not exceed 500 mV p-p. The differential voltage, VDIFF, appearing across IOUTA and IOUTB, is VDIFF = IOUTA - IOUTB x RLOAD Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be expressed as VDIFF = 2 DAC CODE - 16383 /16384 x
IOUTB
AD9772A
INTERPOLATED DIGITAL DATA
(
)
(7)
Figure 14. Block Diagram of Internal DAC, 1.2 V Reference, and Reference Control Circuits
The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET, as shown in Figure 14. RSET, in combination with both the reference control amplifier and voltage reference, REFIO, sets the reference current, IREF, which is mirrored to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is exactly 32 times the value of IREF.
DAC TRANSFER FUNCTION
(32 R
[(
LOAD /RSET
) xV
)
]
REFIO
(8)
The last two equations highlight some of the advantages of operating the AD9772A differentially. First, the differential operation will help cancel common-mode error sources such as noise, distortion, and dc offsets associated with IOUTA and IOUTB. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the singleended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9772A can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8.
REFERENCE OPERATION
The AD9772A provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 16383) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as IOUTA = DAC CODE/16384 x IOUTFS IOUTB
( ) = (16383 - DAC CODE ) /16384 x I
(1)
OUTFS
(2)
where DAC CODE = 0 to 16383 (i.e., decimal representation).
The AD9772A contains an internal 1.20 V band gap reference that can easily be disabled and overridden by an external reference. REFIO serves as either an output or input, depending on whether the internal or external reference is selected. If REFLO is tied to ACOM, as shown in Figure 15, the internal reference is activated, and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 F or greater from REFIO to REFLO. If any additional loading is required, REFIO should be buffered with an external amplifier having an input bias current less than 100 nA. REV. B
-16-
AD9772A
OPTIONAL EXTERNAL REF BUFFER REFLO +1.2V REF ADDITIONAL LOAD REFIO 0.1F 2k FSADJ 250pF CURRENT SOURCE ARRAY 10k 1.2V REFLO 2.7V TO 3.6V AVDD
the input impedance of REFIO does interact and load the digital potentiometer wiper to create a slight nonlinearity in the programmable voltage divider ratio, a digital potentiometer with 10 kW or less resistance is recommended.
2.7V TO 3.6V
AD9772A
AD1580
AVDD 250pF CURRENT SOURCE ARRAY
AD5220
10k
+1.2V REF REFIO FSADJ
Figure 15. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external 1.2 V reference such as the AD1580 may then be applied to REFIO as shown in Figure 16. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is disabled, and the high input impedance of REFIO minimizes any loading of the external reference.
2.7V TO 3.6V
RSET
AD9772A
Figure 17. Single-Supply Gain Control Circuit ANALOG OUTPUTS
10k VREFIO
REFLO +1.2V REF REFIO FSADJ 250pF
AVDD
AD1580
RSET IREF = VREFIO /RSET
CURRENT SOURCE ARRAY
The AD9772A produces two complementary current outputs, IOUTA and IOUTB, which may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section, by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Figure 18 shows the equivalent analog output circuit of the AD9772A, which consists of a parallel combination of PMOS differential current switches associated with each segmented current source. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches and is typically 200 kW in parallel with 3 pF. Due to the nature of a PMOS device, the output impedance is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) and, to a lesser extent, the analog supply voltage, AVDD, and full-scale current, IOUTFS. Although the output impedance's signal dependency can be a source of dc nonlinearity and ac linearity (i.e., distortion), its effects can be limited if certain precautions are noted.
AVDD
AD9772A
REFERENCE CONTROL AMPLIFIER
Figure 16. External Reference Configuration REFERENCE CONTROL AMPLIFIER
The AD9772A also contains an internal control amplifier that is used to regulate the DAC's full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 16, such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scaling factor to set IOUTFS as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9772's DAC, which is proportional to IOUTFS (refer to the Power Dissipation section). The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. IREF can be controlled using the single-supply circuit shown in Figure 17 for a fixed RSET. In this example, the internal reference is disabled, and the voltage of REFIO is varied over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply DAC or digital potentiometer, thus allowing IREF to be digitally controlled for a fixed RSET. This particular example shows the AD5220, an 8-bit serial input digital potentiometer, along with the AD1580 voltage reference. Note, since REV. B
AD9772A
IOUTA RLOAD
IOUTB RLOAD
Figure 18. Equivalent Analog Output Circuit
IOUTA and IOUTB also have a negative and positive voltage compliance range. The negative output compliance range of -1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9772A. The positive output compliance range is -17-
AD9772A
slightly dependent on the full-scale output current, IOUTFS. Operation beyond the positive compliance range will induce clipping of the output signal, which severely degrades the AD9772A's linearity and distortion performance. Operating the AD9772A with reduced voltage output swings at IOUTA and IOUTB in a differential or single-ended output configuration reduces the signal dependency of its output impedance, thus enhancing distortion performance. Although the voltage compliance range of IOUTA and IOUTB extends from -1.0 V to +1.25 V, optimum distortion performance is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed approximately 0.5 V. A properly selected transformer with a grounded center tap will allow the AD9772A to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at IOUTA and IOUTB. DC-coupled applications requiring a differential or single-ended output configuration should size RLOAD accordingly. Refer to Applying the AD9772A Output Configurations section for examples of various output configurations. The most significant improvement in the AD9772A's distortion and noise performance is realized using a differential output configuration. The common-mode error sources of both IOUTA and IOUTB can be substantially reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the reconstructed waveform's frequency content increases and/or its amplitude decreases. The distortion and noise performance of the AD9772A is also dependent on the fullscale current setting, IOUTFS. Although IOUTFS can be set between 2 mA and 20 mA, selecting an IOUTFS of 20 mA will provide the best distortion and noise performance. In summary, the AD9772A achieves the optimum distortion and noise performance under the following conditions: 1. Positive voltage swing at IOUTA and IOUTB limited to 0.5 V. 2. Differential operation. 3. IOUTFS set to 20 mA. 4. PLL clock multiplier disabled. Note that the majority of the ac characterization curves for the AD9772A are performed under the above-mentioned operating conditions.
DIGITAL INPUTS/OUTPUTS
The digital interface is implemented using an edge-triggered master slave latch and is designed to support an input data rate as high as 160 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth as shown in Figures 1a and 1b. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met. The digital inputs (excluding CLK+ and CLK-) are CMOS compatible with its logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (i.e., DVDD or CLKVDD) or VTHRESHOLD = DVDD 2 ( 20%) The internal digital circuitry of the AD9772A is capable of operating over a digital supply range of 3.1 V to 3.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers VOH(MAX). Although a DVDD of 3.3 V will typically ensure proper compatibility with most TTL logic families, series 200 W resistors are recommended between the TTL logic driver and digital inputs to limit the peak current through the ESD protection diodes if VOH(MAX) exceeds DVDD by more than 300 mV. Figure 19 shows the equivalent digital input circuit for the data and control inputs.
DVDD
DIGITAL INPUT
Figure 19. Equivalent Digital Input
The AD9772A features a flexible differential clock input operating from separate supplies (i.e., CLKVDD, CLKCOM) to achieve optimum jitter performance. The two clock inputs, CLK+ and CLK-, can be driven from a single-ended or differential clock source. For single-ended operation, CLK+ should be driven by a single-ended logic source while CLK- should be set to the logic source's threshold voltage via a resistor divider/capacitor network referenced to CLKVDD as shown in Figure 20. For differential operation, both CLK+ and CLK- should be biased to CLKVDD/2 via a resistor divider network as shown in Figure 21. An RF transformer as shown in Figure 3 can also be used to convert a single-ended clock input to a differential clock input.
AD9772A
RSERIES CLK+ CLKVDD 1k VTHRESHOLD CLK- 1k 0.1F CLKCOM
The AD9772A consists of several digital input pins used for data, clock, and control purposes. It also contains a single digital output pin, PLLLOCK, which is used to monitor the status of the internal PLL clock multiplier or provide a 1 clock output. The 14-bit parallel data inputs follow standard positive binary coding, where DB13 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code.
Figure 20. Single-Ended Clock Interface
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REV. B
AD9772A
AD9772A
0.1F 1k CLK+ 1k ECL/PECL 1k CLK- 0.1F 1k CLKCOM IDVDD (mA) 0.1F CLKVDD 100 90 80 70 60 50 40 30 20
fDATA = 160MSPS fDATA = 125MSPS fDATA = 100MSPS
fDATA = 65MSPS fDATA = 50MSPS fDATA = 25MSPS
Figure 21. Differential Clock Interface
10 0 0.0 0.1
The quality of the clock and data input signals are important in achieving the optimum performance. The external clock driver circuitry should provide the AD9772A with a low jitter clock input, which meets the min/max logic levels while providing fast edges. Although fast clock edges help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform, the high gain-bandwidth product of the AD9772A's differential comparator can tolerate sine wave inputs as low as 0.5 V p-p, with minimal degradation in its output noise floor. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 50 W to 200 W) between the AD9772A digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough.
SLEEP MODE OPERATION
CURRENT (mA)
0.2 0.3 RATIO (fOUT/f DATA)
0.4
0.5
Figure 22. IDVDD vs. Ratio @ DVDD = 3.3 V
25 ICLKVDD IPLLVDD 15
20
10
5
The AD9772A has a SLEEP function that turns off the output current and reduces the analog supply current to less than 6 mA over the specified supply range of 3.1 V to 3.5 V. This mode can be activated by applying a Logic Level 1 to the SLEEP pin. The AD9772A takes less than 50 ns to power down and approximately 15 s to power back up.
POWER DISSIPATION
0
0
50
100
150
200
fDATA (MSPS)
Figure 23. IPLLVDD and ICLKVDD vs. fDATA APPLYING THE AD9772A OUTPUT CONFIGURATIONS
The power dissipation, PD, of the AD9772A is dependent on several factors, including 1. AVDD, PLLVDD, CLKVDD, and DVDD, the power supply voltages. 2. IOUTFS, the full-scale current output. 3. fDATA, the update rate. 4. The reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, and is not sensitive to fDATA. Conversely, IDVDD is dependent on both the digital input waveform and fDATA. Figure 22 shows IDVDD as a function of full-scale sine wave output ratios (fOUT/fDATA) for various update rates with DVDD = 3 V. The supply current from CLKVDD and PLLVDD is relatively insensitive to the digital input waveform, but directly proportional to the update rate as shown in Figure 23.
The following sections illustrate some typical output configurations for the AD9772A. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA for optimum performance. For applications requiring the optimum dynamic performance, a differential output configuration is highly recommended. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level-shifting. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground.
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AD9772A
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differentialto-single-ended signal conversion as shown in Figure 24. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only and its linearity performance degrades at the low end of its frequency range due to core saturation.
AD9772A
IOUTA MINI-CIRCUITS T1-1T OPTIONAL RDIFF IOUTB RLOAD
The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8055 is configured to provide some additional signal gain. The op amp must operate from a dual supply since its output is approximately 1.0 V. A high speed amplifier, capable of preserving the differential performance of the AD9772A while meeting other system level objectives (i.e., cost, power), should be selected. The op amp's differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 26 provides the necessary level shifting required in a single-supply system. In this case, AVDD, the positive analog supply for both the AD9772A and the op amp, is also used to level-shift the differential output of the AD9772A to midsupply (i.e., AVDD/2). The AD8057 is a suitable op amp for this application.
AD9772A
IOUTA IOUTB 225 225 COPT 25 25 1k 500
AD8057
1k AVDD
Figure 24. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9772A. A differential resistor, RDIFF, may be inserted into applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination that results in a low VSWR (Voltage Standing Wave Ratio). Note that approximately half the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
Figure 26. Single-Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT
An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 25. The AD9772A is configured with two equal load resistors, RLOAD, of 25 W. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DAC's high slewing output from overloading the op amp's input.
AD9772A
IOUTA IOUTB 225 225 COPT 25 25 500 500
Figure 27 shows the AD9772A configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 W cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 W. In this case, RLOAD represents the equivalent load resistance seen by IOUTA. The unused output (IOUTB) should be connected to ACOM directly. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the Analog Outputs section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested.
AD9772A
IOUTA IOUTB 50 IOUTFS = 20mA VOUTA = 0V TO 0.5V 50
Figure 27. 0 V to 0.5 V Unbuffered Voltage Output SINGLE-ENDED BUFFERED VOLTAGE OUTPUT
AD8055
Figure 25. DC Differential Coupling Using an Op Amp
Figure 28 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9772A output current. U1 maintains IOUTA (or IOUTB) at virtual ground, thus minimizing the nonlinear output impedance effect on the DAC's INL performance as discussed in the Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates is often limited by U1's slewing capabilities. U1 provides a negative unipolar output voltage, and its full-scale output voltage is simply the product of -20- REV. B
AD9772A
RFB and IOUTFS. The full-scale output should be set within U1's voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink will be subsequently reduced.
COPT RFB 200 IOUTFS = 10mA U1 IOUTB 200
For those applications requiring a single 3.3 V supply for both the analog, digital, and phase-lock loop supply, a clean AVDD and/or CLKVD may be generated using the circuit shown in Figure 29. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR-type electrolytic and tantalum capacitors.
TTL/CMOS LOGIC CIRCUITS FERRITE BEADS + 100F - ELECTROLYTIC + 10F-22F - TANTALUM AVDD 0.1F CERAMIC ACOM
AD9772A
IOUTA
VOUT = -IOUTFS RFB 3.3V POWER SUPPLY
Figure 28. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS
Figure 29. Differential LC Filter for 3.3 V
The AD9772A contains the following five power supply inputs: AVDD, DVDD1, DVDD2, CLKVDD, and PLLVDD. The AD9772A is specified to operate over a 3.1 V to 3.5 V supply range, thus accommodating a 3.3 V power supply with up to 6% regulation. However, the following two conditions must be adhered to when selecting power supply sources for AVDD, DVDD1-DVDD2, CLKVDD, and PLLVDD: 1. PLLVDD = CLKVDD = 3.1 V-3.5 V when PLL clock multiplier enabled. (Otherwise PLLVDD = PLLCOM) 2. DVDD1-DVDD2 = CLKVDD 0.30 V To meet the first condition, PLLVDD must be driven by the same power source as CLKVDD with each supply input independently decoupled with a 0.1 F capacitor to its respective grounds. To meet the second condition, CLKVDD can share the power supply source as DVDD1-DVDD2, using the decoupling network shown in Figure 29 to isolate digital noise from the sensitive CLKVDD (and PLLVDD) supply. Alternatively, separate precision voltage regulators can be used to ensure that condition two is met. In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection, placement and routing, and supply bypassing and grounding. Figures 37 to 44 illustrate the recommended printed circuit board ground, power, and signal plane layouts that are implemented on the AD9772A evaluation board. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9772A features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. AVDD, CLKVDD, and PLLVDD must be powered from a clean analog supply and decoupled to their respective analog common (i.e., ACOM, CLKCOM, and PLLCOM) as close to the chip as physically possible. Similarly, DVDD1 and DVDD2, the digital supplies, should be decoupled to DCOM.
Maintaining low noise on power supplies and ground is critical to obtain optimum results from the AD9772A. If properly implemented, ground planes can perform a host of functions on high speed circuit boards, such as bypassing and shielding current transport. In mixed-signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference, and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC. On the analog side, this includes the DAC output signal, reference signal, and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct, and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistors should be considered. The necessity and value of these resistors will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices' Application Note AN-333.
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AD9772A
APPLICATIONS
-10 -20 -30 AMPLITUDE (dBm) -40 -50 -60 -70 -80 -90 -100 -110 0 5 10 15 FREQUENCY (MHz) 20 25
MULTICARRIER The AD9772A's wide dynamic range performance makes it well suited for next generation base station applications in which it reconstructs multiple modulated carriers over a designated frequency band. Cellular multicarrier and multimode radios are often referred to as software radios since the carrier tuning and modulation scheme is software programmable and performed digitally. The AD9772A is the recommended TxDAC in Analog Device SoftCell chipset, which comprises the AD6622, Quadrature Digital Upconverter IC, along with its companion Rx Digital Downconverter IC, the AD6624, and 14-bit, 65 MSPS ADC, the AD6644. Figure 30 shows a generic software radio Tx signal chain based on the AD9772A/AD6622. Figure 31 shows a spectral plot of the AD9772A operating at 64.54 MSPS, reconstructing eight IS-136 modulated carriers spread over a 25 MHz band. For this particular test scenario, the AD9772A exhibited 74 dBc SFDR performance along with a carrier-to-noise ratio (CNR) of 73 dB. Figure 32 shows a spectral plot of the AD9772A operating at 52 MSPS, reconstructing four equal GSM carriers spread over a 15 MHz band. The SFDR and CNR (in 100 kHz BW) measured to be 76 dBc and 83.4 dB, respectively, along with a channel power of -13.5 dBFS. Note, the test vectors were generated using Rohde & Schwarz's WinIQSIM software.
AD6622
SPORT SPORT SPORT SPORT RCF RCF RCF RCF JTAG CIC FILTER CIC FILTER CIC FILTER CIC FILTER NCO QAM NCO QAM SUMMATION NCO QAM NCO QAM OTHER AD6622s FOR INCREASED CHANNEL CAPACITY CLK
Figure 32. Spectral Plot of AD9772A Reconstructing Four GSM Modulated Carriers @ fDATA = 52 MSPS, PLLVDD = 0
Although the above IS-136 and GSM spectral plots are representative of the AD9772A's performance for a particular set of test conditions, the following recommendations are offered to maximize the performance and system integration of the AD9772A into multicarrier applications: 1. To achieve the highest possible CNR, the PLL clock multiplier should be disabled (i.e., PLLVDD to PLLCOM) and the AD9772A's clock input driven with a low jitter/phase noise clock source at twice the input data rate. In this case, the divide-by-two clock appearing at PLLLOCK should serve as the master clock for the digital upconverter IC(s) such as the AD6622. PLLLOCK should be limited to a fanout of one. 2. The AD9772A achieves its optimum noise and distortion performance when configured for baseband operation along with a differential output and a full-scale current, IOUTFS, set to approximately 20 mA. 3. Although the 2 interpolation filters frequency roll-off provides a maximum reconstruction bandwidth of 0.422 fDATA, the optimum adjacent image rejection (due to the interpolation process) is achieved (i.e., > 73 dBc) if the maximum channel assignment is kept below 0.400 fDATA. 4. To simplify the subsequent IF stages filter requirements (i.e., mixer image and LO rejection), it is often advantageous to offset the frequency band from dc to relax the transition band requirements of the IF filter. 5. Oversampling the frequency band often results in improved SFDR and CNR performance. This implies that the data input rate to the AD9772A is greater than fPASSBAND/0.4 where fPASSBAND is the maximum bandwidth in which the AD9772A will be required to reconstruct and place carriers. The improved noise performance results in a reduction in the TxDAC's noise spectral density due to the added process gain realized with oversampling. Also, higher oversampling ratios provide greater flexibility in the frequency planning.
PLLLOCK
CLK
AD9772A
PORT
Figure 30. Generic Multicarrier Signal Chain Using the AD6622 and AD9772A
-20 -30 -40 AMPLITUDE (dBm) -50 -60 -70 -80 -90 -100
0
5
10
15 20 FREQUENCY (MHz)
25
30
Figure 31. Spectral Plot of AD9772A Reconstructing Eight IS-136 Modulated Carriers @ fDATA = 64.54 MSPS, PLLVDD = 0
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AD9772A
BASEBAND SINGLE-CARRIER
The AD9772A is also well suited for wideband single-carrier applications such as WCDMA and multilevel QAM whose modulation scheme requires wide dynamic range from the reconstruction DAC to achieve the out-of-band spectral mask as well as the in-band CNR performance. Many of these applications strategically place the carrier frequency at one quarter of the DAC's input data rate (i.e., fDATA/4) to simplify the digital modulator design. Since this constitutes the first fixed IF frequency, the frequency tuning is accomplished at a later IF stage. To enhance the modulation accuracy as well as reduce the shape factor of the second IF SAW filter, many applications will often specify the pass band of the IF SAW filter to be greater than the channel bandwidth. The trade-off is that the TxDAC must now meet the particular application's spectral mask requirements within the extended pass band of the second IF, which may include two or more adjacent channels. Figure 33 shows a spectral plot of the AD9772A reconstructing a test vector similar to those encountered in WCDMA applications with the following exception. WCDMA applications prescribe a root raised cosine filter with an alpha = 0.22, which limits the theoretical ACPR of the TxDAC to about 70 dB. This particular test vector represents white noise that has been band-limited by a brick wall band-pass filter with the same pass band such that its maximum ACPR performance is theoretically 83 dB and its peak-to-rms ratio is 12.4 dB. As Figure 33 reveals, the AD9772A is capable of approximately 78 dB ACPR performance when one accounts for the additive noise/distortion contributed by the FSEA30 spectrum analyzer.
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 C11 C11 600kHz
should disable the zeros-stuffing operation. Also, to minimize the effects of the PLL clock multipliers phase noise as shown in Figure 9, an external low jitter/phase noise clock source equal to 4 fDATA is recommended. Figure 34 shows the actual output spectrum of the AD9772A reconstructing a 16-QAM test vector with a symbol rate of 5 MSPS. The particular test vector was centered at fDATA/4 with fDATA = 100 MSPS, and fDAC = 400 MHz. For many applications, the pair of images appearing around fDATA will be more attractive since they have the flattest pass band and highest signal power. Higher images can also be used with the understanding that these images will have reduced pass-band flatness, dynamic range, and signal power, thus reducing the CNR and ACP performance. Figure 35 shows a dual-tone SFDR amplitude sweep at the various IF images with fDATA = 100 MSPS and fDAC = 400 MHz and the two tones centered around fDATA/4. Note, since an IF filter is assumed to precede the AD9772A, the SFDR was measured over a 25 MHz window around the images occurring at 75 MHz, 125 MHz, 275 MHz, and 325 MHz.
-20 -30 -40 AMPLITUDE (dBm) -50 -60 -70 -80 -90 -100
0
100
200 FREQUENCY (MHz)
300
400
Figure 34. Spectral Plot of 16-QAM Signal in Direct IF Mode at fDATA = 100 MSPS
90 75MHz 85 SFDR (IN 25MHz WINDOW) (dBFS) C0 C0 Cu1 Cu1 SPAN 6MHz 80 275MHz 75 70 65 60 55 50 -14 325MHz 125MHz
dBm
CENTER 16.25MHz
Figure 33. AD9772A Achieves 78 dB ACPR Performance Reconstructing a WCDMA-Like Test Vector with fDATA = 65.536 MSPS and PLLVDD = 0 DIRECT IF
As discussed in the Digital Modes of Operation section, the AD9772A can be configured to transform digital data representing baseband signals into IF signals appearing at odd multiples of the input data rate (i.e., N fDATA where N = 1, 3, . . .). This is accomplished by configuring the MOD1 and MOD0 digital inputs high. Note, the maximum DAC update rate of 400 MSPS limits the data input rate in this mode to 100 MSPS when the zero-stuffing operation is enabled (i.e., MOD1 high). Applications requiring higher IFs (i.e., 140 MHz) using higher data rates
-12
-10
-8 -6 AOUT (dBFS)
-4
-2
0
Figure 35. Dual-Tone Windowed SFDR vs. AOUT @ fDATA = 100 MSPS
REV. B
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AD9772A
Regardless of which image is selected for a given application, the adjacent images must be sufficiently filtered. In most cases, a SAW filter providing differential inputs represents the optimum device for this purpose. For single-ended SAW filters, a balancedto-unbalanced RF transformer is recommended. The AD9772A's high output impedance provides a certain amount of flexibility in selecting the optimum resistive load, RLOAD, as well as any matching network. For many applications, the data update rate to the DAC (i.e., fDATA) must be some fixed integer multiple of some system reference clock (i.e., GSM - 13 MHz). Furthermore, these applications prefer to use standard IF frequencies which offer a large selection of SAW filter choices of varying passbands (i.e., 70 MHz). These applications may still benefit from the AD9772A's direct IF mode capabilities when used in conjunction with a digital upconverter such as the AD6622. Since the AD6622 can digitally synthesize and tune up to four modulated carriers, it is possible to judiciously tune these carriers in a region which may fall within an IF filter's pass band upon reconstruction by the AD9772A. Figure 36 shows an example in which four carriers were tuned around 18 MHz with a digital upconverter operating at 52 MSPS such that when reconstructed by the AD9772A in the IF mode, these carriers fall around a 70 MHz IF.
-10 -20 -30 AMPLITUDE (dBm) -40 -50 -60 -70 -80 -90 -110 66 68 70 FREQUENCY (MHz) 72 74
differential amplifier, or directly coupled output. To evaluate the output differentially using the transformer, remove jumpers JP12 and JP13 and monitor the output at J6 (IOUT). To evaluate the output differentially, remove the transformer (T2) and install jumpers JP12 and JP13. The output of the amplifier can be evaluated at J13 (AMPOUT). To evaluate the AD9772A single-endedly and directly coupled, remove the transformer and jumpers (JP12 and JP13), and install resistors R16 or R17 with 0 W. The digital data to the AD9772A comes across a ribbon cable which interfaces to a 40-pin IDC connector. Proper termination or voltage scaling can be accomplished by installing RN2 and/or RN3 SIP resistor networks. The 22 W DIP resistor network, RN1, must be installed and helps reduce the digital data edge rates. A single-ended CLOCK input can be supplied via the ribbon cable by installing JP8 or more preferably via the SMA connector, J3 (CLOCK). If the CLOCK is supplied by J3, the AD9772A can be configured for a differential clock interface by installing jumpers JP1 and configuring JP2, JP3, and JP9 for the DF position. To configure the AD9772A clock input for a single-ended clock interface, remove JP1 and configure JP2, JP3, and JP9 for the SE position. The AD9772A's PLL clock multiplier can be disabled by configuring jumper JP5 for the L position. In this case, the user must supply a clock input at twice (2) the data rate via J3 (CLOCK). The 1 clock is made available on SMA connector J1 (PLLLOCK), and should be used to trigger a pattern generator directly or via a programmable pulse generator. Note that PLLLOCK is capable of providing a 0 V to 0.85 V output into a 50 W load. To enable the PLL clock multiplier, JP5 must be configured for the H position. In this case, the clock may be supplied via the ribbon cable (i.e., JP8 installed) or J3 (CLOCK). The divide-by-N ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1). The AD9772A can be configured for baseband or direct IF mode operation by configuring jumpers JP11 (MOD0) and JP10 (MOD1). For baseband operation, JP10 and JP11 should be configured in the L position. For direct IF operation, JP10 and JP11 should be configured in the H position. For direct IF operation without zero-stuffing, JP11 should be configured in the H position while JP10 should be configured in the low position. The AD9772A's voltage reference can be enabled or disabled via JP4 (EXT REF IN). To enable the reference, configure JP in the INT position. A voltage of approximately 1.2 V will appear at the TP6 (REFIO) test point. To disable the internal reference, configure JP4 in the EXT position and drive TP6 with an external voltage reference. Lastly, the AD9772A can be placed in the SLEEP mode by driving the TP11 test point with logic level high input signal.
Figure 36. Spectral Plot of Four Carriers at 60 MHz IF with fDATA = 52 MSPS, PLLVDD = 0 AD9772A EVALUATION BOARD
The AD9772-EB is an evaluation board for the AD9772A TxDAC. Careful attention to layout and circuit design, combined with prototyping area, allows the user to easily and effectively evaluate the AD9772A in different modes of operation. Referring to Figures 37 and 38, the AD9772A's performance can be evaluated differentially or single-endedly using a transformer,
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AD9772A
2 P1 4 P1 6 P1 8 P1 10 P1 12 P1 14 P1 16 P1 P1 1 P1 3 P1 5 P1 7 P1 9 P1 11 P1 13 P1 15 IN13 IN12 IN11 IN10 IN9 IN8 IN7 IN6 RN1 VALUE 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 RN2 VALUE 1 MSB DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 2 3 4 5 6 7 8 9 10 MSB IN13 IN12 IN11 IN10 IN9 IN8 IN7 IN6 RN3 VALUE 1 2 3 4 5 6 7 8 9 10
18 P1 20 P1 22 P1 24 P1 26 P1 28 P1 30 P1 32 P1 34 P1 36 P1 38 P1 40 P1
P1 17 P1 19 P1 21 P1 23 P1 25 P1 27 P1 29 P1 31 P1 33 P1 35 P1 37 P1 39
IN5 IN4 IN3 IN2 IN1 IN0
RN4 VALUE 1 16 2 3 4 5 6 7 8 15 14 13 12 11 10 9 LSB
RN5 VALUE 1 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK RESET 2 3 4 5 6 7 8 9 10 LSB IN5 IN4 IN3 IN2 IN1 IN0 INRESET INCLOCK
RN6 VALUE 1 2 3 4 5 6 7 8 9 10
INCLOCK INRESET
R15 500 +VS C18 0.1F RED TP20
JP12 AMP-A IA JP13 AMP-B IB C16 100pF R13 50 R11 50
R4 500 R12 500 R14 500
2
-IN
7 AD8055 +V 6 U2 OUT -V 4
3
+IN
AMPOUT 1 J13 2
-VS C17 0.1F
BLK TP19
J7
1 DVDD_IN
L1 1
FBEAD 2 C13 10F 10V
RED TP22 DVDD TP23
J8
1 DGND
BLK L2 1 FBEAD 2 C14 10F 10V RED TP24 AVDD TP25
J9
1 AVDD_IN
J10
1 AGND
BLK L3 1 CLKVDD_IN 1 FBEAD 2 RED TP26 CLKVDD TP27
J11
J12
1 CLKGND
c
C15 10F 10V
BLK
Figure 37. Drafting Schematic of Evaluation Board
REV. B
-25-
AD9772A
RED TP16 C5 0.1F AVDD C6 1F FSADJ REFIO REFLO C4 0.1F R10 1.91k BLK TP17 WHT TP5 WHT TP6 AVDD EXT REF 3 REFLO INT REF 1
B 2A
JP4
RED TP14 C7 0.1F TP15 BLK
DVDD IA IB
C8 0.1F
1 2 3 4 5 6 7 8 9 10 11 12
R6 50
48 47 46 45 44 43 42 41 40 39 38 37
TP11 SLEEP WHT
36 35 34 33 32 31 30 29 28 27 26 25
NOTE: SHIELD AROUND R5, C1 CONNECTED TO PLLVDD R5 VAL C1 VAL PLLVDD C9 1F C10 0.1F CLKVDD
PIN 1 IDENTIFIER
LPF
MSB DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
c
U1
AD9772A
CLK- CLK+ DIV0 DIV1 RESET PLL-LOCK
1
c
CLKVDD
3
13 14 15 16 17 18 19 20 21 22 23 24
J1
2
c
TP10 WHT
B 2A 1
JP5
3 B 2A 1 2
DB2 DB1 LSB DB0
DB3
c
C11 0.1F C12 1F
CONNECT GNDs AS SHOWN UNDER USING BOTTOM SIGNAL LAYER
TP3 WHT TP4 WHT
TP7 RED
TP28 WHT
JP6
B A
3
JP7
1
MOD0 DVDD
3 3 B
JP11 DGND
H 2 AL
1
JP10
H 2 AL
1
B
TP1 WHT MOD1 TP2 WHT JP8 EDGE DVDD
3
c
WHT TP12 CLOCK J3
1 2
SE B DF CLKVDD R2 1k
2A 1
NOTE: LOCATE ALL DECOUPLING CAPS (C5 - C12) AS CLOSE AS POSSIBLE TO DUT, PREFERABLY UNDER DUT ON BOTTOM SIGNAL LAYER.
JP2
JP1 DF
c
T1
1
R16 VAL C3 10pF R8 50 T2
3
CLOCK
3
S P
6 4
SE B
1 4 6
IA
S P
J6 IOUT
2
2 DF A
JP3
1
c
R3 1k
C19 0.1F
2 3
c
R9 OPT IB C2 10pF R7 50
2 1
R1 50
3
DF B
2 SE A
c
R17 VAL
JP9
1
Figure 38. Drafting Schematic of Evaluation Board (continued)
-26-
REV. B
AD9772A
Figure 39. Silkscreen Layer--Top
Figure 40. Component Side PCB Layout (Layer 1)
REV. B
-27-
AD9772A
Figure 41. Ground Plane PCB Layout (Layer 2)
Figure 42. Power Plane PCB Layout (Layer 3)
-28-
REV. B
AD9772A
Figure 43. Solder Side PCB Layout (Layer 4)
Figure 44. Silkscreen Layer--Bottom
REV. B
-29-
AD9772A
OUTLINE DIMENSIONS
48-Lead Low Profile Quad Flat Package [LQFP] (ST-48)
Dimensions shown in millimeters
0.75 0.60 0.45 1.60 MAX
48 1
9.00 BSC SQ
37 36
1.45 1.40 1.35
10 6 2
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
PIN 1
(PINS DOWN)
TOP VIEW
7.00 BSC SQ
VIEW A
12 13 24 25
0.15 0.05
SEATING PLANE
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026BBC
VIEW A
0.50 BSC
0.27 0.22 0.17
-30-
REV. B
AD9772A Revision History
Location 6/03--Data Sheet changed from REV. A to REV. B. Page
Change to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Change to DIGITAL FILTER SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ORERING GUIDE Updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Change to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Change to Figure 13a and 13b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Change to DIGITAL INPUTS/OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Change to SLEEP MODE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Change to Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Change to Figure 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Change to POWER AND GROUND CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Change to Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Update to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3/02--Data Sheet changed from REV. 0 to REV. A.
Edits to DIGITAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Change to TPC 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Change to Figure 9 Caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Change to Figure 13a and 13b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
REV. B
-31-
-32-
C02253-0-6/03(B)

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