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8Mx64 bits PC100 SDRAM Unbuffered DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V65801 X-Series
DESCRIPTION
The Hyundai HYM71V65801 X-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of four 8Mx16bit CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy printed circuit board. Two 0.22uF and one 0.0022uF decoupling capacitors per each SDRAM are mounted on the PCB. The HYM71V65801 X-Series are Dual In-line Memory Modules suitable for easy interchange and addition of 64Mbytes memory. The HYM71V65801 X-Series are offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
* PC100MHz support * 168pin SDRAM Unbuffered DIMM * Serial Presence Detect with EEPROM * 1.375" (34.93mm) Height PCB with Single Sided components * Single 3.3 0.3V power supply * All devices pins are compatible with LVTTL interface * Data mask function by DQM * SDRAM internal banks : four banks * Module bank : one physical bank * Auto refresh and self refresh * 4096 refresh cycles / 64ms * Programmable Burst Length and Burst Type -. 1, 2, 4, 8 or Full Page for Sequential Burst -. 1, 2, 4 or 8 for Interleave Burst * Programmable /CAS Latency -. 2, 3 Clocks
ORDERING INFORMATION
PART NO. HYM71V65801TX-8 HYM71V65801TX-10P HYM71V65801TX-10S MAX. FREQUENCY 125MHz 100MHz 100MHz 4 Banks 4K Normal TSOP-II Gold INTERNAL BANK REF. POWER SDRAM PACKAGE PLATING
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1/Dec.99 (c)1999 Hyundai MicroElectronics
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series PIN DESCRIPTION
PIN NAME CK0~CK3 Clock Inputs DESCRIPTION The System Clock Input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh. Enables or disables all inputs except CK, CKE and DQM. Select bank to be activated during /RAS activity. Select bank to be read/written during /CAS activity Row address : RA0~RA11, Column address : CA0~CA8 Auto-precharge flag : A10 /RAS define the operation. Refer to the function truth table for details. /CAS define the operation. Refer to the function truth table for details. /WE define the operation. Refer to the function truth table for details. Controls output buffers in read mode and masks input data in write mode. Multiplexed data input/output pins Power supply for internal circuits and input/output buffers Ground Serial Presence Detect Clock Input Serial Presence Detect Data input/output Serial Presence Detect Address input Write Protect for Serial Presence Detect on DIMM No Connect or Don' t Use
CKE0 /S0, /S2 BA0, BA1
Clock Enable Chip Select SDRAM Bank Address
A0~A11
Address Inputs
/RAS
Row Address Strobe
/CAS
Column Address Strobe
/WE DQM0~DQM7 DQ0~DQ63 VCC VSS SCL SDA SA0~SA2 WP NC
Write Enable Data Input/Output Mask Data Input/Output Power Supply (3.3V) Ground SPD Clock Input SPD Data Input/Output SPD Address Input Write Protect for SPD No Connect
Rev. 1.1/Dec.99
2
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series PIN ASSIGNMENTS
FRONT SIDE PIN NO. 1 2 3 4 5 6 7 8 9 10 NAME VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 85 86 87 88 89 90 91 92 93 94 BACK SIDE PIN NO. NAME VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 41 42 43 44 45 46 47 48 49 50 51 52 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC NC VSS NC NC VCC /CAS DQM4 DQM5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 A11 VCC 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT SIDE PIN NO. NAME VCC CK0 VSS NC /S2 DQM2 DQM3 NC VCC NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VCC 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 BACK SIDE PIN NO. NAME *CK1 NC VSS CKE0 NC DQM6 DQM7 NC VCC NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC SA0 SA1 SA2 VCC
Architecture Key
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC NC VSS NC NC VCC /WE DQM0 DQM1 /S0 NC VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124
Voltage Key
Note : *. CK1, CK3 are connected with termination R/C. (Refer to the Block Diagram.)
Rev. 1.1/Dec.99
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PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms. 2. The padding capacitance of termination R/C for CK1, CK3 is 10pF.
Rev. 1.1/Dec.99
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PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series SERIAL PRESENCE DETECT
BYTE NUMBER BYTE0 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 BYTE6 BYTE7 BYTE8 BYTE9 BYTE10 BYTE11 BYTE12 BYTE13 BYTE14 BYTE15 BYTE16 BYTE17 BYTE18 BYTE19 BYTE20 BYTE21 BYTE22 BYTE23 BYTE24 BYTE25 BYTE26 BYTE27 BYTE28 BYTE29 BYTE30 BYTE31 BYTE32 BYTE33 BYTE34 BYTE35 BYTE36 -61 BYTE62 BYTE63 BYTE64 BYTE65 ~71 BYTE72 FUNCTION DESCRIBED # of Bytes Written into Serial Memory at Module Manufacturer Total # of Bytes of SPD Memory Device Fundamental Memory Type # of Row Addresses on This Assembly # of Column Addresses on This Assembly # of Module Banks on This Assembly Data Width of This Assembly Data Width of This Assembly (Continued) Voltage Interface Standard of This Assembly SDRAM Cycle Time @ /CAS Latency=3 Access Time from Clock @ /CAS Latency=3 DIMM Configuration Type Refresh Rate/Type Primary SDRAM Width Error Checking SDRAM Width Minimum Clock Delay Back to Back Random Column Address Burst Lengths Supported # of Banks on Each SDRAM Device SDRAM Device Attributes, CAS # Latency SDRAM Device Attributes, CS # Latency SDRAM Device Attributes, Write Latency SDRAM Module Attributes SDRAM Device Attributes, General SDRAM Cycle Time @ /CAS Latency=2 Access Time from Clock @ /CAS Latency=2 SDRAM Cycle Time @ /CAS Latency=1 Access Time from Clock @ /CAS Latency=1 Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active Delay (tRRD) Minimum /RAS to /CAS Delay (tRCD) Minimum /RAS Pulse width (tRAS) Module Bank Density Command and Address Signal Input Setup Time Command and Address Signal Input Hold Time Data Signal Input Setup Time Data Signal Input Hold Time Superset Information (may be used in future) SPD Revision Checksum for Bytes 0~62 Manufacturer JEDEC ID Code ....Manufacturer JEDEC ID Code 2ns 1ns 2ns 1ns 8ns 6ns -8 FUNCTION -10P 128 Bytes 256 Bytes SDRAM 12 9 1 Banks 64 Bits LVTTL 10ns 6ns None 15.625s / Self Refresh Supported x16 None tCCD = 1 CLK 1,2,4,8,Full Page 4 Banks /CAS Latency=2,3 /CS Latency=0 /WE Latency=0 Neither Buffered nor Registered +/-10% voltage tolerance, Burst Read Single bit Write, Precharge All, Auto Precharge, Early RAS Precharge 10ns 6ns 20ns 16ns 20ns 48ns 10ns 6ns 20ns 20ns 20ns 50ns 64MB 2ns 1ns 2ns 1ns Intel SPD 1.2A Hyundai JEDEC ID Unused HEI (Korea) HEA (United States) HEU (Europe) E7h 2ns 1ns 2ns 1ns 20h 10h 20h 10h 12ns 6ns 20ns 20ns 20ns 50ns A0h 60h 00h 00h 14h 10h 14h 30h 10ns 6ns 80h 60h -10S -8 VALUE -10P 80h 08h 04h 0Ch 09h 01h 40h 00h 01h A0h 60h 00h 80h 10h 00h 01h 8Fh 04h 06h 01h 01h 00h 0Eh A0h 60h 00h 00h 14h 14h 14h 32h 10h 20h 10h 20h 10h 00h 12h 0Dh ADh FFh 01h 02h 03h 2Dh 3, 8 20h 10h 20h 10h C0h 60h 00h 00h 14h 14h 14h 32h 2 A0h 60h 1 -10S NOTE
Manufacturing Location
Rev. 1.1/Dec.99
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PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series
Continued
BYTE NUMBER BYTE73 BYTE74 BYTE75 BYTE76 BYTE77 BYTE78 BYTE79 BYTE80 BYTE81 BYTE82 BYTE83 BYTE84 BYTE85 BYTE86 BYTE87 ~90 BYTE91 BYTE92 BYTE93 BYTE94 BYTE95 ~98 BYTE99 ~125 BYTE126 BYTE127 BYTE128 ~256 FUNCTION DESCRIBED Manufacturer' s Part Number (Component) Manufacturer' s Part Number (128Mb based) Manufacturer' s Part Number (Voltage Interface) Manufacturer' s Part Number (Data Width) ....Manufacturer' s Part Number (Data Width) Manufacturer' s Part Number (Memory Depth) Manufacturer' s Part Number (Refresh) Manufacturer' s Part Number (Internal Banks) Manufacturer' s Part Number (Package Type) Manufacturer' s Part Number (Module Type) Manufacturer' s Part Number (Hyphen) Manufacturer' s Part Number (Min. Cycle Time) ....Manufacturer' s Part Number (Min. Cycle Time) ....Manufacturer' s Part Number (Min. Cycle Time) Manufacturer' s Part Number Revision Code (for Component) ....Revision Code (for PCB) Manufacturing Date ....Manufacturing Date Assembly Serial Number Manufacturer Specific Data (may be used in future) System Frequency Support Intel Specification Details for 100MHz Support Unused Storage Locations 8 Blank Blank -8 FUNCTION -10P 7 (SDRAM) 1 V (3.3V, LVTTL) 6 5 8 0 (4K Refresh) 1 (4 Banks) T (TSOPII) X (x16 based) - (Hyphen) 1 0 P Blanks Process Code Process Code Work Week Year Serial Number None 100MHz Refer to Note7 A7h 1 0 S 38h 20h 20h -10S -8 VALUE -10P 37h 31h 56h 36h 35h 38h 30h 31h 54h 58h 2Dh 31h 30h 50h 20h 00h 64h A7h 00h A5h 8 7, 8 31h 30h 53h -10S NOTE 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 6 4, 6 3, 6 3, 6 6
Note: 1. The bank address is excluded. 2. 1,2,4,8 for Interleave Burst Type. 3. BCD adopted. 4. ASCII adopted. 5. Basically HYUNDAI writes Part No. except for HYM in Byte 73-90 to use the limited 18 bytes from byte 73 to 90 efficiently. 6. Not fixed but dependent. 7. CLK0, CLK2 connected on the DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support. 8. Refer to Intel SPD Specification Rev.1.2A.
Rev. 1.1/Dec.99
6
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series ABSOLUTE MAXIMUM RATINGS
PARAMETER Ambient Temperature Storage Temperature Voltage on any Pin relative to VSS Voltage on VDD relative to VSS Short Circuit Output Current Power Dissipation Soldering Temperature * Time TA TSTG VIN, VOUT VDD, VDDQ IOS PD TSOLDER SYMBOL RATING 0 ~ 70 -55 ~ 125 -1.0 ~ 4.6 -1.0 ~ 4.6 50 4 260 * 10 UNIT C C V V MA W C * Sec
Note : Operation at above absolute maximum can adversely affect device reliability.
DC OPERATING CONDITION
(TA = 0 to 70C) PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage SYMBOL VCC VIH VIL MIN 3.0 2.0 - 0.3 TYP. 3.3 3.0 0 MAX 3.6 VCC + 0.3 0.8 UNIT V V V NOTE 1 1, 2 1, 3
Note : 1. All voltage are referenced to VSS = 0V. 2. VIH (max) is acceptable 5.6V AC pulse width with 3ns of duration. 3. VIL (min) is acceptable -2.0V AC pulse width with 3ns of duration.
AC OPERATING CONDITION
(TA = 0 to 70C, VDD = 3.3 0.3V, VSS = 0V) PARAMETER AC Input High / Low Level Voltage Input Timing Measurement Reference Level Voltage Input Rise / Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance for Access Time Measurement SYMBOL VIH / VIL Vtrip tR / tF Voutref CL VALUE 2.4 / 0.4 1.4 1 1.4 *Note UNIT V V ns V pF
Note : *. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output circuit.
Rev. 1.1/Dec.99
7
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series CAPACITANCE
(TA = 25C, f = 1MHz) PARAMETER CK0, CK2 CKE0 Input Capacitance /S0, /S2 A0~A11, BA0, BA1 /RAS, /CAS, /WE DQM0~DQM7 Data Input/Output Capacitance DQ0~DQ63 PIN SYMBOL CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CI/O MIN 15 25 15 30 30 5 5 MAX 45 40 30 45 45 20 20 TYP. UNIT pF pF pF pF pF pF pF
OUTPUT LOAD CIRCUIT
Rev. 1.1/Dec.99
8
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series DC CHARACTERISTICS I
(TA = 0 to 70C, VDD = 3.3 0.3V) PARAMETER Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage SYMBOL ILI ILO VOH VOL MIN -4 -1 2.4 MAX 4 1 0.4 UNIT uA uA V V NOTE 1 2 IOH = -4mA IOL = +4mA
Note : 1. VIN = 0 to 3.6V. All other pins are not tested under VIN = 0V. 2. DOUT is disabled. VOUT = 0 to 3.6V.
DC CHARACTERISTICS II
(TA = 0 to 70C, VDD = 3.3 0.3V, VSS = 0V) SPEED PARAMETER SYMBOL TEST CONDITION -8 Operating Current Precharge Standby Current in Power Down Mode IDD1 IDD2P IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS Active Standby Current in Power Down Mode IDD3P IDD3PS IDD3N Active Standby Current in Non Power Down Mode IDD3NS Burst Length = 1, One bank active tRC tRC(min), IOL = 0mA CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), /CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD - 0.2V or 0.2V CKE VIH(max), tCK = Input signals are stable. CKE VIL(max), tCK = min CKE VIL(max), tCK = CKE VIH(min), /CS VIH(min), tCK = min Input signals are changed one time during 2clks. All other pins VDD - 0.2V or 0.2V CKE VIH(max), tCK = Input signals are stable. tCK tCK(min), IOL = 0mA All banks active IDD5 IDD6 tRRC tRRC(min), All banks active CKE 0.2V CL = 3 CL = 2 600 480 480 -10P 480 8 6 80 -10S 480 mA mA mA mA 1 UNIT NOTE
40 28 28 160
mA mA mA mA
160 480 480 1160 8 480
mA
Burst Mode Current
Operating
IDD4
mA 440 mA mA
1
Auto Refresh Current Self Refresh Current
2
Note : 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRRC (Refresh /RAS cycle time) is shown at AC CHARACTERISTICS II.
Rev. 1.1/Dec.99
9
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted) -8 PARAMETER /CAS Latency = 3 /CAS Latency = 2 SYMBOL MIN System Clock Cycle Time tCK3 tCK2 tCHW tCLW tAC3 tAC2 tOH tDS tDH tAS tAH tCKS tCKH tCS tCH tOLZ tOHZ3 tOHZ2 8 1000 10 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 10 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 6 6 6 MAX MIN 10 1000 12 3 3 3 2 1 2 1 2 1 2 1 1 3 3 6 ns /CAS Latency = 2 6 6 ns /CAS Latency = 2 6 ns ns ns ns ns ns ns ns ns ns 1 1 1 1 1 1 1 1 2 ns ns I I MAX MIN 10 1000 ns MAX -10P -10S UNIT NOTE
Clock High Pulse Width Clock Low Pulse Width Access Time from Clock /CAS Latency = 3
Data-Out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE Setup Time CKE Hold Time Command Setup Time Command Hold Time CLK to Data Output in Low-Z time CLK to Data Output in High-Z time /CAS Latency = 3
Note : 1. Assume tR / tF (input rise and fall time ) is 1ns. If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter 2. Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v. If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.1/Dec.99
10
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series AC CHARACTERISTICS II
-8 PARAMETER Operation Auto Refresh SYMBOL MIN /RAS Time Cycle tRC tRRC tRCD tRAS tRP tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tPDE tSRE tREF 68 68 20 48 20 16 1 0 1 4 2 0 2 3 2 1 1 100K 64 70 20 50 20 20 1 0 1 3 2 0 2 3 2 1 1 100K 64 MAX MIN 70 70 20 50 20 20 1 0 1 3 2 0 2 3 2 1 1 100K CLK /CAS Latency = 2 64 CLK CLK ms 1 ns ns ns ns CLK CLK CLK CLK CLK CLK CLK MAX MIN 70 ns MAX -10P -10S UNIT NOTE
/RAS to /CAS Delay /RAS Active Time /RAS Precharge Time /RAS to /RAS Bank Active Delay /CAS to /CAS Delay Write Command to Data-in Delay Data-in to Precharge Command Data-in to Active Command DQM to Data-out Hi-Z DQM to Data-in Mask MRS to New Command Precharge to Data Output Hi-Z /CAS Latency = 3
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note : 1. A new command can be given tRRC after self refresh exit.
Rev. 1.1/Dec.99
11
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series OPERATING OPTION TABLE
HYM71V65801TX-8
/CAS LATENCY 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 3CLKS 2CLKS 2CLKS tRCD 3CLKS 2CLKS 2CLKS tRAS 6CLKS 5CLKS 4CLKS tRC 9CLKS 7CLKS 6CLKS tRP 3CLKS 2CLKS 2CLKS tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns
HYM71V65801TX-10P
/CAS LATENCY 100MHz (10.0ns) 83MHz (12.0ns) 66MHz (15.0ns) 2CLKS 2CLKS 2CLKS tRCD 2CLKS 2CLKS 2CLKS tRAS 5CLKS 5CLKS 4CLKS tRC 7CLKS 7CLKS 6CLKS tRP 2CLKS 2CLKS 2CLKS tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns
HYM71V65801TX-10S
/CAS LATENCY 100MHz (10.0ns) 83MHz (12.0ns) 66MHz (15.0ns) 3CLKS 2CLKS 2CLKS tRCD 2CLKS 2CLKS 2CLKS tRAS 5CLKS 5CLKS 4CLKS tRC 7CLKS 7CLKS 6CLKS tRP 2CLKS 2CLKS 2CLKS tAC 6ns 6ns 6ns tOH 3ns 3ns 3ns
Rev. 1.1/Dec.99
12
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series COMMAND TRUTH TABLE
CKEn-1 Mode Register Set No Operation Bank Active Read H Read with Autoprecharge Write H Write with Autoprecharge Precharge All Banks H Precharge Selected Bank Burst Stop DQM Auto Refresh Entry Self Refresh Exit L H L H Entry Precharge Power Down Exit L H L H Entry Clock Suspend Exit L H X X H L L V V V X H X H X H X X H L L H H X H X H X X X H X H X H X X H H H H H L L L H X L H X L L X L L X H H X X H L X V X X X 1 X X X X L L H L X X L V X L H L L X CA H H X X L H L H X CA H L V H H H CKEn X X L X L H L H H H H X RA L V V /CS L H /RAS L X /CAS L X /WE L X X X DQM X ADDR A10/ AP BA NOTE
OP code
Note : 1. Existing Self Refresh occurs by asynchronously bringing CKE from low to high. 2. X = Don' t care, H = Logic High, L = logic Low, BA = Bank Address, CA = Column Address, OP code = Operand code, NOP = No operation
Rev. 1.1/Dec.99
13
PC100 SDRAM Unbuffered DIMM
HYM71V65801 X-Series PACKAGE DIMENSIONS
Rev. 1.1/Dec.99
14

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