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| www..com ICS557-06 ONE TO FOUR HCSL CLOCK BUFFER Description The ICS557-06 is a one to four differential clock buffer designed for use in PCI-Express applications. The device selects one of the two differential HCSL or LVDS input pairs and fans out to four pairs of differential HCSL or LVDS outputs. Features * * * * * Packaged in 20-pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input differential clock of up to 200 MHz for HCSL and up to 100 MHz for LVDS * Jitter 100 ps (peak-to-peak) * Output-to-output skew of 50 ps Block Diagram VDD 2 OE CLKA CLKA IN1 IN1 IN2 IN2 MUX 2 to 1 CLKB CLKB CLKC CLKC CLKD CLKD 2 SEL GND PD Rr (IREF) MDS 557-06 C I n t e gra te d C i r c u i t S y s t e m s 1 525 Race Stre et, San Jo se, CA 9 5126 Revision 010306 te l (40 8) 2 97-12 01 w w w. i c st . c o m ICS557-06 One to Four HCSL Clock Buffer Pin Assignment SEL VDDIN IN1 IN1 PD IN2 IN2 OE GND IREF 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CLKA CLKA CLKB CLKB GND VDD CLKC CLKC CLKD CLKD Select Table SEL 0 1 Input Pair selected IN2/ IN2 IN1/ IN1 20-pin (173 mil) TSSOP Pin Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name SEL VDDIN IN1 IN1 PD IN2 IN2 OE GND Rr(IREF) CLKD CLKD CLKC CLKC VDDOUT GND CLKB CLKB CLKA CLKA Pin Type Input Power Input Input Input Input Input Input Power Output Output Output Output Output Power Power Output Output Output Output Pin Description SEL=1 selects IN1/IN1. SEL =0 selects IN2/ IN2. Internal pull-up resistor. Connect to +3.3 V. Supply voltage for Input clocks. HCSL/LVDS true input signal 1. HCSL/LVDS complimentary input signal 1. Powers down the chip and tri-states outputs when low. Internal pull-up resistor. HCSL/LVDS true input signal 2. HCSL/LVDS complimentary input signal 2. Provides fast output on, tri-states output (High = enable outputs; Low = disable). Internal pull-up resistor outputs. Connect to ground. Precision resistor attached to this pin is connected to the internal current reference. Differential Complimentary output clock D. Differential True output clock D. Differential Complimentary output clock C. Differential True output clock C. Connect to +3.3 V. Supply Voltage for Output Clocks. Connect to ground. Differential Complimentary output clock B. Differential True output clock B. Differential Complimentary output clock A. Differential True output clock A. MDS 557-06 C In te grated Circuit Systems 2 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer Application Information Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS557-06 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD and GND pairs (2,9 and 15,16) as close to the device as possible. Current Reference Source Rr (Iref) If board target trace impedance (Z) is 50, then Rr = 475 (1%), providing IREF of 2.32 mA, output current (IOH) is equal to 6*IREF. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 2) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). Other signal traces should be routed away from the ICS557-06. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Load Resistors RL Since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. Output Termination The PCI-Express differential clock outputs of the ICS557-06 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-06 can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section. MDS 557-06 C In te grated Circuit Systems 3 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer Output Structures IREF =2.3 mA 6*IREF R R 475 See Output Termination Sections - Pages 3 ~ 5 General PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-06.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. MDS 557-06 C In te grated Circuit Systems 4 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer PCI-Express Layout Guidelines Common Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. L3 length, Route as non-coupled 50 ohm trace. RS RT Differential Routing on a Single PCB L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to a PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max Unit inch inch inch ohm ohm Unit inch inch Unit inch inch PCI-Express Device Routing L1 RS L1' RS L2 L2' RT L3' RT L3 L4 L4' ICS557-06 Output Clock PCI-Express Load or Connector Typical PCI-Express (HCSL) Waveform 700 mV 0 tOR 0.52 V 0.175 V 500 ps 500 ps tOF 0.52 V 0.175 V MDS 557-06 C In te grated Circuit Systems 5 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer LVDS Compatible Layout Guidelines LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm LVDS Device Routing L1 RQ L1' L3 L3' RP RT ICS557-06 Clock Output L2' L2 RT LVDS Device Load Typical LVDS Waveform 1325 mV 1000 mV tOR 500 ps 500 ps tOF 1250 mV 1150 mV 1250 mV 1150 mV MDS 557-06 C In te grated Circuit Systems 6 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS557-06. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Supply Voltage, VDD, VDDA All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 5.5 V Rating -0.5 V to VDD+0.5 V 0 to +70C -65 to +150C 125C 260C 2000 V min. (HBM) DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature 0 to +70C Parameter Supply Voltage Input High Voltage 1 Symbol V VIH VIL IIL IDD IDDOE IDDPD Conditions OE, SEL, PD OE, SEL, PD 0 < Vin < VDD 50, 2pF OE =Low No load, PD =Low Input pin capacitance Output pin capacitance CLK outputs SEL, OE, PD region. Min. 3.135 2.0 VSS-0.3 -5 Typ. Max. 3.465 VDD +0.3 0.8 5 55 20 400 7 6 5 Units V V A mA mA A pF pF nH k k Input Low Voltage1 Input Leakage Current2 Operating Supply Current Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistor CIN COUT LPIN ROUT RPUP 3.0 110 1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included. MDS 557-06 C In te grated Circuit Systems 7 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer AC Electrical Characteristics - CLKOUTA/CLKOUTB Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature 0 to +70C Parameter Input Frequency Output Frequency Input High Voltage Differential Input Voltages Input Offset Voltage Output High Voltage Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 Rise Time1,2 Fall Time 1,2 1,2 1,2 Symbol Conditions HCSL termination LVDS termination Min. Typ. Max. 200 200 100 Units MHz MHz mV mV mV V mV mV mV mV ps VIH VIL (VID) (VIS) VOH VOL HCSL HCSL LVDS LVDS HCSL HCSL Absolute Variation over all edges 660 -150 250 1.125 660 -150 250 700 0 350 1.25 700 0 350 850 450 1.375 850 550 140 Input Low Voltage1,2 Output Low Voltage1,2 100 tOR tOF From 0.175 V to 0.525 V From 0.525 V to 0.175 V 175 175 332 344 700 700 125 Measured at crossing point 45 All outputs All outputs tSTABLE From power-up VDD=3.3 V Input differential clock to output differential clock delay measured at mid point of input levels to mid pint of output levels tSPREAD Settling period after spread change 10 10 3.0 3.0 3 50 55 ps ps ps ps % us us ms ms ns Rise/Fall Time Variation1,2 Skew between Outputs Duty Cycle1,3 Output Enable Time Stabilization Time Spread Change Time Input to Output Delay 5 5 Output Disable Time 1 2 3 4 5 Test setup is RL=50 ohms with 2 pF, Rr = 475 (1%). Measurement taken from a single-ended waveform. Measurement taken from a differential waveform. Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. CLKOUT pins are tri-stated when OE is Low asserted. CLKOUT is driven differential when OE is High unless its PD = low. MDS 557-06 C In te grated Circuit Systems 8 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 93 78 65 20 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case Marking Diagram 20 11 Marking Diagram (Pb free) 20 11 IC S ###### YYWW 557G-06 10 IC S ###### YYWW 557G06LF 10 1 1 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "LF" denotes Pb free package. 4. Bottom marking: (origin). Origin = country of origin if not USA. MDS 557-06 C In te grated Circuit Systems 9 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m ICS557-06 One to Four HCSL Clock Buffer Package Outline and Package Dimensions (20-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 20 Inches* Min Max Symbol Min Max E1 INDEX AREA E 12 D A A1 A2 b c D E E1 e L aaa 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 6.40 6.60 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10 0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.252 0.260 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004 A2 A1 A *For reference only. Controlling dimensions in mm. c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number ICS557G-06 ICS557G-06T ICS557G-06LF ICS557G-06LFT Marking See Page 4 Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Package 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP 20-pin TSSOP Temperature 0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 557-06 C In te grated Circuit Systems 10 525 Ra ce Street, San Jose, CA 9512 6 Revision 010306 tel (4 08) 297-1 201 w w w. i c s t . c o m |
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