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NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com
EM28C1602C3FL
Advance Information
EM28C1602C3FL
Low Voltage, Extended Temperature
FLASH AND SRAM COMBO MEMORY
www..com
FEATURES
*
* Organization:
*
* * * * * * *
1,048K x 16 (Flash) 128K x 16 (SRAM) Basic configuration: Flash Thirty-nine erase blocks - Eight 4K-word parameter blocks - Thirty-one 32K-word main memory blocks SRAM 2Mb SRAM for data storage - 128K-words F_VCC, F_VPP, S_VCC voltages 2.7V (MIN)/3.3V (MAX) F_VCC read voltage 2.7V (MIN)/3.3V (MAX) S_VCC read voltage 1.8V (TYP) F_VPP (in-system PROGRAM/ERASE) 12V 5% (HV) F_VPP (production programming compatibility) 1.0V (MIN) S_VCC (SRAM data retention) Asynchronous access time Flash access time: 90ns @ 2.7V F_VCC SRAM access time: 85ns @ 2.7V S_VCC Low power consumption Enhanced WRITE/ERASE suspend option Read/Write SRAM during program/erase of Flash 128-bit chip OTP protection register for security purposes Cross-compatible command set support PROGRAM/ERASE cycles 100,000 WRITE/ERASE cycles per block
BALL ASSIGNMENT 66-Ball FBGA (Top View)
1 A B C D E F G H
NC
2
NC
3
NC
4
A11
5
A15
6
A14
7
A13
8
A12
9
F_Vss
10
NC
11
NC
12
NC
A16
A8
A10
A9
DQ15
S_W E#
DQ14
DQ7
F_WE #
NC
DQ13
DQ6
DQ4
DQ5
S_Vss
F_RP#
DQ12
S_CE2
S_Vcc
F_Vcc
F_WP #
F_Vpp
A19
DQ11
DQ10
DQ2
DQ3
S_L B#
S_UB#
S_OE #
DQ9
DQ8
DQ0
DQ1
A18
A17
A7
A6
A3
A2
A1
S_CE1#
NC
NC
NC
A5
A4
A0
F_CE#
F_Vss
F_OE#
NC
NC
NC
OPTIONS
* Timing 90ns * Boot Block Top Bottom * Operating Temperature Range Extended Temperature (-40oC to +85oC)
MARKING
-90 T B ET
* Package 66-ball FBGA (8 x 8 grid)
Part Number Example:
FL
EM28C1602C3FL-90 TET
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DEVICE MARKING
Due to the size of the package, NanoAmp's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to NanoAmp part numbers in Table 1. www..com SRAM provides the data retention capability whenever required. The data retention S_VCC is specified as low as 1.0V. The device supports two VPP voltages; in-circuit VPP of 1.65V-3.3V and production compatibility of 12V 5%. The 12V 5% VPP is supported for a maximum of 100 cycles and 10 cumulative hours. The EM28C1602C3FL contains an asynchronous 2Mb SRAM organized as 128K-words by 16 bits. This device is fabricated using an advanced CMOS process and highspeed/ultra-low-power circuit technology. The EM28C1602C3FL is packaged in a 66-ball FBGA package with 0.80mm pitch. Advance
GENERAL DESCRIPTION
The EM28C1602C3FL, a combination of Flash and SRAM memory, provides a compact, low-power solution for systems where PCB real estate is at a premium. The device contains a nonvolatile, electrically block-erasable (flash), programmable, read-only memory containing 16,777,216 bits organized as 1,048,576 words (16 bits). The device also provides soft protection for blocks by configuring soft protection registers with dedicated command sequences. A 128-bit (OTP )one time programmable register is provided. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). The WSM simplifies these operations and relieves the system processor of secondary tasks. An on-chip status register, can be used to monitor the WSM status to determine the progress of a PROGRAM/ERASE command. The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages. The device takes advantage of a dedicated power source for the Flash device (F_VCC) and a dedicated power source for the SRAM device (S_VCC), both at 2.7V-3.3V for optimized power consumption and improved noise immunity. The separate S_VCC pin for the
Table 1 Cross Reference for Abbreviated Device Marks
PART NUMBER EM28C1602C3FL-90 BET EM28C1602C3FL-90 TET PRODUCT MARKING FW220 FW221 SAMPLE MARKING ES220 ES221 MECHANICAL SAMPLE MARKING FY220 FY221
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Advance
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FLASH FUNCTIONAL BLOCK DIAGRAM
DQ0-DQ15 X DEC Data Input Buffer Data Register RP# CE# WE# OE# Y/Z DEC Bank a Blocks Y/Z Gating/Sensing
ID Reg.
CSM
Status Reg.
WSM
Program/ Erase Change Pump Voltage Switch Output Multiplexer
DQ0-DQ15
Output Buffer
I/O Logic Data Comparator
A0-A19
Address Input Buffer
APS Control
Address CNT WSM Address Multiplexer
Y/Z DEC X DEC
Y/Z Gating/Sensing Bank b Blocks
Address Latch
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BALL DESCRIPTIONS
66-BALLFBGA NUMBERS SYMBOL TYPE Input DESCRIPTION Address Inputs: Inputs for the addresses during READ and WRITE operations. Addresses are internally latched during READ and WRITE cycles. Flash: A0-A19; SRAM: A0-A16. Advance
A4, A5, A6, A0-A19 A7, A8, B3, B4, www..com B5, B6, E5, G3, G4, G5, G6, G7, G8, G9, H4, H5, H6 H7 H9 C3 D4 F_CE# F_OE# F_WE# F_RP#
Input Input Input Input
Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Flash Output Enable: Enables flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. Flash Write Enable: Determines if a given cycle is a flash WRITE cycle. F_WE# is active LOW. Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. Flash Write Protect. Controls the lock down function of the flexible locking feature. SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0-DQ7). SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8-DQ15). Data Inputs/Outputs: Input array data on the second CE# and WE# cycle during PROGRAM command. Input commands to the command user interface when CE# and WE# are active. Output data when CE# and OE# are active. (continued on next page)
E3 G10
F_WP# S_CE1#
Input Input
D8
S_CE2
Input
F5 B8 F3 F4
S_OE# S_WE# S_LB# S_UB#
Input Input Input Input Input/ Output
B7, B9, B10, DQ0-DQ15 C7, C8, C9, C10, D7, E6, E8, E9, E10, F7, F8, F9, F10
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BALL DESCRIPTIONS (continued)
66-BALLFBGA NUMBERS E4 SYMBOL F_VPP TYPE Input/ Supply DESCRIPTION Flash Program/Erase Power Supply: [1.65V-3.3V or 11.4V-12.6V]. Operates as input at logic levels to control complete device protection. Provides backward compatibility for factory programming when driven to 11.4V- 12.6V. Lower F_VPP voltages are available; consult factory for availability. Flash Power Supply: [2.7V-3.3V]. Supplies power for device operation. Flash Specific Ground: Do not float any ground pin. SRAM Power Supply: [2.7V-3.3V]. Supplies power for device operation. SRAM Specific Ground: Do not float any ground pin. No Connect: Lead is not internally connected; it may be driven or floated. Advance
www..com D10 A9, H8 D9 D3 A1, A2, A3, A10, A11, A12, C4, H1, H2, H3, H10, H11, H12 F_VCC F_VSS S_VCC S_VSS NC Supply Supply Supply Supply -
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TRUTH TABLE - FLASH
MODES FLASH SIGNALS SRAM SIGNALS F_RP# F_CE# F_OE# F_WE#S_CE1#S_CE2 S_OE# S_WE# S_UB# S_LB# L L H L X L H X H X H L X H X SRAM must be High-Z MEMORY OUPUT MEMORY DQ0-DQ15 BUS CONTROL Flash Flash Other Other Other DOUT DIN High-Z High-Z High-Z NOTES 1, 2, 3 1 4, 5 4, 6 4, 7
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Read H Write H www..com Standby H Output Disable H Reset L
SRAM any mode allowable
TRUTH TABLE - SRAM
MODES Read DQ0-DQ15 DQ0-DQ7 DQ8-DQ15 Write DQ0-DQ15 DQ0-DQ7 DQ8-DQ15 Standby Output Disable Data Retention NOTES: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. FLASH SIGNALS SRAM SIGNALS F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# MEMORY OUPUT MEMORY DQ0-DQ15 BUS CONTROL SRAM SRAM SRAM SRAM SRAM SRAM Other Other Other Other DOUT DOUT LB DOUT UB DIN DIN LB DIN UB High-Z High-Z High-Z High-Z NOTES
Flash must be High-Z
L L L L L L H X L
H H H H H H X L H
L L L
H H H
L H L L H L X X X
L L H L L H X X X
1, 3 8 9 1, 3 10 11 4, 5 4, 5 4, 5 4, 6
Flash any mode allowable
H L H L H L X X X X H H Same as standby
Two devices may not drive the memory bus at the same time. Allowable flash read modes include read array, read configuration, and read status. Outputs are dependent on a separate device controlling bus outputs. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs. The SRAM may be placed into data retention mode by lowering S_VCC to the VDR range, as specified. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to control the bus outputs at a time. Data output on lower byte only; upper byte High-Z. Data output on upper byte only; lower byte High-Z. Data input on lower byte only. Data input on upper byte only.
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ARCHITECTURE AND MEMORY ORGANIZATION
The Flash memory array is segmented into 31 blocks of 32K words, along with eight 4K-word parameter blocks. The device is available with block architecture mapped in either of the two configurations: the parameter blocks located at the www..com top or at the bottom of the memory array, as required by different microprocessors. The EM28C1602C3 top boot configuration with the blocks and address ranges is shown in Figure 1 and the bottom boot configuration in Figure 2. Advance
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FLASH
EM28C1602C3FL NanoAmp Solutions, Inc.
ADDRESS RANGE FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH www..com E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 00000H
Advance
8 x 4K-Word Blocks 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4K-Word Block Parameter Blocks 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block
FFFFFH FF000H FEFFFH FE000H FDFFFH FD000H FCFFFH FC000H FBFFFH FB000H FAFFFH FA000H F9FFFH F9000H F8FFFH F8000H
Figure 1 Top Boot Block Device
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ADDRESS RANGE FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH www..com E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 0FFFFH 08000H 07FFFH 00000H
Advance
32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 8 x 4K-Word Blocks
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 07FFFH 07000H 06FFFH 06000H 05FFFH 05000H 04FFFH 04000H 03FFFH 03000H 02FFFH 02000H 01FFFH 01000H 00FFFH 00000H
4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block Parameter Blocks 4K-Word Block 4K-Word Block
Figure 2 Bottom Boot Block Device
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FLASH
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FLASH MEMORY OPERATING MODES
COMMAND STATE MACHINE Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available www..com commands are listed in Table 2, their definitions are given in Table 3 and their descriptions in Table 4. Program and erase algorithms are automated by the on-chip WSM. Table 5 shows the CSM transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the write state machine status (WSMS) bit (SR7) (see Table 7) is set to a logic HIGH level (VIH), allowing the CSM to respond to the full command set again. OPERATIONS Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/O pins DQ0-DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control pins F_CE# and F_WE# must be at a logic LOW level (VIL), and F_OE# and F_RP# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at logic HIGH (VIH). Advance
Table 6 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. The on-chip status register allows the monitoring of the progress of various operations that can take place. The status register is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1) and reading the register data on I/O pins DQ0-DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 7). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 3 for the CSM command definitions and data for each of the bus cycles. STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored toggling F_OE#, F_CE#, and address lines by reading the resulting status code on I/O pins DQ0-DQ7. The highorder I/Os (DQ8-DQ15) are set to 00h internally, so only the low-order I/O pins (DQ0-DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated on the falling edge of F_OE# or F_CE#, whichever occurs first. The latest falling edge of either of these two signals updates the latch within a
Table 2 Command State Machine Codes For Device Mode Selection
COMMAND DQ0-DQ7 10h/40h 20h 50h 60h 70h 90h 0Fh B0h D0h FFh AFh CODE ON DEVICE MODE Program setup/alternate program setup Block erase setup Clear status register Reserved Read status register Read device identity Soft protection Program/erase suspend Program/erase resume - erase confirm Read array/OTP exit OTP entry
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given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register read. To ensure that the status register output contains updated status data, CE# or OE# must be toggled for each subsequent STATUS READ. The status register provides the internal state of the www..com microprocessor. During periods WSM to the external when the WSM is active, the status register can be polled to determine the WSM status. Table 7 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0-DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM. COMMAND STATE MACHINE OPERATIONS The CSM decodes instructions for the commands Advance
listed in Table 2. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 3 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSMS bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
Table 3 Command Definitions
FIRST CYCLE COMMAND READ ARRAY IDENTIFY DEVICE READ STATUS REGISTER WORD PROGRAM BLOCK ERASE PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME CLEAR STATUS REGISTER SOFT PROTECTION OTP ENTRY OTP EXIT
NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9.
SECOND CYCLE CSM/INPUT FFh 90h 70h 10h/40h 20h B0h D0h 50h 0Fh AFh FFh WRITE WRITE WRITE BA X X SPC AFh FFh OPERATION READ READ READ WRITE WRITE ADDRESS WA IA BA WA BA DATA AD ID SRD PD D0h
OPERATION WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE
ADDRESS X X X X X X X X X X X
The command data is written through DQ0-DQ7 ID = Manufacturer ID: 002Ch; Device ID (Top Boot): 4492h; Device ID (Bottom Boot): 4493h IA = Identify address: 00000h for manufacturer code and 00001h for device code BA = Any address within the block to be selected WA = Word address AD = Array data SRD = Data read from status register PD = Data to be written at location WA SPC = Soft protect command: 00h = Clear all soft protection FFh = Set all soft protection F0h = Clear addressed block soft protection 0Fh = Set addressed block soft protection 10. X = Don't Care
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Table 4 Command Descriptions
CODE DEVICE MODE 10h Alt. Program Setup 20h Erase Setup www..com BUS CYCLE First First DESCRIPTION Operates the same as a PROGRAM SETUP command. Prepares the CSM for an ERASE CONFIRM command. If the next command is not ERASE CONFIRM, the CSM will set both SR4 and SR5 of the status register to a "1," place the device into read status register mode, and wait for another command. A two-cycle command: The first cycle prepares for a PROGRAM operation, the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The flash outputs status register data on the falling edge of F_OE# or F_CE#, whichever occurs first. The WSM can set the program status (SR4), and erase status (SR5) bits in the status register to "1," but it cannot clear them to "0." Issuing this command clears those bits to "0." Places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device will automatically enter this mode after a PROGRAM or ERASE operation has been initiated. Puts the device into the read configuration mode so that reading the device will output the manufacturer/device codes. Puts the device into the soft protection mode so that the protection bit for each block can be set and cleared. Suspends the currently executing PROGRAM/ERASE operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR2) or erase suspend (SR6) and the WSMS bit (SR7) to a "1" (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control pins except F_RP#, which will immediately shut down the WSM and the remainder of the chip if F_RP# is driven to VIL. If the previous command was an ERASE SETUP command, then the CSM will close the address and data latches, and it will begin erasing the block indicated on the address pins. During programming/erase, the device will respond only to the ERASE SUSPEND command and will output status register data on the falling edge of F_OE# or F_CE#, whichever occurs last. If a PROGRAM or ERASE operation was previously suspended, this command will resume the operation. During the array mode, array data will be output on the data bus. Exits the OTP area on second FFh command. Allows programming or reading of the OTP area on second AFh command. Advance
40h
Program Setup
First
50h
Clear Status Register Read Status Register
First
70h
First
90h 0Fh B0h
Read Device Identity Soft Protection Program Suspend Erase Suspend
First First First First
D0h
Erase Confirm
First
Program/Erase Resume FFh Read Array OTP Exit AFh OTP Entry
First First Second Second
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CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. www..com When the status bits are cleared, the device returns to the read array mode. Advance
READ OPERATIONS
The following READ operations are available: READ ARRAY, READ DEVICE IDENTIFICATION and READ STATUS REGISTER. READ ARRAY The array is read by entering the command code FFh on DQ0-DQ7. Control pins F_CE# and F_OE# must be at a logic LOW level (VIL), and F_WE# and F_RP# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up, the device defaults to the read array mode. READ DEVICE IDENTIFICATION DATA Device identification codes are read by entering command code 90h on DQ0-DQ7. Two bus cycles are required for this operation, the first to enter the command code and the second to read the selected code. Control pins CE# and OE# must be at a logic LOW level (VIL) and WE# and RP# must be at a logic HIGH level (VIH). The manufacturer code is obtained on DQ0-DQ15 in the second cycle, after the identify address 00000h is latched. The device code is obtained on DQ0-DQ15 in the second cycle, after the identify address 00001h is latched (see Table 3). READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0-DQ7. Control pins F_CE# and F_OE# must be at a logic LOW level (VIL), andF_ WE# and F_RP# must be at a logic HIGH level (VIH). Two bus cycles are required for this operation: one to enter the command code, and one to read the status register. The status register contents are updated on the falling edge of F_CE# or F_OE#, whichever occurs last within the cycle.
command code on DQ0-DQ7), the WSM takes over and correctly sequences the device to complete the PROGRAM operation. The WRITE operation may be monitored through the status register (see the Status Register section). During this time, the CSM will only respond to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which time all commands to the CSM become valid again. During programmust remain in the ming, VPP appropriate VPP voltage range as shown in the recommended operating conditions table. Different combinations of RP#, WP#, and VPP pin voltage levels ensure that data in certain blocks are secure and therefore cannot be programmed (see Table 5 for a list of combinations). Only "0s" are written and compared during a PROGRAM operation. If "1s" are programmed, the memory cell contents do not change and no error occurs. The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). Once the WSM reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER or PROGRAM RESUME commands. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 3 for programming operation and Figure 4 for program suspend and program resume).
ERASE OPERATIONS
An ERASE operation must be used to initialize all bits in an array block to "1s." After BLOCK ERASE confirm is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Block erasure is initiated by a command sequence to the CSM: BLOCK ERASE setup (20h) followed by BLOCK ERASE CONFIRM (D0h) (see Table 3). A twocommand erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. Monitoring of the ERASE operation is possible through the status register (see the Status
PROGRAMMING OPERATIONS
There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 2). After the desired command code is entered (10h or 40h
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Table 5 Command State Machine Transition Table
COMMAND INPUTS (and next state) Current State SR7 Data when Read Array Read Array (FFh) Read array Write setup (10h/ 40h) Write setup Block erase setup (20h) Erase setup Erase confirm (D0h) Prog./ erase susp. (B0h) Read array Prog./ erase resume (D0h) Read SR (70h) Read status Clear SR (50h) Read array Identify device (90h) Soft prot. setup (0Fh) Soft prot. (SPC) Otp entry (AFh) Otp entry
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Read Array 1
Identify Soft prot. Soft prot. device setup setup/ read array Identify device Soft prot. setup Soft prot. setup Soft prot. block Soft prot. setup/ read array Soft prot. setup/ read array Soft prot.
Read Status
1
Status
Read array
Write setup
Erase setup
Read array
Read status
Read array
Otp entry
Identify Device
1
ID
Read array
Write setup
Erase setup
Read array
Read status
Read array
Identify device
Otp entry
Soft Prot. Setup Soft Protection Complete Write Setup Program Not Complete Program Suspend Status Program Suspend Read Array Program Complete
1 1
Status Status
Soft prot. all Read array Write setup Erase setup
Read array Read array Read status Read array
Read array Otp entry
Identify Soft prot. Soft prot. device setup setup/ read array
1 0
Status Status Program (not complete) Prog. susp. status
Program Program (not complete) Program suspend read array
1
Status Program Program suspend Program Program Program Program susp. read array susp. susp. read read status array array Array Program Program suspend Program Program Program Program susp. read array susp. susp. read read status array array Read Array Write setup Erase setup Read array Read status Read array
1
Program suspend read array
1
Status
Identify Soft prot. Soft prot. device setup setup/ read array Erase command error
Otp entry
Erase Setup Erase Comd. Error
1 1
Status Status
Erase command error Read array Write setup Erase setup
Erase
Erase Read array
Erase Read status Read array
Identify device
Soft Soft prot. prot. setup/ setup Read array
Otp entry
Erase Not Complete Erase Suspend Status Erase Suspend Array Erase Complete
0
Status
Erase (not complete)
Erase susp. to status Erase Erase susp. read array Erase susp. read array Read array Erase Erase susp. status Erase susp. status Read status
Erase (not complete)
1
Status
Erase susp. read array Erase susp. read array Read array
Write setup
Erase susp. read array Erase susp. read array Erase setup
Erase suspend read array
1
Array
Write setup
Erase
Erase
Erase suspend read array
1
Status
Write setup
Read array
Identify device
Soft prot. setup
Soft prot. setup/ read array
Otp entry
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Register section). During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, PROGRAM SETUP, PROGRAM RESUME and ERASE www..com ERASE SUSPEND operation, array RESUME. During the data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set (see Figure 6). It is also possible that an ERASE in any block can be suspended and a WRITE to another block can be initiated. After the completion of a WRITE, the ERASE can be resumed by writing an ERASE RESUME command. Advance
Table 6 Bus Operations
MODE Read (array, status register, device identification register) Standby Output Disable Reset Write F_RP# VIH F_CE# VIL F_OE# VIL F_WE# VIH ADDRESS X DQ0-DQ15 DOUT
VIH VIH VIL VIH
VIH VIL X VIL
X VIH X VIH
X VIH X VIL
X X X X
High-Z High-Z High-Z DIN
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Table 7 Status Register Bit Definition
WSMS ESS ES PS www..com 7 6 5 4 VPPS 3 PSS 2 BLS 1 R 0
STATUS BIT # STATUS REGISTER BIT SR7
DESCRIPTION
WRITE STATE MACHINE STATUS(WSMS) Check write state machine bit first to determine word 1 = Ready program or block erase completion, before checking 0 = Busy program or erase status bits. ERASE SUSPEND STATUS (ESS) 1 = BLOCK ERASE Suspended 0 = BLOCK ERASE in Progress/Completed ERASE STATUS (ES) 1 = Error in Block Erasure 0 = Successful BLOCK ERASE PROGRAM STATUS (PS) 1 = Error in PROGRAM 0 = Successful PROGRAM VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP = OK When ERASE SUSPEND is issued, WSM halts execution and sets both WSMS and ESS bits to "1." ESS bit remains set to "1" until an ERASE RESUME command is issued. When this bit is set to "1," WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to "1," WSM has attempted but failed to program a word. The VPP status bit does not provide continuous indication of the VPP level. The WSM interrogates the VPP level only after the program or erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP level is also checked before the PROGRAM/ERASE operation is verified by the WSM. When PROGRAM SUSPEND is issued, WSM halts execution and sets both WSM and PSS bits to "1." PSS bit remains set to "1" until a PROGRAM RESUME command is issued. If a PROGRAM or ERASE operation is attempted to one of the locked blocks, this is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future.
SR6
SR5
SR4
SR3
SR2
PROGRAM SUSPEND STATUS (PSS) 1 = PROGRAM Suspended 0 = PROGRAM in Progress/Completed BLOCK LOCK STATUS (BLS) 1 = PROGRAM/ERASE Attempted on a Locked Block; Operation Aborted 0 = No Operation to Locked Blocks RESERVED FOR FUTURE ENHANCEMENT
SR1
SR0
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Figure 3 Automated Word Programming Flowchart
Start
Advance
WRITE
WRITE PROGRAM SETUP WRITE DATA
Data = Addr = Data = Addr =
40h or 10h Don't care Word to be programmed Address of word to be programmed
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Issue PROGRAM SETUP Command and Word Address
WRITE
READ
Issue Word Address and Word Data
Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
Standby
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop
Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode.
YES
Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION C O M M A N D COMMENTS Standby Standby Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP low Check SR43 1 = Word program error
SR1 = 0? YES
NO PROGRAM Attempted on a Locked Block
Standby
NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed
VPP Range Error
Word Program Failed
NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts.
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BUS OPERATION C O M M A N D COMMENTS
EM28C1602C3FL NanoAmp Solutions, Inc.
Figure 4 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
Start
www..com BUS OPERATION C O M M A N D COMMENTS WRITE READ PROGRAM SUSPEND Data = B0h Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready Check SR2 1 = Suspended READ MEMORY Data = FFh Read data from block other than that being programmed. PROGRAM RESUME Data = D0h Addr = Don't care Advance
Issue PROGRAM SUSPEND Command
Standby Standby WRITE READ WRITE
Read Status Register Bits
NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command PROGRAM Complete
Finished Reading ? YES Issue PROGRAM RESUME Command
NO
PROGRAM Resumed
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Figure 5 BLOCK ERASE Flowchart
BUS OPERATION C O M M A N D COMMENTS WRITE WRITE ERASE SETUP ERASE Data = 20h Addr = Don't care Data = D0h Block Addr = Address within block to be erased Status register data; toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy Advance
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WRITE
READ
Standby
Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode.
BUS OPERATION C O M M A N D COMMENTS Standby Standby Standby Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP block Check SR4 and SR5 1 = BLOCK ERASE command error Check SR53 1 = BLOCK ERASE error
Standby
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked.
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Figure 6 ERASE SUSPEND/ERASE RESUME Flowchart
Start
Advance
COMMAND ERASE SUSPEND
COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register Check SR7 1 = Ready Check SR6 1 = Suspended
WRITE READ
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Issue ERASE SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE or WRITE READ or WRITE
READ MEMORY WRITE SETUP
Data = FFh Data = 40h or 10h Addr = Don't Care Read data from block other than that being erased
NO SR7 = 1? YES NO SR6 = 1? YES ERASE Complete PROGRAM
WRITE DATA
Data = Word to be programmed Addr = Address of word to be programmed Data = D0h Addr = Don't Care
WRITE
ERASE RESUME
READ or PROGRAM? READ Issue READ ARRAY Command
PROGRAM Loop
NO
READ or PROGRAM Complete? YES Issue ERASE RESUME Command
(Note 2)
ERASE Continued1
NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure.
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BUS OPERATION
EM28C1602C3FL NanoAmp Solutions, Inc.
OTP MODE
The device has 128 bits of OTP (one time programmable) area. There are 64 bits that are programmed at the factory with a unique 64-bit code that is not modifiable. The other 64-bit OTP area is left blank to program for customer design requirements if needed. Protection of the userprogrammable, 64-bit www..com contents is provided, after the area is programmed, by programming the lock-bit. To program the OTP area, two "AFh" commands must be written, followed by two WRITE cycles of the normal program sequences. When in the OTP mode, the WSM programs the OTP area and not the array. During programming, a read can acquire only the WSM status (status register output). When the programming is complete, the device remains in the OTP mode and only the status can be read in the OTP area. Writing two "FFh" commands exits the OTP mode and causes the device to go into the read array mode. To read the OTP area after programming, the OTP mode must be re-entered. To read the OTP area contents, two "AFh" commands must be written, followed by a READ. Writing two "FFh" commands exits the OTP mode and causes the device to go into the read array mode. After programming the 64-bit OTP area, the lock-bit can be programmed. The lock-bit is at address 00040H and is on DQ15. Once the lock-bit is programmed to a "0," the 64bit, user-programmable area is permanently protected (see Figure 7). The lock- bit can be read in OTP mode, as described above. Advance
Icc supply current is reduced by applying a logic HIGH level on F_CE# and F_RP# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on F_CE# and F_RP# reduces the current to ICC2 (MAX). If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete.
SOFT BLOCK DATA PROTECTION
Soft protection is available with CSM command 0Fh (see Table 3). The protection bit for each block can be set and cleared individually, or all at once. After the soft protection bit of a block is set, the block is protected when VPP > VPPLK, RP# is HIGH, and WP# is LOW. When VPP VPPLK the block is protected (locked) as well. A block is unlocked when WP# is HIGH, even if its soft protection bit is set (see Table 8).. When the device is powered down or RP# reset, the soft protection blocks will be set to the protected state. So, if WP# goes LOW after first power-up, RP# reset, or power-down, all blocks will be protected. The CSM command 0Fh is needed to clear the soft protected blocks. When WP# goes LOW the cleared blocks will be unprotected. The block lock status bit SR1 is used to monitor the individual block lock status after the second WRITE cycle of the soft protection CSM command. Additionally, to monitor the block lock status of any block, the read status register command 70h can be used. On the command's second cycle, any address within a block is issued and SR1 will indicate the block lock status for that block. When monitoring the block lock status bit SR1, the correct status can only be obtained with WP# LOW.
00000H 00002H 4 Words 00004H Factory-Programmed1 00006H 00020H 00022H 00024H 00026H 00040H
DQ15
AUTOMATIC POWER SAVE MODE (APS)
Substantial power savings are realized during periods when the Flash array is not being read and the device is in the active mode. During this time the device switches to the automatic power save (APS) mode. When the device switches to this mode, ICC is reduced to ICC2. The low level of power is maintained until another operation is initiated. In this mode, the I/O pins retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control pins toggle. At least one transition of F_CE# must occur after power-up to activate this mode's availability.
4 Words User-Programmed2
Figure 7 OTP Area Map
NOTE: 1. Always locked. 2. Locked by programming DQ15 at address 00040H.
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STANDBY MODE
EM28C1602C3FL NanoAmp Solutions, Inc.
Table 8 Data Protection Combinations
DATA PROTECTION PROVIDED www..com All blocks locked All blocks locked All blocks unlocked Soft-protected blocks unlocked VPP VPPLK X RP# X VIL VIH VIH WP# X X VIH VIL Advance
VPPLK VPPLK
VPP / VCC PROGRAM AND ERASE VOLTAGES
The flash memory of the EM28C1602C3FL provides in-system programming and erase with VPP in the 1.65V-3.3V range. VPP at 12V 5% is supported for a maximum of 100 cycles and 10 cumulative hours. The device can withstand 100,000 WRITE/ERASE operations with VPP = VCC. During WRITE and ERASE operations, the WSM monitors the VPP voltage level. WRITE/ERASE operations areallowed only when VPP is within the ranges specified in Table 9.
Table 9 VPP RANGE (V)
In-System In-Factory MIN 1.65 11.4 MAX 2.2 12.6
POWER-UP
During a power-up, it is not necessary to sequence VCC Q, VCC and VPP. However, it is recommended that RP# be held LOW during power-up for additional protection while VCC is ramping above VLKO to a stable operative level. After a power-up or RESET, the status register is reset, and the device will enter the array read mode. POWER-UP PROTECTION The likelihood of unwanted WRITE or ERASE operations is minimized since two consecutive cycles are required to execute either operation. When VCC < VLKO, the device does not accept any WRITE cycles, and noise pulses < 5ns on CE# or WE# do not initiate a WRITE cycle.
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FLASH ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Pin Except VCC and VPP with Respect to VSS ..................... -0.5V to +4.0V VPP Voltage (for BLOCK ERASE and PROGRAM) with Respect www..com to VSS ................ -0.5V to +13.0V** VCC Supply Voltage with Respect to VSS ..................... -0.3V to +4.0V Output Short Circuit Current ................................. 100mA Operating Temperature Range ................. -40oC to +85oC Storage Temperature Range .................. -55oC to +125 oC Soldering Cycle .......................................... 260oC for 10s *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum DC voltage on Vpp may overshoot to +13.5V for periods less than 20ns. Advance
RECOMMENDED OPERATING CONDITIONS
PARAMETER Operating temperature VCC supply voltage Supply voltage, when used as logic control VPP in-factory programming voltage Data retention supply voltage Block erase cycling SYMBOL
tA
MIN -40 2.7 1.65 11.4 1.0 100,000
MAX +85 3.3 3.3 12.6 - -
UNITS
oC
NOTES
F_VCC, S_VCC VPP1 VPP2 S_VDR
V V V V Cycles 1
NOTE: 1. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours.
VCC 14.5K I/O 14.5K VSS 30pF
Figure 8 Output Load Circuit
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COMBINED DC CHARACTERISTICS
VCC = 2.7V-3.3V DESCRIPTION www..com Input Low Voltage Input High Voltage Output Low Voltage IOL = 100 A Output High Voltage IOH = 100 A VPP Lock Out Voltage VPP During Program/Erase Operations VCC Program/Erase Lock Voltage Input Leakage Current Output Leakage Current F_VCC Read Current at 5MHz F_VCC plus S_VCC Standby Current F_VCC Program Current F_VCC Erase Current F_VCC/S_VCC Erase Suspend Current F_VCC/S_VCC Program Suspend Current Read-While-Write Current S_VCC Read/Write Operating Supply Current - Word Access Mode VIN = VIH or VIL Chip Enabled, IOL = 0
VCC=VCC(MAX) VCC=VCC(MAX) Vcc=Vcc(MAX) CE#=Vil,OE#=VihRP#=Vih Vcc=Vcc(MAX) Vcc = Vcc (MIN),
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CONDITIONS
SYMBOL VIL VIH VOL VOH 0.1V VPPLK VPP1 VPP2 VLKO IL IOZ ICC1 ICC3 ICC4+IPP3 ICC5+IPP4 ICC6 ICC7 ICC8 ICC10
MIN -0.2 VCC 0.2V - VCC - 1.65 11.4 1.5 - - - - - - - - - -
TYP - - - - - - - - - - - 25 - - - - - 3
MAX 0.2 VCC + 0.2V 0.10 - 1.0 3.3 12.6 - 1 10 30 70 55 45 25 25 95 8
UNITS V V V V V V V V A A mA A mA mA A A mA mA
NOTES
Vcc=Vcc(MIN),
2
3
4
NOTE: 1. 2. 3. 4.
All currents are in RMS unless otherwise noted. 12V VPP is supported for a maximum of 100 cycles and may be connected for up to 10 cumulative hours. Icc is dependent on cycle rates. Operating current is a linear function of operating frequency and voltage. Operating current can be calculated using the formula shown with operating frequency (f) expressed in MHz and operating voltage (V) in volts. Example: When operating at 2 MHz at 2V, the device will draw a typical active current of 0.8*2* = 3.2mA in the page access mode. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system.
(continued on the next page)
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COMBINED DC CHARACTERISTICS (continued)
VCC = 2.7V-3.3V DESCRIPTION VPP Read Current www..com VPP Standby Current VPP Erase Suspend Current VPP Program Suspend Current CONDITIONS VPP VCC VPP VCC VPP VCC VPP VCC VPP = VPP1 VPP = VPP2 VPP = VPP1 VPP = VPP2
NOTE: 1. All currents are in RMS unless otherwise noted.
Advance
SYMBOL IPP1 IPP2 IPP5 IPP6
MIN - - - - - - - -
TYP - - - - - - - -
MAX 15 200 10 200 10 200 10 200
UNITS NOTES A A A A A A A A
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FLASH READ CYCLE TIMING REQUIREMENTS
-90 VCC = 2.7V-3.3V MIN MAX 90 90 30 600 25 0 20 90
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PARAMETER Address to output delay w wCE#.LOW toa s h e e t 4 u . c o m w d a t output delay OE# LOW to output delay F_RP# HIGH to output delay CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# change CE# HIGH between subsequent synchronous READs READ Cycle Time
SYMBOL tAA tACE tAOE tRWH tOD tOH tCBPH tRC
UNITS ns ns ns ns ns ns ns ns
FLASH WRITE CYCLE TIMING REQUIREMENTS
-90 VCC = 2.7V-3.3V MIN MAX 150 0 70 50 70 0 0 0 30 0 200 30 0 0 200 6 0.5 0.5 1
PARAMETER Reset HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH CE# hold from WE# HIGH Data hold from WE# HIGH Address hold from WE# HIGH Write pulse width HIGH WP# setup to WE# going HIGH VPP setup to WE# going HIGH OE# hold from WE# going HIGH WP# hold from valid SRD VPP hold from valid SRD WE# HIGH to busy status WRITE duration Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration
SYMBOL tRS tCS tWP tDS tAS tCH tDH tAH tWPH tWHS tVPS tOHH tWHH tVPH tWB tWED1 tWED2 tWED3 tWED4
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us s s s
FLASH ERASE AND PROGRAM CYCLE TIMING REQUIREMENTS
2.7V-3.3V Vcc 1.65V-3.3V VPP PARAMETER Boot/parameter BLOCK ERASE time Main BLOCK ERASE time Boot/parameter BLOCK WRITE time Main BLOCK WRITE time Program/erase suspend latency TYP 0.5 1 0.1 0.3 1 MAX 4 5 - - 3 12V VPP TYP 0.5 1 0.1 0.3 1 MAX 4 5 - - 3 UNITS NOTES s s s s s
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WRITE/ERASE OPERATION
VIH A0-A19 VIL Note 1 tAS tAH tAS AIN tAH
Advance
VIH www..com CE# VIL tCS VIH OE# VIL VIH WE# VIL tDS DQ0-DQ15 VIH VIL VIH RP# VIL VIH WP# VIL tVPS VPP VPPH VIL WRITE or block address asserted, and WRITE data or ERASE CONFIRM tVPH tWHS [Unlock soft-protected blocks] tWHH tRS CMD in tWB tDH tDS CMD/ Data-in tDH Status (SR7=0) Status (SR7=1) CMD in tWP tWPH tOHH tWED1, 2, 3, 4 tCH
WRITE SETUP or ERASE SETUP input
WRITE or ERASE executed, status register checked for completion
Command for next operation issued
DON'T CARE
TIMING PARAMETERS
SYMBOL tWPH tWP tAS tAH tDS t DH tCS t CH tVPS tRS -90 MIN 30 70 70 0 50 0 0 0 200 150 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tWED1 tWED2 tWED3 tWED4 tVPH tWB tWHS tWHH tOHH -90 MIN 6 0.5 0.5 1 0 200 0 0 30 UNITS s s s s ns ns ns ns ns
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READ OPERATION
A0-A20 VIH VALID ADDRESS VIL
tRC
Advance
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tAA tOD
VIH CE# VIL
tACE
VIH OE# VIL
tOH
VIH WE# VIL VOH DQ0-DQ15 VOL
tAOE
High-Z
tRWH
VALID OUTPUT
RP#
VIH VIL
UNDEFINED
READ TIMING PARAMETERS
-90 VCC = 2.7V-3.3V MIN MAX 90 90 30 600 -90 VCC = 2.7V-3.3V MIN MAX 25 0 90
SYMBOL tAA tACE tAOE tRWH
UNITS ns ns ns ns
SYMBOL
tOD tOH t RC
UNITS ns ns ns
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EM28C1602C3FL NanoAmp Solutions, Inc.
SRAM OPERATING MODES
SRAM READ ARRAY The operational state of the SRAM is determined by S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as indicated in the Truth Table. In order to perform an SRAM READ operation, S_CE1#, and S_OE#, must be at VIL, and S_CE2 and www..comS_WE# must be at VIH. When in this state, S_UB# and S_LB# control whether the lower byte is read (S_UB# VIH, S_LB# VIL), the upper byte is read (S_UB# VIL, S_LB# VIH), both upper and lower bytes are read (S_UB# VIL, S_LB# VIL), or neither are read (S_UB# VIH, S_LB# VIH) and the device is in a standby state. While performing an SRAM READ operation, current consumption may be reduced by reading within a 16-word page. This is done by holding S_CE1# and S_OE# at VIL, S_WE# and S_CE2 at VIH, and toggling addresses A0-A3. S_UB# and S_LB# control the data width as described above. SRAM WRITE ARRAY In order to perform an SRAM WRITE operation, S_CE1# and S_WE# must be at VIL, and S_CE2 and S_OE# must be at VIH. When in this state, S_UB# and S_LB# control whether the lower byte is written (S_UB# VIH, S_LB# VIL), the upper byte is written (S_UB# VIL, S_LB# VIH), both upper and lower bytes are written (S_UB# VIL, S_LB# VIL), or neither are written (S_UB# VIH, S_LB# VIH) and the device is in a standby state. Advance
SRAM FUNCTIONAL BLOCK DIAGRAM
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SRAM
EM28C1602C3FL NanoAmp Solutions, Inc.
TIMING TEST CONDITIONS
Input pulse levels .................... 0.1V VCC to 0.9V VCC Input rise and fall times ....................................... 5ns Input timing reference levels ............................. 0.5V Output timing reference levels .......................... 0.5V www..com Operating Temperature ..................... -40oC to +85oC Advance
SRAM READ CYCLE TIMING
DESCRIPTION Read Cycle Time Address Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Enable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change SYMBOL tRC tAA tCO tOE tLB, tUB t LZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH MIN 85 MAX 85 85 35 85 0 0 0 0 0 0 5 UNITS ns ns ns ns ns ns ns ns ns ns ns ns
15 15 15
SRAM WRITE CYCLE TIMING
DESCRIPTION Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to High-Z Output Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output SYMBOL t WC tCW t AW tLBW, tUBW t AS tWP tWR tWHZ tDW tDH tOW MIN 50 50 50 0 50 0 0 50 0 0 MAX 85 UNITS ns ns ns ns ns ns ns ns ns ns ns
15
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SRAM
EM28C1602C3FL NanoAmp Solutions, Inc.
READ CYCLE 1 (S_CE1# = S_OE# = VIL; S_CE2, S_WE# = VIH)
tRC
Advance
ADDRESS
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tOH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
READ CYCLE 2 (S_WE# = VIH)
tRC
ADDRESS
tAA tHZ (1, 2)
S_CE1#
tCO
S_CE2
tLZ(2) tOE tOHZ (1)
S_OE#
tOLZ tLB, tUB
S_LB#, S_UB#
tLBLZ, tUBLZ tLBHZ, tUBHZ DATA VALID
DATA OUT
High-Z
DON'T CARE
READ TIMING PARAMETERS
SYMBOL tRC tA A tCO tOE tLB, tUB tLZ MIN MAX 85 85 85 35 85 UNITS ns ns ns ns ns ns SYMBOL tOLZ tHZ tOHZ tLBHZ, tUBHZ tOH MIN 0 0 0 0 5 MAX 15 15 15 UNITS ns ns ns ns ns
0
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SRAM
tAA
EM28C1602C3FL NanoAmp Solutions, Inc.
WRITE CYCLE (S_WE# CONTROL)
tWC
Advance
ADDRESS
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S_CE1#
tAW
tWR
tCW
S_CE2
tLBW, tUBW
S_LB#, S_UB#
tAS tWP
S_WE#
tDW tDH
DATA IN
High-Z
tWHZ
DATA VALID tOW
DATA OUT
High-Z DON'T CARE
WRITE TIMING PARAMETERS
SYMBOL tWC tCW tA W tLBW, tUBW tAS tWP MIN MAX 85 85 85 85 UNITS ns ns ns ns ns ns SYMBOL tWR tWHZ t DW t DH tOW MIN 0 0 50 0 0 MAX 15 UNITS ns ns ns ns ns
0 50
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SRAM
EM28C1602C3FL NanoAmp Solutions, Inc.
WRITE CYCLE 2 (S_CE1# CONTROL)
tWC
Advance
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ADDRESS
tCW
S_CE1#
tAS tLBW, tUBW
S_LB#, S_UB#
tWP
S_WE#
tDW tDH
DATA IN
tLZ tWHZ
DATA VALID
DATA OUT
High-Z DON'T CARE
WRITE TIMING PARAMETERS
SYMBOL tWC tCW tA W tLBW, tUBW tAS tWP MIN MAX 85 85 85 85 UNITS ns ns ns ns ns ns SYMBOL tWR tWHZ t DW t DH tOW MIN 0 0 50 0 0 MAX 15 UNITS ns ns ns ns ns
0 50
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SRAM
tAW
tWR
EM28C1602C3FL NanoAmp Solutions, Inc.
Advance
66-BALL FBGA
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A1 BALL C ORN ER
S2
A1 BALL C ORN ER
S1 e E b D
TO P V IEW: Ba ll Down BO TTOM V IEW : Ball Up
A2 A SEATING PLAN E - Z (Coplanari ty) A1
S IDE VI EW
FBGA PACKAGE DIMENSIONS
Package height Solder ball height (Standoff) Package body thickness Ball lead diameter Body length Body width Ball pitch Seating plane coplanarity Corner to first bump distance Corner to first bump distance A A1 A2 b D E e Z S1 S2 MIN 1.20 0.30 0.92 0.325 11.90 7.90 NOM 1.30 0.35 0.97 0.40 12.00 8.00 0.80 1.20 1.60 MAX 1.40 0.40 1.02 0.475 12.10 8.10 0.10 1.30 1.70
All dimensions in millimeters. Solder ball material: 63% Sn, 37% Pb Substrate: plastic laminate Mold compound: epoxy novolac
1.10 1.50
Revision History
Revision # A B Date January 2001 May 8, 2001 Description Preliminary Release Updated ballout, removed -11
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