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Datasheet, V1.2, 06 Feb 2007
CCM-PFC
ICE1PCS02 ICE1PCS02G
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) with Input Brown-Out Protection
Pow e r M a na ge m e nt & S upply
Never
stop
thinking.
CCM-PFC Revision History: Previous Version: Page 2007-02-06 V 1.1 Datasheet
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Edition 2007-02-06 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen
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CCM-PFC
Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) with Input Brown-Out Protection
Product Highlights
* * * * * * *
* * * * * * * * * * * * * * * *
ICE1PCS02 ICE1PCS02G
ICE1PCS02
PG-DIP-8
Leadfree DIP and DSO Package Wide Input Range Direct sensing, Input Brown-Out Detection Optimized for applications which require fast Startup Output Power Controllable by External Sense Resistor Fast Output Dynamic Response during Load Jumps Trimmed, internal fixed Switching Frequency (65kHz)
ICE1PCS02G test
PG-DSO-8
Features
Ease of Use with Few External Components Supports Wide Input Range Average Current Control External Current and Voltage Loop Compensation for Greater User Flexibility Trimmed internal fixed Switching Frequency (65kHz+7.7% at 25oC) Direct sensing, Input Brown-Out Detection with Hysteresis Short Startup(SoftStart) duration Max Duty Cycle of 97% (typ) Trimmed Internal Reference Voltage (5V+2%) VCC Under-Voltage Lockout Cycle by Cycle Peak Current Limiting Over-Voltage Protection Open Loop Detection Soft Overcurrent Protection Enhanced Dynamic Response Fulfills Class D Requirements of IEC 1000-3-2
Description
The ICE1PCS02/G is a 8-pin wide input range controller IC for active power factor correction converters. It is designed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC. The IC operates in the CCM with average current control, and in DCM only under light load condition. The switching frequency is trimmed and fixed internally at 65kHz. Both current and voltage loop compensations are done externally to allow full user control. There are various protection features incorporated to ensure safe system operation conditions. The internal reference is trimmed (5V+2%) to ensure precise protection and output control level. The ICE1PCS02/G is a design variant of ICE1PCS01 to incorporate the new input brown-out protection function and optimised to have a faster startup time with controlled peak startup current.
Typical Application
Auxiliary Supply
85 ... 265 VAC
VOUT
VCC
EMI-Filter CCM PFC
VINS
ICE1PCS02 /G
Protection Unit Voltage Loop Compensation
VSENSE
Brown-out PWM Logic Driver
GATE
Fixed Oscillator
ICOMP
Ramp Generator Nonlinear Gain
GND
VCOMP
Current Loop Compensation
ISENSE
Type ICE1PCS02 ICE1PCS02G
Version 1.2
Package PG-DIP-8 PG-DSO-8
3 06 Feb 2007
CCM-PFC ICE1PCS02/G
1 1.1 1.2 2 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.7 3.8 3.8.1 3.8.2 3.9 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 5
Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Input Brown-Out Protection (IBOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Open Loop Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Fixed Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
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Pin Configuration and Functionality
1
1.1
Pin 1 2 3 4 5 6 7 8
Pin Configuration and Functionality
Pin Configuration
Symbol GND ICOMP ISENSE VINS VCOMP Function IC Ground Current Loop Compensation Current Sense Input Brown-out Sense Input Voltage Loop Compensation ICOMP (Current Loop Compensation) Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA2 and averages the current sense signal. ISENSE (Current Sense Input) The ISENSE Pin senses the voltage drop at the external sense resistor (R1). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block. During power up time, high inrush currents cause high voltage drop at R1, driving currents into pin 3 which could be beyond the absolute maximum ratings. Therefore a series resistor (R2) of around 220 is recommended in order to limit this current into the IC. VINS (Brown-out Sense Input) This VINS pin senses a filtered input voltage divider and detects for the input voltage Brown-out condition. A Brown-out condition of VINS<0.8V, shuts down the IC. The IC turns on at VINS>1.5V. VSENSE (Voltage Sense/Feedback) The output bus voltage is sensed at this pin via a resistive divider. The reference voltage for this pin is 5V. VCOMP (Voltage Loop Compensation) This pin provides the compensation of the output voltage loop with a compensation network to ground (see Figure 2). VCC (Power Supply) The VCC pin is the positive supply of the IC and should be connected to an external auxiliary supply. The operating range is between 10V and 21V. The turn-on threshold is at 11.2V and under voltage occurs at 10.2V. There is no internal clamp for a limitation of the power supply. GATE The GATE pin is the output of the internal driver stage, which has a capability of 1.5A source and sink current. Its gate drive voltage is internally clamped at 11.5V (typically).
VSENSE VOUT Sense (Feedback) Input VCC GATE IC Supply Voltage Gate Drive Output
Package PG-DIP-8 / PG-DSO-8
GND
1
8
GATE
ICOMP
2
7
VCC
ISENSE
3
6
VSENSE
VINS
4
5
VCOMP
Figure 1
Pin Configuration (top view)
1.2
Pin Functionality
GND (Ground) The ground potential of the IC.
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2
Figure 2
D6 L1 R3 Vout R7 R4 R1 auxiliary supply R2 C2 C1 D1
Version 1.2
GND VCC GATE
PWM Logic Gate Driver
R S R S
RFI Filter
D2 ... D5
Vin 85 ... 265 VAC
ICE1PCS02/G
Fixed 65kHz Oscillator
OSC CLK
Representative Block diagram
Protection Block
undervoltage lockout UVLO VCC
Toff min
250ns
Peak Current Limit Ramp Generator
open-loop protect
C3
Over-current Comparator PWM Comparator
C1
VSENSE
Representative Block diagram
6
Protection Logic Fault Brown-Out Detection 0.8V C4 S R C5 1.5V
300ns
1.5V
C2
0.8V
Deglitcher
Current Sense Opamp
R8
-1.43x
VINS
D7
OP1
ISENSE
Voltage Loop
0.73 V
0 -ve
C6
Fault
R9
Current Loop
S1 +/-30uA, 42uS
OTA1
Current Loop Compensation
ICOMP
1.1mS +/-50uA linear range
Nonlinear Gain
Soft Over Current Control
5V
VCOMP
4.75V
+ve 0 -ve
OTA2
5.25V
C3
S2
4.0V
R6
Representative Block diagram
CCM-PFC ICE1PCS02/G
06 Feb 2007
Fault
Window Detect
C4
C5
CCM-PFC ICE1PCS02/G
3
3.1
Functional Description
General
Functional Description
The ICE1PCS02/G is a 8 pin control IC for power factor correction converters. It comes in both DIP and DSO packages and is suitable for wide range line input applications from 85 to 265 VAC. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control. It is a design derivative from the ICE1PCS01/G with the differences in the supporting functions, namely the input brown-out detection, internal fixed switching frequency 65kHz and shortened startup time. The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM) resulting in a higher harmonics but still meeting the Class D requirement of IEC 1000-3-2. The outer voltage loop controls the output bus voltage. Depending on the load condition, OTA1 establishes an appropriate voltage at VCOMP pin which controls the amplitude of the average input current. The IC is equipped with various protection features to ensure safe operating condition for both the system and device.
If VCC drops below 10.2V, the IC is off. The IC will then be consuming typically 200A, whereas consuming 18mA during normal operation. The IC can be turned off and forced into standby mode by pulling down the voltage at pin 6 (VSENSE) to lower than 0.8V. In this standby mode, the current consumption is reduced to 3mA. Other condition that can result in the standby mode is when a Brown-out condition occurs, ie pin 4 (VINS) <0.8V.
3.3
Start-up
Figure 4 shows the operation of voltage loop's OTA1 during startup. The VCOMP pin is pull internally to ground via switch S1 during UVLO and other fault conditions (see later section on "System Protection"). During power up when VOUT is less than 85% of the rated level, it sources a constant 30A into the compensation network at pin 5 (VCOMP) causing the voltage at this pin to rise linearly. This results in a controlled linear increase of the input current from 0A thus reducing the stress on the external component.
VSENSE
( R4 x VOUT ) R3 + R4
+/-30uA, 42uS OTA1
VCOMP
5V fault
3.2
Power Supply
S1
R6 C4 C5
An internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 11.2V and both voltages at pin 6 (VSENSE) >0.8V and pin 4 (VINS) >1.5V, the IC begins operating its gate drive and performs its Startup as shown in Figure 3. .
(VVSENSE > 0.8 V) (VVSENSE < 0.8 V) (VVSENSE > 0.8 V)
ICE1PCS02/G
Figure 4
Startup Circuit
AND (VVINS > 1.5 V) OR (VVINS < 0.8 V) AND (VVINS > 1.5 V)
VCC 11.2 V 10.5 V
As VOUT has not reached within 5% from the rated value, VCOMP voltage is level-shifted by the window detect block as shown in Figure 5, to ensure there is no long period of low or no current. When VOUT approaches its rated value, OTA1's sourcing current drops and so does the level shift of the window detect block. The normal voltage loop then takes control.
t IC's State
OFF Start Normal Up Operation Open loop/ Standby Normal Operation OFF
Figure 3
State of Operation respect to VCC
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CCM-PFC ICE1PCS02/G
Functional Description
.
VOUT VOUT,Rated
Window Detect
Max Vcomp current
Normal Control VOUT =rated
105% 100%
VOUT
95%rated 85%rated
16%
t
t
av(IIN)
Level-shifted VCOMP
Supply related Current related Output related OLP
UVLO / IBOP PCL / SOC OVP OLP
VCOMP
Figure 6
Protection Features
t
Figure 5 Startup with controlled maximum current
ICE1PCS02/G is different from ICE1PCS01/G in this block as it does not has a reduced current (~10uA in ICE1PCS01/G) during startup. The OTA1 in ICE1PCS02/G has the same maximum source current of 30uA (typ) in startup as in the normal operation. This higher sourcing current in the startup time, will charge VCOMP faster to its normal operating point, which in turn results in a faster startup for VOUT.
3.4
System Protection
The IC provides several protection features in order to ensure the PFC system in safe operating range: * VCC Undervoltage Lockout (UVLO) * Input Brown-out Detection (IBOP) * Soft Over Current Control (SOC) * Peak Current Limit (PCL) * Open-Loop Detection (OLP) * Output Over-Voltage Protection (OVP) After the system is supplied with the correct level of VCC and VIN, the system will enter into its normal mode of operation. Figure 6 shows situation when these protections features are active, as a function of the output voltage VOUT. An activation of the UVLO, IBOP and OLP results in the internal fault signal going high and brings the IC into the standby mode. As the function of UVLO has already described in the earlier "Power Supply" section, the following sections continue to describe the functionality of these protection features.
3.4.1 Input Brown-Out Protection (IBOP) Brown-out occurs when the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system without IBOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. ICE1PCS02/G provides a new IBOP feature whereby it senses directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network as shown in Figure 7. This network provides a filtered value of VIN which turns the IC on when the voltage at pin 4 (VINS) is more than 1.5V. The IC enters into the standby mode when VINS goes below 0.8V. The hysteresis prevents the system to oscillate between normal and standby mode. Note also that VIN needs to at least 16% of the rated VOUT in order to overcome OLP and powerup the system.
D2 ... D5
Vin 85 ... 265 VAC
C1
Brown-Out Detection C4 brown-out S R 0.8V
R8
VINS
20k 1.5V 5V
D7
C5
C6
R9
ICE1PCS02/G
Figure 7
Input Brown-Out Protection (IBOP)
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CCM-PFC ICE1PCS02/G
Functional Description
3.4.2 Soft Over Current Control (SOC) The IC is designed not to support any output power that corresponds to a voltage lower than -0.73V at the ISENSE pin. A further increase in the inductor current, which results in a lower ISENSE voltage, will activate the Soft Over Current Control (SOC). This is a soft control as it does not directly switch off the gate drive like the PCL. It acts on the nonlinear gain block to result in a reduced PWM duty cycle. 3.4.3 Peak Current Limit (PCL) The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 3 (ISENSE) reaches -1.08V. This voltage is amplified by OP1 by a factor of -1.43 and connected to comparator C2 with a reference voltage of 1.5V as shown in Figure 8. A deglitcher with 300ns after the comparator improves noise immunity to the activation of this protection.
3.5
Fixed Switching Frequency
ICE1PCS02/G has an internally fixed switching frequency as opposed to the ICE1PCS01/G which can be externally set. This frequency is trimmed to 65kHz with an accuracy +/-7.7% at 25oC.
3.6
Average Current Control
3.6.1 Complete Current Loop The complete system current loop is shown in Figure 9.
From Full-wave Retifier L1 R7 D1 C2 R4 R2 R1 R3 Vout
GATE ISENSE
Full-wave Rectifier Current Limit 1.5V
C2
Current Loop
Deglitcher
300ns
voltage proportional to averaged Inductor current
Gate Driver
ISENSE
R2 1.43x IINDUCTOR R1
Turn Off Driver
ICOMP
Current Loop Compensation OTA2 1.1mS +/-50uA (linear range) S2 4V Fault
PWM Comparator
C1
RQ S
PWM Logic Nonlinear Gain
Input From Voltage Loop
C3
OP1
ICE1PCS02/G
ICE1PCS02/G
Figure 8
Peak Current Limit (PCL)
Figure 9
Complete System Current Loop
3.4.4 Open Loop Protection (OLP) Whenever VSENSE voltage falls below 0.8V, or equivalently VOUT falls below 16% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage VIN for normal operation. In this case, most of the blocks within the IC will be shutdown. It is implemented using comparator C3 with a threshold of 0.8V as shown in the IC block diagram in Figure 2. 3.4.5 Over-Voltage Protection (OVP) Whenever VOUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Figure 6. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 5.25V. A VSENSE voltage higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage VOUT.
It consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks. 3.6.2 Current Loop Compensation The compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3 has to be installed at this node to ground (see Figure 9). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 4V in the event of standby mode. 3.6.3 Pulse Width Modulation (PWM) The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction.
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CCM-PFC ICE1PCS02/G
Functional Description
Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle DOFF for a CCM PFC system is given as V IN D OFF = ------------V OUT From the above equation, DOFF is proportional to VIN. The objective of the current loop is to regulate the average inductor current such that it is proportional to the off duty cycle DOFF, and thus to the input voltage VIN. Figure 10 shows the scheme to achieve the objective.
ramp profile
3.6.4 Nonlinear Gain Block The nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is the voltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC).
3.7
PWM Logic
ave(IIN) at ICOMP
The PWM logic block prioritizes the control input signals and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output. In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal Toffmin resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 12.
GATE drive
t
Figure 10 Average Current Control in CCM The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of TOFFMIN (250ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 11 shows the timing diagrams of TOFFMIN and the PWM waveforms.
TOFFMIN 250ns PWM cycle
Peak Current Limit
Current Limit Latch Q S L1 R PWM on Latch S L2 R Q
G1
HIGH = turn GATE on
Current Loop PWM on signal Toffmin 250ns
Figure 12
PWM Logic
3.8
Voltage Loop
VCREF(1) VRAMP PWM ramp released
The voltage loop is the outer loop of the cascaded control scheme which controls the PFC output bus voltage VOUT. This loop is closed by the feedback sensing voltage at VSENSE which is a resistive divider tapping from VOUT. The pin VSENSE is the input of OTA1 which has an accurate internal reference of 5V (+/-2%). Figure 13 shows the important blocks of this voltage loop. 3.8.1 Voltage Loop Compensation The compensation of the voltage loop is installed at the VCOMP pin (see Figure 13). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up.
t
(1)
VCREF is a function of VICOMP
Figure 11
Ramp and PWM waveforms
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CCM-PFC ICE1PCS02/G
Functional Description
From Full-wave Retifier
L1 R7
D1 C2
R3
Vout
VCC
R4
PWM Logic HIGH to turn on
Gate Driver
LV Z1
External MOS
Current Loop + PWM Generation VIN
Nonlinear Gain
Gate Driver
GATE
GATE
* LV: Level Shift
Av(IIN)
OTA1
ICE1PCS02/G
5V
t
VSENSE
Figure 14
Gate Driver
ICE1PCS02/G
R6 C4
VCOMP
The output is active HIGH and at VCC voltages below the under voltage lockout threshold VCCUVLO, the gate drive is internally pull low to maintain the off state.
C5
Figure 13
Voltage Loop
3.8.2 Enhanced Dynamic Response Due to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes. The IC provides therefore a "window detector" for the feedback voltage VVSENSE at pin 6 (VSENSE). Whenever VVSENSE exceeds the reference value (5V) by +5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of VOUT.
3.9
Output Gate Driver
The output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 14) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 11.5V.
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CCM-PFC ICE1PCS02/G
Electrical Characteristics
4
4.1
Note:
Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit.
Parameter
VCC Supply Voltage VINS Voltage ICOMP Voltage ISENSE Voltage ISENSE Current VSENSE Voltage VSENSE Current VCOMP Voltage GATE Voltage Junction Temperature Storage Temperature Thermal Resistance Junction-Ambient for PG-DSO-8 Thermal Resistance Junction-Ambient for PG-DIP-8 ESD Protection
1)
Symbol
VCC VVINS VICOMP VISENSE IISENSE VVSENSE IVSENSE VVCOMP VGATE Tj TS RthJA (DSO) RthJA(DIP) VESD
Limit Values min.
-0.3 -0.3 -0.3 -24 -1 -0.3 -1 -0.3 -0.3 -40 -55 -
Unit
V V V V mA V mA V V C C K/W K/W kV
Remarks
max.
22 20 7 7 1 7 1 7 22 150 150 185 90 2
Recommended R2=220 R3>400k Clamped at 11.5V(typ) if driven internally.
PG-DSO-8 PG-DIP-8 Human Body Model1)
According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)
4.2
Note:
Operating Range
Within the operating range the IC operates as described in the functional description.
Parameter
VCC Supply Voltage Junction Temperature
Symbol
VCC TJCon
Limit Values min.
-40
Unit
V C
Remarks
max.
125
VCCUVLO 21
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Electrical Characteristics 4.3
Note:
Characteristics
The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range TJ from - 40 C to 125C.Typical values represent the median values, which are related to 25C. If not otherwise stated, a supply voltage of VCC =15V is assumed for test condition.
4.3.1
Supply Section
Parameter
VCC Turn-On Threshold VCC Turn-Off Threshold/ Under Voltage Lock Out VCC Turn-On/Off Hysteresis Start Up Current Before VCCon Operating Current with active GATE Operating Current during Standby
Symbol min.
VCCon VCCUVLO VCChy ICCstart ICCHG ICCStdby
Limit Values typ.
11.2 10.2 1 100 13 2.3
Unit Test Condition
V V V A mA mA VVCC=VVCCon -0.1V CL= 4.7nF VVSENSE= 0.5V
max.
11.9 10.8 1.3 200 16.3 2.9
10.5 9.4 0.8 50 9.6 1.7
4.3.2
PWM Section Symbol min.
fSW fSW DMAX DMIN TOFFMIN 100 250 56 60 94
Parameter
Fixed Oscillator Frequency Max. Duty Cycle Min. Duty Cycle Min. Off Time
Limit Values typ.
65 65 97
Unit Test Condition
72 70 kHz kHz % % ns VVCOMP= 0V, VVSENSE= 5V VICOMP= 6.4V VVCOMP= 5V, VVSENSE= 5V VISENSE= 0.1V Tj = 25C
max.
99.3 0 600
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Electrical Characteristics
4.3.3 System Protection Section Symbol min.
Open Loop Protection (OLP) VSENSE Threshold Peak Current Limitation (PCL) ISENSE Threshold Soft Over Current Control (SOC) ISENSE Threshold Output Over-Voltage Protection (OVP) Input Brown-out Protection (IBOP) High to Low Threshold Input Brown-out Protection (IBOP) Low to High Threshold Input Brown-out Protection (IBOP) VINS Bias Current VOLP VPCL VSOC VOVP VVINSL VVINSH IVIN0V 0.77 -1.15 -0.79 5.12 0.76 1.40 -1.0
Parameter
Limit Values typ.
0.81 -1.08 -0.73 5.25 0.82 1.50 -0.2
Unit Test Condition
V V V V V V A VVINS= 0V
max.
0.86 -1.00 -0.66 5.38 0.88 1.60 0
4.3.4
Current Loop Section Symbol min.
GmOTA2 IOTA2 VICOMPF 3.6
Parameter
OTA2 Transconductance Gain OTA2 Output Linear Range1) ICOMP Voltage during OLP
1)
Limit Values typ.
0.95 +/- 50 4.0
Unit Test Condition
mS A V VVSENSE= 0.5V At Temp = 25C
max.
1.15
0.75
The parameter is not subject to production test - verified by design/characterization
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Electrical Characteristics
4.3.5 Voltage Loop Section Symbol min.
OTA1 Reference Voltage OTA1 Transconductance Gain OTA1 Max. Source Current At Startup OTA1 Max. Source Current Under Normal Operation OTA1 Max. Sink Current Under Normal Operation Enhanced Dynamic Response VSENSE High Threshold VSENSE Low Threshold VSENSE Input Bias Current at 5V VSENSE Input Bias Current at 1V VCOMP Voltage during OLP VOTA1 GmOTA1 IOTA1SO1 IOTA1SO IOTA1SK 4.90 31.5 21 21 21
Parameter
Limit Values typ.
5.00 42 30 30 30
Unit Test Condition
V S A VVSENSE= 4V VVCOMP= 0V A A VVSENSE= 4.25V VVCOMP= 4V VVSENSE= 6V VVCOMP= 4V
max.
5.10 52.5 38 38 38
VHi VLo IVSEN5V IVSEN1V VVCOMPF
5.12 4.63 0 0 0
5.25 4.75
5.38 4.87 1.5 1
V V A A V VVSENSE= 5V VVSENSE= 1V VVSENSE= 0.5V IVCOMP= 0.5mA
0.2
0.4
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Electrical Characteristics
4.3.6 Driver Section Symbol
VGATEL -0.2 GATE High Voltage VGATEH GATE Rise Time GATE Fall Time GATE Current, Peak, Rising Edge GATE Current, Peak, Falling Edge
1)
Parameter
GATE Low Voltage
Limit Values min. typ.
0.8 1.6 0.2 11.5 10.5 7.5 60 40 -
Unit Test Condition
1.2 1.5 2.0 1.5 V V V V V V V V ns ns A A VCC = 5 V IGATE = 5 mA VCC = 5 V IGATE = 20 mA IGATE = 0 A IGATE = 20 mA IGATE = -20 mA VCC = 20V CL = 4.7nF VCC = 11V CL = 4.7nF VCC = VVCCoff + 0.2V CL = 4.7nF VGate = 2V ...8V CL = 4.7nF VGate = 8V ...2V CL = 4.7nF CL = 4.7nF1) CL = 4.7nF1)
max.
tr tf IGATE IGATE
-1.5 -
Design characteristics (not meant for production testing)
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CCM-PFC ICE1PCS02/G
Outline Dimension
5
Outline Dimension
PG-DIP-8-4 (Plastic Dual In-Line Package)
Dimensions in mm
Figure 15 PG-DIP-8 Outline Dimension
PG-DSO-8-13 (Plastic Dual Small Outline)
1.75 MAX. 0.1 MIN. (1.5)
0.33 0.08 x 45 4 -0.21)
1.27 0.41 +0.1 -0.05 8 5
0.1
C
6 0.2
0.64 0.25
0.2 M A C x8
Index Marking 1
4
5 -0.21)
1)
A
Index Marking (Chamfer)
Dimensions in mm
Does not include plastic or metal protrusion of 0.15 max. per side
Figure 16 PG-DSO-8 Outline Dimension
Version 1.2
17
8 MAX.
0.2
+0.05 -0.01
06 Feb 2007
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