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Ordering number : EN 4365B
CMOS LSI
LC5852N
Four-Bit Single-Chip Microcontroller with On-Chip LCD Drivers for Small-Scale Control in Medium-Speed Applications
Overview
The LC5852N is a high-performance four-bit single-chip built-in LCD driver microprocessor that provides a variety of attractive features including low-voltage operation and low power dissipation. The LC5852N was developed as an upwardly compatible version of the LC5851N and provides a ROM capacity increased from 1024 to 2048 15bit words and a RAM capacity increased from 64 x 4 bits to 128 x 4 bits.
Package Dimensions
unit: mm 3057-QIP64A
[LC5852N]
Applications
* System control and LCD display in cameras, radios and similar products * System control and LCD display in miniature electronic test equipment and consumer health maintenance products * The LC5852N is optimal for end products with LCD displays and, in particular, for battery operated products.
SANYO: QIP64A
Features
The LC5852N is an upwardly compatible version of the LC5851N and, as such, has the following features. * Extremely broad allowable operating ranges
Power supply option EXT-V EXT-V EXT-V EXT-V Li Ag 10 s 20 s 61 s 122 s, 244 s 122 s, 244 s 122 s, 244 s Cycle time Power supply voltage range VSS2 = -4.0 to -5.5 V VSS2 = -4.0 to -5.5 V VSS2 = -2.3 to -5.5 V VSS2 = -2.0 to -5.5 V VSS2 = -2.6 to -3.6 V* VSS1 = -1.3 to -1.65 V Note When using an 800 kHz ceramic resonator When using a 400 kHz ceramic resonator When using a 65 kHz crystal oscillator When using a 32 kHz crystal oscillator When using a 32 kHz crystal oscillator When using a 32 kHz crystal oscillator
Note: * When the backup flag is set, the BAK pin is shorted to VSS2. (See the user's manual for details.)
* Low current drain -- Ceramic oscillator (CF): -- Crystal oscillator (Xtal): -- Crystal oscillator (Xtal):
400 kHz (5.0 V) 32 kHz (1.5 V, Ag specifications) 32 kHz (3.0 V, Li specifications)
HALT mode (typical) 150 A 2.0 A (for LCD biases other than 1/3) 3.5 A (for an LCD bias of 1/3) 1.0 A (for LCD biases other than 1/3) 5.0 A (for an LCD bias of 1/3)
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O3095HA (OT)/91994TH (OT) No. 4365-1/29
LC5852N * Timer functions -- One six-bit programmable timer -- Time base timer (for clock applications) * Standby functions -- Clock standby function (HALT mode) The LC5852N provides a halt function that reduces power dissipation. In halt mode, only the oscillator, divider and LCD driver circuits operate. All other internal operations are stopped. This mode allows the LC5852N to easily implement a low-power clock function. -- Full standby function (HOLD mode) -- HALT mode is cleared by two external factors and two internal factors. * Improved I/O functions -- External interrupt pins -- Input pins that can clear HALT mode (up to 9 pins) -- Input ports with software controllable input resistors: up to 8 pins -- Input ports with built-in floating prevention circuits: up to 8 pins -- LCD drivers; common: 4 pins, segment pins: 25 pins -- General-purpose I/O ports: 8 pins -- General-purpose inputs: 9 pins -- General-purpose outputs (1): 6 pins (ALM pin, LIGHT pin) -- General-purpose outputs (2): 25 pins (when all 25 LCD segment ports are used as generalpurpose outputs) -- Pseudo-serial output port: 1 set (Three pins: output, BUSY, clock) * Powerful hardware to improve processing capabilities -- On-chip segment PLA circuit and segment decoder: The LCD driver outputs can handle LCD panel segment display without incurring software overhead. -- All LCD driver output pins can be switched to be used as output ports. -- One six-bit programmable timer -- Part of the RAM area can be used as a working area. -- Built-in clock oscillator and 15-stage divider (also used for LCD alternation signal generation) * Highly flexible LCD panel drive output pins (25) Supported Maximum number Required drive types of segments common pins 1/3 bias--1/4 duty......100 segments ..........4 pins 1/3 bias--1/3 duty......75 segments ............3 pins 1/2 bias--1/4 duty......100 segments ..........4 pins 1/2 bias--1/3 duty......75 segments ............3 pins 1/2 bias--1/2 duty......50 segments ............2 pins Static ..........................25 segments ............1 pin -- The LCD output pins can be converted to use as general-purpose output pins. CMOS type: 25 pins (maximum) p-channel open drain type: 3 pins (maximum) * An oscillator appropriate for the system specifications can be selected. 32 or 65 kHz crystal oscillator, or 400 or 800 kHz ceramic oscillator
Delivery formats
QIP-64A or chip product
Function Overview
* * * * Program ROM: 2048 x 15 bits On-chip RAM: 128 x 4 bits All instructions execute in a single cycle HALT mode clear and interrupt functions (External factors) Changes in the S and M port input signals Changes in the INT pin input signal (Internal factors) Overflow from the clock divider circuit Timer underflow * Subroutines can be nested up to four levels (including interrupts)
No. 4365-2/29
LC5852N Pin and Pad Assignment Chip size: 4.19 x 3.66 mm Pad size: 120 x 120 m Chip thickness: 480 m (chip specification products)
Pin No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Symbol VDD BAK VSS1 VSS2 ALM LIGHT S4 S3 I/O A1 I/O A2 I/O A3 I/O A4 I/O B1 I/O B2 I/O B3 I/O B4 RES INT P1 P2 P3 P4 M1
Coordinates Xm 1899 1899 1899 1899 1899 1899 1899 1899 1899 1595 1415 1235 1055 875 695 515 253 73 -107 -287 -707 -887 -1067 Ym 138 358 538 718 898 1078 1258 1438 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630 1630
Pin No. 63 64 1 2 3 4 5 6 7 -- 8 -- 9 10 -- 11 12 13 14 15 16 -- --
Pad No. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Symbol M2 M3 M4 TESTA TEST CUP1 CUP2 S2 S1 (VDD) OSC-IN 10P OSC-OUT COM1 COM4 Seg01 Seg02 Seg03 Seg04 Seg05 Seg06 TEST TEST
Coordinates Xm -1247 -1427 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1899 -1553 -1373 Ym 1630 1630 1630 1450 1270 1090 910 730 550 370 190 10 -169 -349 -529 -709 -889 -1069 -1249 -1429 -1609 -1630 -1630
Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Pad No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69
Symbol Seg07 Seg08 Seg09 Seg10 Seg11 Seg12 Seg13 COM4 Seg14 Seg15 Seg16 Seg17 Seg18 Seg19 Seg20 Seg21 Seg22 Seg23 Seg24 Seg25 COM3 COM2 VSS3
Coordinates Xm -1033 -853 -673 -493 -313 -133 46 226 459 639 819 999 1179 1359 1539 1719 1899 1899 1899 1899 1899 1899 1899 Ym -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -1630 -954 -774 -594 -414 -234 -54
Note: 1. 2. 3. 4. 5. 6. 7. 8.
The pin numbers are those for the QIP-64A mass production package. The pad coordinates given above take the center of the chip as the origin and specify the center of the pad. TESTA pin (pin 2) in the QIP-64A product must be connected to the minus side of the power supply. TEST pin (pin 3) in the QIP-64A product must be left open. Pad 27 in the chip product must either be connected to the minus side of the power supply or left open. Pads 28, 45 and 46 in the chip product must be left open. If the chip product is used, the substrate must be connected to VDD. Do not use dip-soldering techniques to mount the QIP-64A package product.
No. 4365-3/29
LC5852N System Block Diagram
LC5852N System Block Diagram AC: ALU: INT CTL: PC: TM: IR: HALT: SCG: STS1: STS2: STS3: Accumulator Arithmetic and logic unit Interrupt control circuit Program counter Preset timer (6 bits) Instruction register Intermittent control circuit System clock generator Status register 1 Status register 2 Status register 3 CF: BCF: SCF1: SCF2: SCF3: SCF4: SCF5: o15: SCF7: Carry flag Backup flag M port flag STS3 flag S port flag INT signal change flag Timer overflow flag Contents of the fifteenth stage of the divider circuit Divider circuit overflow flag
No. 4365-4/29
LC5852N Pin Functions
Pin VDD I/O -- QIP-64 Pin No. 40 Power supply plus side LSI internal logic block minus power supply In Li specification products, connect a capacitor between BAK and VDD to prevent incorrect operation. Power supply minus side * External component connections differ depending on mask options and other factors. In products for Ag use, connect VSS1 to the power supply minus side. In other products, connect VSS2 to the power supply minus side. * The pins other than the minus pin are used for the LCD driver power supply. Connections for the LCD drive voltage boost (cut) capacitor. * Crystal oscillator use (XT option) * Ceramic resonator use (CF option) The CF option can only be specified for EXT-V specification products. Backup flag set Backup flag cleared (depending on the power supply option) Function Option At reset
BAK
--
41
VSS1 VSS2 VSS3
-- -- --
42 43 39
* Ag specifications * Li specifications * EXT-V specifications
CUP1 CUP2
-- --
4 5
OSC-IN
Input
8 Used for real-time clock and the system clock.
OSC-OUT
Output
9
10P
--
--
Connected to OSC-IN or OSC-OUT and used for the oscillator phase compensation capacitor. Can only be used in the chip product.
S1 S2 S3 S4
Input
7 6 47 46
Dedicated input port * Includes either a o10 (32 ms), o8 (8 ms), or o2 (2 ms) chattering exclusion circuit (PLA mask option). * These values are for the case where a 32.768 kHz crystal is used. * Pull-down resistors are built in.
Inclusion (or exclusion) of a low level hold transistor
The pull-down resistor transistor is on.
M1 M2 M3 M4
Input
62 63 64 1
Dedicated input port * Input connections for acquiring data to internal RAM * Pull-down resistors are built in.
Inclusion (or exclusion) of a low level hold transistor
The pull-down resistor transistor is on.
I/O A1 I/O A2 I/O A3 I/O A4
I/O
48 49 50 51
I/O port * Input connections for acquiring data to internal RAM * Output connections for data output from internal RAM * The input or output state can be switched by two instructions.
Input mode
I/O B1 I/O B2 I/O B3 I/O B4 P1 P2 P3 P4
I/O
52 53 54 55 58 59 60 61
I/O port * Input connections for acquiring data to internal RAM * Output connections for data output from internal RAM * The input or output state can be switched by two instructions.
Input mode
Output
Output port * Output connections for data output from internal RAM
Either a high- or low-level output. (Undefined) * Modulated signals (4 kHz, 2 kHz, or unmodulated) * Modulated signals (4 kHz, 1 kHz, or unmodulated)
ALM
Output
44
Dedicated output This pin can output a signal modulated either at 4 kHz or 2 kHz, or at 4 kHz or 1 kHz under program control. Alternatively, an unmodulated signal can be output. * These values are for the case where a 32.768 kHz crystal is used.
Low-level output
LIGHT
Output
45
Dedicated output This pin can drive a power transistor.
Low-level output
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LC5852N
Continued from preceding page.
QIP-64 Pin No.
Pin
I/O
Function LSI internal reset input * Reset can be performed on either a high or low input level. * Built-in pull-up or pull-down resistor Note: The applied signal must be held for at least 500 s.
Option
At reset
RES
Input
56
Pull-up or pull-down resistor selection
INT
Input
57
External interrupt request input * Interrupt detection can be performed for either falling or rising edges. * Built-in pull-up or pull-down resistor
* Pull-up or pulldown resistor selection * Signal change type (rising or falling) selection
TESTA
Input
2
Test input * QIP-64 products: connect to the power supply - side * Chip products: Leave open or connect to the power supply - side Test input This pin must be left open. (It cannot be used in user systems.) * Switching between LCD drive outputs and generalpurpose outputs * LCD drive method switching -- STATIC -- 1/2 bias - 1/2 duty -- 1/2 bias - 1/3 duty -- 1/2 bias - 1/4 duty -- 1/3 bias - 1/3 duty -- 1/3 bias - 1/4 duty * General-purpose outputs -- CMOS
TEST
--
3
Seg1 Seg2 to Seg25
Output
11 12 to36
* LCD drive/general-purpose output pins -- LCD drive I STATIC II 1/2 bias - 1/2 duty III 1/2 bias - 1/3 duty IV 1/2 bias - 1/4 duty V 1/3 bias - 1/3 duty VI 1/3 bias - 1/4 duty Items I to V are specified as master options. * General-purpose output mode (CMOS output) -- LCD/general-purpose output control under program control is disabled by adoption of the segment PLA. -- Arbitrary combinations of LCD drive and general purpose outputs are possible.
* LCD drive -- All segments lit -- All segments off * Set by a mask option * General-purpose outputs -- High level -- Low level * Set by a mask option
LCD common polarity drive outputs These pins are used as follows depending on the LCD drive method used. (Note that these are typical specifications for 32.768 kHz when o0 is used for the alternation frequency.) Static COM1 COM2 COM3 COM4 10 38 37 24 COM1 COM2 COM3 COM4 Alternation frequency r 1/2 duty r r 1/3 duty r r r 1/4 duty r r r r 32 Hz
Output
x x x
x x
x
32 Hz
32 Hz
42.7 Hz
Note: An x indicates that the corrsponding common pin is not used with that LCD drive method. LCD drive type. Do not use hold mode in CF specification products that use the LCD driver. (The alternation frequency signal is stopped in hold mode.)
No. 4365-6/29
LC5852N Application Circuit Examples 1. Representative application for Ag specification products (1/3 bias - 1/4 duty) 2. Representative application for lithium specification products (1/2 bias - 1/4 duty)
3. Representative application for EXT-V specification products (1/2 bias - 1/4 duty)
No. 4365-7/29
LC5852N Oscillator Circuit Options
Option Circuit Form Note
CF * 400 kHz * 800 kHz
* The cycle time is 4 x n times the f1 period (n : 2). * The divider outputs (o1 to o15) are used, for example, as the LCD drive waveform generation clock and as the S and K port chattering prevention clock.
Xtal (32.768 kHz)
* The cycle time is four times the f1 period. * The divider outputs (o1 to o15) are used, for example, as the LCD drive waveform generation clock, as the S and K port chattering prevention clock and as a clock time base. * The 10P connection can only be used in chip products.
Xtal (65 kHz)
* The cycle time is four times the f1 period. (Used when the cycle time is 61 s.) * The divider outputs (o1 to o15) are used, for example, as the LCD drive waveform generation clock and as the S and K port chattering prevention clock. * The 10P connection can only be used in chip products.
No. 4365-8/29
LC5852N Crystal Oscillator Options
Option Circuit Form Note
32 kHz
The resistor Rd for use with a 32 kHz frequency is built in.
65 kHz
INT Pin Options
Option Circuit Form Note
Pull-up resistor, pull-down resistor, or resistor open selection
Built-in resistor selection * Use of the pull-up resistor * Use of the pull-down resistor * Open
Rising edge, falling edge detection selection
Signal change edge detection selection * Rising edge detection * Falling edge detection
RES Pin Options
Option Circuit Form Note
Pull-up resistor, pull-down resistor, or resistor open and level selection
Built-in resistor and polarity selection * Pull-up resistor and reset on low * Pull-down resistor and reset on high * Both resistors open and reset on low * Both resistors open and reset on high
No. 4365-9/29
LC5852N Input Port Options
Option Circuit Form Note This option can be specified individually for each pin in S1 to S4 and M1 to M4. When use of the hold transistor is selected: * This transistor is used to reduce the current drain in the pull-up or pull-down resistor when, for example, a push-button switch is used for S1 or a slide switch is used for S2. * When the input open specifications are used, this transistor turns the resistor on prior to reading the input value and then turns the resistor off after the input value is read. If the input is floating when read, the low-level input hold transistor will operate and hold that level. When the hold transistor is unused: * The pull-down transistor can be used as a pull-down resistor. * The pull-down transistor can be turned on and off under program control. * The pull-down resistor can be used in the on state without change. * Select the unused option if the input is connected to an external control signal line that will never go to the floating state. * On reset -- The resistor will be in the on state during the reset period. -- The resistor will keep up the on state when reset is cleared.
Use of the hold transistor (low level hold transistor)
Hold transistor unused (open)
The use of the low level hold transistor can be specified individually for each pin in the S1 to S4 and M1 to M4 ports. 1. The S port includes independent (in bit units) chattering exclusion circuits with periods of o10, o8, or o6. 2. The M port includes chattering exclusion circuits that operate for halt mode clear request signals. These circuits exclude chattering for periods of o10, o8, or o6 when three of the ports are at the low level and a signal change occurs on the remaining port. LCD Output Options
Option Circuit Form * Used as LCD segment drive pins * The LCD drive type is specified independently. The LCD drive type is common to all LCD drive pins and can be selected from the following set: static, 1/2 bias--1/2 duty, 1/2 bias--1/3 duty, 1/2 bias--1/4 duty, 1/3 bias--1/3 duty, or 1/3 bias--1/4 duty. * General-purpose CMOS output ports
LCD drive
CMOS output port
P-channel open-drain output port
* General-purpose p-channel open-drain output ports This option can be specified for three specific ports using PLA option specification. Available ports...Pads 64 to 66 (pins 34 to 36)
No. 4365-10/29
LC5852N Mask Option Overview 1. Power supply specification selection * Ag (Silver battery/1.5 V) specifications * Li (Lithium battery/3.0 V) specifications * EXT-V specifications (the operating voltage range depends on the oscillator used) 2. Oscillator selection * Crystal oscillator (32.768 kHz) * Crystal oscillator (65.536 kHz) * Ceramic oscillator 3. LCD drive * Static * 1/2 bias--1/2 duty * 1/2 bias--1/3 duty * 1/2 bias--1/4 duty * 1/3 bias--1/3 duty * 1/3 bias--1/4 duty Note: The LCD ports can all be used as general-purpose outputs. In this case, specify the "UNUSE" option. 6. LCD alternation frequency * SLOW (OSC/2048) * TYP (OSC/1024) * FAST (OSC/512) * STOP 5. S port low-level hold transistor * Level hold transistor present * No level hold transistor 6. M port low-level hold transistor * Level hold transistor present * No level hold transistor 7. S and M port chattering exclusion frequency * SLOW (OSC/1024) * TYP (OSC/256) * FAST (OSC/64) 8. INT pin resistor selection and signal edge type selection * Pull-up resistor (negative) * Pull-down resistor (positive) * Open (negative) * Open (positive) 9. External reset * RES pin * Simultaneous input to S1 through S4 10. RES pin * Pull-up resistor (low-level reset) * Pull-down resistor (high-level reset) * Open (low-level reset) * Open (high-level reset) 11. Power-on reset function (internal reset) * USE * UNUSE 12. Timer input clock * SLOW (OSC/512) * FAST (OSC/8) 13. Alarm modulation base frequency * SLOW (OSC/8, OSC/32) * TYP (OSC/8, OSC/16) 14. Cycle time * SLOW (OSC/8) * FAST (OSC/4) Note: Specify "SLOW" for this option if a ceramic oscillator is used.
No. 4365-11/29
LC5852N Internal Register Functions
Symbol R/W Function Program counter The PC is an 11-bit counter that specifies the program memory (ROM) address of the next instruction to be executed. Normally, the PC is incremented on each instruction execution, from 000H to 7FFH. However, when a branch or subroutine call is executed, or when an interrupt or initializing reset occurs, the PC is set to a value corresponding to the particular operation. The table below shows how the PC is set for these operations. PC Operation Initializing reset INT pin external interrupt S or M port external interrupt PC -- Timer internal interrupt Divider internal interrupt Unconditional jump (JMP) PC10 0 0 0 0 0 Page PC9 0 0 0 0 0 P9 P9 PC8 0 0 0 0 0 P8 P8 PC7 0 0 0 0 0 P7 P7 PC6 0 0 0 0 0 P6 P6 PC5 0 0 0 0 0 P5 P5 PC4 0 1 1 1 1 P4 P4 PC3 0 0 0 1 1 P3 P3 PC2 0 0 1 0 1 P2 P2 PC1 0 0 0 0 0 P1 P1 PC0 0 0 0 0 0 P0 P0 Initialization value at reset
Conditional jump (BAB0, BAB1, BAB2, BAB3, Page BAZ, BANZ, BCH, BCNH) Subroutine call instruction (CALL) Return instruction (RTS, RTSR) Page: P0 - P9: Page
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
CALL address + 1
ROM paging performed in 1024 word pages Pages are specified with the SF and RF instructions. Instruction code bits (immediate data)
Program memory The on-chip ROM consists of 2048 15-bit words and holds the user programs to be executed.
ROM
R/O
RAM
R/W
Data memory The on-chip RAM consists of 128 4-bit digits of static RAM in two pages with 64 4-bit digits per page. This RAM has the following features: * RAM addresses can be specified directly (immediate addressing) as values in the range 00H to 3FH. * Arithmetic operations can be performed between the AC and any RAM location. * Due to the provision of the segment PLA circuit, RAM dedicated to display is not required. * RAM locations 38H to 3FH have a function that allows direct arithmetic operations with other data without using the AC. * The AC is used for RAM input, i.e., writing.
Undefined
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LC5852N
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Initialization value at reset
Symbol
R/W
Function
RAM
R/W
Undefined
Accumulator
AC
R/W
Undefined
Stack pointer The stack consists of four 13-bit words supporting subroutine calls and interrupts up to four levels deep.
STACK
R/W
01H
P0 to P10: Program counter (PC) APG: RAM page flag OPG: ROM page flag
APG
R/W
RAM page flag The RAM page flag is a single bit that allows the RAM to be expanded to two pages, where a single RAM page is 64 x 4 bits.
00H
OPG
R/W
ROM page flag The ROM page flag is a single bit that allows the ROM to be expanded to two pages, where a single ROM page is 1024 x 15 bits.
00H
TIM
W
Timer counter The timer is a 6-bit down counter. The timer is set from immediate data in an instruction.
Undefined
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LC5852N
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Initialization value at reset
Symbol
R/W
Function
Status register 1 (STS1) Status register 1 is a four-bit register whose bits are used as shown below.
STS1
R/W
00H
* The test flags cannot be used by application programs.
Status register 2 (STS2) Status register 2 is a four-bit register whose bits are used as shown below.
STS2
R/O
Undefined
SCF1: Set when there was a change in an M port signal (when enabled by an SSW instruction). SCF2: Set when any bit in STS3 is set. SCF3: Set when there was a change in an S port signal (when enabled with an SSW instruction).
Status register 3 (STS3) Status register 3 is a four-bit register whose bits are used as shown below.
STS3
R/O
Undefined
SCF4: Set when there was a change in the INT pin signal (when enabled by an SIC instruction). SCF5: Timer underflow (when enabled by an SIC instruction) SCF4: Divider overflow (when enabled by an SIC instruction)
No. 4365-14/29
LC5852N
Specifications
These electrical specifications are provisional and subject to change.
EXT-V Specifications
Absolute Maximum Ratings at VDD = 0 V
Parameter Symbol VSS1 Maximum supply voltage VSS2 VSS3 VSS3 Maximum input voltage VIN1 LCD drive method (1/3 bias) LCD drive method (Any method other than 1/3 bias) S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT, RES, OSCIN, 10P, TESTA (with I/OA1 to 4 and I/OB1 to 4 in input mode, 10P is for chip products) ALM, LIGHT, P1 to 4, CUP2, OSCOUT, TEST, I/OA1 to 4, I/OB1 to 4 (with I/OA and I/OB in output mode) SEGOUT, COM1 to 4, CUP1 Conditions/Pins min -7.0 -7.0 -8.5 -7.0 VSS2 - 0.3 typ max +0.3 +0.3 +0.3 +0.3 +0.3 Unit V V V V V
Maximum output voltage
VOUT1 VOUT2
VSS2 - 0.3 VSS3 -20 -30
+0.3
V V
Operating temperature Storage temperature
Topr Tstg
+70 +125
C C
Allowable Operating Ranges at Ta = -20 to +70C, VDD = 0 V
Parameter Symbol VSS1 Supply voltage VSS2 VSS3 VSS1 Supply voltage VSS2 VSS3 VSS1 Supply voltage VSS2 VSS3 VSS1 Supply voltage VSS2 VSS3 Input high level voltage Input low level voltage Input high level voltage Input low level voltage Operating frequency VIH1 VIL1 VIH2 VIL2 fopg1 VSS2 = -2.0 to -5.5 V OSCIN/OSCOUT, 32 kHz crystal oscillator, Figure 2 OSCIN/OSCOUT, 65 kHz crystal oscillator, Figure 2 OSCIN external input, Figure 8 OSCIN/OSCOUT, CF 400 kHz, Figure 1 OSCIN/OSCOUT, CF 800 kHz, Figure 1 OSCIN pin, when external input used, Figure 8 All input ports except OSCIN 400 kHz CF specifications External input used 65 kHz crystal oscillator specifications 32 kHz crystal oscillator specifications Conditions/Pins min -5.5 -5.5 -8.25 -5.5 -5.5 -8.25 -5.5 -5.5 -8.25 -5.5 -5.5 -8.25 0.3 x VSS2 VSS2 0.2 x VSS2 VSS2 32 typ max -1.3 -2.0 -2.0 -1.3 -2.3 -2.3 -1.7 -3.5 -3.5 -2.0 -4.0 -4.0 0 0.7 x VSS2 0 0.8 x VSS2 33 Unit V V V V V V V V V V V V V V V V kHz
Operating frequency
fopg2
VSS2 = -2.3 to -5.5 V
60
66
kHz
Operating frequency
fopg3
VSS2 = -3.5 to -5.5 V
32
220
kHz
Operating frequency Operating frequency
fopg4 fopg5
VSS2 = -4.0 to -5.5 V VSS2 = -4.0 to -5.5 V
360 720
400 800
440 880
kHz kHz
Continued on next page. No. 4365-15/29
LC5852N Electrical Characteristics at Ta = -20 to +70C, VDD = 0 V
Parameter Symbol RIN1A Input resistance RIN1B RIN2A RIN2B Input resistance RIN3 Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output high level voltage Output low level voltage Segment driver output impedances * When used as CMOS output ports Output high level voltage Output low level voltage Output high level voltage Output low level voltage VOH (5) VOL (5) VOH (6) VOL (6) VSS2 = -2.4 V, IOH = -10 A VSS2 = -2.4 V, IOL = 100 A VSS2 = -2.4 V, IOH = -5 A VSS2 = -2.4 V, IOL = 20 A VSS2 = -2.4 V, IOH = -10 A VSS2 = -2.9 V, VOL = VSS2 VSS2 = -2.4 V, IOH = -0.4 A, VSS2 = -2.4 V, IOL = 0.4 A VSS2 = -2.4 V, IOH = -4 A VSS2 = -2.4 V, IOL = 4 A VSS2 = -2.4 V, IOH = -0.4 A VSS2 = -2.4 V, IOL = 0.4 A VSS2 = -2.4 V, IOH = -4 A VSS2 = -2.4 V, IOH = -4A, IOL = 4 A VSS2 = -2.4 V, IOL = 4 A COM1, 2 -0.2 VSS2/2 - 0.2 VSS2/2 + 0.2 VSS2 + 0.2 -0.2 COM1 VSS2 + 0.2 V Segment Pads 62 to 64, QIP64 pins 34 to 36 Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 -1 -0.3 VSS2 + 0.3 -1 -0.3 VSS2 + 0.3 VSS2 + 1 VSS2 + 1 V V V V VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOH (4) VOL (4) VSS2 = -2.9 V, VIN = 0.8 x VSS2 VSS2 = -2.9 V, VIN = VDD VSS2 = -2.9 V, VIN = VSS2 VSS2 = -2.9 V, VIN = VDD VSS2 = -2.9 V, VIN = VDD or VSS2 VSS2 = -2.4 V, IOH = 1 mA VSS2 = -2.4 V, IOL = 1 mA VSS2 = -2.4 V, IOH = 0.3 mA VSS2 = -2.4 V, IOL = 0.5 mA VSS2 = -2.4 V, IOH = 0.1 mA VSS2 = -2.4 V, IOH = -50 A VSS2 = -2.4 V, IOL = 0.1 mA Conditions/Pins Low-level hold transistor*, Figure 3 Low-level pull-in transistor*, Figure 3 INT pin pull-up resistor INT pin pull-down resistor RES ALM ALM LIGHT, Port P LIGHT, Port P I/O ports I/O ports I/O ports -1 -0.6 -1 min 10 200 200 200 5 -1 -0.3 VSS2 + 0.3 -0.3 VSS2 + 0.3 -0.3 -0.2 VSS2 + 0.3 VSS2 + 1 VSS2 + 1 VSS2 + 1 700 700 700 typ max 200 2000 2000 2000 50 Unit k k k k k V V V V V V V
* When used as p-channel open-drain output ports Output high level voltage Output off leakage current * Static drive Output high level voltage Output low level voltage Output high level voltage Output low level voltage * Duplex drive (1/2 bias--1/2 duty) Output high level voltage Output low level voltage Output high level voltage VOH (5) VOL (5) VOH (7) VOM -0.2 All segments VSS2 + 0.2 V V V VOH (5) VOL (5) VOH (7) VOL (7) -0.2 All segments VSS2 + 0.2 V V V VOH (5) IOFF Segment Pads 62 to 64, QIP64 pins 34 to 36 -1 -0.3 1 V A
Output middle level voltage
V
Output low level voltage
VOL (7)
V
Note: * S1, S2, S3, S4, M1, M2, M3, M4
Continued on next page. No. 4365-16/29
LC5852N
Continued from preceding page.
Parameter Symbol Conditions min typ max Unit
* 1/2 bias--1/3 duty and 1/2 bias--1/4 duty methods Output high level voltage Output low level voltage Output high level voltage VOH (5) VOL (5) VOH (7) VOM VSS2 = -2.4 V, IOH = -0.4 A VSS2 = -2.4 V, IOL = 0.4 A VSS2 = -2.4 V, IOH = -4 A VSS2 = -2.4 V, IOH = -4 A, IOL = 4 A VSS2 = -2.4 V, IOL = 4 A VSS2 = -2.4 V, IOH = -0.4 A VSS2 = -2.4 V, IOH = -0.4 A IOL = 0.4 A VSS2 = -2.4 V, IOL = 0.4 A VSS2 = -2.4 V, IOH = -4 A VSS2 = -2.4 V, IOH = -4 A IOL = 4 A VSS2 = -2.4 V, IOL = 4 A COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) -0.2 VSS2/2 -0.2 VSS2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 VSS3 + 0.2 All segments -0.2 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) VSS2/2 - 0.2 VSS2/2 + 0.2 VSS2 + 0.2 -0.2 All segments VSS2 + 0.2 V V V
Output middle level voltage
V
Output low level voltage
VOL (7)
V
* 1/3 bias--1/3 duty and 1/3 bias--1/4 duty methods Output high level voltage VOH (5) VOM1-1 VOM1-2 Output low level voltage Output high level voltage VOL (5) VOH (7) VOM2-1 VOM2-2 Output low level voltage VOL (7) -0.2 VSS2/2 - 0.2 VSS2 - 0.2 VSS2/2 + 0.2 VSS2 + 0.2 VSS3 + 0.2 V V V V V V V V
Output middle level voltage
Output middle level voltage
Electrical Characteristics at Ta = -20 to +70C, VDD = 0 V
Parameter Symbol RIN1A RIN1B Input resistance RIN2A RIN2B RIN3 Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output high level voltage Output low level voltage VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOH (4) VOL (4) VSS2 = -5.0 V, VIN = 0.8 * VSS2 VSS2 = -5.0 V, VIN = VDD VSS2 = -5.0 V, VIN = VSS2 VSS2 = -5.0 V, VIN = VDD VSS2 = -5.0 V, VIN = VDD or VSS2 VSS2 = -3.5 to -5.25 V, IOH = -1.5 mA VSS2 = -3.5 to -5.25 V, IOL = 1.5 mA VSS2 = -3.5 to -5.25 V, IOH = -0.5 mA VSS2 = -3.5 to -5.25 V, IOL = 0.7 mA VSS2 = -3.5 to -5.25 V, IOH = -0.13 mA VSS2 = -3.5 to -5.25 V, IOH = -50 A VSS2 = -3.5 to -5.25 V, IOL = 0.13 mA Conditions Low-level hold transistor*, Figure 3 Low-level pull-in transistor*, Figure 3 INT pin pull-up resistor INT pin pull-down resistor RES ALM ALM LIGHT, Port P LIGHT, Port P I/O ports I/O ports I/O ports -1 -0.6 -1 min 10 100 100 100 10 -1 typ 45 350 350 350 20 -0.3 VSS2 + 0.3 -0.3 VSS2 + 0.3 -0.3 -0.2 VSS2 + 0.3 VSS2 + 1 VSS2 + 1 VSS2 + 1 max 150 1000 1000 1000 50 Unit k k k k k V V V V V V V
Note: * S1, S2, S3, S4, M1, M2, M3, M4
Continued on next page. No. 4365-17/29
LC5852N
Continued from preceding page.
Parameter Segment driver output impedances * When used as CMOS output ports Output high level voltage Output low level voltage Output high level voltage Output low level voltage VOH (5) VOL (5) VOH (6) VOL (6) VSS2 = -3.5 to -5.25 V, IOH = -15 A VSS2 = -3.5 to -5.25 V, IOL = 150 A VSS2 = -3.5 to -5.25 V, IOH = -10 A VSS2 = -3.5 to -5.25 V, IOL = 60 A VSS2 = -3.5 to -5.25 V, IOH = -15 A VSS2 = -3.5 to -5.25 V, VOL = VSS2 VSS2 = -3.5 to -5.25 V, IOH = -0.4 A VSS2 = -3.5 to -5.25 V, IOL = 0.4 A VSS2 = -3.5 to -5.25 V, IOH = -4 A VSS2 = - 3.5 to -5.25 V, IOL = 4 A VSS2 = -3.5 to -5.25 V, IOH = -0.4 A VSS2 = -3.5 to -5.25 V, IOL = 0.4 A VSS2 = -3.5 to -5.25 V, IOH = -4 A VSS2 = -3.5 to -5.25 V, IOH = -4 A, IOL = 4 A VSS2 = -3.5 to -5.25 V, IOL = 4 A VSS2 = -3.5 to -5.25 V, IOH = -0.4 A VSS2 = -3.5 to -5.25 V, IOL = 0.4 A VSS2 = -3.5 to -5.25 V, IOH = -4 A VSS2 = -3.5 to -5.25 V, IOH = -4 A, IOL = 4 A VSS2 = -3.5 to -5.25 V, IOL = 4 A VSS2 = -3.5 to -5.25 V, IOH = -0.4 A VSS2 = -3.5 to -5.25 V, IOH = -0.4 A, IOL = 0.4 A VSS2 = -3.5 to -5.25 V, IOL = 0.4 A VSS2 = -3.5 to -5.25 V, IOH = -0.4 A VSS2 = -3.5 to -5.25 V, IOH = -4 A, IOL = 4 A VSS2 = -3.5 to -5.25 V, IOL = 4 A COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) -0.2 VSS2/2 - 0.2 VSS2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 VSS3 + 0.2 All segments COM1, 2 -0.2 VSS2/2 - 0.2 VSS2/2 +0.2 VSS2 +0.2 -0.2 COM1 VSS2 + 0.2 V Segment Pads 62 to 64, QIP64 pins 34 to 36 Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 -1 -0.3 VSS2 + 0.3 -1 -0.3 VSS2 + 0.3 VSS2 + 1 VSS2 + 1 V V V V Symbol Conditions min typ max Unit
* When used as p-channel open-drain output ports Output high level voltage Output off leakage current * Static drive Output high level voltage Output low level voltage Output high level voltage Output low level voltage * Duplex drive (1/2 bias--1/2 duty) Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage VOH (5) VOL (5) VOH (7) VOM2-1 VOL (7) -0.2 All segments VSS2 + 0.2 V V V V V VOH (5) VOL (5) VOH (7) VOL (7) -0.2 All segments VSS2 + 0.2 V V V VOH (5) IOFF Segment Pads 62 to 64, QIP64 pins 34 to 36 -1 -0.3 1 V A
* 1/2 bias--1/3 duty and 1/2 bias--1/4 duty methods Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage VOH (5) VOL (5) VOH (7) VOM2-1 VOL (7) -0.2 All segments VSS2 + 0.2 -0.2 VSS2/2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 V V V V V
COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods)
* 1/3 bias--1/3 duty and 1/3 bias--1/4 duty methods Output high level voltage VOH (5) VOM1-1 VOM1-2 Output low level voltage Output high level voltage VOL (5) VOH (7) VOM2-1 VOM2-2 Output low level voltage VOL (7) -0.2 VSS2/2 - 0.2 VSS2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 VSS3 + 0.2 V V V V V V V V
Output middle level voltage
Output low level voltage
Continued on next page. No. 4365-18/29
LC5852N
Continued from preceding page.
Parameter Power supply leakage current Input leakage current Output voltage Symbol ILEK IIN VSS1 VSS3 Output voltage VSS1 VSS3 | IDD1 | Conditions VSS2 = VSS3 = -4.5 V VSS2 = -2.0 to +4.5 V VSS2 = -2.9 V VSS2 = -2.9 V VSS2 = -4.5 V VSS2 = -4.5 V VSS2 = -2.9 V, Ta = 25C, HALT mode VSS2 = -4.5 V, Ta = 25C, HALT mode, Stack: Figure 9, 1/3 bias--1/3 duty: Figure 7, other methods: Figure 4 VSS2 = -4.5 V, Ta = 25C, HALT mode Stack: Figure 9, 1/3 bias--1/3 duty: Figure 7, other methods: Figure 4 VSS2 = -4.5 V, Ta = 25C, HALT mode C1 = C2 = 0.1 F, Cl = 25 k, fopg = 32.768 kHz, Cg = 20 pF Ta = 25C VIN = VSS2 to VDD C1 = C2 = C3 = 0.1 F, fopg = 32.768 kHz, Ta = 25C, Figure 7 C1 = C2 = C3 = 0.1 F, fopg = 32.768 kHz, Ta = 25C, Figure 7 -1 -1.45 -4.35 -2.25 -6.70 3.0 min typ max 10 +1 -1.35 -4.1 -2.2 -6.6 6.0 Unit A A V V V V A
Power supply current | IDD2 |
7
13
A
Power supply current
| IDD3 |
C1 = C2 = 0.1 F, Cl = 25 k, fopg = 65.536 kHz, Cg = 10 pF
10
20
A
Power supply current
| IDD4 |
C1 = C2 = 0.1 F, fopg = 400 kHz, Cg = Cd = 100 pF or 330 pF, Rf = 1 M, Figure 6 C1 = C2 = 0.1 F, fopg = 800 kHz, Cg = Cd = 100 pF, Rf = 1 M, Figure 6 C1 = C2 = 0.1 F, Cl = 25 k, fopg = 32.768 kHz, Cg = 20 pF C1 = C2 = 0.1 F, Cl = 25 k, fopg = 65.536 kHz, Cg = 10 pF C1 = C2 = 0.1 F, Cl = 25 k, Figure 5, fopg = 32.768 kHz, Cg = 20 pF C1 = C2 = 0.1 F, Cl = 25 k, Figure 5, fopg = 65.536 kHz, Cg = 10 pF C1 = C2 = 0.1 F, Cl = 25 k, Figure 5, fopg = 32.768 kHz, Cg = 20 pF C1 = C2 = 0.1 F, Cl = 25 k, Figure 5, fopg = 65.536 kHz, Cg = 10 pF fopg = 400 kHz, Figure 6, Cg = Cd = 100 pF or 330 pF, Rf = 1 M fopg = 400 kHz, Figure 6, Cg = Cd = 100 pF or 330 pF, Rf = 1 M fopg = 400 kHz, Figure 6, Cg = Cd = 100 pF or 330 pF, Rf = 1 M 3.5
90
150
A
Power supply current
| IDD5 |
VSS2 = -4.5 V, Ta = 25C, HALT mode Ta = 25C, Stack: Figure 9, 1/3 bias--1/3 duty: Figure 7, other methods: Figure 4
130
200
A
Oscillator hold voltage
| VHOLD1 |
2.0
5.5
V
Oscillator hold voltage
| VHOLD2 |
Ta = 25C
2.3
5.5
V
Oscillator start voltage
| VStt1 |
Stack: Figure 10, 1/3 bias--1/3 duty: Figure 7, other methods: Figure 4, Ta = 25C Ta = 25C VSS2 = -2.9 V, Ta = 25C, VSS2 = -4.5 V, Ta = 25C VSS2 = -2.9 V, Ta = 25C, VSS2 = -4.5 V, Ta = 25C Ta = 25C
2.2
V
Oscillator start voltage
| VStt2 |
2.6
V
10 10 10 10
S S S S
Oscillator start time
TStt1
Oscillator start time
TStt2
Oscillator start voltage
| VStt4 |
4.0
V
Oscillator hold voltage
| VHOLD4 |
Ta = 25C
5.5
V
Oscillator start time
TStt4
VSS2 = -4.5 V, Ta = 25C
30
ms
Continued on next page. No. 4365-19/29
LC5852N
Continued from preceding page.
Parameter Oscillator start voltage Symbol | VStt5 | Ta = 25C Conditions fopg = 800 kHz, Figure 6, Cg = Cd = 100 pF, Rf = 1 M fopg = 800 kHz, Figure 6, Cg = Cd = 100 pF, Rf = 1 M fopg = 800 kHz, Figure 6, Cg = Cd = 100 pF, Rf = 1 M 10P pin (chip products only) 10P pin (chip products only) OSCOUT pin OSCOUT pin 10 10 20 20 3.5 min typ max 4.0 Unit V
Oscillator hold voltage
| VHOLD5 |
Ta = 25C
5.5
V
Oscillator start time
TStt5 10P
VSS2 = -4.5 V, Ta = 25C VSS2 = -2.9 V VSS2 = -4.5 V VSS2 = -2.9 V VSS2 = -4.5 V
30
ms pF pF pF pF
Oscillator correction capacitance
10P 20P 20P
Figure 1 Ceramic Oscillator Specifications
Figure 2 Crystal Oscillator Specifications (32 kHz or 65 kHz)
Recommended Ceramic Oscillators
Manufacturer Item frequency 400 kHz 800 kHz Type number CSB400P CSB800J Murata Cg (pF) 100 100 Cd (pF) 100 100 Rf (M) 1 1 Type number KBR-400B KBR-800H Kyocera Cg (pF) 330 100 Cd (pF) 330 100 Rf (M) 1 1
Figure 3 S1 to S4 and M1 to M4 Input Circuits
Figure 4 Power Supply Current and Oscillator Hold Voltage Test Circuit
Figure 5 Oscillator Start Voltage, Oscillator Start Time and Frequency Stability Test Circuit
Figure 6 Oscillator Start Voltage, Oscillator Start Time, Power Supply Current and Oscillator Hold Voltage Test Circuit
No. 4365-20/29
LC5852N
Figure 7 Power Supply Current and Oscillator Hold Voltage Test Circuit
Figure 8 External Input Specifications
Figure 9 Power Supply Current and Oscillator Hold Time Test Circuit
No. 4365-21/29
LC5852N These electrical specifications are provisional and subject to change.
Ag Specifications
Absolute Maximum Ratings at Ta = 25C, VDD = 0 V
Parameter Symbol VSS1 Maximum supply voltage VSS2 VSS3 VSS3 Maximum input voltage VIN1 LCD drive method (1/3 bias) LCD drive method (methods other than 1/3 bias) S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT, TESTA (with I/OA1 to 4 and I/OB1 to 4 in input mode), 1OP, OSCIN, RES, BAK ALM, LIGHT, P1 to 4, I/OA1 to 4, I/OB1 to 4, CUP2 (with I/OA1 to 4 and I/OB1 to 4 in output mode), TESTA, OSCOUT SEGOUT, COM1 to 4, CUP1 Conditions/Pins min -4.0 -4.0 -5.5 -4.0 VSS1 - 0.3 typ max +0.3 +0.3 +0.3 +0.3 +0.3 Unit V V V V V
Maximum output voltage
VOUT1 VOUT3
VSS1 - 0.3 VSS1 - 0.3 -20 -30
+0.3 +0.3 +65 +125
V V C C
Operating temperature Storage temperature
Topr Tstg
Allowable Operating Ranges at Ta = 25 2C, VDD = 0 V
Parameter Symbol VSS1 Supply voltage VSS2 VSS3 VSS3 Input high level voltage Input low level voltage Operating frequency VIH VIL fopg LCD drive method (1/3 bias) LCD drive method (methods other than 1/3 bias) S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, RES, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) Ta = -20 to +65C -0.2 VSS1 32 VBAK = VSS1 Conditions/Pins min -1.65 -3.3 -4.95 VSS3 = VSS2 0 VSS1 + 0.2 33 V V kHz typ max -1.3 -2.4 -3.7 Unit V V V
Electrical Characteristics at Ta = 25 2C, VDD = 0 V
Parameter Symbol RIN1A RIN1B Input resistance RIN2A RIN2B RIN3 Output high level voltage Output low level voltage VOH (1) VOL (1) VOH (2) VSS1 = -1.55 V, VIL = VSS1 + 0.2 V VSS1 = -1.55 V VSS1 = -1.55 V, VIL = VSS1 VSS1 = -1.55 V, VIH = VDD VSS1 = -1.55 V, VIH = VDD VSS = -1.35 V, IOH = -250 A VSS1 = -1.35 V, IOL = 250 A Conditions/Pins Low-level hold transistor*, Figure 1 Low-level pull-down resistor*, Figure 1 INT pull-up resistor INT pull-down resistor RES pull-down resistor ALM, LIGHT ALM, LIGHT min 10 200 200 200 5 -0.65 VSS1 + 0.65 -0.2 typ 50 550 400 550 max 200 2000 2000 2000 50 Unit k k k k k V V
Output high level voltage
VSS = -1.55 V, I/OA1 to 4, I/OB1 to 4, IOH = -20 A, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) VSS1 = -1.55 V, I/OA1 to 4, I/OB1 to 4, IOL = 20 A, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode)
V
Output low level voltage
VOL (2)
VSS1 + 0.2
Note: * S1, S2, S3, S4, M1, M2, M3, M4
Continued on next page. No. 4365-22/29
LC5852N
Continued from preceding page.
Parameter Segment driver output impedances * When used as CMOS output ports Output high level voltage Output low level voltage VOH (3) VOL (3) VSS1 = -1.55 V, IOH = -3 A VSS1 = -1.55 V, IOL = 3 A VSS1 = -1.55 V, IOH = -3 A VSS1 = -1.55 V, VOL = VSS1 VSS1 = -1.55 V, IOH = -0.4 A VSS1 = -1.55 V, IOL = 0.4 A VSS1 = -1.55 V, IOH = -4 A VSS1 = -1.55 V, IOL = 4 A VSS1 = -1.55 V, IOH = -0.4 A VSS1 = -1.55 V, IOL = 0.4 A VSS1 = -1.55 V, IOH = -4 A VSS1 = -1.55 V, IOH = -4 A, IOL = 4 A VSS2 = -1.55 V, IOL = 4 A VSS1 = -1.55 V, IOH = -0.4 A VSS1 = -1.55 V, IOL = 0.4 A VSS1 = -1.55 V, IOH = -4 A VSS1 = -1.55 V, IOH = -4 A, IOL = 4 A VSS2 = -1.55 V, IOL = 4 A VSS1 = -1.55 V, IOH = -0.4 A VSS1 = -1.55 V, IOH = -0.4 A, IOL = 0.4 A VSS1 = -1.55 V, IOH = -0.4 A, IOL = 0.4 A VSS1 = -1.55 V, IOL = 0.4 A VSS1 = -1.55 V, IOH = -4 A VSS1 = -1.55 V, IOH = -4 A, IOL = 4 A VSS1 = -1.55 V, IOH = -4 A, IOL = 4 A VSS2 = -1.55 V, IOL = 4 A COM1 to 3 (for 1/3 duty methods) COM 1 to 4 (for 1/4 duty methods) -0.2 VSS1 - 0.2 VSS2 - 0.2 VSS1 + 0.2 VSS2 + 0.2 VSS3 + 0.2 V V V -0.2 COM1 to 3 (for 1/3 duty methods) COM 1 to 4 (for 1/4 duty methods) VSS1 - 0.2 VSS1 + 0.2 VSS2 + 0.2 V V COM1, 2 -0.2 VSS1 - 0.2 VSS1 + 0.2 VSS2 + 0.2 -0.2 COM1 VSS2 + 0.2 V Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33 -0.3 VSS2 + 0.3 V V Symbol Conditions/Pins min typ max Unit
* When used as p-channel open drain outputs Output high level voltage Output off leakage current * Static drive Output high level voltage Output low level voltage Output high level voltage Output low level voltage * Duplex drive (1/2 bias--1/2 duty) Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage VOH (3) VOL (3) VOH (4) VOM VOL (4) -0.2 SEGOUT VSS2 + 0.2 V V V V V VOH (3) VOL (3) VOH (4) VOL (4) -0.2 SEGOUT VSS2 + 0.2 V V V VOH (3) IOFF Segment Pads 62 to 64, QIP64 pins 34 to 36 -1 -0.3 1 V A
* 1/2 bias--1/3 duty and 1/2 bias--1/4 duty methods Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage VOH (3) VOL (3) VOH (4) VOM VOL (4) -0.2 SEGOUT VSS2 + 0.2 V V
* 1/3 bias--1/3 duty and 1/3 bias--1/4 duty methods Output high level voltage VOH (3) VOM1-3 -0.2 V
Output M1 level voltage
VSS1 - 0.2 SEGOUT VSS2 - 0.2
VSS1 + 0.2
V
Output M2 level voltage
VOM2-3
VSS2 + 0.2
V
Output low level voltage Output high level voltage Output M1 level voltage Output M2 level voltage Output low level voltage
VOL (3) VOH (4) VOM1-4 VOM2-4 VOL (4)
VSS3 + 0.2
V
Continued on next page. No. 4365-23/29
LC5852N
Continued from preceding page.
Parameter * Output voltage LCD drive: 1/3 bias methods (doubler) (tripler) LCD drive: 1/2 bias methods (doubler) VSS2 VSS3 VSS2 VSS1 = -1.35 V, C1 to 4 = 0.1 F VSS1 = -1.35 V, C1 to 4 = 0.1 F VSS1 = -1.35 V, C1 = C2 = 0.1 F fopg = 32.768 kHz, Figure 7 fopg = 32.768 kHz, Figure 7 fopg = 32.768 kHz, Figure 2 -2.5 -3.75 -2.5 V V V Symbol Conditions/Pins min typ max Unit
* Supply current (when the backup flag is cleared to zero) LCD drive: 1/3 bias methods | IDD | VSS1 = -1.55 V, C1 to 4 = 0.1 F Cd = Cg = 20 pF VSS1 = -1.55 V, C1 = C2 = 0.1 F Cd = Cg = 20 pF Cd = Cg = 20 pF Cd = Cg = 20 pF VSS1 = -1.35 V, Cd = Cg = 20 pF In HALT mode, Cl = 25 k, Figure 7, 32.768 kHz, X'tal In HALT mode, Cl = 25 k, Figure 2, 32.768 kHz, X'tal Cl = 25 k, Figure 3, 32.768 kHz, X'tal Cl = 25 k, Figure 2, 32.768 kHz, X'tal Cl = 25 k, Figure 3, 32.768 kHz, X'tal 8 16 10 20 1.3 1.3 4.5 A
LCD drive: methods other than 1/3 bias Oscillator start voltage VSS1 Oscillator hold voltage VSS1 Oscillator start time Oscillator correction capacitance
| IDD | | Vstt | | VHOLD | Tstt 10P 20P
1.1
4.5
A
1.35 1.6 10 12 24
V V s pF pF
External connection (for chip products) OSCOUT
No. 4365-24/29
LC5852N These electrical specifications are provisional and subject to change.
Li Specifications
Absolute Maximum Ratings at Ta = 25 2C, VDD = 0 V
Parameter Symbol VSS1 Maximum supply voltage VSS2 VSS3 VSS3 VIN1 Maximum input voltage VIN2 VOUT1 Maximum output voltage VOUT2 VOUT3 Operating temperature Storage temperature Topr Tstg LCD drive: 1/3 bias methods LCD drive: methods other than 1/3 bias 10P, OSCIN S1 to 4, M1 to 4, I/IA1 to 4, I/OB1 to 4, RES, INT, TESTA, (with I/OA1 to 4 and I/OB1 to 4 in input mode) TEST, OSCOUT ALM, LIGHT, P1 to 4, I/OA1 to 4, I/OB1 to 4, CUP2 (with I/OA1 to 4 and I/OB1 to 4 in output mode) SEGOUT, COM1 to 4, CUP1 Conditions/Pins VBAK = VSS1 or VSS2 min -4.0 -4.0 -5.5 -4.0 VBAK - 0.3 VSS2 - 0.3 VBAK - 0.3 VSS2 - 0.3 VSS3 - 0.3 -20 -30 typ max +0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +0.3 +65 +125 Unit V V V V V V V V V C C
Allowable Operating Ranges at Ta = 25 2C, VDD = 0 V
Parameter Symbol VBAK VSS2 Supply voltage VSS2 VSS3 VSS3 Input high level voltage Input low level voltage Operating frequency VIH VIL fopg VBAK = VSS2/2 (with the backup flag cleared to zero) VBAK = VSS2 (with the backup flag cleared to zero) LCD drive: 1/3 bias methods LCD drive: methods other than 1/3 bias S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) S1 to 4, M1 to 4, I/OA1 to 4, I/OB1 to 4, INT (with I/OA1 to 4 and I/OB1 to 4 in input mode) Ta = -20 to +65C -0.4 VSS2 32 Conditions/Pins min -3.6 -3.6 -3.6 -4.95 VSS3 = VSS2 0 VSS2 + 0.4 33 V V kHz typ max -1.3 -2.6 -1.3 -3.7 Unit V V V
Electrical Characteristics at Ta = 25 2C, VDD = 0 V
Parameter Symbol RIN1A RIN1B Input resistance RIN2A RIN2B RIN3 Note: * S1, S2, S3, S4, M1, M2, M3, M4 VSS2 = -2.9 V, VIL = VSS2 + 0.4 V VSS2 = -2.9 V, VSS2 = -2.9 V, VIL = VSS2 VSS2 = -2.9 V, VIH = VDD VSS2 = -2.9 V, VIH = VDD Conditions/Pins Low-level hold transistor*, Figure 1 Pull-down resistor*, Figure 4 INT pull-up resistor INT pull-down resistor RES pull-down resistor min 10 200 200 200 5 typ max 200 2000 2000 2000 50 Unit k k k k k
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LC5852N
Continued from preceding page.
Parameter Output high level voltage Output low level voltage Symbol VOH (1) VOL (1) VOH (2) VSS2 = -2.4 V, IOH = -250 A VSS2 = -2.4 V, IOH = 250 A Conditions/Pins ALM ALM min -0.65 VSS2 + 0.65 -0.4 typ max Unit V V
Output high level voltage
VSS2 = -2.9 V, I/OA1 to 4, I/OB1 to 4, IOH = -40 A, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) VSS2 = -2.9 V, I/OA1 to 4, I/OB1 to 4, IOL = 40 A, P1 to 4 (with I/OA1 to 4 and I/OB1 to 4 in output mode) VSS2 = -2.9 V, IOH = -150 A VSS2 = -2.9 V, IOL = 150 A LIGHT LIGHT
V
Output low level voltage
VOL (2)
VSS2 + 0.4
V
Output high level voltage Output low level voltage Segment driver output impedances * When used as CMOS output ports Output high level voltage Output low level voltage
VOH (3) VOL (3)
-1.5 VSS2 + 1.5
V V
VOH (4) VOL (4)
VSS2 = -2.9 V, IOH = -5 A VSS2 = -2.9 V, IOL = 5 A VSS2 = -2.4 V, IOH = -10 A VSS2 = -2.9 V, VOL = VSS2 VSS2 = -2.9 V, IOH = -0.4 A VSS2 = -2.9 V, IOL = 0.4 A VSS2 = -2.9 V, IOH = -4 A VSS2 = -2.9 V, IOL = 4 A VSS2 = -2.9 V, IOH = -0.4 A VSS2 = -2.9 V, IOL = 0.4 A VSS2 = -2.9 V, IOH = -4 A VSS2 = -2.9 V, IOH = -4 A, IOL = 4 A VSS2 = -2.9 V, IOL = 4 A VSS2 = -2.9 V, IOH = -0.4 A VSS2 = -2.9 V, IOL = 0.4 A VSS2 = -2.9 V, IOH = -4 A VSS2 = -2.9 V, IOH = -4 A, IOL = 4 A VSS2 = -2.9 V, IOL = 4 A
Segment Pads 38 to 41 and 44 to 61, QIP64 pins 11 to 23 and 25 to 33
-0.3 VSS2 + 0.3
V V
* When used as p-channel open-drain output ports Output high level voltage Output off leakage current * Static drive Output high level voltage Output low level voltage Output high level voltage Output low level voltage * Duplex drive (1/2 bias--1/2 duty) Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage VOH (4) VOL (4) VOH (5) VOM VOL (5) -0.2 All SEGOUT pins VSS2 + 0.2 -0.2 COM1 to 4 VSS2/2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 V V V V V VOH (4) VOL (4) VOH (5) VOL (5) -0.2 All SEGOUT pins VSS2 + 0.2 -0.2 COM1 VSS2 + 0.2 V V V V VOH (4) IOFF Segment Pads 62 to 64, QIP64 pins 34 to 36 -1 -0.3 1 V A
* 1/2 bias--1/3 duty and 1/2 bias--1/4 duty methods Output high level voltage Output low level voltage Output high level voltage Output middle level voltage Output low level voltage VOH (4) VOL (4) VOH (5) VOM VOL (5) -0.2 All SEGOUT pins VSS2 + 0.2 -0.2 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) VSS2/2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 V V V V V
Continued on next page. No. 4365-26/29
LC5852N
Continued from preceding page.
Parameter Symbol Conditions/Pins min typ max Unit
* 1/3 bias--1/3 duty and 1/3 bias--1/4 duty methods Output high level voltage VOH (4) VOM1-4 VSS2 = -2.9 V, IOH = -0.4 A VSS2 = -2.9 V, IOH = -0.4 A, IOL = 0.4 A VSS2 = -2.9 V, IOH = -0.4 A, IOL = 0.4 A VSS2 = -2.9 V, IOL = 0.4 A VSS2 = -2.9 V, IOH = -4 A VSS2 = -2.9 V, IOH = -4 A, IOL = 4 A VSS2 = -2.9 V, IOH = -4 A, IOL = 4 A VSS2 = -2.9 V, IOL = 4 A VSS2 = -2.9 V, C1 to 3 = 0.1 F VSS2 = -2.9 V, C1 to 3 = 0.1 F VSS2 = -2.9 V, C1 = C2 = 0.1 F fopg = 32.768 kHz, Figure 7 fopg = 32.768 kHz, Figure 7 fopg = 32.768 kHz, Figure 4 COM1 to 3 (for 1/3 duty methods) COM1 to 4 (for 1/4 duty methods) -0.2 VSS2/2 - 0.2 VSS2 - 0.2 VSS2/2 +0.2 VSS2 + 0.2 VSS3 + 0.2 -0.2 VSS2/2 - 0.2 All SEGOUT pins VSS2 - 0.2 VSS2 + 0.2 V VSS2/2 +0.2 V
Output M1 level voltage
V
Output M2 level voltage
VOM2-4
Output low level voltage Output high level voltage Output M1 level voltage Output M2 level voltage Output low level voltage * Output voltage LCD drive: 1/3 bias methods (halver) (tripler) LCD drive: 1/2 bias methods (halver)
VOL (4) VOH (5) VOM1-5 VOM2-5 VOL (5)
VSS3 + 0.2
V V V V V
VSS1 VSS3 VSS1
-1.35 -4.1 -1.35
V V V
* Supply current (when the backup flag is cleared to zero) LCD drive: 1/3 bias methods | IDD | VSS2 = -2.9 V, C1 to 3 = 0.1 F, Cd = Cg = 20 pF VSS2 = -2.9 V, C1 = C2 = 0.1 F, Cd = Cg = 20 pF VBAK = VSS2, Cd = Cg = 20 pF VBAK = VSS2/2, Cd = Cg = 20 pF VBAK = VSS2, Cd = Cg = 20 pF VBAK = VSS2 = -2.9 V, Cd = Cg = 20 pF External connection OSCOUT In HALT mode, Cl = 25 k, Figure 7, 32.768 kHz Xtal In HALT mode, Cl = 25k, Figure 4, 32.768 kHz Xtal Cl = 25 k, Figure 5, 32.768 kHz Xtal Cl = 25k, Figure 4, 32.768 kHz Xtal Cl = 25k, Figure 4, 32.768 kHz Xtal Cl = 25k, Figure 5, 32.768 kHz Xtal 8 16 10 20 2.6 0.8 3.0 A
LCD drive: methods other than 1/3 bias Oscillator start voltage VSS2 Oscillator hold voltage VSS2 (when the backup flag is cleared to zero) (when the backup flag is cleared to zero) Oscillator start time Oscillator correction capacitance
| IDD | | Vstt | | VHOLD (1) | | VHOLD (2) | Tstt 10P 20P
0.7
3.0
A
1.35
V
3.6
V
1.3
3.6 10 12 24
V s pF pF
Figure 1 Ceramic Oscillator Specifications
Figure 2 Crystal Oscillator Specifications (32 kHz or 65 kHz)
No. 4365-27/29
LC5852N
Figure 3 S1 to S4 and M1 to M4 Input Circuits
Figure 4 Power Supply Current and Oscillator Hold Voltage Test Circuit
Figure 5 Oscillator Start Voltage, Oscillator Start Time and Frequency Stability Test Circuit
Figure 6 Oscillator Start Voltage, Oscillator Start Time, Power Supply Current and Oscillator Hold Voltage Test Circuit
Figure 7 Power Supply Current and Oscillator Hold Voltage Test Circuit
Figure 8 External Input Specifications
Figure 9 Power Supply Current and Oscillator Hold Time Test Circuit
No. 4365-28/29
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s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of February, 1997. Specifications and information herein are subject to change without notice. No. 4365-29/29

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