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32K x 32 SRAM MODULE
PUMA 2S1000 - 020/025/35/45
Elm Road, West Chirton, North Shields, Tyne and Wear, NE29 8SE England, Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 4.4 : April 2001
Description The PUMA 2S1000 is a 1Mbit high speed static RAM organised as 32K x 32 in a 66 pin ceramic PGA package. Access times of 20ns, 25ns, 35ns or 45ns are available. The device has a user configurable output width by 8 ,16 or 32 bits, and features a low power standby mode with 3.0V battery back-up capability. The package includes on board decoupling capacitors and is suitable for thermal ladder operations. It may be screened in accordance with MIL-STD-883.
1,048,576 bit CMOS High Speed Static RAM Features * Very Fast Access times of 20/25/35/45 ns. * User Configurable as 8 / 16 / 32 bit wide output. * Operating Power 1.6 W (max) 8 bit * Low Power Standby 44 mW (max) - L Version * Upgradeable Package. * Package Suitable for Thermal Ladder Applications. * On board decoupling capacitors. * Low voltage data retention. * May be screened in accordance with MIL-STD-883.
Block Diagram
Pin Definition
1
A0~A14 OE WE4 WE3 WE2 WE1
12 WE2 13 CS2 14 GND 15 D11 16 A10 17 A11 18 A12 19 VCC 20 CS1 21 NC 22 D3
23 D15 24 D14 25 D13 26 D12 27 OE 28 NC 29 WE1 30 D7 31 D6 32 D5 33 D4
34 D24 35 D25 36 D26 37
45 VCC 46 CS4 47 WE4 48 D27 49 A3 50 A4 51 A5 52 WE3 53 CS3 54 GND 55 D19
56 D31 57 D30 58 D29 59 D28 60 A0 61 A1 62 A2 63 D23 64 D22 65 D21 66 D20
D8 2 D9 3 D10 4 A13 5 A14 6 NC 7 NC 8 NC 9 D0 10 D1 11 D2
32Kx8 SRAM
CS1 CS2 CS3 CS4 D0~D7 D8~D15 D16~D23 D24~D31
32Kx8 SRAM
32Kx8 SRAM
32Kx8 SRAM
VIEW FROM ABOVE
A6 38 A7 39 NC 40 A8 41 A9 42 D16 43 D17 44 D18
Pin Functions A0~A14 CS1~4 WE1~4 V CC Address Inputs Chip Select Write Enable Power (+5V) D0~D31 OE NC GND Data Inputs/Outputs Output Enable No Connect Ground
ISSUE 4.4 : April 2001
PUMA 2S1000 - 25/35/45
DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin relative to VSS (2) Power Dissipation Storage Temperature VT PT TSTG -0.5V to +7.0 4 -65 to +150 V W
o
C
Notes : (1)Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage Input High Voltage Input Low Voltage Operating Temperature
Symbol
V CC VIH VIL TA TAI TAM
min
4.5 2.2 -0.5 0 -40 -55
typ(1)
5.0 -
max
5.5 VCC+0.5 0.8 70 85 125
Unit
V V V
o o
C C C (I suffixI) (M, MB suffix)
o
DC Electrical Characteristics (VCC=5V10%,TA=-55C to +125C)
Parameter
I/P Leakage Current Output Leakage Current Average Supply Current
Symbol
ILI1 8 bit 32 bit 16 bit 8 bit ILO ICC32 ICC16 ICC8 ISB ISB2 VOL VOH
Test Condition
VIN=0V to VCC
(2) (2) (2)
min
-8 2.4
typ(1)
-
max Unit
8 8 660 410 285 160 8 0.4 A A mA mA mA mA mA V V
CS =VIH or OE=VIH,VI/O=0V to VCC,WE =VIL -8 CS =VIL, Min. cycle, II/O=0mA, 100% Duty. As above As above CS =VIH, Min Cycle. CS VCC-0.2V, 0.2VVINVCC-0.2V
(2) (2)
Standby Supply Current Output Voltage Low Output Voltage High
Notes:
TTL
-L Version
IOL=8.0mA IOH=-4.0mA
CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
Capacitance (VCC=5V10%,TA=25C)
Parameter
Input Capacitance I/O Capacitance:
Symbol
CIN CI/O
Test Condition
VIN =0V VI/O=0V
typ
-
max
38 18
Unit
pF pF
Note:This parameter is calculated and not measured.
2
PUMA 2S1000 - 25/35/45
ISSUE 4.4 : April 2001
Operating Modes The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the PUMA 2S1000.
Mode
Not Selected OutputDisable Read Write 1 = VIH,
CS
1 0 0 0
OE
X 1 0 X
WE
X 1 1 0
VCC Current
ISB,ISB1,ISB2 ICC ICC ICC X = Don't Care
I/O Pin Reference Cycle
High Z High Z DOUT DIN Read Cycle Write Cycle Power Down
0 = VIL,
Note: CS is accessed through CS1~4, and WE is accessed through WE1~4. For correct operation, CS1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation. WE1~4 must also be operated in the same manner.
Low Vcc Data Retention Characteristics - L Version Only (VCC = 5.0V10%, TA=-55C to +125C)
Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
Symbol
VDR ICCDR1 -L Version ICCDR2 t CDR tR
Test Condition
CSVCC-0.2V, VIN0V As above See Retention Waveform See Retention Waveform
min
2.0 0 t RC
typ
-
max
5.5 8 1.2 -
Unit
V mA mA ns ns
VCC=2.0V, CSVCC-0.2V, VIN0V -
Note: CS above is accessed through CS1~4. AC Test Conditions * Input pulse levels: 0V to 3.0V * Input rise and fall times: 3ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * Vcc=5V10% Output Load
I/O Pin 166 1.76V 30pF
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ISSUE 4.4 : April 2001
PUMA 2S1000 - 25/35/45
AC OPERATING CONDITIONS Read Cycle
Parameter
Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to Output in High Z Output Disable to Output in High Z
(3)
Symbol
tRC tAA tACS tOE tOH tCLZ tOLZ
(3)
20 min max
20 3 3 0 0 0 20 20 9 8 8
min
25
-
25 max
25 25 12 12 12
min
35 5 6 0 0 0
35 max
35 35 15 15 15
min
45 5 6 0 0 0
45 max
45 45 20 20 20
Unit
ns ns ns ns ns ns ns ns ns
5 6 0 0 0
tCHZ tOHZ
Write Cycle
Parameter
Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write
Symbol
tWC tCW tAW tAS tWP tWR tWHZ tDW tDH tOW
20 min max
20 13 13 0 13 0 0 10 0 0 8 -
min
25 20 20 0 15 0 0 20 0 5
25 max
15 -
min
35 30 30 0 20 0 0 20 0 5
35 max
18 -
45 min
45 40 40 0 25 0 0 20 0 5
max
20 -
Unit
ns ns ns ns ns ns ns ns ns ns
Consult factory
4
PUMA 2S1000 - 25/35/45
ISSUE 4.4 : April 2001
Read Cycle 1 Timing Waveform
(1)
t Address t AA OE
RC
t OE t OLZ CS1~4 t CLZ t ACS
t
OH
t CHZ(3) t OHZ(3)
Dout
High-Z
Data Valid
Read Cycle 2 Timing Waveform
(1) (2) (4)
t
RC
Address
t AA t
OH
t
OH
Dout
Data Valid
Notes: (1) WE1~4 is High for Read Cycle. (2) Device is continuously selected, CS1~4=VIL. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. (4) OE=VIL.
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ISSUE 4.4 : April 2001
PUMA 2S1000 - 25/35/45
Write Cycle No.1 Timing Waveform
t WC Address
OE
t AS(3) t AW t CW(4)
(6)
tWR
(2)
CS1~4 t WP(1) WE1~4 t OHZ(3,9) High-Z t DW High-Z t OW t DH
Dout
Din
Data Valid
Write Cycle No.2 Timing Waveform
(5)
t WC Address t CW C S 1~4
(6) (4)
t AW t WP(1) W E1 ~4 t AS(3) t WHZ(3,9) D out High-Z t DW D in High-Z Data Valid t OW
t WR(2)
t OH
(8) (7)
tDH
6
PUMA 2S1000 - 25/35/45
ISSUE 4.4 : April 2001
Data Retention Waveform
Vcc
4.5V
DATA RETENTION MODE
4.5V
tCDR VDR
CS1~4
0V
tR
2.2V
CS1~4>Vcc-0.2V
AC Write Characteristics Notes (1) (2) (3) (4) (5) (6) (7) (8) (9) A write occurs during the overlap (tWP) of a low CS and a low WE. tWR is measured from the earlier of CS or WE going high to the end of write cycle. During this period, I/O pins are in the output state. Input signals out of phase must not be applied. If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain in a high impedance state. OE is continuously low. (OE=VIL) Dout is in the same phase as written data of this write cycle. Dout is the read data of next address. If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied to I/O pins. tWHZ and tOHZ is defined as the time at which the outputs achieve the open circuit conditions and is not referenced to output voltage levels. This parameter is sampled and not 100% tested. CS and WE above refer to CS1~4 and WE1~4 respectively.
7
ISSUE 4.4 : April 2001
PUMA 2S1000 - 25/35/45
PACKAGE DETAILS 66 Pin Ceramic PGA
27.55 (1.085) square 27.05 (1.065) square
4.83 (0.190) 4.32 (0.170)
2.54 (0.100) typ.
15.24 (0.60) typ
0.51 (0.020) 0.38 (0.015)
1.40 (0.055) 1.14 (0.045) 1.27 (0.050) 0.64 (0.025) 8.13 (0.320) max 1.52 (0.060) 1.02 (0.040)
2.54 (0.100) typ.
Dimensions in mm (inches) SCREENING Military Screening Procedure Module Screening Flow for high reliability product is in accordance with Mil-883 method 5004 .
MB MODULE SCREENING FLOW
SCREEN
Visual and Mechanical
External visual Temperature cycle 2017 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles, -65oC to +150oC) 100% 100%
TEST METHOD
LEVEL
Burn-In
Pre-Burn-in electrical Burn-in Per applicable Device Specifications at TA=+25oC TA=+125oC,160hrs minimum. Per applicable Device Specification a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes Calculated at Post Burn-in at TA=+25oC Per applicable Device Specification 2009 Per vendor or customer specification 100% 100% 100% 100% 100% 100% 10% Sample 100% 100% 100%
Final Electrical Tests
Static (DC) Functional Switching (AC)
Percent Defective allowable (PDA) Quality Conformance External Visual
8
PUMA 2S1000 - 25/35/45
ISSUE 4.4 : April 2001
ORDERING INFORMATION
PUMA 2S1000LMB - 35
Speed 020 025 35 45 = = = = 20 ns 25 ns 35 ns 45 ns
Temp. range/screening
Blank = Commercial Temperature. I = Industrial Temperature. M = Military Temperature. MB = Screened in accordance with MIL-STD-883.
Power Consumption
Blank = Standard Part. L = Low Power Part. 1000 = 32K x 32, configurable as 64K x 16 and 128K x 8 S = Static RAM. PUMA 2 = 66 pin Ceramic PGA.
Memory Organisation
Memory Technology Package
Note : Although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director.
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