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UTRON
Rev. 1.1 REVISION HISTORY REVISION Rev. 0.9 Rev. 1.0
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.1
DESCRIPTION Original. 1. The Operating Temperature is revised from Industrial temperature to Extended temperatureG -20J ~80J 2. The symbols CE1#,OE# and WE# are revised as CE1 , OE and WE Add order information for lead free product
DATE Jan.2001 Jun 18,2001
May 15,2003
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
1

UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT621024(E) is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT621024(E) is designed for low power application. It is particularly well suited for battery back-up nonvolatile memory application. The UT621024(E) operates from a single 5V power supply and all inputs and outputs are fully TTL compatible.
FEATURES
Access time : 35/55/70ns (max.) Low power consumption : Operating : 60/50/40 mA (typical) Standby : 2A (typical) L-version 1A (typical) LL-version Single 5V power supply All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage : 2V (min.) OperatingTemperature : Extended : -20J ~80J Package : 32-pin 600 mil PDIP 32-pin 450 mil SOP 32-pin 8mmx20mm TSOP-1 32-pin 8mmx13.4mm STSOP
PIN CONFIGURATION
NC A16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2
WE
FUNCTIONAL BLOCK DIAGRAM
1024 X 1024 MEMORY ARRAY
A14 A12 A7 A6 A5 A4 A3
UT621024(E)
A13 A8 A9 A11
OE
A0-A16
DECODER
Vcc Vss
A2 A1 A0 I/O1 I/O2
A10
CE
I/O8 I/O7 I/O6 I/O5 I/O4
I/O1-I/O8
I/O DATA CIRCUIT
COLUMN I/O
I/O3 Vss
PDIP / SOP
A11 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26
OE
A10
CE CE2
OE
A8
CE
I/O 8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 A3
CONTROL CIRCUIT
A13
WE
WE
CE2 A15 Vcc
PIN DESCRIPTION
SYMBOL A0 - A16 I/O1 - I/O8 CE ,CE2 DESCRIPTION Address Inputs Data Inputs/Outputs Chip enable 1,2 Inputs Write Enable Input Output Enable Input VCC VSS NC Power Supply Ground No Connection
NC A16 A14 A12 A7 A6 A5 A4
UT621024(E)
25 24 23 22 21 20 19 18 17
TSOP-I/STSOP
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to Vss Operating Temperature Extended Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to +7.0 -20 to +80 -65 to +150 1 50 260 UNIT V J J W mA J
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Standby Output Disable Read Write
CE H X L L L
CE2 X L H H H
I/O OPERATION X X H L X X X H H L High - Z High -Z High - Z DOUT DIN
SUPPLY CURRENT ISB,ISB1 ISB,ISB1 ICC ICC ICC
Note: H = VIH, L=VIL, X = Don't care.
) DC ELECTRICAL CHARACTERISTICS (VCC = 5VO 10%, TA = -20J to 80J
PARAMETER SYMBOL TEST CONDITION *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current IIL VSS O VIN O VCC Output Leakage Current IOL VSS O VI/OO VCC CE =VIH or CE2 = VIL or Output High Voltage Output Low Voltage Average Operating Power Supply Courrent VOH VOL ICC = VIH or = VIL IOH = - 1mA IOL= 4mA Min.Cycle, 100% Duty, CE =VIL, CE2 = VIH, II/O = 0mA Cycle time = 1s, 100% Duty, . CE O 0.2V,CE2U VCC-0.2V, II/O = 0Ma CE =VIH or CE2 = VIL CE U VCC-0.2V or .CE2O 0.2V -L - LL
Notes: 1. Overshoot : Vcc+2.0v for pulse width less than 10ns. 2. Undershoot : Vss-2.0v for pulse width less than 10ns. 3. Overshoot and Undershoot are sampled, not 100% tested. 4. Those parameters are for reference only under 50
MIN. 2.2 - 0.5 -1 -1 2.4 -35 -55 -70 -
TYP. 60 50 40 2 1
MAX. VCC+0.5 0.8 1 1 0.4 100 85 70 10 3 200 4 40* 100 4 15*
UNIT V V A A V V mA mA mA mA mA A A
ICC1
Standby Power Supply Current
ISB ISB1
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
, CAPACITANCE (TA=25J f=1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX. 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL=100pF, IOH/IOL=-1mA/4mA
) AC ELECTRICAL CHARACTERISTICS (VCC = 5VO 10% , TA = -20J to 80J
(1) READ CYCLE PARAMETER SYMBOL UT621024(E) -35 MIN. MAX. 35 35 35 25 10 5 25 25 5 UT621024(E) -55 MIN. MAX. 55 55 55 30 10 5 30 30 5 UT621024(E) -70 MIN. MAX. 70 70 70 35 10 5 35 35 5 UNIT
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER
tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH
ns ns ns ns ns ns ns ns ns
SYMBOL
Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write-Time Output Active from End of Write Write to Output in High-Z
tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
UT621024(E) -35 MIN. MAX. 35 30 30 0 25 0 20 0 5 15
UT621024(E) UT621024(E) UNIT -55 -70 MIN. MAX. MIN. MAX. 55 70 ns 50 60 ns 50 60 ns 0 0 ns 40 45 ns 0 0 ns 25 30 ns 0 0 ns 5 5 ns 20 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2)
tRC
Address
tAA tOH
Dout Previous data valid Data Valid
tOH
READ CYCLE 2 ( CE and CE2 and OE Controlled) (1,3,4,5)
tRC
Address
tAA
CE
tACE
CE2
OE
tOE tCLZ tOLZ
Dout High-Z Data Valid
tCHZ tOHZ tOH
High-Z
Notes : 1. WE is high for read cycle. 2.Device is continuously selected OE =low, CE =low, CE2=high. 3.Address must be valid prior to or coincident with CE =low, CE2=high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measuredO 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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UTRON
Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5,6)
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
tWC
Address
tAW
CE
tCW
CE2
tAS
WE
tWP
tWR
tWHZ
Dout (4)
High-Z
tOW
(4)
tDW
Din
tDH
Data Valid
WRITE CYCLE 2 ( CE and CE2 Controlled) (1,2,5,6)
tWC
A ddress
tAW
CE
tAS tCW
tWR
CE2
tWP
WE
tWHZ
D out (4) H igh-Z
tDW
D in D ata V alid
tDH
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1
Notes : 1. WE , CE must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE , high CE2, low WE .
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
3. During a WE controlled write cycle with OE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured O 500mV from steady state.
) DATA RETENTION CHARACTERISTICS (TA = -20J to +80J
PARAMETER Vcc for Data Retention Data Retention Current SYMBOL TEST CONDITION VDR CE U VCC-0.2V or CE2 0.2V IDR Vcc=3V CE U VCC-0.2V or CE2 0.2V See Data Retention Waveforms (below) MIN. 2.0 -L - LL 0 tRC* TYP. MAX. 80 20* 40 10* UNIT V A A ns ns
1 0.5
Chip Disable to Data Retention Time Recovery Time
tCDR tR
tRC* = Read Cycle Time *Those parameters are for reference only under 50J
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) ( CE controlled)
VDR U 2V VCC Vcc(min.) Vcc(min.)
tCDR
CE VIH CE U VCC-0.2V
tR
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR U 2V VCC VCC(min.) VCC(min.)
tCDR
CE2 VIL CE2 O 0.2V
tR
VIL
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
32 PIN 600 mil PDIP Package Outline Dimension
UNIT SYMBOL A1 A2 B D E E1 e eB L S Q1 NOTE: 1. D/E1/S dimension do not include mold flash.
INCH(BASE) 0.010(MIN) 0.150 O 0.005 0.018 O 0.005 1.650 O 0.005 0.600 O 0.010 0.544 O 0.004 0.100 (TYP) 0.640 O 0.020 0.130 O 0.010 0.075 O 0.010 0.070 O 0.005
MM(REF) 0.254(MIN) 3.810 O 0.127 0.457 O 0.127 41.910 O 0.127 15.240 O 0.254 13.818 O 0.102 2.540 (TYP) 16.256 O 0.508 3.302 O 0.254 1.905 O 0.254 1.778 O 0.127
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1 32 pin 450mil SOP Package Outline Dimension
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
UNIT SYMBOL A A1 A2 b D E E1 e L L1 S y K
INCH(BASE) 0.118 (MAX) 0.004 (MIN) 0.111 (MAX) 0.016 (TYP) 0.817 (MAX) 0.445 O 0.005 0.555 O 0.012 0.050 (TYP) 0.0347 O 0.008 0.055 O 0.008 0.026 (MAX) 0.004 (MAX) o o 0 ~10
MM(REF) 2.997 (MAX) 0.102 (MIN) 2.82 (MAX) 0.406 (TYP) 20.75 (MAX) 11.303 O 0.127 14.097 O 0.305 1.270 (TYP) 0.881 O 0.203 1.397 O 0.203 0.660 (MAX) 0.101 (MAX) o o 0 ~10
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
32 pin TSOP-I Package Outline Dimension
HD
C L
1
32
e
16 17
b
E
"A"
Seating Plane
y
D
16
17
A
A2
GAUGE PLANE
A1
SEATING PLANE
1
32
"A" DETAIL VIEW
L1
UNIT SYMBOL A A1 A2 b D E e HD L1 y K
INCH(BASE) 0.047 (MAX) 0.004 O 0.002 0.039 O 0.002 0.008 + 0.002 - 0.001 0.724 O 0.004 0.315 O 0.004 0.020 (TYP) 0.787 O 0.008 0.0315 O 0.004 0.003 (MAX) o o 0 a 5
MM(REF) 1.20 (MAX) 0.10 O 0.05 1.00 O 0.05 0.20 + 0.05 -0.03 18.40 O 0.10 8.00 O 0.10 0.50 (TYP) 20.00 O 0.20 0.80 O 0.10 0.076 (MAX) o o 0 a 5
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
10
0.254
0
P80037

UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
HD
c L
1 32
e 16 17
"A"
D Seating Plane
b
E
y
16
17
GAUGE PLANE A A2 0.254 0 A1 SEATING PLANE L1
"A" DATAIL VIEW
1 32
UNIT SYMBOL A A1 A2 b D E e HD L1 y K
INCH(BASE) 0.047 (MAX) 0.004 O 0.002 0.039 O 0.002 0.008 O 0.001 0.465 O 0.004 0.315 O 0.004 0.020 (TYP) 0.528 O 0.008 0.0315 O 0.004 0.003 (MAX) o o 0 a 5
MM(REF) 1.20 (MAX) 0.10 O 0.05 1.00 O 0.05 0.200 O 0.025 11.800 O 0.100 8.000 O 0.100 0.50 (TYP) 13.40 O 0.20. 0.80 O 0.10 0.076 (MAX) o o 0 a 5
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
PART NO. UT621024PC-35LE UT621024PC-35LLE UT621024SC-35LE UT621024SC-35LLE UT621024LC-35LE UT621024LC-35LLE UT621024LS-35LE UT621024LS-35LLE UT621024PC-55LE UT621024PC-55LLE UT621024SC-55LE UT621024SC-55LLE UT621024LC-55LE UT621024LC-55LLE UT621024LS-55LE UT621024LS-55LLE UT621024PC-70LE UT621024PC-70LLE UT621024SC-70LE UT621024SC-70LLE UT621024LC-70LE UT621024LC-70LLE UT621024LS-70LE UT621024LS-70LLE ACCESS TIME (ns) 35 35 35 35 35 35 35 35 55 55 55 55 55 55 55 55 70 70 70 70 70 70 70 70 STANDBY CURRENT (A) 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 PACKAGE 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
12

UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION (for lead free product)
PART NO. UT621024PCL-35LE UT621024PCL-35LLE UT621024SCL-35LE UT621024SCL-35LLE UT621024LCL-35LE UT621024LCL-35LLE UT621024LSL-35LE UT621024LSL-35LLE UT621024PCL-55LE UT621024PCL-55LLE UT621024SCL-55LE UT621024SCL-55LLE UT621024LCL-55LE UT621024LCL-55LLE UT621024LSL-55LE UT621024LSL-55LLE UT621024PCL-70LE UT621024PCL-70LLE UT621024SCL-70LE UT621024SCL-70LLE UT621024LCL-70LE UT621024LCL-70LLE UT621024LSL-70LE UT621024LSL-70LLE ACCESS TIME (ns) 35 35 35 35 35 35 35 35 55 55 55 55 55 55 55 55 70 70 70 70 70 70 70 70 STANDBY CURRENT (A) 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 200 100 PACKAGE 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP 32 PIN PDIP 32 PIN PDIP 32 PIN SOP 32 PIN SOP 32 PIN TSOP-I 32 PIN TSOP-I 32 PIN STSOP 32 PIN STSOP
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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UTRON
Rev. 1.1
UT621024(E)
128K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
P80037
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