View CY28370_587714.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY28370
High-performance SiS645/650/660 Pentium 4 Clock Synthesizer
Features
* * * * * * * Supports Intel Pentium 4-type CPUs 3.3V power supply Eight copies of PCI clocks One 48-MHz USB clock Two copies of ZCLK clocks One 48-MHz/24-MHz programmable SIO clock Two differential CPU clock pairs * * * * * * * SMBus support with readback capabilities Spread Spectrum EMI reduction Dial-a-FrequencyTM features Dial-a-RatioTM features Dial-a-DBTM features 48-pin SSOP package Watchdog function
Block Diagram
XIN XOUT PLL1 CPU_STP# IREF FS(0:4) MULT0 VTTPWRGD PCI_STP# PLL2 Power on Latch
/2
Pin Configuration[1]
REF(0:2) CPU(0:1)T CPU(0:1)C SDCLK AGP(0:1) ZCLK(0:1) PCI(0:5) PCI_F(0:1) 48M 48M_24M#
PD# SDATA SCLK
WD Logic I2C Logic
SRESET#
VDDR **FS0/REF0 **FS1/REF1 **FS2/REF2 VSSR XIN XOUT VSSZ ZCLK0 ZCLK1 VDDZ *SRESET#/PCI_STP# VDDP **FS3/PCI_F0 **FS4/PCI_F1 PCI0 PCI1 VSSP VDDP PCI2 PCI3 PCI4 PCI5 VSSP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VDDSD SDCLK VSSSD CPU_STP#* CPU1T CPU1C VDDC VSSC CPU0T CPU0C IREF VSSA VDDA SCLK SDATA PD#/VTTPWRGD* VSSAGP AGP0 AGP1 VDDAGP VDD48M 48M 24_48M/MULT0* VSS48M
48 pin SSOP
Note: 1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation Document #: 38-07373 Rev. *B
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised December 27, 2002
&<
CY28370
Table 1. Frequency Table FS(4:0) 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 CPU (MHz) 66.67 100.00 111.11 100.00 100.00 133.90 133.33 133.33 100.00 100.00 111.11 100.00 100.60 133.33 100.00 133.33 125.00 150.00 140.00 166.67 100.00 133.33 133.33 133.33 111.11 125.00 105.00 120.00 133.33 100.00 180.00 160.00
[2]
SDRAM (MHz) 66.67 133.33 166.67 200.00 100.00 133.90 166.67 200.00 166.67 133.33 166.67 200.00 134.13 133.33 166.67 166.67 125.00 150.00 140.00 166.67 100.00 133.33 166.67 200.00 133.33 166.67 140.00 150.00 133.33 133.33 135.00 213.33
ZCLK (MHz) 66.67 66.67 66.67 66.67 133.33 133.90 133.33 133.33 125.00 133.33 133.33 133.33 100.60 100.00 100.00 111.11 100.00 120.00 140.00 133.33 66.67 95.24 95.24 100.00 133.33 166.67 140.00 150.00 133.33 133.33 135.00 128.00
AGP (MHz 66.67 66.67 66.67 66.67 66.67 66.95 66.67 66.67 62.50 66.67 66.67 66.67 67.07 66.67 71.43 66.67 71.43 66.67 70.00 66.67 66.67 66.67 66.67 66.67 66.67 62.50 60.00 66.67 57.14 50.00 60.00 64.00
PCI (MHz) 33.33 33.33 33.33 33.33 33.33 33.48 33.33 33.33 31.25 33.33 33.33 33.33 33.53 33.33 35.71 33.33 35.71 33.33 35.00 33.33 33.33 33.33 33.33 33.33 33.33 31.25 30.00 33.33 28.57 25.00 30.00 32.00
VCO (MHz) 400.00 400.00 666.66 400.00 400.00 669.50 666.66 400.00 500.00 400.00 666.66 400.00 402.40 400.00 500.00 666.66 500.00 600.00 560.00 666.66 400.00 666.66 666.66 400.00 666.66 500.00 420.00 600.00 400.00 400.00 540.00 640.00
Pin Description
Pin 6 7 40,44 39,43 16,17,20,23 14
Name XIN XOUT CPU(0:1)T CPU(0:1)C PCI (0:5) FS3/PCI_F0
PWR VDDR VDDC VDDC VDDP VDDP
I/O I O O O O I/O PD
Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. "True" host output clocks. See Table 1 for frequencies and functionality. "Complementary" host output clocks. See Table 1 for frequencies and functionality. PCI Clock Outputs. See Table 1. Power-on bidirectional input/output. At power-up, FS3 is the input. When VTTPWRGD transitions to a logic HIGH, FS3 state is latched and this pin becomes PCI_F0 Clock Output. See Table 1.
Document #: 38-07373 Rev. *B
Page 2 of 19
CY28370
Pin Description (continued)[2]
Pin 15 Name FS4/PCI_F1 PWR VDDP I/O I/O PD I/O PD I/O PD I/O PD I I PU Description Power-on bidirectional input/output. At power-up, FS4 is the input. When VTTPWRGD transitions to a logic HIGH, FS4 state is latched and this pin becomes PCI_F1 Clock Output. See Table 1. Power-on bidirectional input/output. At power-up, FS0 is the input. When VTTPWRGD transitions to a logic HIGH, FS0 state is latched and this pin becomes REF0, buffered Output copy of the device's XIN clock. Power-on bidirectional input/output. At power-up, FS1 is the input. When VTTPWRGD is transited to logic LOW, FS1 state is latched and this pin becomes REF1, buffered Output copy of the device's XIN clock. Power-on bidirectional input/output. At power-up, FS2 is the input. When VTTPWRGD is transited to logic LOW, FS2 state is latched and this pin becomes REF2, buffered Output copy of the device's XIN clock. Current reference programming input for CPU buffers. A resistor is connected between this pin and VSS. See Figure 2. Power-down Input/VTT Power Good Input. At power-up, VTTPWRGD is the input. When this input is transitions initially from LOW to HIGH, the FS (0:4) and MULT0 are latched. After the first LOW-to-HIGH transition, this pin become a PD# input with an internal pull-up. When PD# is asserted LOW, the device enters power-down mode. See power management function. Fixed 48-MHz USB Clock Output Power-on bidirectional input/output. At power-up, MULT0 is the input. When VTTPWRGD is transited to logic LOW, MULT0 state is latched and this pin becomes 24_48M, SIO programmable clock output. HyperZip Clock Outputs. See Table 1. Serial Data Input. Conforms to the SMBus specification of a Slave Receive/Transmit device. It is an input when receiving data. It is an open drain output when acknowledging or transmitting data. Serial Clock Input. Conforms to the SMBus specification. PCI Clock Disable Input. If Byte12 Bit7 = 0, this pin becomes an SRESET# open drain output, and the internal pulled up is not active. See system reset description. System Reset Control Output. If Byte12 Bit7 = 1 (Default), this pin becomes PCI Clock Disable Input. When PCI_STP# is asserted low, PCI (0:5) clocks are synchronously disabled in a low state. This pin does not affect PCI_F (0:1) if they are programmed to be free-running clocks via the device's SMBus interface. CPU Clock Disable Input. When asserted low, CPU (0:1)T clocks are synchronously disabled in a high state and CPU (0:1)C clocks are synchronously disabled in a low state. SDRAM Clock Output. AGP clock outputs. See Table 1 for frequencies and functionality.
2
FS0/REF0
VDDR
3
FS1/REF1
VDDR
4
FS2/REF2
VDDR
38 33
IREF PD#/VTTPRGD
27 26
48M
VDD48M
O I/O PU O I/O
24_48M/MULT0 VDD48M
9,10 34
ZCLK (0:1) SDATA
VDDZ
35 12
SCLK SRESET#
I O
PCI_STP#
I PU
45
CPU_STP#
I PU VDDSD VDDAGP O O
47 30,31 48 29 11 1 13,19 42 28 36 18,24 41
SDCLK AGP (0:1) VDDSD VDDAGP VDDZ VDDR VDDP VDDC VDD48M VDDA VSSP VSSC
PWR 3.3V power supply for SDRAM clock outputs. PWR 3.3V power supply for AGP clock outputs. PWR 3.3V power supply for HyperZip clock outputs. PWR 3.3V power supply for REF clock outputs. PWR 3.3V power supply for PCI clock outputs. PWR 3.3V power supply for CPU clock outputs. PWR 3.3V power supply for 48-MHz/24-MHz clock outputs. PWR 3.3V analog power supply. PWR GND for PCI clock outputs. PWR GND for CPU clock outputs.
Document #: 38-07373 Rev. *B
Page 3 of 19
CY28370
Pin Description (continued)[2]
Pin 8 25 5 46 32 37 Name VSSZ VSS48M VSSR VSSSD VSSAGP VSSA PWR I/O Description PWR GND for HyperZip clock outputs. PWR GND for 48-MHz/24-MHz clock outputs. PWR GND for REF clock outputs. PWR GND for SDRAM clock outputs. PWR GND for AGP clock outputs. PWR GND for analog.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 2. Command Code Definition Bit 7 0 = Block Read or Block Write operation 1 = Byte Read or Byte Write operation
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the controller. For Block Write/Read operations, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The Block Write and Block Read protocol is outlined in Table 3 while Table 4 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h).
Description
(6:0) Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be "0000000" Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit "00000000" stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 0 - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data Byte N/Slave Acknowledge... Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8-bit "00000000" stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Block Read Protocol Description
Note: 2. PU = internal pull-up. PD = internal pull-down. T = three-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 - 1.8V and HIGH => 2.0V.
Document #: 38-07373 Rev. *B
Page 4 of 19
CY28370
Table 3. Block Read and Block Write Protocol (continued) .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 Start Slave address - 7 bits Write Acknowledge from slave Description Bit 1 2:8 9 10 Start Slave address - 7 bits Write Acknowledge from slave Byte Read Protocol Description Data byte N from slave - 8 bits Not acknowledge Stop
Command Code - 8 bits "1xxxxxxx" stands for byte 11:18 operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 28 29 Acknowledge from slave Acknowledge from slave Stop 20:27 Byte Count - 8 bits
Command Code - 8 bits "1xxxxxxx" stands for byte 11:18 operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 20 28 29 38 39 Acknowledge from slave Repeat start Read Acknowledge from slave Not acknowledge Stop
21:27 Slave address - 7 bits
30:37 Data byte from slave - 8 bits
Since SDR and DDR Zero Delay Buffers will share this same address this device starts from Byte 4. Byte 4: CPU Clock Register Bit 7 6 5 4 3 2 1 0 @Pup H/W Setting H/W Setting H/W Setting H/W Setting 0 H/W Setting 1 0 15 FS4 SSCG Pin# 14 4 3 2 Name FS3 FS2 FS1 FS0 For selecting frequencies in Table 1. For selecting frequencies in Table 1. For selecting frequencies in Table 1. For selecting frequencies inTable 1. If this bit is programmed to a "1," it enables Writes to bits (7:4, 2) for selecting the frequency via software (SMBus). If this bit is programmed to a "0," it enables only Reads of bits (7:4, 2) that reflect the hardware setting of FS(0:4). For selecting frequencies in Table 1. Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. Master Output Control. 0 = running, 1 = three-state all outputs. Description
Byte 5: CPU Clock Register (All bits are read-only) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 X X X X X X 26 15 14 4 3 2 MULT0 FS4 FS3 FS2 FS1 FS0 Pin# Name Reserved Reserved MULT0 (pin 26) Value. This bit is read-only FS4 read back. This bit is read-only. FS3 read back. This bit is read-only. FS2 read back. This bit is read-only. FS1 read back. This bit is read-only. FS0 read back. This bit is read-only. Description
Document #: 38-07373 Rev. *B
Page 5 of 19
CY28370
Byte 6: CPU Clock Register Bit 7 6 5 4 3 @Pup 0 0 0 0 1 14 15 40,39 PCI_F0 PCI_F1 Pin# Name Reserved PCI_STP# control of PCI_F0. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. PCI_STP# control of PCI_F1. 0 = Free Running, 1 = Stopped when PCI_STP# is LOW. Description Function Test Bit, always program to 0.
Controls CPU0T and CPU0C functionality when CPU_STP# is asserted LOW CPU0T/C 0 = Free Running, 1 + Stopped with CPU_STP# asserted LOW This is a Read and Write Control bit. Controls CPU1T and CPU1C functionality when CPU_STP# is asserted LOW CPU1T/C 0 = Free Running, 1 Stopped with CPU_STP# asserted to LOW This and Read and Write Control bit. CPU0T/C CPU1T/C CPU0T, CPU0C Output Control, 1 = enabled, 0 = disabled. This is a Read and Write Control bit. CPU1T, CPU1C Output Control, 1 = enabled, 0 = disabled. This is a Read and Write Control bit.
2 1 0
0 1 1
44,43 40,39 44,43
Byte 7: PCI Clock Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 14 15 23 22 21 20 17 16 Name PCI_F0 PCI_F1 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Description PCI_F0 Output Control 1 = enabled, 0 = forced LOW. PCI_F1 Output Control 1 = enabled, 0 = forced LOW. PCI5 Output Control 1 = enabled, 0 = forced LOW. PCI4 Output Control 1 = enabled, 0 = forced LOW. PCI3 Output Control 1 = enabled, 0 = forced LOW. PCI2 Output Control 1 = enabled, 0 = forced LOW. PCI1 Output Control 1 = enabled, 0 = forced LOW. PCI0 Output Control 1 = enabled, 0 = forced LOW.
Byte 8: Silicon Signature Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 Revision ID Vendor ID 1000 = Cypress Description
Byte 9: Peripheral Control Register Bit @Pup 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 Pin# 33 Name PD# PD# Enable. 0 = enable, 1 = disable. Description
39,40,43, PD# output 0 = when PD# is asserted LOW, CPU(0:1)T stop in a HIGH state, CPU(0:1)C stop in a 44 control LOW state. 1 = when PD# is asserted LOW, CPU(0:1)T and CPU(0:1)C stop in H-Z. 27 26 26 48M 48M_24M 48M_24M SS2 SS1 SS0 48M Output Control 1 = enabled, 0 = forced LOW. 48M_24M Output Control 1 = enabled, 0 = forced LOW. 48M_24M, 0 = pin28 output is 24 MHz, 1 = pin28 output is 48 MHz. SS2 Spread Spectrum control bit (0 = down spread, 1 = center spread). SS1 Spread Spectrum control bit. See Table 9. SS0 Spread Spectrum control bit. See Table 9. Page 6 of 19
Document #: 38-07373 Rev. *B
CY28370
Byte 10: Peripheral Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 47 4 3 2 10 9 30 31 Name SDCLK REF2 REF1 REF0 ZCLK1 ZCLK0 AGP1 AGP0 Description SDCLK Output Enable 1 = enabled, 0 = disabled. REF2 Output Control 1 = enabled, 0 = forced LOW. REF1 Output Control 1 = enabled, 0 = forced LOW. REF0 Output Control 1 = enabled, 0 = forced LOW. ZCLK1 Output Enable 1 = enabled, 0 = disabled. ZCLK0 Output Enabled 1 = enabled, 0 = disabled. AGP1 Output Enabled 1 = enabled, 0 = disabled. AGP0 Output Enabled 1 = enabled, 0 = disabled.
Byte 11: Dial-a-SkewTM and Dial-a-RatioTM Control Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Description DARSD2 Programming these bits allows modifying the frequency ratio of the SDCLK clock relative to the DARSD1 VCO. See Table 5. DARSD0 DARAG2 Programming these bits allows modifying the frequency ratio of the AGP(1:0), PCI(5:0) and DARAG1 PCIF(0:1) clocks relative to the VCO. See Table 6. DARAG0 DASSD1 Programming these bits allows shifting skew between CPU and SDCLK signals. See Table 7. DASSD0
Table 5. Dial-a-Ratio SDCLK DARSD(2:0) 000 001 010 011 100 101 110 111 Table 6. Dial-a-Ratio AGP(0:1)[3] DARAG(2:0) 000 001 010 011 100 101 110 111
Notes: 3. The ratio of AGP to PCI is retained at 2:1. 4. See Figure 2 for CPU measurement point. See Figure 3 for SDCLK measurement point.
VC0/SDCLK Ratio Frequency Selection Default 2 3 4 5 6 8 9
VC0/AGP Ratio Frequency Selection Default 6 7 8 9 10 10 10
Document #: 38-07373 Rev. *B
Page 7 of 19
CY28370
Table 7. Dial-a-Skew SDCLK CPU DASSD(1:0) 00 01 10 11 Byte 12: Watchdog Time Stamp Register Bit 7 6 5 4 3 2 1 0 @Pup 1 0 0 0 0 0 0 0 WD3 WD2 WD1 WD0 Name Description SRESET#/PCI_STP#. 1 = Pin 12 is the input pin as PCI_STP# signal. 0 = Pin 12 is the output pin as SRESET# signal. Frequency Revert. This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = selects frequency of existing H/W setting1 = selects frequency of the second to last S/W setting. (the software setting prior to the one that caused a system reboot). WDTEST. For WD-Test, ALWAYS program to '0.' WD Alarm. This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). This bits selects the Watchdog Time Stamp Value. See Table 8. SDCLK-CPU Skew 0 ps (Default)[4] +150 ps (CPU lag)* +300 ps (CPU lag)* +450 ps (CPU lag)*
Table 8. Watchdog Time Stamp Table WD(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Function Off 1 second 2 seconds 3 seconds 4 seconds 5 seconds 6 seconds 7 seconds 8 seconds 9 seconds 10 seconds 11 seconds 12 seconds 13 seconds 14 seconds 15 seconds
Byte 13: Dial-a-FrequencyTM Control Register N (All bits are read and write functional)[5] Bit 7 6 5 4 3 @Pup 0 0 0 0 0 Description Reserved N6, MSB N5 N4 N3
Note: 5. Byte 13 and Byte 14 should be written together in every case.
Document #: 38-07373 Rev. *B
Page 8 of 19
CY28370
Byte 13: Dial-a-FrequencyTM Control Register N (All bits are read and write functional)[5] (continued) Bit 2 1 0 @Pup 0 0 0 Description N2 N3 N0, LSB
Byte 14: Dial-a-Frequency Control Register R (All bits are read and write functional)[5] Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Reserved R5 MSB R4 R3 R2 R1 R0, LSB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from the DAF registers into R and N. Description
Dial-a-Frequency Feature
SMBus Dial-a-Frequency feature is available in this device via Byte13 and Byte14. P is a large value PLL constant that depends on the frequency selection achieved through the FS(4:0) 00111, 01101, 10111, 11100, 11110 00001, 00011, 00100, 01001, 01011, 01100, 10000, 10001, 10010, 10011, 10100, 11001, 11010, 11101, 11111 00101, 00110, 01000, 00111, 01110, 01111, 10101, 10110, 10010, 11011 0000, 00010, 01010, 11000 hardware selectors (FS4, FS0). P value may be determined from the following table. P 127995867 95996900 76797520 63997933
Spread Spectrum Clock Generation (SSCG)
Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by Table 9. Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Down Down Down Down Center Center Center Center a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. See the SMBus register section of this data sheet for the exact bit and byte functionally. The following table is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates.
Spread Mode
Spread% -0.50 -0.75 -1.00 -1.50 +0.25, -0.25 +0.37, -0.37 +0.50, -0.50 +0.75, -0.75
Document #: 38-07373 Rev. *B
Page 9 of 19
CY28370
System Self Recovery Clock Management
This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. The watchdog timer is triggered whenever a frequency change or output divided change occurs. The system BIOS first needs to enable the watchdog time out value through I2C and then change the target frequency. After waiting for the clock to reach its final frequency, the BIOS should then disable a watchdog timer. If the system is not operating then the watchdog times out and generates a reset pulse, the width of which is programmed in the Watchdog Timer Register.
RESET W ATCHDOG TIMER Set WD(0:3) Bits = 0
INITIALIZE W ATCHDOG TIMER Set Frequency Revert Bit Set WD(0:3) = (# of Sec ) x 2
SET SOFTW ARE FSEL Set SW Freq_Sel = 1 Set FS(0:4)
SET DIAL-A-RATIO Select a different divider ratio
SET DIAL-A-FREQUENCY Load M and N Registers Set Pro_Freq_EN = 1
Wait for 6msec For Clock Output to Ramp to Target Frequency
Hang?
N
CLEAR W D Set WD(0:3) Bits = 0
Exit
Y
W ATCHDOG TIMEOUT
Frequency Revert Bit = 0 Set Frequency to FS_HW_Latched
Frequency Revert Bit = 1 Set Frequency to FS_SW
Set SRESET# = 0 for 6 msec
Reset
Figure 1. Watchdog Flowchart Table 10. Group Timing Relationship and Tolerances Offset CPU to SDCLK CPU to AGP CPU to ZCLK CPU to PCI Typical 0 ns Typical 2 ns Typical 2 ns Typical 2 ns Tolerance (or Range) 2 ns 1-4 ns 1-4 ns 1-4 ns Conditions CPU leads CPU leads CPU leads CPU leads Notes 6 6 6 6
Note: 6. See Figure 2 for CPU clock measurement point. SeeFigure 3 for SDCLK, AGP, ZCLK, and PCI Outputs measurement point.
Document #: 38-07373 Rev. *B
Page 10 of 19
CY28370
Table 11. CPU Clock Current Select Function Mult0 0 1 Board Target Trace/Term Z 50 Ohms (not used) 50 Ohms Reference R, Iref - VDD (3*Rr) Rr = 221 1%, Iref = 5.00 mA Rr = 475 1%, Iref = 2.32 mA Output Current IOH = 4*Iref IOH = 6*Iref VOH @ Z 1.0V @ 50 0.7V @ 50
Table 12. Maximum Lumped Capacitive Output Loads Clock PCI(0:5), PCI_F(0:1) AGP(0:1), SDCLK ZCLK 48M_24, 48M Clock REF(0:2) CPU(0:1)T, CPU(0:1)C For Differential CPU Output Signals The following diagram shows lumped test load configurations for the differential Host Clock Outputs.
33
Max. Load 30 30 10 20 30 2
Units pF pF pF pF pF pF
T PCB
49.9 2pF
CPUT
Measurem ent Point
MULTSEL
33
T PCB
49.9 2pF
Measurem ent Point
CPUC IREF
475
Figure 2. 0.7V Configuration
O u tp u t u n d e r T e s t P ro b e 3 .3 V s ig n a ls
tD C
-
Load C ap
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
Tr
Tf
Figure 3. Lumped Load For Single-Ended Output Signals (for AC Parameters Measurement)
Document #: 38-07373 Rev. *B
Page 11 of 19
CY28370
CPU_STP# Clarification The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. CPU_STP# Assertion When CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped after being sampled by two falling CPU clock edges. The final state of the stopped CPU signals is CPU = HIGH and CPU0# = LOW. There is no change to the output drive current values during the stopped state. The CPU is driven HIGH with a current value equal to (Mult 0 "select") x (Iref), and the CPU# signal will not be driven. Due to external pull-down circuitry CPU# will be LOW during this stopped state.
CPU_STP# CPUT CPUC
Figure 4. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no short or stretched clock pulses will be produced when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
CPU_STP# CPUT CPUC CPUT CPUC
Figure 5. CPU_STP# Deassertion Waveform
Document #: 38-07373 Rev. *B
Page 12 of 19
CY28370
PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tsetup) (see Figure 6). The PCI_F (0:2) clocks will not be affected by this pin if their control bits in the SMBus register are set to allow them to be free-running.
t setup
PCI_STP# PCI_F(0:2) 33M PCI(0:6) 33M
Figure 6. PCI_STP# Assertion Waveform PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI(0:6) and stoppable PCI_F(0:2) clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level.
t setup
PCI_STP# PCI_F(0:2) PCI(0:6)
Figure 7. PCI_STP# Deassertion Waveform[7] PD# (Power-down) Clarification The PD# (power-down) pin is used to shut off ALL clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is low, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low "stopped" state. PD#-Assertion (Transition from logic "l" to logic "0") When PD# is sampled LOW by two consecutive rising edges of CPUC clock, all clock outputs (except CPUT) clocks must be held LOW on their next HIGH to LOW transition. CPUT clocks must be hold with CPUT clock pin driven HIGH with a value of 2x Iref and CPUC undriven. Due to the state of internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# Deassertion (transition from logic "0" to logic "l") The power-up latency between PD# rising to a valid logic "1" level and the starting of all clocks is less than 3.0 ms.
Note: 7. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin 34 and the other is SMBus Byte 0 Bit 3. These two inputs are logically ANDed. If either the external pin or the internal SMBus register bit is set low, the stoppable PCI clocks will be stopped in a logic LOW state. Reading SMBus Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW, thereby indicating that the device's stoppable PCI clocks are not running.
Document #: 38-07373 Rev. *B
Page 13 of 19
CY28370
CPU_STP#
CPU(0:1)T
CPU(0:1)C CPU Internal
CPU# Internal
Figure 8. Power-down Assertion/Deassertion Timing Waveforms-Nonbuffered Mode
VID (0:3), SEL (0,1) VTTPWRGD PWRGD
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
Wait for VTT_GD#
Sample Sels State 2 State 3 (Note A)
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 9. VTTPWRGD Timing Diagram[8]
TP W = H RG igh D
S1
S2
VT
D ela y 0 .2 5m S
S a m ple Inpu ts F S (3 :0 )
W a it for 1 .1 46 m s E nab le O u tp uts
V D D A = 2.0V
S0
S3
P ow er O ff
V D D 3.3 = O ff
N orm a l O pe ratio n
Figure 10. Clock Generator Power-up/Run State Diagram
Note: 8. Device is not affected, VTTPWRGD is ignored.
Document #: 38-07373 Rev. *B
Page 14 of 19
CY28370
Maximum Ratings[9]
Input Voltage Relative to VSS:.............................. VSS - 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: ................................-65C to + 150C Operating Temperature:.................................... 0C to +70C Maximum Power Supply:................................................ 3.5V
AC Parameters
100 MHz Parameter Crystal TDC TPeriod VHIGH VLOW Tr / Tf TCCJ Xin Duty Cycle Xin Period Xin High Voltage Xin Low Voltage Xin Rise and Fall Times Xin Cycle to Cycle Jitter Description Min. 47.5 69.841 0.7Vdd 0 Max. 52.5 71.0 Vdd 0.3Vdd 10.0 500 150 150 45 9.8 175 55 10.2 700 20% 125 125 280 45 15.0 5.25 5.05 0.5 430 55 15.3 - - 1.6 175 250 45 0.5 55 1.6 175 250 45 30.0 12.0 12.0 0.5 2.0 500 250 55 45 30.0 12.0 12.0 0.5 2.0 500 250 45 0.5 280 45 15.0 5.25 5.05 0.5 1.6 175 250 55 1.6 175 250 55 45 7.35 175 133 MHz Min. 47.5 69.841 0.7Vdd 0 Max. 52.5 71.0 Vdd 0.3Vdd 10.0 500 150 150 55 7.65 700 20% 125 125 430 55 15.3 ps ps mV % ns ns ns ns ps ps % ns ps ps % nS nS nS nS pS ps Unit % ns Volts Volts ns ps ps ps % ns ps 11,14,17 14, 20, 24 14, 20, 24 14, 20, 24 14, 20, 24 14, 15 15, 23, 24 15, 24 15, 24 15,20, 24 11, 13 11, 13 21 22 11, 12 11, 13 11, 13 11, 13 11, 12 11, 13 11,13 11, 13 10,11,13 21 22 11, 12 11, 13 11, 13 Notes 10,17 10,11,13,1 7
CPU at 0.7V Timing TSKEW Any CPU to CPU Clock Skew TCCJ TDC TPeriod Tr / Tf DeltaTr DeltaTf Vcross AGP TDC TPeriod THIGH TLOW Tr / Tf Tskew Unbuffered TCCJ ZCLK TDC Tr / Tf TSKEW TCCJ PCI TDC TPeriod THIGH TLOW Tr / Tf TSKEW TCCJ CPU Cycle to Cycle Jitter CPU and CPUC Duty Cycle CPU and CPUC Period CPU and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Crossing Point Voltage at 0.7V Swing AGP Duty Cycle AGP Period AGP High Time AGP Low Time AGP Rise and Fall Times Any AGP to Any AGP Clock Skew AGP Cycle to Cycle Jitter ZCLK(0:1) Duty Cycle ZCLK(0:1) Rise and Fall Times Any ZCLK(0:1) to Any ZCLK(0:1) Skew ZCLK(0:1) Cycle to Cycle Jitter PCI_F(0:1) PCI (0:5) Duty Cycle PCI_F(0:1) PCI (0:5) Period PCI_F(0:1) PCI (0:5) High Time PCI_F(0:1) PCI (0:5) Low Time PCI_F(0:1) PCI (0:5) Rise and Fall Times Any PCI Clock to Any PCI Clock Skew PCI_F(0:1) PCI (0:5) Cycle to Cycle Jitter
Document #: 38-07373 Rev. *B
Page 15 of 19
CY28370
AC Parameters (continued)
100 MHz Parameter SDCLK TDC TPeriod THIGH TLOW Tr / Tf TCCJ 48M TDC TPeriod Tr / Tf TCCJ 24M TDC TPeriod Tr / Tf TCCJ REF TDC TPeriod Tr / Tf TCCJ Description SDCLK Duty Cycle SDCLK Period SDCLK High Time SDCLK Low Time SDCLK Rise and Fall Times SDCLK Cycle to Cycle Jitter 48M Duty Cycle 48M Period 48M Rise and Fall Times 48M Cycle to Cycle Jitter 24 MHz Duty Cycle 24 MHz Period 24 MHz Rise and Fall Times 24 MHz Cycle to Cycle Jitter REF Duty Cycle REF Period REF Rise and Fall Times REF Cycle to Cycle Jitter 1.0 1.0 10.0 0 45 69.8413 1.0 45 41.66 1.0 Min. 45 7.4 3.0 2.8 0.4 - 45 20.829 1.0 1.6 250 55 20.834 2.0 350 55 41.67 4.0 500 55 71.0 4.0 1000 10.0 10.0 1.5 10.0 0 1.0 1.0 45 69.8413 1.0 45 41.66 1.0 Max. 55 15 133 MHz Min. 45 7.4 1.87 1.67 0.4 - 45 20.829 1.0 1.6 250 55 20.834 2.0 350 55 41.67 4.0 500 55 71.0 4.0 1000 10.0 10.0 1.5 Max. 55 15 Unit % ns ns ns ns ps % ns ns ps % ns ns ps % ns ns ps ns ns ms ns ns 16 Notes 11, 13 11, 13 21 22 11, 12 11, 12 11, 13 11, 13 11, 12 11, 13 11, 13 11, 13 11, 12 11, 13 11, 13 11, 13 11, 12 11, 13
Enable/Disable and Set-up tpZL, tpZH Output Enable Delay (all outputs) tpLZ, tpZH tstable tss tsh Output Disable Delay (all outputs) All Clock Stabilization from power-up Stopclock Set-up Time Stopclock Hold Time
DC Characteristics
Current Accuracy Conditions Configuration Load Nominal test load for given configuration Nominal test load for given configuration Min. -7% Inom[25] -12% Inom Max. +7% Inom +12% Inom Iout VDD = nominal (3.30V) M0 = 0 or 1 and Rr shown in table Iout VDD = 3.30 5% All combinations of M0 or 1 and Rr shown in table
Document #: 38-07373 Rev. *B
Page 16 of 19
CY28370
Current Accuracy
Notes: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required. 10. This parameter is measured as an average over 1-us duration with a crystal center frequency of 14.318 MHz. 11. All outputs loaded per Table 1. 12. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data sheet). 13. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals (see test and measurement setup section of this data sheet). 14. This measurement is applicable with Spread On or Spread OFF. 15. Measured from VOL = 0.175 to VOH = 0.525V. 16. CPU_STP# and PCI_STP# setup time with respect to any PCI_F clock to guarantee that the effected clock will stop or start at the next PCI_F clock's rising edge. 17. When Xin is driven from an external clock source. 18. When Crystal meets minimum 40 ohm device series resistance specification. 19. This is required for the duty cycle on the REF clock out to be as specified. The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within data sheet specifications. 20. Measured at crossing point (Vx) or where subtraction of CLK-CLK# crosses 0V. 21. THIGH is measured at 2.4V for all non host outputs. 22. TLOW is measured at 0.4V for all non host outputs. 23. Determined as a fraction of 2*(Trise-Tfall)/ (Trise+Tfall). 24. For CPU load. See Figure 2. 25. Inom refers to the expected current based on the configuration of the device.
DC Component Parameters (VDD = 3.3V 5%, TA = 0C to 70C Parameter Idd3.3V Ipd3.3V Cin Cout Lpin Cxtal
Notes:
Description Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Power-down Supply Current PD# Asserted
Conditions All frequencies at maximum values[26]
Min.
Typ.
Max. 300 Note 27 5 6 7
Unit mA mA pF pF nH pF
Measured from the Xin or Xout pin to Ground
30
36
42
Ordering Information
Part Number CY28370OC CY28370OCT Package Type 48-pin Shrunk Small Outline Package (SSOP) 48-pin Shrunk Small Outline Package (SSOP)-Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C
Document #: 38-07373 Rev. *B
Page 17 of 19
CY28370
Package Drawing and Dimensions
48-lead Shrunk Small Outline Package O48
51-85061-C
Pentium 4 is a registered trademark of Intel Corporation. Dial-a-Frequency, Dial-a-Ratio, and Dial-a-dB are trademarks of Cypress Semiconductor. Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All product and company names mentioned in this document are the trademarks of their respective holders.
Notes: 26. All outputs loaded as per maximum capacitive load table. 27. Absolute value = (programmed CPU Iref) +10 mA.
Document #: 38-07373 Rev. *B
Page 18 of 19
(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY28370
Document History Page
Document Title: CY28370 High-performance SiS645/650/660 Pentium 4 Clock Synthesizer Document Number: 38-07373 REV. ** *A *B ECN NO. 112789 118704 122913 Issue Date 05/07/02 10/15/02 12/27/02 Orig. of Change DMG RGL RBI New Data Sheet Add SiS660 to the current title Add power up requirements to maximum ratings information. Description of Change
Document #: 38-07373 Rev. *B
Page 19 of 19

▲Up To Search▲

Price & Availability of CY28370

	To Download CY28370 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .