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DK4_XA USER MANUAL
DK4000-XA Development Kit For PSD4000 Series of Flash PSDs
CONTENTS
s
(Please see next pages)
January 2002
1/3
DK4000-XA DEVELOPMENT KIT For PSD4000 Series of Flash PSDs
Rev 0.98
Contents:
PSDsoft Express - Point and Click Windows based Development Software DK4000 Eval Board with PSD4135G2 FlashLINK JTAG In-System Programmer (ISP) Ribbon and "Flying Lead" JTAG cables for FlashLINK Serial UART cable CDROM - Data Book, Software and Videos 110V or 220V Power supply
DK4000 - XA DEVELOPMENT KIT ................................................................................... 3
Introduction ...................................................................................................................................3
A couple of definitions:....................................................................................................................................3 Hardware ........................................................................................................................................................3 Software..........................................................................................................................................................3
Detailed Descriptions....................................................................................................................5 Other board features.....................................................................................................................5
Step-By-Step Instructions for ISP Programming: ...........................................................................................6
Using DK4000 as a Development Platform for P51XA users: ....................................................8
Concept...........................................................................................................................................................8 Downloading to the Development Board ........................................................................................................8 JTAG - ISP......................................................................................................................................................8
P51XA Design Overview ...............................................................................................................9
Memory Swapping in the PSD......................................................................................................................10 What really happens .....................................................................................................................................12 Creating your own IAP code bundle .............................................................................................................12
References...................................................................................................................................12
Application notes...........................................................................................................................................12
APPENDIX ........................................................................................................................ 13
Appendix A - Jumper configuration on DK4000........................................................................14 Appendix B Software functional description ...........................................................................15 Appendix C Development Board Schematic and parts list .....................................................16
Main Schematic ............................................................................................................................................16 Power Supply Schematic ..............................................................................................................................17 XA Daughter Board Schematic.....................................................................................................................18 DK4000 Parts List .........................................................................................................................................19
Appendix D: FlashLINK Information ..........................................................................................21
Features ........................................................................................................................................................21 Overview .......................................................................................................................................................21 Operating considerations ..............................................................................................................................21 FlashLINK pinouts.........................................................................................................................................23 Loop back connector schematic ...................................................................................................................26
Appendix E Results codes and debug tree for htestXA.obj ...................................................27
Results codes............................................................................................................................................27 Success Code...............................................................................................................................................27 Debug tree.................................................................................................................................................27
Appendix F: Board errata ...........................................................................................................28
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DK4000 - XA Development Kit
Introduction
Congratulations on purchasing ST's DK4000 Development kit. The DK4000 (110V or 220 Volt version) is a low cost kit for evaluating the PSD4000 series of FLASH Programmable System Devices called PSDs. The DK4000 kit is extremely versatile, and can be used in several different modes. For example, it can be used to demonstrate the PSD4000's capability of JTAG In-System Programmability (ISP). Also, once initial code is resident in the PSD, the program code can be updated while the MCU is running, called InApplication Programming (IAP). Philips P51XA family users can utilize the DK4000 as an evaluation platform for code development. The DK4000 - XA Development Board is specific to the Philips P51XA microcontroller family. However, other proliferation boards are be available. Check the website at www.st.com/psm for availability.
A couple of definitions:
In-System Programming (ISP)- A JTAG interface (IEEE 1149.1 compliant) is included on the PSD enabling the entire device to be rapidly programmed while soldered to the circuit board (Main FLASH, Secondary Boot FLASH, the PLD and all configuration areas). This requires no MCU participation, so the PSD can be programmed or reprogrammed anytime, anywhere, even while completely blank. The MCU is not required for ISP. In-Application Programming (IAP) - Since two independent FLASH memory arrays are included in the PSD, the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (a few examples are CAN, Ethernet, UART, J1850) using this unique architecture. For IAP, all code is updated through the MCU.
Hardware
* * * * * PSD4135G2 - 4Mb Main FLASH(512kx8), 256Kb Boot FLASH(32kx8), 64Kb SRAM(8kx8). See website for data sheet www.waferscale.com . Eval/Demo Board with P51XA or other MCU, LCD Display, JTAG and UART ports for ISP/IAP FlashLINK JTAG ISP Programmer (uses PC's parallel port) Straight thru serial cable (Male-Female) Power Supply
Software
To ensure you have the latest versions, check the website often. 1. PSDsoft Express - Point and Click Windows programming development software. This will install to its own directory. * MCU Selection by manufacturer and part number * Graphical definition of pin functions * Easy creation of memory map * JTAG ISP Programming. 2. The distribution disk contains the following directories, each with executable code. For convenience, copy each distribution disk directory to your machine under ...\PSDexpress\dk4kp-XA\... . For example, ...PSDexpress\dk4kp-XA\hwtest-XA\, ...PSDexpress\ dk4kp-XA\demo1-XA\, etc. * Hwtest-XA. Validates DK4000 board hardware including serial port * Demo1-XA. Simple program for IAP demo, displays "have no fear..." Each directory contains the following * *.zip for the psd * *.zip for the C level source code * readme.txt file containing late breaking information * *.obj file suitable for direct PSD programming.
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Since the *.obj file is the natural format needed by PSDsoft for direct programming of the PSD, no unzipping is necessary to change the executing code in the development board. The hardware test (hwtest_xa.obj) is resident on the development board. A detailed description of each software bundle is included in the appendix. The following table is a specific listing of the files and their locations on the distribution disk. Directory Hwtest-XA Files XAp_hwt_10s_.zip XAc_hwt_10s_.zip Readme.txt htestXA.obj Demo1-XA UXAdemop10_.zip UXAdemoc10_.zip Readme.txt demo_xa.obj Description Hardware test Contains all PSD source files Contains all C level code files (a) Late breaking information Duplicate obj file (also in PSD zip file above) "no need to fear..." Contains all PSD source files Contains all C level code files (a) Late breaking information Duplicate obj file (also in PSD file above)
Notes a. TASKING C for XA 3.0r5 or later
*** Notice: An additional code bundle will be posted on the web in the future to cover the IAP functionality. Please go to www.st.com/psm, and select "Development Tools" and scroll down to DK4000 where the latest software and manual can then be downloaded.
4
Detailed Descriptions
Figure 1 DK4000-XA Development Board The following features are included in the development board and shown graphically in the above figure. * Display - A two line by 16 character LCD display. * Power switch * UART Serial Port(female) - Connected to MCU serial port; used for In-Application Programming (IAP) * Philips P51XA or other MCU * PSD4000 software - The PSD4000 is programmed with HWTest demonstration code. User can program alternative programs via JTAG ISP. * JTAG programming Port - Used in conjunction with FlashLINK programmer for ISP. * Reset Button - For resetting the MCU and PSD.
Other board features
Other features of the DK4000 board are listed below. These elements are unpopulated to provide lowest cost to the user. * * * Provision for chaining JTAG connector is provided in P2 and JP2. Provision for off board expansion is provided by board connectors suitable for 0.025 square posts Provision for 9v battery input is provided near power connector(solder pads only).
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Step-By-Step Instructions for ISP Programming:
a) Install PSDsoft Express on your PC running Windows 95/98/NT/2000. Check web for latest version. b) Plug the FlashLINK Programmer into your PC's parallel port and plug in the ribbon cable to the JTAG port on the eval board. For help, see the Appendix C of the FlashLINK manual. c) Plug in power supply and turn on power. An LCD contrast control is provided as R11. The typical setting is near the counterclockwise stop. d) Run PSDsoft Express. Here is the initial screen if no project was open in a prior session.
Figure 2 Opening screen upon PSDsoft Express invocation Use cancel at this point since all we need to do is program the PSD with an existing demonstration file (*.obj) and there is no need to create a new project. Later, in the "Using the DK4000 as a development platform", a further tutorial is given on using PSDsoft Express with the Eval Board for development.
Figure 3 Invocation reminder screen e) In the Design Flow (shown below), click on the ST JTAG/ISP button. Bottom row of boxes left side.
Figure 4 PSDsoft Express flow
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The following screen appears inquiring if it's desired to program a single device or multiple devices in the JTAG chain. Select "Only one" and OK.
Figure 5 JTAG-ISP Operations dialog Clicking OK brings up the JTAG Operations - Single device dialog shown in the following figure.
Figure 6 PSDsoft Express, JTAG Operations dialog f) In Step 1, browse to find the *.obj file shown in the above figure g) In "select device" box, choose the PSD4000 device you have installed on the board h) In step 3, select the operation of "Program". Click execute. i) Observe in the lower pane the JTAG activities that occur while programming your device. j) Watch the display. When the download has completed, as indicated in the log window, push the reset button on the Development Board. The displays below will sequence one time and then operation will stop.
No need to fear Easy FLASH is here *** COMP L E T E ** *
Figure 7 Eval Board Displays for Demo1 (demo_xa.obj) 7
If you cycle power to the board, you will see that the display will resequence, confirming that the program and all configuration information are stored in the PSD's non-volatile FLASH Memory. k) For better understanding of the program you may want to examine the following references: 1. System memory map in the "P51XA Design Overview" section of this document . 2. PSDsoft Express project (demo_xa.ini) 3. The file source code (included) to see how the executing code was configured
*** Notice: An additional code bundle will be posted on the web in the future to cover the IAP functionality. Please go to www.st.com/psm, and select "Development Tools" and scroll down to DK4000 where the latest software and manual can then be downloaded.
Using DK4000 as a Development Platform for P51XA users:
Concept
The ST * * * * * DK4000 Development Board provides the following capabilities Demonstrate design concepts early, optimizing "time to market" Jump start user application with proven framework (hardware and software) Substitute for user target system until target prototypes are available Gives instant platform for testing ISP and IAP demonstration Allows programming the PSD using included FlashLINK cable
Downloading to the Development Board
Executable code can be downloaded to the Development Board two different ways: via the JTAG (ISP) or via the UART (IAP). This manual only describes the ISP capabilities at this time. The IAP capabilities will be supported in the future using PSDload available on the website.
JTAG - ISP
The PSD4000 series JTAG interface provides the capability of programming all memory areas within the PSD ( PLD, configuration, main and secondary FLASH memories). This interface can also be used to program a completely blank component as JTAG is enabled as the default PSD state. See Application Note 54 (AN054) for further description of the JTAG interface on our CD or our website. The LCD will be non operational during JTAG - ISP since the MCU is not operating. During this interval, the PSD is not connected to the MCU bus. To restrain the MCU during this interval, the JTAG interface contains a signal, ( RST ) that is connected to the MCU reset pin. ST provides a FlashLINK programmer to facilitate the JTAG programming operation. The FlashLINK programmer connects the PC parallel port to the Eval Board JTAG header and is driven by PSDsoft Express, the PSD development tool.
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P51XA Design Overview
The following figure depicts how the memory is allocated in this project for the htestXA.obj. The default configuration is 16 bit multiplexed for the following system resources; * * * * PSD code memory (flash and boot areas) PSD SRAM LCD CSIOP space (PSD registers).
P51XA Program Space P51XA Data Space
8FF F F
fs0
64K bytes P S D M ain Flash
8FF F F 64K bytes 80000 7FF F F 64K bytes 70000 6FF F F 64K bytes 60000 5FF F F 64K bytes 50000 4FF F F 64K bytes 40000 3FF F F 64K bytes 30000 2FF F F 64K bytes 20000 1FF F F 64K bytes 10000 0A 000 08000 07000 06000 00400 00000 -
fs7
64K bytes P S D M ain Flash
fs6
64K bytes P S D M ain Flash
fs5
64K bytes P S D M ain Flash nothing m apped
fs4
nothing m apped 64K bytes P S D M ain Flash
fs3
64K bytes P S D M ain Flash
fs2
64K bytes P S D M ain Flash
fs1
64K bytes P S D M ain Flash nothing m apped
06000 04000 02000 00000
-
08000 07F F F 05F F F 03F F F 01F F F
csboot3, csboot2, csboot1, csboot0,
8K B P SD 2nd F la sh 8K B P SD 2nd F la sh 8K B P SD 2nd F la sh 8K B P SD 2nd F la sh
rs0, 8K bytes P S D S R A M csiop, P S D cntl regs lcd_e, ext LC D chip sel nothing m apped P 51XA -G 3 R egs/S R A M
09F F F 070FF 06001 05F F F 003FF
64K bytes
Figure 8 Memory Map of DK4000/P51XA Board
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Memory Swapping in the PSD
For this test (htestXA.obj), the dip switch should be in the following position . As a component of this test, a copy of the executing code that resides in csboot0/1 is made. The destination of this copy is the main flash area FS0, as shown in the figure below. After the copy operation, the following map applies.
P51XA Program Space P51XA D ata Space
8F FF F
fs0
C opy of Boot area
M ain Flash
8F FF F 64K bytes 80000 7F FF F 64K bytes 70000 6F FF F 64K bytes 60000 5F FF F 64K bytes 50000 4F FF F 64K bytes 40000 3F FF F 64K bytes 30000 2F FF F 64K bytes 20000 1F FF F 64K bytes 10000 0A 000 08000 07000 06000 00400 00000 -
fs7
64K bytes P S D M ain Flash
fs6
64K bytes P S D M ain Flash
fs5
64K bytes P S D M ain Flash nothing m apped
fs4
nothing m apped 64K bytes P S D M ain Flash
fs3
64K bytes P S D M ain Flash
fs2
64K bytes P S D M ain Flash
fs1
64K bytes P S D M ain Flash nothing m apped
06000 04000 02000 00000
-
08000 07F FF 05F FF 03F FF 01F FF
csboot3, csboot2, csboot1, csboot0,
8KB PSD 2nd Flash 8KB PSD 2nd Flash 8KB PSD 2nd Flash 8KB PSD 2nd Flash
rs0, 8K bytes P S D S R A M csiop, P S D cntl regs lcd_e, ext LC D chip sel nothing m apped P 51XA -G 3 R egs /S R A M
09F FF 070FF 06001 05F FF 003FF
64K bytes
Figure 9 Memory map after running of htestXA.obj For normal boot, the second LCD screen shows "executing from, BOOT area". The message exists in a fixed location in the code and is read from this location and copied to the LCD at boot up. When the code copy is performed, a different message is inserted into the same fixed location based on the destination of the copy (as shown in FS0). When this version of the code is executed, the message is displayed "executing from MAIN FLASH". This method yields a single unambiguous confirmation of the execution source, which is very convenient for demonstrating memory swapping operations.
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Now let's boot from FS0 to demonstrate the swapping capability of the PSD. Place the dip switch in the and press the reset button. You should see the execution source annunciated to following position the display "booting from MAIN FLASH". The following memory map applies.
P51XA Program Space
8F F F F 64K by tes 80000 7F F F F 64K by tes 70000 6F F F F 64K by tes 60000 5F F F F 64K by tes 50000 4F F F F 64K by tes 40000 3F F F F 64K by tes 30000 2F F F F 64K by tes 20000 1F F F F 64K by tes 10000 0F F F F
nothing m apped csboot3, csboot2, csboot1, csboot0,
8KB PSD 2nd F lash 8KB PSD 2nd F lash 8KB PSD 2nd F lash 8KB PSD 2nd F lash
P51XA D ata Space
8F F F F 86000 84000 82000 80000 87FF F 85FF F 83FF F 81FF F
fs7
64K bytes P S D M ain Flas h
fs6
64K bytes P S D M ain Flas h
V M re g = 0 x0 C
fs5
64K bytes P S D M ain Flas h
fs4
64K bytes P S D M ain Flas h nothing m apped
fs3
64K bytes P S D M ain Flas h
fs2
64K bytes P S D M ain Flas h
fs1
64K bytes P S D M ain Flas h
10000 0A 000 08000 07000 06000 00400 00000 -
64K by tes
fs0
C opy of B oot area
M ain Flas h
00000
rs0, 8K bytes P S D S R A M csiop, P S D c ntl regs lcd_e, ext LC D chip sel nothing m apped P 51XA -G 3 R egs/S R A M
09FF F 070F F 06001 05FF F 003F F
Figure 10 Memory map for alternate memory boot The memory movement within the MCU memory map is accomplished via the logic contained in the PLD equations in the PSD. Each segment that moves must have dual ranged defined in these equations. The selection is made based on a single logic bit (exe_src_a) that resides in the PSD PAGE register. Following are the equations for the system. These can bee seen in the PSDsoft Express project included with the kit. Note that "#" indicates a logical OR and "&" indicates a logical AND. Csboot0 = ( (0x0 - 0x01FFF) & exe_src_a )#( (80000 - 81FFF) & exe_src_a ) Csboot1 = ( (0x02000 - 0x03FFF) & exe_src_a ) #( (82000 - 83FFF) & exe_src_a ) Fs0 = ( (0x80000 - 0x8FFFF) & exe_src_a ) # ( ( 0x0 - 0x03FFF) & exe_src ) Note that the logic variable (bit) controlling the actual location of the memory is "exe_src_a". When this bit is zero (0), the memory segments are as shown in Figure 9. When exe_src_a is one (1), FS0 appears in the execution location as shown in Figure 10, and the csboot areas are not in the map at all. The physical location of this logic bit, exe_src_a, is in the bit6 position of the PAGE register. Actually this bit can be anywhere, the only important element is that it is contained in the PLD equations, as shown above, and accessible by the MCU. Control of this bit is via a board mounted dip switch.
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The power up sequence is as follows: a. Execute C startup b. Read the dip switch c. Modify the PSD PAGE and VM registers to obtain the correct memory map. Once the PAGE and VM register write operations have completed, the next instruction is fetched from the new memory location (FS0). This same sequence of events occurs every time power is applied to the board. Since the PAGE register is always 00h at power up, the software always executes steps a) and b) from the boot area. Then, based on the DIP switch selection, the code will either stay in the boot area or jump to the main FLASH area.
What really happens
There is a subtlety involved in the transfer of execution described above. This subtlety is due to the fact that the MCU really doesn't know the source of the instruction bytes; boot area or main FLASH. All the MCU knows is that valid instructions on valid address boundaries are presented on the bus when the MCU needs them. Then the MCU executes the instruction and generates the next address. The key element involved is the generation of the address by the MCU. To understand this critical transfer of control, let's examine the instruction-by-instruction transition from one memory to the other. After the reset signal is deasserted, the MCU is executing from the csboot area normally. This continues until the exe_src_a bit is written, moving FS0 into the execution location (0x00x3FFF). At this same time, csboot area is, for all practical purposes, gone from the system memory map. At this point, the MCU is generating the next address from the instruction received from the csboot area. However, the next instruction will come from the FS0 area. This next instruction fetch must be appropriate to maintain the program flow. That is, the next instruction must be received by the MCU on an instruction boundary and be appropriate for the program flow. In addition, any issues with the stack and stack pointer must be resolved so program flow can continue (subroutine return addresses, temporary variables, etc.). Pipelining operations can result in execution from the pipeline instead of the new memory, but the pipeline will continue to be filled from the new memory. The method we've used to ensure correct operation is to place identical code at identical locations in both applications through the point of the swap. After the point of the swap, the code bundles can diverge without problems. While this result is inherently ensured in a code copy scenario like htestXA.obj, it's not so automatic when the applications are different such as those existing in a true IAP scenario.
Creating your own IAP code bundle
A few easy steps can ensure that program flow for this critical area is guaranteed to occur properly. These steps involve the absolute location of certain modules within the base application and the new IAP application. Locating these modules is accomplished using linker controls. With this framework, booting from one application to another is EASY.
References
IEEE Std 1149.1-1990 IEEE Test Access Port and Boundary Scan Architecture Flashlink User Manual (included in the Appendix of this document)
Application notes
AN054 JTAG Information AN069 - Design Guide, PSDsoft Express and PSD4135G2 AN070 Design Guide, P51XA
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Appendix
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Appendix A - Jumper configuration on DK4000
Jumper Description Default position (shown by dotted line) No measure No chain Internal power supply None (no jumper) XA (non default position) Board position Upper center Upper right Lower right Lower right Lower center
JP1 JP2 JP3 JP4 JP10 (rev C only)
Measure PSD current JTAG chaining Internal / external power supply 9v battery connector Display control
JT A G , P 1
PSD I Meas
se ria l p o rt
JP1
N O C H A IN
JP 2
PSD
M C U are a P ow e r S u p p ly In t E xt
JP10 JP 3 XA
off
NORM
LCD C o n tra st
b a tte ry co n n e ctio n
d 7 -1 4 L C D D isp la y
R e se t
P ow e r o n in d ica to r
Figure 11 Assembly Drawing with default jumper positions
on
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Appendix B Software functional description
1. htestXA This code exercises all components of the development board: the display, PSD memory and chip selects, as well as the UART channel (single character only on receive and transmit). This confirms functionality and is used as a production test. The following list describes the viewable LCD screens. * * * * * * Invocation banner, software version Display execution source. (boot area or main flash) Motherboard LED test PSD RAM test Code Copy. Executing boot code is copied to main flash block FS0 (BOOT-> FLASH) Displays flash ID and does erase of FS0 prior to the copy operation. UART test (waiting for host to send "0", dev board reply is a "1", baud rate is19200 with 8 data bits, no parity and one stop bit)
After this code has run one time, a copy of the executing code exists in the FLASH area. The system can run from this code copy by placing the dip switch in the appropriate configuration as described in the "Memory Swapping in the PSD" section of this document. 2. Demo This is a simple program that displays the following text on the LCD display. No Need to fear, EASYflash is here . The intent is to show a minimal level of functionality. No UART support is provided.
An additional code bundle will be posted on the web in the future to cover the IAP functionality. .
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Appendix C Development Board Schematic and parts list
Main Schematic
Note. In the XA design, the C167 component is not populated on the main board shown below. The daughter board supplies the MC U.
A[23..16] VCC 3 1 xx_MHz Y2 2 22pf C 1 Y1 4 10M R1 2 CNTL0(_WR) xx_MHz 0.01 C 3 8 3 CNTL2(_BHE) 1 VCC CNTL1(_RD) VCC 1 1 JP1 2 3 3 2 C18 0.1 C19 1 DS1 VCC A[7..0] A[15..8] ADIO[15..0] ADIO[15..0] A[23..16]
22pf C 2 VCC VCC V+ V-
Icc meas
82 72 56 46 17
C1+ C1C2+ C2-
9 29 69
U1 3 4 C4 137 5 0.1 P3.0 6 5 P3.1 6 6 P3.2 6 7 68 P3.3 69 P3.4 70 P3.5 73 P3.6 74 P3.7 75 P3.8 76 P3.9 TXD0 P3.10 77 P 3 . 1 17 8 RXD0 79 P3.12 80 P3.13 81 P3.15 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 P6.[7..0] P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 37 84 3 VCC 3 3 XTAL2 TXD0 RXD0 138 XTAL1
U2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 100 101 102 103 104 105 106 107 108 111 112 113 114 115 116 117 85 86 87 88 89 90 91 92 95 96 97 98 99 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 140 141 142 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 A16 A17 A18 A19 A20 A21 A22 A23 RD WR/WRL READY EA P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0 P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 RESET NMI VCC ADIO0 3 ADIO1 4 ADIO2 5 ADIO3 6 ADIO4 7 ADIO5 10 ADIO6 11 ADIO7 12 ADIO8 13 ADIO9 14 ADIO10 15 ADIO11 16 ADIO12 17 ADIO13 18 ADIO14 19 ADIO15 20 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
Vcc Vcc Vcc Vcc Vcc
Vcc Vcc Vcc Vcc Vcc
Vcc_1 Vcc_1 Vcc_1
C7 2 0.1 C6 0.1 C5 0.1 14 7 13 8 T1out T2out R1in R2in T1in T2in R1out R2out 11 10 12 9 TXD0 RXD0 R5 R4 100 100 10k 6
J4
R2 100 1 6 R S - 2 32 2 7 3 R3 8 4 9 5
R57 100 P3.[13..0]
P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TXD0 P3.11/RXD0 P3.12/ BHE/ WRH P3.13/SCLK P3.15/CLKOUT
PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
Vcc A0 PB0 PB1 4 6 5 RS E R/W V0 GND
2 3 1
3
16
1
144 136 126 109 93
U3
C3 0.1
U5 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 PB2 PB3 12 11 10 9 8 7 6 5 27 26 23 25 4 28 3 31 2 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 CS1 D0 D1 D2 D3 D4 D5 D6 D7 13 14 15 17 18 19 20 21 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
R11 10K 2
AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 P4.0/A16 A17 A18 A19 A20 A21 A22 P4.7/A23 RD WR/ WRL READY ALE EA P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0 P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0
100pf C40
CNTL0(_WR) 59 CNTL1(_RD) 60 CNTL0( WR) 40 C CNTL2(_BHE) NTL1( RD) CNTL2( BHE) PD0 PD1 PD2 PD3 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 79 80 1 2 71 72 73 74 75 76 77 78 PD0(ALE) PD1(CLKIN) PD2( CSI) PD3( WRH) PE0(TMS) PE1(TCK/ST) PE2(TDI) PE3(TDO) PE4(TSTAT/RDY) PE5(TERR) PE6(VSTBY) PE7(VBATON) RESET
HC16201-A A[7..0]
D7 D6 D5 D4 D3 D2 D1 D0
14 13 12 11 10 9 8 7
ADIO7 ADIO6 ADIO5 ADIO4 ADIO3 ADIO2 ADIO1 ADIO0
1
VCC CS2 OE WE 30 24 29 CNTL1(_RD) CNTL0(_WR)
PB4 22
MS628128 A[15..8]
DB9F
VCC MR U4 0805 MR RESET 3 2 MR RESET P6.[7..0] S1 MAX6315 RESET P5.[15..0] R6 P5.[15..0]
C167CR P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 P5.10/AN10/T6UED P5.11/AN11/T5UED P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4UED P5.15/AN15/T2UED
P6.0/ P6.1/ P6.2/ P6.3/ P6.4/ P6.5/ P6.6/ P6.7/ CS0 CS1 CS2 CS3 CS4 HOLD HLDA BREQ
PA[7..0] PB[7..0]
PA[7..0]
R10 R9 A16 A17 A18 A19 A20 A21 A22 A23
VCC R8 R7 10K typ
PB0 PB0
RESET 39
PSD42xxG
GND GND GND GND GND
PB7 PB6 PB5 PB4 1 2 3 4
P9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P7.[7..0] P8.[7..0] P8.[7..0] P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 P7.0 P7.1 P7.2 P7.3 P7.4 P7.5 P7.6 P7.7 Vref Agnd GND VCC
8 30 49 50 70
left side
P3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 GND VCC
P4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 GND VCC
P5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO Vref OWE Vss Vss Vss Vss Vss
GND PE[7..0] PE[7..0] P1L[7..0] P2.[15..0] 8 7 6 5 S2
P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN RSTIN RSTOUT NMI
P6
VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
R54 10k P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7
143 139 127 110 94
83 71 55 45 18
38
2 emulator 1
1
2
R55 Agnd 10k NMI P6.[7..0]
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 GND VCC
P7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0 P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0 GND VCC
P8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A23 A22 A21 A20 A19 A18 A17 A16 PD0 PD1 PD2 PD3 CNTL0(_WR) CNTL1(_RD) CNTL2(_BHE) RESET PE6 PE7 GND VCC
P10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 GND VCC
P11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
ADIO15 ADIO14 ADIO13 ADIO12 ADIO11 ADIO10 ADIO9 ADIO8 ADIO7 ADIO6 ADIO5 ADIO4 ADIO3 ADIO2 ADIO1 ADIO0 GND VCC
P12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A14 A15 A12 A13 A10 A11 A8 A9 A7 A6 A5 A4 A3 A2 A1 A0 GND VCC
PD[3..0] PD[3..0] C8 C9
0.1
0.1
3
2
Agnd
Vss Vss Vss Vss Vss
Title DK4000 Development Board, 167CR Size B Date: Document Number DK4000 Tuesday, May 16, 2000 Sheet 1 of 2 Rev B
1
2
JP8 1
JP9
GND VCC
16
Power Supply Schematic
A[15..8] 1 2 pads for 9V BATTERY RESET CNTL2(_BHE) CNTL1(_RD) CNTL0(_WR) PD[3..0] D1 D3 D6 1N4148 1N4004 D4 POWER 1 S3 + 10k C10 1 10k U6 MIC5237-5.0 2 R13 C11 0.1 uF 1 IN TAB OUT GND 3 1 2 JP3 C12 1 uF INTERNAL POWER SUPPLY 1 2 3 1 3 C13 0.1 uF EXTERNAL POWER SUPPLY PD[3..0] P6.[7..0] ADIO[15..0] ADIO[15..0] TP_PS1 VCC P6.[7..0] P8.[7..0] A[15..8] A[7..0] A[7..0] 1 2 D2
P8.[7..0]
1N4004
P13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
J7
1 2 9-12 VDC REGULATED SOURCE + 1N4004 1N4004 D5
R12
C14 0.1 uF
C15 0.01 uF
C16 0.01 uF
C17 0.01 uF
15V GND
VCC
TP_GND
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 GND VCC C20
P14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RESET CNTL2(_BHE) CNTL1(__RD) CNTL0(__WR) PD3 PD2 PD1 PD0 A23 A22 A21 A20 A19 A18 A17 A16 TXD0 RXD0 GND VCC C22 TXD0 RXD0
P15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND VCC C24
P16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P8.0 P8.1 P8.2 P8.3 P8.4 P8.5 P8.6 P8.7 GND VCC C26
4
2
C36 0.1 uF
C37 0.1 uF
C28 0.1 uF
C29 0.1 uF
C30 0.1 uF
C31 0.1 uF
C32 0.1 uF
C33 0.1 uF
C34 0.1 uF
C35
ADIO15 R49
0.1 uF A D I O 1 4 R50 ADIO13 10k
1 R48 10k 10k PE[7..0] PE[7..0] PE3 TDO VCC R14 R15 R16 R17 R18 R19 R20 R21 VCC 2 JP7 1 10K R22 10K R23 VCC 3 3 3
0.01 uF + + C21 1 0.01 uF C23 1
A[23..16] A[23..16] 0.01 uF + C25 1 P5.[15..0] P5.[15..0] 0.01 uF + C27 1
2 JP5 1
2 JP6 1
167CR Clock Options VCC P2 JEN TRST GND STAT D15 LED Power On P5.2 10k P5.3 10k PA0 PA1 PA2 PA3 VCC PA4 PA5 D11 LED D12 LED D13 LED D14 LED R28 PA4 820 R29 PA5 820 R30 PA6 820 Title DK4000 Dev board, 167CR PA7 820 PA[7..0] Size B Date: Document Number DK4000 Tuesday, May 16, 2000 Sheet 2 of 2 Rev B R31 PA6 D7 D8 D9 LED LED LED R24 PA0 820 R25 PA1 820 R26 PA2 820 D10 LED R27 PA3 820 P5.7 10k R39 P5.6 10k R38 P5.15 10k R47 P5.5 10k R37 P5.14 10k R56 P5.4 10k R36 P5.13 10k R45 P5.12 10k R44 R35 R34 P5.11 10k R43 R53 820 P5.0 10k P5.1 10k R33 P5.10 10k R42 R32 P5.9 10k R41 P5.8 10k R40
10K typ
TDI_2 P1
PE2 PE4 PE0 PE1 PE5
TDI TSTAT TMS TCK TERR
JEN TRST GND STAT TDI PE3/ TSTAT VCC RST PE0/TMS GND TCK GND TDO_1 PE4/ TERR
1 2 3 4 5 6 7 8 9 10 11 12 13 14
NO CHAIN 1 3 5 JP2
TDO 2 4 6 TMS TSTAT
TERR
1 2 3 4 TDI_2 5 PE3/ TSTAT 6 VCC 7 RST 8 PE0/TMS 9 GND 10 TCK 11 GND 12 TDO_2 PE4/ TERR 13 14 CON14 JTAG OUT
CON14 JTAG IN
STAT NMI
MR MR JEN PB0 PA[7..0] PA[7..0] PA7
17
XA Daughter Board Schematic
ADIO[15..0]
J13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Size A
Document Number XA Daughter Board Schematic, DK4000 Friday, August 25, 2000 Sheet 1 of 1
Rev B
Vdd
Vdd
1 GND VCC
C2 0.1 uF
3 1 xx_MHz
Y2
2
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
J15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
+
C1
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND VCC
Date:
+
C3 1 C4 0.1 uF
+
C11 1 C12 0.1 uF
23
2
U1 xx_MHz 21 3 1 20 XTAL1
22pf C9
Y1 4 10M R1
44
22pf C10
XTAL2
P0.0/A4D0 P0.0/A5D1 P0.2/A6D2 P0.3/A7D3 P0.4/A8D4 P0.5/A9D5 P0.6/A10D6 P0.7/A11D7 P2.0/A12D8 P2.1/A13D9 P2.2/A14D10 P2.3/A15D11 P2.4/A16D12 P2.5/A17D13 P2.6/A18D14 P2.7/A19D15
43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
XA-G3
A0
J14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RESET CNTL2(_PSEN) CNTL1(_RD) CNTL0(_WR) PD3 PD2 PD1 PD0 A23 A22 A21 A20 A19 A18 A17 A16 TXD0 RXD0 VCC
J16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RXD1 TXD1 T2 T2EX INT0 INT1 T0
PD3 A1 A2 A3 2 3 4 5 6 7 8 9 11 13 14 15 16 17 P1.0/A0/ WRH P1.1/A1 P1.2/A2 P1.3/A3 P1.4/RxD1 P1.5/TxD1 P1.6/T2 P1.7/T2EX P3.0/RxD0 P3.1/TxD0 P3.2/ INT0 P3.3/ INT1 P3.4/T0 P3.5/T1/BUSW
EA/Vpp/WAIT
35
INT0 INT1 C7 1 GND VCC 10K R2 10K R3 10K R4 + C8 0.1 T0
PSEN ALE
32 33
P3.6/ WRL 10 RST Vss Vss P3.7/ RD
18 19
+
C5 1 C6 0.1 uF PD[3..0] PD0 A[23..16]
VCC
1
22
18
DK4000 Parts List
eval board parts list DK4000 ref des QTY PER 1 ds1 1 GENERIC P/N pcbevm0002 dis101-0001 DESCRIPTION asian 21insq, us 25 in sq@ display hantronix hdm16216h-b VENDOR 5/17/2000 tmw
PART NUMBER
y1 u1 u2
1 1 1
y101-0002 umcu0002
crystal, 11.059MHZ microcontroller PSD42xxG psd socket 232 driver max 6315 regulator diode zener diode, 15v signal diode led, t5(t1.75) 22 pf caps, cer cap, 1uf tant cap, 1uf cer, 1206 0.1 cap, smt, cer
digikey Phillips ST Yamiachi analog devices maxim, 5v micrel
CTX078-ND P51XA PSD42xxG IC149-080-030-S5 adm202jrn max6315leuk mic5237-5.0bt s1ab mmsz5254bt1 fdLL4148 SLX-LX5093ID grm40c0g22050ad grm42-6y5v105z016ad 1206zc105mat2a grm40z5u104z016ad
u3 u4 u6 d1-4 d5 d6 d7-15 c1-2 c10,c21,c23,c25 c12,c19 c3-9,c11, c1318,c20,c22, c24
1 1 1 4 1 1 9 2 4 2 18
u232-0001 usup0002 ureg-0001 cr101-0001 vr101-0001 cr101-0002 led101-0002 cap0805-2209 cap1206-1004 cap1206-1004 cap0805-1003
motorola national lumex murata murata AVX murata
19
C40 r1 r2-4, R57 r5-10, r12-r23, r3247, R54, R55 r11 R24-31, R53 jp1, jp3 j1,j3 jp2 j2 j4 s1 s2 s3 t1 j7 p1 P13-P16
1 1 3 35 1 9 2 2 1 1 1 1 1 0 1 1 1 1 1 4 1 4 2 2 2
cap0805-1009 res0805-1005 res0805-1000 res0805-1002 res0805-8200 con225-1003 rec225-1002 con225-3003 rec225-3002 con232-0001 sw102-0001 swdip0004 sw101-0002 tr101-0001 con103-0001 con104-2007
resistor, smt, 10M, 1/8 watt, 0805 resistor, smt, 100, 1/8 watt resistor, smt, 10k, 1/8 watt, 0805 variable resistor, 10k resistor, smt. 820, 1/8 watt 3 position header shunt (use with jpx above) post 3x3 triple shunt (use with jp3) rt angle rs232 connector(female, 9 pin) reset switch, momentary 4 position dip switch,side actuated on-off switch class 2 transformer, 500ma,female connector for ps, male 7x2 ribbon connector jtag connectors
samsung samsung samsung digikey samtec samtec samtec samtec amp bourns cts digikey digikey digikey samtec samtec
rm10j106ct rm12j101ct rm10f1002ct 3309P-103-ND rm10f820ct tsw-103-23-L-s-LL snt-100-bk-g tsw-103-23-L-T-LL mnt-103-bk-g 745988-4 7914g 195-4mst EG1906-ND dpd090050-p-5 pj-202a tst-107-01-L-D-LL
tp_ps,tp_gnd
con225-1014 std102-0250 std101-0250 tp101-0001 riv101-0281
14 pin single in line connector/spacer (display) samtec standoffs for board richco standoffs for display, 0.250 richco test points koa rivet rivet king
dw-14-17-T-S-250-LL SRS4-5-01 dlcbsat-4-01 rcw c-1 (std tubular rivet)
20
Appendix D: FlashLINK Information
Features
* * * * * * * * * Allows PC parallel port to communicate with PSD9xx via PSDsoft Express Provides interface medium for JTAG communications Supports basic IEEE 1149.1 JTAG signals (TCK, TMS, TDI, TDO) Supports additional signals to enhance download speed ( TERR, TSTAT) Can be used for programming and/or testing Wide power supply range of 2.7 to 5.5v Pinout independent with target side flying leads Convenient desktop packaging allows varying applications (desk, lab or production) Synchronous JTAG interface allows speeds as fast as pc parallel port can drive
Overview
Flashlink is a hardware interface from a standard PC parallel port to one or more PSD8xx/9xx devices located within a target PC board, as shown below. This interface cable allows the PSD to be exercised for purposes of programming and/or testing. PSDsoft Express/PSDsoft2000 is the source for driving FlashLINK.
F ly ing le ad ca ble M ate s w ith P C pa rallel po rt
6 fe et 6 in ch e s
F la sh Lin k ad ap ter
1 2 W IR E S
T a rget de vic e
Figure 12 Typical FlashLINK application
Operating considerations
Operating power for FlashLINK is derived from the target system in the range of 2.7 to 5.5 v. Compatibility over this voltage range is ensured by the design of FlashLINK. No settings are involved. On a cautionary note, it is recommended that the target system be powered by a regulated and stable source of power, which is energized at the final value of Vcc. It is not recommended that the input voltage be varied using the verneer on a regulated power supply, as this may cause the internal FlashLINK IC's (74VHC240) to misoperate toward the lower end of the supply range. Each FlashLINK is packaged with a six-inch "flying lead" cable for maximum adaptability. A ribbon cable requires the use a certain connector and pin configuration on the target assembly. This flying lead cable mates to the FlashLINK adapter on one end and has loose sockets on the other end to slide onto 0.025" square posts on the target assembly.
21
The signals are defined in the following table. SIGNAL NAME DESCRIPTION Type Flashlink is Signal
PIN #
1
JEN\
2 3 4 5 6 7 8 9 10 11 12 13 14
TRST\ * GND CNTL * TDI TSTAT Vcc RST\ TMS GND TCK GND TDO TERR\
Enables JTAG-ISP pins on PSD. Only used when JTAG-ISP signals are multiplexed with other I/O.(optional) JTAG reset on target (optional per 1149.1) Signal ground Generic control signal, (optional) JTAG IEEE 1149.1 serial data input JTAG-ISP programming status (optional) VDC Source from target (2.7 - 5.5 VDC) Target system reset (recommended) JTAG IEEE 1149.1 mode select Signal ground JTAG IEEE 1149.1 clock Signal ground JTAG IEEE 1149.1 serial data output JTAG-ISP programming error (optional)
OC,100K
Source
OC,10K
Source
OC,10K
Source Source Destination Source Source Source Destination Destination
OC,10K
Notes 1. Bold signals are required connections 2. All signal grounds are connected inside FlashLINK adapter 3. OC = open collector, pulled-up to Vcc inside FlashLINK adapter 4. * = Not supported by PSDsoft, signals remain inactive. 5. The target device must supply Vcc to the FlashLINK Adapter (2.7 to 5.5 VDC, 15mA max @ 5.5V). Figure 13 Pin descriptions for FlashLINK adapter assembly All 14 signals may not be needed for a given application. Here's how they break down: (6) Required signals (four JTAG-ISP pin config): TDI, TDO, TMS, TCK, Vcc, GND (2) Optional signals for faster ISP (6 JTAG-ISP pin config): TSTAT, TERR\ (1) Optional signal to control multiplexing of the JTAG signals: JEN\ (1) Recommended signal to allow FlashLINK to reset target system during and after ISP: RST\ (1) Optional IEEE-1149.1 signal for JTAG chain reset: TRST\ (1) Optional generic control signal from FlashLINK to target system: CNTL (2) Two additional ground lines to help reduce EMI if a ribbon cable is used. These ground lines "sandwich" the TCK signal in the ribbon cable. These lines are not needed for use with the flying lead cable. That is why the flying lead cable has only 12 of 14 wires populated.
22
FlashLINK pinouts
There is still no industry "standard" JTAG connector. Each manufacturer differs. ST has a specific connector and pinout for the FlashLINK programmer adapter. The connector scheme on the FlashLINK adapter can accept a standard 14 pin ribbon connector (2 rows of 7 pins on 0.1" centers, standard keying) or any other user specific connector that can slide onto 0.025" square posts. The pinout for the FlashLINK adapter connector is shown in the previous Figure. A standard ribbon cable is good way to quickly connect to the target circuit board. If a ribbon cable is used, then the receiving connector on the target system should be the same connector type with the same pinout as the FlashLINK adapter shown in Figure 4. Keep in mind that the JTAG signal TDI is sourced from the FlashLINK adapter and should be routed on the target circuit card so that it connects to the TDI input pin of the PSD device. Although the name "TDI" infers "Data In" by convention, it is an output from FlashLINK and an input to the PSD device. Also keep in mind that the JTAG signal TDO is an input received by the FlashLINK adapter and is sourced by the PSD device on the TDO output pin. See App note 54 for further details.
S T JTAG -ISP CO NNECTO R DEFINITIO N
VIEW : L O O K IN G IN T O F A C E O F S H R O U D E D M ALE C O N N E C TO R . 0 .0 2 5 " P O S T S O N 0 .1 " C E N T E R S . C o n n e c to r re fe re n ce : M o le x 7 0 2 4 7 -1 4 0 1 R e c o m m e n d e d rib bo n c a b le fo r q u ic k c o n n e c tio n o f F la s hL in k a d a p te r to e n d p ro d u c t: S a m te c : H C S D -0 7-D -0 6 .0 0 -0 1 -S -N or D ig ik e y : M 3 C C K -14 0 6 5 -N D N o te : T D I is a s ig n a l s o urc e o n th e F la s h lin k a n d a s ig n a l d e s tina tio n o n th e ta rg e t b o a rd . T D O is a s ig n a l d es tin a tio n o n th e F la s h L in k a n d a s ign a l s o u rc e o n th e ta rg e t b o a rd .
14
13
7(55 7'2
12 11
*1' 7&.
10 9 KEY W AY
*1' 706
8 7
567
6
9&&
5
767$7 7',
4 3
&17/ *1'
2 1
7567 -(1
Figure 7 - Pinout for FlashLINK Adapter and Target System Each FlashLINK is sold with a six-inch "flying lead" cable for maximum adaptability since a ribbon cable requires the use a certain connector on the target assembly. This flying lead cable mates to the FlashLINK adapter on one end and has loose sockets on the other end to slide onto 0.025 square posts on the target assembly.
23
Target System , 3v or 5v
FlashLink Adapter C onncetor
V cc
V cc 7
7
Recom m ended b u ffe rin g fo r so m e PSDs 1
9 TMS T C K 11 TDI 5 TSTAT 6 T E R R 14 T D O 13 JE N 1 op tio na l 2 op tio na l TRST 3 GND* 4 op tio na l CNTL 8 re co m m e nde d RST 10 GND* G N D * 12 * all gro un d p ins are conn ected to ge the r insid e fla sh lin k a ssem bly stra ight through ribb on ca ble 2 ro w , 7 po sition
1
9 11 5 op tio na l op tio na l 6 14 13 1 2 3 4 8 10 12
D evice 1 TMS TCK TDI TDO TSTAT TERR\ F lash P S D TMS TCK TDI TDO A ny JT A G D evice in B yP ass M od e TMS TCK TDI TDO D evice N D evice 2
B ufferin g recom m end ed for P S D 81 3/8 33 /83 4/ 9 13 /93 4 o nly. N ot requ ire d o n P S D 4 00 0 serie s o r P S D 8 35 /93 5.
S yste m R eset C ircu itry
TSTAT TERR\
F lash P S D
Figure 14 JTAG Chaining Example
24
0. 01UF SOLDERI NG PAD PATTE RN CBL 1 D0 (TCK) DB2 1 D1 (TMS) DB3 2 D2 (TDI) DB4 3 D3 (J EN\) DB5 4 D4 (TRST) DB6 5 D5 (RST) DB7 6 G ND DB1 8 7 A CKN DB1 0 8 PA P DB1 2 9 ERRN DB1 5 10 SEL DB1 3 11 BUSY DB11 12 D6 DB8 13 A UTO LINE FEED DB1 4 14 PA D1 4 V CC R2 6 S2 1 PA D1 S1 1 PA D1 R2 9 4. 7K R2 8 4. 7K R4 3 4. 7K 74 A C05 U3 C 6 U3 D 8 74 A C05 V CC 0. 01UF D2 41 48 C2 5 10 74 A C05 V CC V CC 9 U3 E 11 74 A C05 5 SHIELD (DRAIN WIRE) V CC 0 R8 0 47 0K R2 5 10 K 5 U1 A red org pink yellow green lt gree n grey black orgt brnt white 47 47 47 47 47 47 47 R1 47 R3 47 R5 47 R7 10 0p f 10 0p f 10 0p f R9 R1 1 R1 0 10 0p f 47 R8 R6 1 R4 R2 2 4 6 8 A1 A2 A3 A4 G 74 V HC24 0 R4 2 4. 7K U2 A 10 0p f 10 0p f 10 0p f 1 R3 9 10 K 2 74 A C05 U2 B 3 U2 C 6 74 A C05 U3 B 3 4 4 74 A C05 9 U2 D Y1 Y2 Y3 Y4 18 16 14 12 V CC 17 15 13 11 19
C2 4 U1 B A4 A3 A2 A1 G
(FOR U1)
V CC 3 5 7 9 47 47 47 R1 2 47 R1 4 47 R1 6 47 47 47 R1 8 R1 9 R1 7 R1 5 /JEN TRSTN CO NTROL TDI TS TA TN V CCIN RSTN TMS G ND TCK G ND TDO TERRN R1 3 P1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 70 24 7- 14 01 MO LEX
Y4 Y3 Y2 Y1
74 V HC24 0
C5 2
C5 3
C5 4
C5 5
8 47 74 A C05 R2 0 47 R2 1
C5 6
C5 7
C5 8
10 K
R2 2
10 0K R3 4
(FRAME GND)
10 K
R2 3
10 K
R3 0
10 0K 10 0K 10 0K
R3 1 D4 R3 2 1N58 17 R3 3
0. 01UF
C2 6
V CC
(FOR U2)
(FOR U3)
R5 0 10
D3 41 48 2 1 R4 1 4. 7K R4 0 10 K 0 U3 A 1 2 U2 E 74 A C05 11 10 74 A C05 U2 F 13 12 74 A C05 U3 F W a fers c ale Integ r a tion 13 12 74 A C05 10 K R3 8 47 28 0 Ka to Roa d Fre mon t, CA 94 53 8 Title Flas hL ink Sc he matic Siz e B Da te: Do c u me nt Numb er Flas hL ink PCB Mon da y , Ju ly 26 , 1 999 Sh ee t 1 of 1 Re v G1 10 K R3 7 10 K R3 6 10 K R3 5 R8 1 3 Q1 2N39 04 C5 0 1UF 0. 01UF D1 6. 2V C5 1 R5 1 10 0K
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Loop back connector schematic
J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CO N14 PC outp ut signal 14 pin dual row 0.02 5 sq recepta cle(polarized , same as cab le 5) TDI TMS TCK PC intp ut signal !TSTAT !TERR !TDO PC conn ector line ACKN (8 ) ERRN (1 0) PAP (9) J2 G ND TDI TS TA T V CC TMS TCK TDO TERR 1 J1 1 VCC CO N1 GND CO N2
to flas h link assy
Figure 15 Loop Back Tester, Passive, FlashLINK
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Appendix E Results codes and debug tree for htestXA.obj
Results codes Results = 0 1 2 3 4 5 6 7 8 9 A B C D E F binary abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 1 Hex to Binary Conversion Debug tree X = don't care a b x x x 1 x x 1 x
Success Code
c x 1 x x
d 1 x x x Page register test PSD ram error External Ram error UART error
action Replace PSD ( U1 on EVD) and retest Replace PSD ( U1 on EVD) and retest Replace SRAM (U3 EVM) and retest Repair U4 or surrounding circuitry, EVM (this is under the EVD board)
Table 2 Debug Tree
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Appendix F: Board errata
Following is a brief list of issues with correlated on a revision level basis
Mother board
Rev C. JP10 added for XA display functionality. Rev B. hardware mod for display-XA functionality.
Daughter board (XA)
Rev B initial release
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DK4_XA - USER MANUAL
Table 1. Document Revision History
Date Rev. 1.0 Description of Revision Document written in the WSI format DK4_XA: DK4000-XA Development Kit For PSD4000 Series of Flash PSDs Front page, and back two pages, in ST format, added to the PDF file Any references to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft Express
31-Jan-2002
1.1
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DK4_XA - USER MANUAL
For current information on PSD products, please consult our pages on the world wide web: www.st.com/psm If you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.psd@st.com ask.memory@st.com (for application support) (for general enquiries)
Please remember to include your name, company, location, telephone number and fax number.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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