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GAL26V12
High Performance E2CMOS PLD Generic Array LogicTM
FEATURES * HIGH PERFORMANCE E CMOS TECHNOLOGY -- 7.5 ns Maximum Propagation Delay -- Fmax = 142.8 MHz -- 4.5 ns Maximum from Clock Input to Data Output -- TTL Compatible 16 mA Outputs -- UltraMOS(R) Advanced CMOS Technology * LOW POWER CMOS -- 90 mA Typical Icc * E2 CELL TECHNOLOGY -- Reconfigurable Logic -- Reprogrammable Cells -- 100% Tested/Guaranteed 100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * TWELVE OUTPUT LOGIC MACROCELLS -- Maximum Flexibility for Complex Logic Designs * PRELOAD AND POWER-ON RESET OF REGISTERS -- 100% Functional Testability * APPLICATIONS INCLUDE: -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Standard Logic Speed Upgrade * ELECTRONIC SIGNATURE FOR IDENTIFICATION
INPUT
2 (R)
FUNCTIONAL BLOCK DIAGRAM
I/CLK 1
PRESET
INPUT 8
INPUT 8 INPUT 10 INPUT/CLK 2 12 INPUT
OLMC 0 OLMC 1
I/O/Q
I/O/Q
OLMC 2
I/O/Q
PROGRAMMABLE AND-ARRAY (150X52)
OLMC 3
14
I/O/Q
INPUT
OLMC 4
16
I/O/Q
INPUT
OLMC 5
16
I/O/Q
INPUT
OLMC 6
14
I/O/Q
INPUT 12 INPUT 10 INPUT 8
OLMC 7
I/O/Q
OLMC 8 OLMC 9
I/O/Q
I/O/Q
OLMC 10
8
I/O/Q
DESCRIPTION The GAL26V12, at 7.5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest performance available of any 26V12 device on the market. E2 technology offers high speed (<100ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL26V12 is fully function/fuse map/parametric compatible with other 26V12 devices. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, LATTICE is able to guarantee 100% field programmability and functionality of all GAL(R) products. LATTICE also guarantees 100 erase/rewrite cycles.
INPUT
OLMC 11
RESET
I/O/Q
PACKAGE DIAGRAMS
DIP PLCC
I/CLK2 I
I I/CLK1 I I/O/Q I/O/Q
I/CLK1 I I I/CLK2 I 1 28 I I/O/Q I/O/Q I/O/Q
I
I
4
2
28
26 25
I I VCC I I I I
5
I/O/Q I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q
I Vcc I I I I I I I 7
GAL 26V12
21
I/O/Q I/O/Q I/O/Q GND I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q
7
GAL26V12
Top View
23
9
21
11 12 14 16
19 18
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I
I
14
15
I/O/Q
Copyright (c)2000 Lattice Semiconductor Corp. GAL, E2CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconductor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
November 2000
Specifications GAL26V12
GAL 26V12 ORDERING INFORMATION Commercial Grade Specifications
Tpd (ns)
7.5 10
Tsu (ns)
6 7
Tco (ns)
4.5 7
Icc (mA)
130 130 130
Ordering #
GAL26V12C-7LJ GAL26V12C-10LP GAL26V12C-10LJ GAL26V12C-15LP GAL26V12C-15LJ GAL26V12C-20LP GAL26V12C-20LJ
Package
28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC
15
10
8
105 105
20
12
12
105 105
Industrial Grade Specifications
Tpd (ns)
10
Tsu (ns)
7
Tco (ns)
7
Icc (mA)
150 150
Ordering #
GAL26V12C-10LPI GAL26V12C-10LJI GAL26V12C-15LPI GAL26V12C-15LJI GAL26V12C-20LPI GAL26V12C-20LJI
Package
28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC 28-Pin Plastic DIP 28-Lead PLCC
15
10
8
150 150
20
12
12
150 150
PART NUMBER DESCRIPTION
XXXXXXXX _ XX X XX
GAL26V12C Device Name Grade Blank = Commercial I = Industrial
Speed (ns) L = Low Power Power
Package P = Plastic DIP J = PLCC
2
Specifications GAL26V12
OUTPUT LOGIC MACROCELL (OLMC)
The GAL26V12 has a variable number of product terms per OLMC. Of the ten available OLMCs, four OLMCs have access to eight product terms (pins 15, 16, 26 and 27), two have ten product terms (pins 17 and 25), two have twelve product terms (pins 18 and 24), two have fourteen product terms (pins 19 and 23), and two OLMCs have sixteen product terms (pins 20 and 22). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. In the registered mode configuration the clock source for the register can be selected. The two clock options, CLK1 and CLK2, originate from input pin1 and pin4 respectively. The GAL26V12 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen.
AR
D Q CLK1/ CLK2 SP 2 TO 1 MUX
Q
4 TO 1 MUX
GAL26V12 OUTPUT LOGIC MACROCELL (OLMC)
OUTPUT LOGIC MACROCELL CONFIGURATIONS
Each of the Macrocells of the GAL26V12 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by four architecture bits (S0, S1, S2 and S3), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED MODE In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. There are two options for the feedback of the registered mode - internal /Q feedback and I/O pin feedback. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. Similarly the I/O pin feedback with both true and complement input to the AND array. The resulting polarity depends on the input polarity selection as well as the registered I/O output polarity configuration. COMBINATORIAL MODE In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "productterm driven" (dynamic I/O). In combinatorial mode there are also two options for the feedback. The first feedback option into the AND array is from the I/O pin side of the output buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. The second option is to drive the feedback from /Q of the buried register. This option provides the combinatorial output with the ability to register the feedback of the same combinatorial output.
3
Specifications GAL26V12
REGISTERED MODE
AR
AR
D
Q
D
Q
CLK1/ CLK2
Q
CLK1/ CLK2
Q
SP
SP
ACTIVE LOW REGISTERED OUTPUT WITH BURIED FEEDBACK S0 = 0 S1 = 0 S3 = 1 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
ACTIVE HIGH REGISTERED OUTPUT WITH BURIED FEEDBACK S0 = 1 S1 = 0 S3 = 1 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
AR
AR
D
Q
D
Q
CLK1/ CLK2
Q
CLK1/ CLK2
Q
SP
SP
ACTIVE LOW REGISTERED OUTPUT WITH I/O FEEDBACK S0 = 0 S1 = 0 S3 = 0 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
ACTIVE HIGH REGISTERED OUTPUT WITH I/O FEEDBACK S0 = 1 S1 = 0 S3 = 0 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
4
Specifications GAL26V12
COMBINATORIAL MODE
ACTIVE LOW COMBINATORIAL OUTPUT WITH I/O FEEDBACK S0 = 0 S1 = 1 S3 = 1 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
ACTIVE HIGH COMBINATORIAL OUTPUT WITH I/O FEEDBACK S0 = 1 S1 = 1 S3 = 1 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
AR
AR
D
Q
D
Q
CLK1/ CLK2
Q
CLK1/ CLK2
Q
SP
SP
ACTIVE LOW COMBINATORIAL OUTPUT WITH BURIED REGISTER FEEDBACK S0 = 0 S1 = 1 S3 = 0 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
ACTIVE HIGH COMBINATORIAL OUTPUT WITH BURIED REGISTER FEEDBACK S0 = 1 S1 = 1 S3 = 0 S2 = 1 Selects CLK1 S2 = 0 Selects CLK2
5
Specifications GAL26V12
GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP
1
0 4 8 12 16 20 24 28 32 36 40 44 48
28
0000 0052 . . . 0468 ASYNCH RESET OLMC 27 S0-7800 S1-7812 S2-7824 S3-7836
27
2
0520 . . . 0936
OLMC 26 S0-7801 S1-7813 S2-7825 S3-7837
26
3
0988 . . . . 1508
OLMC 25 S0-7802 S1-7814 S2-7826 S3-7838
25
4
1560 . . . . . 2184
OLMC 24 S0-7803 S1-7815 S2-7827 S3-7839
24
5
2236 . . . . . . 2964 OLMC 23 S0-7804 S1-7816 S2-7828 S3-7840
23
6
3016 . . . . . . . 3848 OLMC 22 S0-7805 S1-7817 S2-7829 S3-7841
VCC
7
22
8
0 4 8 12 16 20 24 28 32 36 40 44 48 CLK1 CLK2 AR SP
21
6
Specifications GAL26V12
GAL26V12 LOGIC DIAGRAM / JEDEC FUSEMAP (CONT.)
0 4 8 12 16 20 24 28 32 36 40 44 48 CLK1 CLK2 AR SP
3900 . . . . . . . 4732
OLMC 20 S0-7806 S1-7818 S2-7830 S3-7842
20
9
4784 . . . . . . 5512 OLMC 19 S0-7807 S1-7819 S2-7831 S3-7843
19
10
5564 . . . . . 6136 OLMC 18 S0-7808 S1-7820 S2-7832 S3-7844
18
11
6188 . . . . 6760 OLMC 17 S0-7809 S1-7821 S2-7833 S3-7845
17
12
6812 . . . 7228
OLMC 16 S0-7810 S1-7822 S2-7834 S3-7846
16
13
7280 . . . 7696
OLMC 15 S0-7811 S1-7823 S2-7835 S3-7847 SYNCH PRESET 0 4 8 12 16 20 24 28 32 36 40 44 48
15
14
7748
B0
B1
7848 7849...
L S B
M S B
B3
B4
B5
B6
B7
Electronic Signature ...7910 7911
7
Specifications GAL26V12C Specifications GAL26V12
ABSOLUTE MAXIMUM RATINGS(1)
Supply voltage VCC ....................................... -0.5 to +7V Input voltage applied ........................... -2.5 to VCC +1.0V Off-state output voltage applied........... -2.5 to VCC +1.0V Storage Temperature.................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
RECOMMENDED OPERATING COND.
Commercial Devices: Ambient Temperature (TA) ............................. 0 to +75C Supply voltage (VCC) with Respect to Ground ..................... +4.75 to +5.25V Industrial Devices: Ambient Temperature (TA) ........................... -40 to 85C Supply voltage (VCC) with Respect to Ground ......................... +4.5 to +5.5V
DC ELECTRICAL CHARACTERISTICS
Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Output Low Voltage Output High Voltage Low Level Output Current High Level Output Current Output Short Circuit Current VCC = 5V VOUT = 0.5V TA = 25C 0V VIN VIL (MAX.) 3.5V VIN VCC IOL = MAX. Vin = VIL or VIH IOH = MAX. Vin = VIL or VIH CONDITION MIN.
Vss - 0.5
TYP.4 -- -- -- -- -- -- -- -- --
MAX. 0.8 Vcc+1 -10 10 0.5 -- 16 -3.2 -130
UNITS V V A A V V mA mA mA
VIL VIH IIL1 IIH VOL VOH IOL IOH IOS2
2.0 -- -- -- 2.4 -- -- -30
COMMERCIAL ICC3 Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V Outputs Open
ftoggle = 15MHz
-7/-10 -15/-20
-- --
90 75
130 105
mA mA
INDUSTRIAL ICC3 Operating Power
Supply Current
VIL = 0.5V VIH = 3.0V Outputs Open
ftoggle = 15MHz
-10/-15/-20
--
110
150
mA
1) The leakage current is due to the internal pull-up on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Guaranteed but not 100% tested. 3) Icc specified for a ten-bit binary counter pattern. 4) Typical values are at Vcc = 5V and TA = 25 C
8
Specifications GAL26V12C Specifications GAL26V12 Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAM. TEST COND.1
DESCRIPTION MIN. Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Synch. Preset before Clk Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynch. Reset of Register Asynchronous Reset Pulse Duration Asynch. Reset to Clock Recovery Time Synch. Preset to Clock Recovery Time -- -- -- 6 5.5 0 95.2
-7
-10 MAX. MIN. 7.5 4.5 2 -- -- -- -- -- -- -- 7 6.5 0 71.4
-15
-20 MAX. 20 12 10 -- -- -- -- UNITS ns ns ns ns ns ns MHz
MAX. MIN. 10 7 2.5 -- -- -- -- -- -- -- 10 10 0 55.5
MAX. MIN. 15 8 2.5 -- -- -- -- -- -- -- 12 12 0 41.6
tpd tco tcf2 tsu1 tsu2 th
A A -- -- -- -- A
fmax3
A A
125.0 142.8
-- --
105.2 125
-- --
80.0 83.3
-- --
45.4 62.5
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
3.5 3.5 -- -- -- 6 5 5
-- -- 7.5 7.5 9 -- -- --
4 4 -- -- -- 8 8 8
-- -- 10 10 13 -- -- --
6 6 -- -- -- 10 10 10
-- -- 15 15 20 -- -- --
8 8 -- -- -- 15 15 12
-- -- 20 20 20 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
CAPACITANCE (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
9
Specifications GAL26V12C Specifications GAL26V12 Commercial
AC SWITCHING CHARACTERISTICS
Over Recommended Operating Conditions
PARAM. TEST COND.1
DESCRIPTION Input or I/O to Combinatorial Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Synch. Preset before Clk Hold Time, Input or Feedback after Clock Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynch. Reset of Register Asynchronous Reset Pulse Duration Asynch. Reset to Clock Recovery Time Synch. Preset to Clock Recovery Time -- -- -- 7 6.5 0 71.4
-10 MIN.
-15
-20 MAX. 20 12 10 -- -- -- -- UNITS ns ns ns ns ns ns MHz
MAX. MIN. 10 7 2.5 -- -- -- -- -- -- -- 10 10 0 55.5
MAX. MIN. 15 8 2.5 -- -- -- -- -- -- -- 12 12 0 41.6
tpd tco tcf2 tsu1 tsu2 th
A A -- -- -- -- A
fmax3
A A
105.2 125.0
-- --
80.0 83.3
-- --
45.4 62.5
-- --
MHz MHz
twh twl ten tdis tar tarw tarr tspr
-- -- B C A -- -- --
4 4 -- -- -- 8 8 8
-- -- 10 10 13 -- -- --
6 6 -- -- -- 10 10 10
-- -- 15 15 20 -- -- --
8 8 -- -- -- 15 15 12
-- -- 20 20 20 -- -- --
ns ns ns ns ns ns ns ns
1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Description section. 3) Refer to fmax Description section.
CAPACITANCE (TA = 25C, f = 1.0 MHz)
SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance MAXIMUM* 8 8 UNITS pF pF TEST CONDITIONS VCC = 5.0V, VI = 2.0V VCC = 5.0V, VI/O = 2.0V
*Guaranteed but not 100% tested.
10
Specifications GAL26V12
SWITCHING WAVEFORMS
INPUT or I/O FEEDBACK
VALID INPUT
INPUT or I/O FEEDBACK
VALID INPUT
tpd
COMBINATORIAL OUTPUT
ts u
CLK
th
tc o
Combinatorial Output
REGISTERED OUTPUT
1/
fm a x
(external fdbk)
Registered Output
INPUT or I/O FEEDBACK
tdis
OUTPUT
ten
CLK
1/
fm a x
(int ern al fd bk )
Input or I/O to Output Enable/Disable
REGISTERED FEEDBACK
tc f
tsu
tw h
CLK
tw l
fmax with Feedback
Clock Width
INPUT or I/O FEEDBACK DRIVING AR
th
INPUT or I/O FEEDBACK DRIVING SP
ts u
ts p r
ta r w
REGISTERED OUTPUT
tarr
CLK
tc o
tar
CLK
REGISTERED OUTPUT
Synchronous Preset Asynchronous Reset
11
Specifications GAL26V12
fmax DESCRIPTIONS
CLK
CLK
LOGIC A RRA Y
RE GIST ER
LOGIC ARRAY
REGISTER
ts u
tc o
fmax with External Feedback 1/(tsu+tco)
Note: fmax with external feedback is calculated from measured tsu and tco.
tc f tp d
fmax with Internal Feedback 1/(tsu+tcf)
Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd.
CLK
LOGI C ARRAY
REGISTER
fmax With No Feedback
Note: fmax with no feedback may be less than 1/twh + twl. This is to allow for a clock duty cycle of other than 50%.
SWITCHING TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 2ns 10% - 90% 1.5V 1.5V See Figure
FROM OUTPUT (O/Q) UNDER TEST TEST POINT R1 +5V
3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure) Test Condition A B C Active High Active Low Active High Active Low R1 300 300 300 R2 390 390 390 390 390 CL 50pF 50pF 50pF 5pF 5pF
R2
C L*
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
12
Specifications GAL26V12
ELECTRONIC SIGNATURE
An electronic signature is provided in every GAL26V12 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell.
OUTPUT REGISTER PRELOAD
When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL26V12 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically.
SECURITY CELL
A security cell is provided in every GAL26V12 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell.
LATCH-UP PROTECTION
GAL26V12 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias minimizes the potential for latch-up caused by negative input undershoots. Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots.
INPUT BUFFERS
GAL26V12 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices.
DEVICE PROGRAMMING
GAL devices are programmed using a Lattice-approved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle.
13
Specifications GAL26V12
POWER-UP RESET
Circuitry within the GAL26V12 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown below. Because of the asynchronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL26V12. First, the VCC rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements.
Vcc
4.0 V
CLK
INTERNAL RE GISTER Q - OUTP UT
tpr
Internal Register Reset to Logic "0"
ACTIV E LOW OUTPUT REGIS TER
Device Pin Reset to Logic "1"
ACTIVE HIGH OUTPUT REGIS TER
Device Pin Reset to Logic "0"
INPUT/OUTPUT EQUIVALENT SCHEMATICS
PIN
Output Data Feedback PIN
Vcc
T ri - S t a t e Cont rol Vcc
Active Pull-up Circuit
Vref
Vcc ESD Protection Circuit
Vcc
Output Data
PIN
PIN
ESD Protection Circuit
Feedback (To Input Buffer)
Input
Output
14
Specifications GAL26V12
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Normalized Tpd vs Vcc
1.2 1.2
Normalized Tco vs Vcc
1.2
Normalized Tsu vs Vcc
Normalized Tpd
Normalized Tco
1.1
Normalized Tsu
4.75 5.00 5.25 5.50
1.1
1.1
1
1
1
0.9
0.9
0.9
0.8 4.50 4.75 5.00 5.25 5.50
0.8 4.50
0.8 4.50 4.75 5.00 5.25 5.50
Supply Voltage (V)
Supply Voltage (V)
Supply Voltage (V)
Normalized Tpd vs Temp
1.3 1.3
Normalized Tco vs Temp
1.4
Normalized Tsu vs Temp
Normalized Tpd
Normalized Tco
Normalized Tsu
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7
1.3 1.2 1.1 1 0.9 0.8 0.7 -55 -25 0 25 50 75 100 125
Temperature (deg. C)
Temperature (deg. C)
Temperature (deg. C)
Delta Tpd vs # of Outputs Switching
0 0
Delta Tco vs # of Outputs Switching
Delta Tpd (ns)
-0.25
Delta Tco (ns)
1 2 3 4 5 6 7 8 9 10 11 12
-0.25
-0.5
-0.5
-0.75
-0.75
-1
-1 1 2 3 4 5 6 7 8 9 10 11 12
Number of Outputs Switching
Number of Outputs Switching
Delta Tpd vs Output Loading
12 10 12
Delta Tco vs Output Loading
RISE
Delta Tpd (ns)
10
RISE FALL
8 6 4 2 0 -2 0 50
Delta Tco (ns)
150 200 250 300
FALL
8 6 4 2 0 -2
100
0
50
100
150
200
250
300
Output Loading (pF)
Output Loading (pF)
15
Specifications GAL26V12
TYPICAL AC AND DC CHARACTERISTIC DIAGRAMS
Vol vs Iol
3 2.5 5 4
Voh vs Ioh
4
Voh vs Ioh
3.75
Voh (V)
3 2 1 0
1.5 1 0.5 0 0.00 20.00 40.00 60.00 80.00 100.00
Voh (V)
10.00 20.00 30.00 40.00 50.00 60.00
Vol (V)
2
3.5
3.25
3 0.00 1.00 2.00 3.00 4.00
0.00
Iol (mA)
Ioh(mA)
Ioh(mA)
Normalized Icc vs Vcc
1.3 1.3
Normalized Icc vs Temp
1.50
Normalized Icc vs Freq.
Normalized Icc
Normalized Icc
Normalized Icc
-55 -25 0 25 50 75 100 125
1.2 1.1 1 0.9 0.8 0.7 4.50 4.75 5.00 5.25 5.50
1.2 1.1 1 0.9 0.8 0.7
1.40 1.30 1.20 1.10 1.00 0.90 0.80 0 25 50 75 100
Supply Voltage (V)
Temperature (deg. C)
Frequency (MHz)
Delta Icc vs Vin (1 input)
10 0 10
Input Clamp (Vik)
Delta Icc (mA)
8 6 4 2 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
Iik (mA)
20 30 40 50 60 -2.00 -1.50 -1.00 -0.50 0.00
Vin (V)
Vik (V)
16

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