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Programmable Synchronous DC/DC Hysteretic Controller for Advanced Processors
POWER MANAGEMENT Description
The SC1154 is a synchronous-buck switch-mode controller designed for use in single ended power supply applications where efficiency is the primary concern. The controller is a hysteretic type, with a user selectable hysteresis. The SC1154 is ideal for implementing DC/ DC converters needed to power advanced microprocessors such as Pentium(R) lI in both single and multiple processor configurations. Inhibit, under-voltage lockout and soft-start functions are included for controlled power-up. SC1154 features include an integrated 5 bit D/A converter, temperature compensated voltage reference, current limit comparator, over-current protection, and an adaptive deadtime circuit to prevent shoot-through of the power MOS.ET during switching transitions. Power good signaling, logic compatible shutdown, and over-voltage protection are also provided. The integrated D/A converter provides programmability of output voltage from 1.3V to 3.5V with no external components. The SC1154 high side driver can be configured as either a ground-referenced or as a floating bootstrap driver. The high and low side MOS.ET drivers have a peak current rating of 2 amps.
SC1154
PRELIMINARY
.eatures
K K K K K K
Programmable hysteresis 5 bit DAC programmable output (1.3V-3.5V) On-chip power good and OVP functions Designed to meet latest Intel specifications Up to 95% efficiency +1% tolerance over temperature
Applications
K K K K
Server Systems and Workstations Pentium(R) II Core Supplies Multiple Microprocessor Supplies Voltage Regulator Modules
Typical Application Circuit
+5V
R1 * R3 * R2 1k 2 R4 1k DROOP
U1 SC1154CSW 1 IOUT PWRGD 28
R9 10k
R10 1k PWRGD
"POWER GOOD"
C6 0.1 INHIB
VID0
27
3
OCP
VID1
26 R11 1k C7 0.1
"INHIBIT"
4 R5 * R6 20k C2 0.001 C1 0.1
VHYST
VID2
25
5
VREFB
VID3
24
L1 0.5uH
6
VSENSE
VID25
23 Cin H. Cin Bulk
+
Vin
7
AGND
INHIBIT
22
8 C3 0.1 +5V 10 C4 0.01
SOFTST
IOUTLO
21 C8 0.033
9
N/C
LOSENSE
20
LODRV
HISENSE
19
11
LOHIB
BOOTLO
18 R12 1.0
Q1 .DB6035AL
12
DRVGND
HIGHDR
17
13
LOWDR
BOOT
16 +12V C9 1.0 R14 1.6 Q2 .DB7030BL
L2 1.0uH
14
DRV
VIN12V
15
Cout Bulk
Cout H.
1
C5
C10
R8 10k
R7 *
*) for the values see specific application circuit somewhere else in the datasheet
Revision 3, June 2001
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SC1154
POWER MANAGEMENT Absolute Maximum Ratings
Parameter VIN12V BOOT to DRVGND BOOT to BOOTLO BOOTLO tp DRVGND VIDS, INHIB, LODRV, PWRGD, OCP, DROOP AGND to DRVGND LOHIB to AGND LOSENSE to AGND IOTLO to AGND HISENSE to AGND VSENSE to AGND Continuous Power Dissipation, TA = 25 0C Continuous Power Dissipation, TC = 25 0C Operating Junction Temperature Range Lead Temperature (Soldering) 10 Sec. Storage Temperature PD PD TJ TL TSTG Symbol VINMAX Maximum -0.3 to 14 -0.3 to 25 -0.3 to 15 -0.5 to 18 -0.5 to 7.3 0.5 -0.3 to 14 -0.3 to 14 -0.3 to 14 -0.3 to 14 -0.3 to 5 1.2 6.25 0 to +125 300 -65 to 150
PRELIMINARY
Units V V V V V V V V V V V W W C C C
DC Electrical Characteristics
Unless specified: 0 < TJ < 125C, VIN = 12V
Parameter Supply Voltage Range Supply Current (Quiescent) Symbol VIN12V IINq INH = 5V, VID not 11111, Vin above UVLO threshold during start-up, fsw = 200 kHz, BOOTLO = 0V, C D H = C D L = 50pF INH = OV or VID = 11111 or Vin below UVLO threshold during start-up, BOOT = 13V, BOOTLO = OV INH = 5V, VID not 11111, VIN above UVLO threshold during start-up, fsw = 200kHz, BOOT = 13V, BOOTLO = 0V, C D H = 50pF 5 Conditions Min 11.4 Typ 12 15 Max 13 Units V mA
High Side Driver Supply Current (Quiescent)
IBOOTq
10
A
mA
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SC1154
POWER MANAGEMENT DC Electrical Characteristics (Cont.)
Unless specified: 0 < TJ < 125C, VIN = 12V
PRELIMINARY
Parameter Reference/Voltage Identification Reference Voltage Accuracy
Symbols
Conditions
Min
Typ
Max
Units
VREF
11.4V < VIN12V< 12.6V, over full VID range (see Output Voltage Table)
-1
1
%
VIDO - VID4 High Threshold Voltage VIDO - VID4 Low Threshold Voltage Pow er Good Undervoltage Threshold Output Saturation Voltage Hysteresis Over Voltage Protection OVP Trip Point Hysteresis Soft Start Charge Current
(1)
VTH(H) VTH(L)
2.25 1
V V
VTH(PWRGD) VSAT VHYS(PWRGD) IO = 5mA
90 0.5 10
95
%VREF V mV
VOVP VHYS(OVP)
12
15 10
20
%VOUT mV
ICHG
VSS = 0.5V, resistance from VREFB pin to AGND = 20k, VREFB = 1.3V Note: ICHG = (IVREFB / 5) V(S/S) = 1V
10.4
13
15.6
A
Discharge Current Inhibit Comparator Start Threshold VIN 12V UVLO Start Threshold Hysteresis Hysteretic Comparator Input Offset Voltage Input Bias Current Hysteresis Accuracy Hysteresis Setting
Idischg
1
mA
Vstart(NH)
1
2.0
2.4
V
VstartUVLO VhysUVLO
9.25 1.8
10.25 2
11.25 2.2
V V
VosHYSCMP IbiasHYSCMP VHYS ACC VHYS SET
VDROOP pin grounded
5 1 7 60
mV uA mV mV
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SC1154
POWER MANAGEMENT DC Electrical Characteristics (Cont.)
Parameter Droop Compensation Initial Accuracy Overcurrent Protection OCP Trip Point Input Bias Current High-Side VDS Sensing Gain Initial Accuracy IOUT Source IOUT Sink Current VIOUT Voltage Swing VIOUT
AC C
PRELIMINARY
Conditions Min Typ Max Units
Symbols
VDROOP ACC VDROOP = 50 mV
5
mV
VOCP IbiasOCP
0.09
0.1
0.11 100
V nA
2 VHISENSE = 12V, VIOUTLO = 11.9V 500 40 0 0 0 2.85 1.8 50 65 80 50 3.75 2.0 1.0 6
V/V mV A A V V V V V
IsourceIOUT VIOUT = 0.5V, VHISENSE = 12V, VIOUTLO = 11.5V IsinkIOUT VIOUT (11) VIOUT (4.5) VIOUT (3) VIOUT = 0.05V, VHISENSE = 12V, VIOUTLO = 12V VHISENSE = 11V, RIOUT = 10kOhm VHISENSE = 4.5V, RIOUT = 10kOhm VHISENSE = 3V, RIOUT = 10kOhm
LOSENSE High Level Input Voltage LOSENSE Low Level Input Voltage Sample/Hold Resistance Buffered Reference VREFB Load Regulation Deadtime Circuit LOHIB High Level Voltage LOHIB Low Level Input Voltage LOWDR High Level Input Voltage LOWDR Low Level Input Voltage Drive Regulator Output Voltage Load Regulation Short Circuit Current
VihLOISENSE VHISENSE = 4.5V (Note 1) VilLOISENSE RS/H VHISENSE = 4.5V (Note 1) (Note 1)
VldregREFB 10A < IREFB < 500A
2
mV
VihLOHIB VilLOHIB VihLOWDR VilLOWDR
(Note 1) (Note 1) (Note 1) (Note 1)
2 1.0 2 1.0
V V V V
VDRV
11.4 < VIN12V < 12.6V, IDRV = 50mA
7 100 100
9
V mV mA
VldregDRV 1mA < IDRV < 50mA IshortDRV
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SC1154
POWER MANAGEMENT DC Electrical Characteristics (Cont.)
Parameter High-Side Output Driver Peak Output Current IsrcHIGHDR IsinkHIGHDR duty cycle < 2%, tpw < 100us, TJ = 125C VBOOT - VBOOTLO = 6.5V, VHIGHDR =1.5V(src), or VHIGHDR = 5V (sink) TJ = 125C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 6V TJ = 125C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.5V duty cycle < 2%, tpw < 100us, TJ = 125C VDRV - VBOOTLO = 6.5V, VLOWDR = 1.5V (src), or VLOWDR = 5V (sink) (Note 1) TJ = 125C VDRV = 6.5V, VLOWDR = 6V TJ = 125C VDRV = 6.5V, VLOWDR = 0.5V 2 45 5 2 A Symbol Conditions Min Typ
PRELIMINARY
Max Units
Equivalent Output Resistance
RsrcHIGHDR
RsinkHIGHDR Low -Side Output Driver Peak Output Current IsrcLOWDR IsinkLOWDR Equivalent Output Resistance RsrcLOWDR RsinkLOWDR
A
45 5
AC Electrical Characteristics (Note 1)
Parameter Hysteretic Comparators Propagation Delay Time from VSENSE to HIGHDR or LOWDR (excluding deadtime) Output Drivers HIGHDR rise/fall time trHIGHDR trHIGHDR trLOWDR tfLOWDR CI = 9nF, VBOOT = 6.5V, VBOOTLO = grounded, TJ =125C CI = 9nF, VDRV = 6.5V, TJ =125C 60 ns tHCPROP 10mV overdrive, 1.3V < Vref < 3.5V 150 250 ns Symbol Conditions Min Typ Max Units
LOWDR rise/falltime Overcurrent Protection Comparator Propagation Delay Time Deglitch Time
60
ns
tOCPROP tOCDGL 1
1 3
s s
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SC1154
POWER MANAGEMENT AC Electrical Characteristics (Cont.) (Note 1)
Parameter Overvoltage Protection Comparator Propagation Delay Time Deglitch Time (Includes comparator protection delay time) High-Side Vds Sensing Response Time tVDSRESP VHISENSE = 12V, VIOUTLO pulsed from 12V to 11.9V, 100ns rise and fall times VHISENSE = 4.5V, VIOUTLO pulsed from 4.5V to 4.4V, 100ns rise and fall times VHISENSE = 3V, VIOUTLO pulsed from 3.0v to 2.9V, 100ns rise and fall times Short Circuit Protection Rising Edge Delay Sample/Hold Switch turn-on/turn-off Delay Pow er Good Comparator Propagation Delay Softstart Comparator Propagation Delay Deadtime Driver Nonoverlap Time LODRV Propagation Delay TLODRVDLY 400 ns tNOL CLOWDR = 9nF, 10% threshold on LOWDR 30 100 ns tSLST overdrive = 10mV 560 900 ns tPWRGD 1 s tVDSRED tSWXDLY LOSENSE grounded 3V < VHISENSE < 11V VLOSENSE = VHISENSE 300 30 tOVPROP tOVPDGL 1 1 3 s s Symbol Conditions Min
PRELIMINARY
Typ Max Units
2
s
3
s
3
s
500 100
ns ns
Notes: (1). Guaranteed, but not tested. (2). This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC1154
POWER MANAGEMENT Test Circuit PRELIMINARY
Timing Diagram
Simplified Block Diagram
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SC1154
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Device
(1)
PRELIMINARY
Temp Range (TJ) 0 to 125C
P ackag e SO-28 Evaluation Board
SC1154CSW.TR SC1154EVB
Note: (1) Only available in tape and reel packaging. A reel contains 1000 devices.
(28-Pin SOIC)
Pin Descriptions
Pin # 1 Pin Name IOUT DROOP 2 3 4 5 6 7 8 9 10 11 12 13 OCP VHYST VREFB VSENSE AGND SOFTST NC LODRV LOHIB DRVGND LOWDR Pin Function Current Out. The output voltage on this pin is proportional to the load current as measured across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD. Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a function of load current. The voltage is set by a resistor divider between IOUT and AGND. Over Current Protection. This pin is used to set the trip point for over current protection by a resistor divider between IOUT and AGND. Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor divider between VREFB and AGND. Buffered Reference Voltage (from VID circuitry). Output Voltage Sense. Small Signal Analog and Digital Ground. Soft Start. Connecting a capacitor from this pin to AGND sets the time delay. Not connected. Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is grounded, this pin can be used to control LOWDR. Low Side Inhibit. This pin is used to eliminate shoot-thru current. Power Ground. Low Side Driver Output.
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SC1154
POWER MANAGEMENT Pin Descriptions (Cont.)
Pin # 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name DRV VIN12V BOOT HIGHDR BOOTLO HISENSE LOSENSE IOUTLO INHIBIT VID4 VID3 VID2 VID1 VID0 PWRGD Pin Function Drive Regulator for the MOSFET Drivers. 12V Supply. Bootstrap. This pin is used to generate a floating drive for the high side FET driver. High Side Driver Output. Bootstrap Low. In desktop applications, this pin connect to DRVGND. High Current Sense. Connected to the drain of the high side FET,or the input side of a current sense resistor between the input and the high side FET. Low Current Sense. Connected to the source of the high side FET, or the FET side of a current sense resistor between the input and the high side FET. This is the sampling capacitor bottom leg. Voltage on this pin is voltage on the LOSENSE pin when the high side FET is on. Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V through a pull-up resistor. Programming Input (MSB) Programming Input Programming Input Programming Input Programming Input (LSB) Power Good. This open collector logic output is high if the output voltage is within 5 - 10% of the set point.
PRELIMINARY
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POWER MANAGEMENT Block Diagram
PWRGD
IOUT
HISENSE
IOUTLO
LOSENSE
SOFTST
++ --
50uA G=2 ANALOG BIAS PREREG I(VREFB) / 5 FAULT
BANDGAP RISING EDGE DELAY
Vcc
VIN12V DRIVE REGULATOR DRV
R + -
Q
-
+
S
SHUTDOWN 1.15VREF 0.93VREF
HIGHDR LOWDR
FILTER
0.93VREF
BOOT
DEGLITCH
UVLO
+ + +
INH
10
VID DAC
DEGLITCH
HIGHD
-
+
-
+
BOOTL
10V +
FILTER
Vcc VREF
+
1.15VREF
FILTER
+ + -
LOWDR
VSENSE
DRVGN 2V
-
-
+
VREF
+
11111
DECODE
100mV
OCP
AGND
INHIBIT
VID0 VID2 VID4 VID1 VID3
DROOP
VSENSE
VHYST VREFB
LOHIB
LODRV
PRELIMINARY
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SC1154
SC1154
POWER MANAGEMENT Output Voltage Table
0 = GND; 1 = Floating or +5V pull-up
PRELIMINARY
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VIDO 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0
VD C (V) 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 NO CPU 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50
NOTE: (1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, and the controller will be set to a low-Iq state.
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SC1154
POWER MANAGEMENT Applications Information - .unctional Description
Reference/Voltage Identification The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID pins are TTL compatable inputs to the VID selection network. They are internally pulled up to +5V generated from the +12V supply by a resistor divider, and provide programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.3V to 2.05V in 50mV increments. Refer to the Output Voltage Table for the VID code settings. The output voltage of the VID network, VRE. is within 1% of the nominal setting over the full input and output voltage range and junction temperature range. The output of the reference/VID network is indirectly brought out through a buffer to the VRE.B pin. The voltage on this pin will be within 3mV of VRE.. It is not recommended to drive loads with VRE.B other than setting the hysteresis of the hysteretic comparator, because the current drawn from VRE.B sets the charging current for the soft start capacitor. Refer to the soft start section for additional information. Hysteretic Comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by connecting the center point of a resistor divider from VRE.B to AGND to the HYST pin. The hysteresis of the comparator will be equal to twice the voltage difference between VRE.B and HYST, and has a maximum value of 60mV. The maximum propagation delay from the comparator inputs to the driver outputs is 250ns. Low Side Driver The low side driver is designed to drive a low R DS(ON) N-channel MOS.ET, and is rated for 2 amps source and sink. The bias for the low side driver is provided internally from VDRV. High Side Driver The high side driver is designed to drive a low RDS(ON) N-channel MOS.ET, and is rated for 2 amps source and sink. It can be configured either as a ground referenced driver or as a floating bootstrap driver. When configured as a floating driver, the bias voltage to the driver is de 2001 Semtech Corp.
PRELIMINARY
veloped from the DRV regulator. The internal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 25V. The driver can be referenced to ground by connecting BOOTLO to PGND, and connecting +12V to the BOOT pin. Deadtime Control Deadtime control prevents shoot-through current from flowing through the main power .ETs during switching transitions by actively controlling the turn-on times of the .ET drivers. The high side driver is not allowed to turn on until the gate drive voltage to the low-side .ET is below 2 volts, and the low side driver is not allowed to turn on until the voltage at the junction of the two .ETs (VPHASE) is below 2 volts. An internal low-pass filter with an 11MHz pole is located between the output of the low-side driver (DL) and the input of the deadtime circuit that controls the high-side driver, to filter out noise that could appear on DL when the high-side driver turns on. Current Sensing Current sensing is achieved by sampling and holding the voltage across the high side .ET while it is turned on. The sampling network consists of an internal 50 switch and an external 0.1. hold capacitor. Internal logic controls the turn-on and turn-off of the sample/hold switch such that the switch does not turn on until VPHASE transitions high and turns off when the input to the high side driver goes low. Thus sampling will occur only when the high side .ET is conducting current. The voltage at the IOUT pin equals 2 times the sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high side .ET and the voltage across the sense resistor can be sampled by the current sensing circuit. Droop Compensation The droop compensation network reduces the load transient overshoot/undershoot at VOUT, relative to VRE.. VOUT is programmed to a voltage greater than VRE. equal to VRE. (1+R7/R8) (see Typ. App. Circuit, Pg 1) by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load
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SC1154
POWER MANAGEMENT Applications Information - .unctional Description (Cont.)
current transient. The overshoot during a high to low load current transient is reduced by subtracting the voltage that is on the DROOP pin from VRE.. The voltage on the IO pin is divided down with an external resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VOUT is regulated to: VOUT = VRE. (1+R7/R8) - IOUT R2/(R1+R2). Inhibit The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INHIBIT is low, the output drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the controller is in a low IQ state. When INHIBIT goes high, the short across the soft start capacitor is removed, the soft start current source is enabled, and normal converter operation begins. When the system logic supply is connected to INHIBIT, it controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the INHIBIT circuit; thus the +12V supply and the system logic supply (either +5V or 3.3V) must be above UVLO thresholds before the controller is allowed to start up. Vin The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start threshold during power-up. While the controller is disabled, the output drivers will be low, the soft start capacitor will be shorted and the soft start current is disabled and the controller will be in a low IQ state. When VIN exceeds the start threshold, the short across the soft start capacitor is removed, the soft start current source is enabled and normal converter operation begins. There is a 2V hysteresis in the undervoltage lockout circuit for noise immunity. Soft Start The soft start circuit controls the rate at which VOUT powers up. A capacitor is connected between SO.TST and AGND and is charged by an internal current source. The value of the current source is proportional to the reference voltage so the charging rate of CSS is also proportional to the reference voltage. By making the charging current proportional to VRE., the power-up time for VOUT
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PRELIMINARY
will be independent of VRE.. Thus, CSS can remain the same value for all VID settings. The soft start charging current is determined by the following equation: ISS = IRE.B/5. Where IRE.B is the current flowing out of the VRE.B pin. It is recommended that no additional loads be connected to VRE.B, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine the soft start charging current. The maximum current that can be sourced by VRE.B is 500A. Power Good The power good circuit monitors for an undervoltage condition on VOUT. If VSENSE is 7% (nominal) below VRE., then the power good pin is pulled low. The PWRGD pin is an open drain output. Overvoltage Protection The overvoltage protection circuit monitors VOUT for an overvoltage condition. If VSENSE is 15% above VRE., than a fault latch is set and both output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 2s deglitch timer is included for noise immunity. Overcurrent Protection The overcurrent protection circuit monitors the current through the high side .ET. The overcurrent threshold is adjustable with an external resistor divider between IOUT and AGND, with the divider voltage connected to the OCP pin. If the voltage on the OCP pin exceeds 100mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 2s deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high side .ET against a short-toground fault on the terminal common to both power .ETs (VPHASE). Drive Regulator The drive regulator provides drive voltage to the low side driver, and to the high side driver when the high side driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA.
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+5V
2001 Semtech Corp.
U1 SC1154
PWRGD PWRGD J0 GND INHIB C9 0.1 28 +12V IOUT R10 10k R11 1k
1
"POWER GOOD"
+12V
R1 2k DROOP J1 VID0 27 OCP J2 VID1 26
R3 4.3k
2
POWER MANAGEMENT Application Circuit
C1
C2
3
"INHIBIT"
R12 1k C10 0.1
0.001 VHYST J3 L1 23 0.5uH J4 POS/IN VID2 25
0.001
R2 1k 24
R4 1k
4
R5 82.5 VREFB VID3
C3 0.1
5
R6 20k VSENSE VID4
C4 0.1
6
+
Vin +5V/12V
7 AGND INHIBIT R13 0 R14,15,16 0
22
C5 0.001 SOFTST C11 0.033 R17 NS R18 NS D1 MBRA130L 18 Q1 R20 .DB6035AL 1.0 C33,34 +12V DRV R22 1.6 C14 2.2 Q4 .DB7030BL R23 1.6 VIN12V 15 Q3 .DB7030BL C13 1.0 0.0022 2pl. C12 22.0 R19 0 IOUTLO 21
C15-23 1.0
C24-32 820u. 16V
8
_
GND/IN
+5V 19
C6 0.1 N/C LOSENSE 20
9
R7 100 LODRV HISENSE
14
LOHIB BOOTLO DRVGND HIGHDR 17 Q2 R21 .DB6035AL 1.0 R24,25 3.3 2pl. LOWDR BOOT 16 R26,27 3.3 2pl. C35,36 0.0022 2pl. C59 1.0
10
C7 0.01
11
12
13
L2 1.0uH@40A
POS/OUT
+
C37-46 1500u. 6.3V D2 MBRB2515L
14
C47-58 10.0
Vout
C8 2.2
_
GND/OUT
R9 150
R8 10k
PRELIMINARY
40A+ Evaluation Board
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SC1154
SC1154
POWER MANAGEMENT Typical Characteristics
V IN = 5V; I OUT = 0A to 40A Droop & Offset Disabled V OUT = 1.5V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40
3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40
PRELIMINARY
Efficiency
V OUT = 2.0V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40
Efficiency
V OUT = 2.8V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 25 30 35 40 45 Current, A 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40
Efficiency
V OUT = 3.5V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 25 30 35 40 45 Current, A 3% 2% Regulation 1% 0% -1% -2% -3% 0 5 10 15 20 Current, A 25 30 35 40
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Efficiency
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SC1154
POWER MANAGEMENT Typical Characteristics
V IN = 12V; I OUT = 0A to 40A Droop & Offset Disabled V OUT = 1.5V
90.0% 80.0% 70.0% Efficiency 60.0% 50.0% 40.0% 30.0% 20.0% 10.0% 0.0% 0 5 10 15 20 25 30 35 40 45 Current, A Regulation 0.6% 0.5% 0.4% 0.3% 0.2% 0.1% 0.0% -0.1% 0 -0.2% -0.3% Current, A 10 20 30 40 50
PRELIMINARY
V OUT = 2.0V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% 1% 2% 3% 0 5 10 15 20 Current, A 25 30 35 40
Efficiency
V OUT = 2.8V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% 1% 2% 3% 0 5 10 15 20 Current, A 25 30 35 40
Efficiency
V OUT = 3.5V
100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 0 5 10 15 20 Current, A 25 30 35 40 3% 2% Regulation 1% 0% 1% 2% 3% 0 5 10 15 20 Current, A 25 30 35 40
Efficiency
2001 Semtech Corp.
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SC1154
POWER MANAGEMENT Evaluation Board Artwork
Top Layer
PRELIMINARY
Bottom Layer
Mid Layer
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SC1154
POWER MANAGEMENT Evaluation Board Artwork (Cont.)
Top Overlay
PRELIMINARY
Bottom Overlay
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SC1154
POWER MANAGEMENT Materials List
Quantity 3 6 1 1 11 2 9 10 12 4 1 1 1 1 2 2 1 4 1 1 1 1 2 1 2 2 4 1 Reference C1,C2,C5 C3,C4,C6,C7,C9,C10 C11 C 12 C13, C15-C23, C59 C8,C14 C 24 - C 32 C 37 - C 46 C 47 - C 58 C 33 - C 36 D1 D2 (optional) L1 L2 Q1,Q2 Q3,Q4 R1 R2,R4,R11,R12 R3 R5 R6 R7 R8,R10 R9 R20,R21 R22,R23 R24,R25,R26,R27 U1 Part/Description 0.001F 0.1F 0.033F 22F 1F 2.2F 820F, 16V 1500F, 6.3V, thru hole 10F .0022F MBRA130L. Schottky MBRB2515L 0.5uH, Toroid 1.0uH, Toroid D2Pak, MOSFET D2Pak, MOSFET 2k 1k 4.3k 68.1 20k 100 10k 150 1 1.6 3.3 SC1154CSW.TR Vendor TDK, Murata, Taiyo-Yuden any any any any any SANYO P/N: 16MV820AX SANYO P/N: 6R3MV1500AX any any ON Semi ON Semi Micrometals P/N: T51-26C, 18 AWG Magnetics, #77310, 3ts, 4 X 20 AWG Fairchild P/N: FDB6035AL Fairchild P/N: FDB7030BL any any any any any any any any any any any Semtech Corp. 805-498-2111
PRELIMINARY
2001 Semtech Corp.
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SC1154
POWER MANAGEMENT Layout Guidelines (See pg. 1)
1. Locate R8 and C5 close to pins 6 and 7.
2. Locate C6 close to pins 5 and 7. 3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND. 4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND. 5. Locate bootstrap capacitor C13 close to the IC. 6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective. 7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise. 8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin. 9. Input bulk capacitors should be placed as close as possible to the power FETs because of the very high ripple current flow in this path.
PRELIMINARY
10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower Vout settings, it needs to be placed next to the aforementioned FET in very close proximity. 11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be achieved by connecting the AGND to the ground side of the bulk output capacitors. 12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple vias. 13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the chip with the cathode connected to BOOTLO and anode connected to DRVGND.
Outline Drawing - SO-28
Contact Information
Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 .AX (805)498-3804
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