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preliminary information amd k86 family bios and software tools developers guide tm
? 1997 advanced micro devices, inc. all rights reserved. advanced micro devices, inc. ("amd") reserves the right to make changes in its products without notice in order to improve design or performance characteristics. the information in this publication is believed to be accurate at the time of publication, but amd makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. amd disclaims responsibility for any consequences resulting from the use of the information included in this publication. this publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of merchantability or fitness for a particular purpose. amd products are not authorized for use as critical components in life support devices or systems without amds written approval. amd assumes no liability whatsoever for claims associated with the sale or use (including the use of engineering samples) of amd products except as provided in amds terms and conditions of sale for such product. trademarks amd, the amd logo, and the combinations thereof are trademarks of advanced micro devices, inc. am386, am486, and risc86 are registered trademarks; k86, amd-k5, amd-k6, and the amd-k6 logo are trademarks of advanced micro devices, inc. mmx is a trademark and pentium is a registered trademark of the intel corporation. other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. preliminary information
contents iii 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information contents 1 introduction 1 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 cpu identification algorithms 3 3 amd-k5? processor 5 bios consideration checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 amd-k5 processor system management mode (smm) . . . . . . . . . . . 7 operating mode and default register values . . . . . . . . . . . . . . . . . . . 7 smm initial register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 smm state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 smm base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 auto halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 i/o trap restart slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 exceptions and interrupts in smm . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 amd-k5 processor reset state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 segment register attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 state of the amd-k5 processor after init . . . . . . . . . . . . . . . . . . . . 20 amd-k5 processor test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . 21 hardware configuration register (hwcr) . . . . . . . . . . . . . . . . . . . . 22 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 normal bist. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 test access port (tap) bist . . . . . . . . . . . . . . . . . . . . . . . . . . 26 output-float test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
iv contents amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information cache and tlb testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 array access register (aar) . . . . . . . . . . . . . . . . . . . . . . . . . 28 array pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 array test data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 standard debug functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 i/o breakpoint extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 debug compatibility with the pentium processor. . . . . . . . . 39 branch tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 functional-redundancy checking . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 boundary scan architecture support . . . . . . . . . . . . . . . . . . . . . . . . . 41 boundary scan test functional description . . . . . . . . . . . . . 42 boundary scan architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 42 registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 jtag register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 44 public instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 hardware debug tool (hdt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 amd-k5 processor x86 architecture extensions . . . . . . . . . . . . . . . 57 additions to the eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 control register 4 (cr4) extensions . . . . . . . . . . . . . . . . . . . . . . . . . 58 machine-check exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4-mbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 global pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 virtual-8086 mode extensions (vme) . . . . . . . . . . . . . . . . . . 67 protected virtual interrupt (pvi) extensions . . . . . . . . . . . . 79 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 machine-check address register (mcar) . . . . . . . . . . . . . . 80 machine-check type register (mctr) . . . . . . . . . . . . . . . . . 80 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 array access register (aar) . . . . . . . . . . . . . . . . . . . . . . . . . 82 hardware configuration register (hwcr) . . . . . . . . . . . . . . 82 write allocate registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 enable write allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 new amd-k5 processor instructions . . . . . . . . . . . . . . . . . . . . . . . . . 85 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 cmpxchg8b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 mov to and from cr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 rdtsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 rdmsr and wrmsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 rsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 illegal instruction (reserved opcode) . . . . . . . . . . . . . . . . . . . . . . . . 93
contents v 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 4 amd-k6? mmx? enhanced processor 95 bios consideration checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 model-specific registers (msrs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 smm issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 amd-k6 processor system management mode . . . . . . . . . . . . . . . . . 97 initial register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 smm state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 smm base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 auto halt restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 i/o trap restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 exceptions and interrupts within smm . . . . . . . . . . . . . . . . . . . . . . 101 amd-k6 processor reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 segment register attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 state of the amd-k6 processor after init . . . . . . . . . . . . . . . . . . . 104 amd-k6 processor cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 amd-k6 processor test and debug . . . . . . . . . . . . . . . . . . . . . . . . . 105 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 boundary-scan test access port (tap) . . . . . . . . . . . . . . . . . . . . . . 107 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 l1 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 amd-k6 processor x86 architecture extensions . . . . . . . . . . . . . . 117 model-specific registers (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 machine-check address register (mcar) . . . . . . . . . . . . . 117 machine-check type register (mctr) . . . . . . . . . . . . . . . . 117 test register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 time stamp counter (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . 118
vi contents amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information extended feature enable register (efer). . . . . . . . . . . . . 118 syscall target address register (star) . . . . . . . . . . . . 118 write handling control register (whcr). . . . . . . . . . . . . . 119 machine check exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 new amd-k6 processor instructions . . . . . . . . . . . . . . . . . . . . . . . . 122 system call extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 syscall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 sysret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 mmx? instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 index 129
list of figures vii 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information list of figures figure 1. smm memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. hardware configuration register (hwcr) . . . . . . . . . . . . . . . 23 figure 3. array access register (aar) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. test formats: dcache tags for the amd-k5 processor model 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5. test formats: dcache tags for the amd-k5 processor model 1 and greater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. test formats: dcache data for all models of the amd-k5 processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. test formats: icache tags for the amd-k5 processor model 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 8. test formats: icache tags for the amd-k5 processor model 1 and greater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 9. test formats: icache instructions for the amd-k5 processor model 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 10. test formats: icache instructions for the amd-k5 processor model 1 and greater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11. test formats: 4-kbyte tlb for all models of the amd-k5 processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. test formats: 4-mbyte tlb for all models of the amd-k5 processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 13. control register 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 14. 4-kbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 15. 4-mbyte paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 16. page-directory entry (pde) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 17. page-table entry (pte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 18. eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 19. task state segment (tss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 20. machine-check address register (mcar) . . . . . . . . . . . . . . . . 80 figure 21. machine-check type register (mctr) . . . . . . . . . . . . . . . . . . . 81 figure 22. write allocate top-of-memory and control register (watmcr)msr 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 23. write allocate programmable memory range register (wapmrr)msr 86h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 24. debug register dr7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 25. debug register dr6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 26. debug registers dr5 and dr4. . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 27. debug registers dr3, dr2, dr1, and dr0. . . . . . . . . . . . . . . 116
viii list of figures amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 28. extended feature enable register (efer) . . . . . . . . . . . . . . 118 figure 29. syscall target address register (star) . . . . . . . . . . . . . . 119 figure 30. write handling control register (whcr) msr c000_0082h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
list of tables ix 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information list of tables table 1. summary of amd-k5 processor cpu ids and bios boot strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 2. summary of amd-k6 mmx enhanced processor cpu ids and bios boot strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 3. initial state of registers in smm . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. smm state-save area map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. smm revision identifier fields . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. i/o trap dword fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. i/o trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8. summary of interrupts and exceptions . . . . . . . . . . . . . . . . . . . 17 table 9. state of the amd-k5 processor after reset. . . . . . . . . . . . . . 18 table 10. segment register attribute fields initial values . . . . . . . . . . 20 table 11. hardware configuration register (hwcr) fields. . . . . . . . . . 23 table 12. bist error bit definition in eax register . . . . . . . . . . . . . . . . 25 table 13. array ids in array pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. branch-trace message special bus cycle fields . . . . . . . . . . . 39 table 15. amd-k5 processor device identification register . . . . . . . . . 45 table 16. public tap instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 17. control bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18. boundary scan register bit definitions . . . . . . . . . . . . . . . . . . 49 table 19. control register 4 (cr4) fields . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 20. page-directory entry (pde) fields . . . . . . . . . . . . . . . . . . . . . . 64 table 21. page-table entry (pte) fields . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 22. virtual-interrupt additions to eflags register . . . . . . . . . . 71 table 23. instructions that modify the if or vif flagsreal mode . . . 71 table 24. instructions that modify the if or vif flagsprotected mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 25. instructions that modify the if or vif flagsvirtual-8086 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 26. instructions that modify the if or vif flagsvirtual-8086 mode interrupt extensions (vme). . . . . . . . . . . . . . . . . . . . . . . 74 table 27. instructions that modify the if or vif flagsprotected mode virtual interrupt extensions (pvi) . . . . . . . . . . . . . . . . . 75 table 28. interrupt behavior and interrupt-table access . . . . . . . . . . . . 78 table 29. machine-check type register (mctr) fields . . . . . . . . . . . . . 81 table 30. initial state of registers in smm . . . . . . . . . . . . . . . . . . . . . . . . 97 table 31. amd-k6 processor state-save map . . . . . . . . . . . . . . . . . . . . . . 98 table 32. smm revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 33. amd-k6 processor i/o trap dword configuration. . . . . . . . . 101 table 34. state of the amd-k6 processor after reset. . . . . . . . . . . . . 102 table 35. data returned by the cpuid instruction . . . . . . . . . . . . . . . . 105 table 36. boundary scan register bit definitions . . . . . . . . . . . . . . . . . 109 table 37. amd-k6 processor device identification register . . . . . . . . 110
x list of tables amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information table 38. supported tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 39. dr7 len and rw definitions . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 40. extended feature enable register (efer) definition . . . . . 118 table 41. syscall target address register (star) definition. . . . . 119 table 42. mmx instructions and descriptions. . . . . . . . . . . . . . . . . . . . . 127
revision history xi 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information revision history date rev description sept 1996 a initial release mar 1997 b added write allocation information for k86 family of processors. see write allocate registers on page 82 for information about the amd-k5 processor and write handling control register (whcr) on page 119 for information about the amd-k6? mmx? enhanced processor. mar 1997 b added test and debug section for the amd-k6 mmx enhanced processor. see amd-k6? proces- sor test and debug on page 105 for more information. mar 1997 c reorganized entire guide apr 1997 d changed bios boot string for the amd-k6 processor in table 2, summary of amd-k6? mmx? enhanced processor cpu ids and bios boot strings, on page 4. june 1997 e revised document to comply with mmx trademark. june 1997 e replaced overbar with # to identify active-low signals. june 1997 e revised information in write handling control register (whcr) on pages 119 through 121. june 1997 e added (tm) to recommended boot-string for the amd-k6 mmx enhanced processor on pages 3, 4, and 95.
xii revision history amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information
introduction 1 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 1 introduction this document highlights the bios and software modifications r equired to fully support the k86? family of processors, which includes the amd-k5? processor and the amd-k6? mmx? enhanced processor. there can be more than one way to implement the functionality detailed in this document, and the information provided is for demonstration purposes. audience it is assumed that the reader possesses the proper knowledge of the k86 processors, the x86 architecture, and programming requirements to understand the information presented in this document.
2 introduction amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information
cpu identification algorithms 3 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 2 cpu identification algorithms the cpuid instruction provides complete information about the processor (vendor, type, name, etc.) and its capabilities (features). after detecting the processor and its capabilities, software can be accurately tuned to the system for maximum performance and benefit to users. for example, game software can test the performance level available from a particular processor by detecting the type or speed of the processor. if the performance level is high enough, the software can enable additional capabilities or more advanced algorithms. another example involves testing whether the processor supports mmx? technology. if the software finds this feature present when it checks the feature bits, it can utilize these more powerful instructions for better performance on new multimedia software. for more detailed information refer to the amd processor recognition application note , order# #20734, located at http://www.amd.com tables 1 and 2 outline the family codes and model codes for the amd k86 processors. table 1 shows the cpu speed, the p-rating, and the recommended bios boot-string associated with each amd-k5 processor. table 2 shows the recommended bios boot-string for the amd-k6 mmx enhanced processor. this recommended boot-string is amd-k6(tm)/xxx. the value for xxx is
4 cpu identification algorithms amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information determined by calculating the core frequency of the processor. use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. note: tables 1 and 2 contain information intended to prepare the infrastructure for potential future products. these products may or may not be announced, but bios software should be prepared to support these options. table 1. summary of amd-k5? processor cpu ids and bios boot strings instruction family code model code cpu speed (mhz) cpu bus speed (mhz) recommended bios boot-string cpuid functions 8000_0002, 3, 4 return values 5 (amd-k5? processor) 0 75 50 amd-k5-pr75 undefined 90 60 amd-k5-pr90 undefined 100 66 amd-k5-pr100 undefined 1 90 60 amd-k5-pr120 amd-k5(tm) processor 100 66 amd-k5-pr133 amd-k5(tm) processor 2 105 60 amd-k5-pr150 amd-k5(tm) processor 116.7 66 amd-k5-pr166 amd-k5(tm) processor 3 133 66 amd-k5-pr200 amd-k5(tm) processor table 2. summary of amd-k6? mmx? enhanced processor cpu ids and bios boot strings instruction family code model code cpu speed (mhz) cpu bus speed (mhz) recommended bios boot-string display 5 (amd-k6? mmx? enhanced processor) 6 tbd 60 amd-k6(tm)/xxx tbd 66 amd-k6(tm)/xxx
amd-k5? processor 5 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 3 amd-k5? processor the amd-k5 processor is socket 7-compatible and software-compatible with the pentium ? processor. compatible in this sense means the devices are pin-for-pin compatible and that the same software can be executed on both processors with no software modifications. the bios for the amd-k5 processor requires minimal changes to fully support the amd-k5 processor family. bios consideration checklist cpuid n use the cpuid instruction to properly identify the amd-k5 processor. n determine the processor type, stepping and features using functions 0000_0001h and 8000_0001h of the cpuid instruction. n boot-up display: the processor name is retrieved using cpuid extended functions 8000_0002h, 8000_0003h, and 8000_0004h. see cpu identification algorithms on page 3 for more information.
6 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information cpu speed detection n use speed detection algorithms that do not rely on repetitive instruction sequences. n use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. see the example of frequency-determination assembler code available on the amd website at http://www.amd.com. n display the p-rating shown in table 1, summary of amd-k5? processor cpu ids and bios boot strings, on page 4. model-specific registers (msrs) n access only msrs implemented in the amd-k5 processor. n program the write allocate registershardware configuration register (hwcr), write allocate top-of-memory and control register (watmcr), and write allocate programmable memory range register (wapmrr). see write allocate registers on page 82 and the implementation of write allocate in the k86? processors application note , order# 21326 for more information. cache testing n perform cache testing on the amd-k5 processor using the array access register msr. see array access register (aar) on page 28 for more information. smm issues n the system management mode (smm) functionality of the amd-k5 processor is identical to pentium. n implement the amd-k5 processor smm state-save area in the same manner as pentium except for the idt base and possibly pentium processor-reserved areas. see amd-k5? processor system management mode (smm) on page 7 for more information.
amd-k5? processor 7 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information amd-k5? processor system management mode (smm) system management mode (smm) is an alternate operating mode entered by way of a system management interrupt (smi) and handled by an interrupt service routine. smm is designed for system control activities such as power management. these activities appear transparent to conventional operating systems like dos and windows. smm is primarily targeted for use by the basic input output system (bios) and specialized low-level device drivers. the code and data for smm are stored in the smm memory area, which is isolated from main memory. the processor enters smm by the system logics assertion of the smi# interrupt and the processors acknowledgment by the assertion of smiact#. at this point the processor saves its state into the smm memory state-save area and jumps to the smm service routine. the processor returns from smm when it executes the rsm (resume) instruction from within the smm service routine. subsequently, the processor restores its state from the smm save area, de-asserts smiact#, and resumes execution with the instruction following the point where it entered smm. the following sections summarize the smm state-save area, entry into and exit from smm, exceptions and interrupts in smm, memory allocation and addressing in smm, and the smi# and smiact# signals. operating mode and default register values the software environment within smm has the following characteristics: n addressing and operation in real mode n 4-gbyte segment limits n default 16-bit operand, address, and stack sizes, although instruction prefixes can override these defaults n control transfers that do not override the default operand size truncate the eip to 16 bits n far jumps or calls cannot transfer control to a segment with a base address requiring more than 20 bits, as in real mode segment-base addressing
8 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information n a20m# is masked n interrupt vectors use the real-mode interrupt vector table n the if flag in eflags is cleared (intr not recognized) n the tf flag in eflags is cleared n the nmi and init interrupts are disabled n debug register dr7 is cleared (debug traps disabled) figure 1 shows the default map of the smm memory area. it consists of a 64-kbyte area, between 0003_0000h and 0003_ffffh, of which the top 32 kbytes (0003_8000h to 0003_ffffh) must be populated with ram. the default code-segment (cs) base address for the areacalled the smm base addressis at 0003_0000h. the top 512 bytes (0003_fe00h to 0003_ffffh) contain a fill-down smm state-save area. the default entry point for the smm service routine is 0003_8000h. figure 1. smm memory smm state-save area smm base address (cs) service routine entry point fill down smm service routine 32-kbyte minimum ram 0003_8000h 0003_fe00h 0003_ffffh 0003_0000h
amd-k5? processor 9 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information smm initial register values table 3 shows the initial state of registers when entering smm. smm state-save area when the processor acknowledges an smi interrupt by asserting smiact#, it saves its state in the 512-byte smm state-save area shown in table 4. the save begins at the top of the smm memory area (smm base address + ffffh) and fills down to smm base address + fe00h. table 4 shows the offsets in the smm state-save area relative to the smm base address. the smm service routine can alter any of the read and write values in the state-save area. the contents of any reserved locations in the state-save area are not necessarily the same between the amd-k5 processor and pentium or 486 processors. table 3. initial state of registers in smm register initial contents selector base limit cs 3000h 0003_0000h 4 gbytes ds 0000h 0000_0000h 4 gbytes es 0000h 0000_0000h 4 gbytes fs 0000h 0000_0000h 4 gbytes gs 0000h 0000_0000h 4 gbytes ss 0000h 0000_0000h 4 gbytes general-purpose registers unmodified eflags 0000_0002h eip 0000_8000h cr0 bits 0, 2, 3, and 31 cleared (pe, em, ts, and pg); remainder are unmodified cr4 0000_0000h gdtr unmodified ldtr unmodified idtr unmodified tr unmodified dr7 0000_0400h dr6 undefined
10 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information table 4. smm state-save area map offset (hex) contents fffc cr0 fff8 cr3 fff4 eflags fff0 eip ffec edi ffe8 esi ffe4 ebp ffe0 esp ffdc ebx ffd8 edx ffd4 ecx ffd0 eax ffcc dr6 (ffff_cff3h) ffc8 dr7 ffc4 tr ffc0 ldtr ffbc gs ffb8 fs ffb4 ds ffb0 ss ffac cs ffa8 es ffa4 i/o trap dword ffa0 reserved ff9c i/o trap eip ff98 reserved ff94 reserved ff90 idt base ff8c idt limit ff88 gdt base ff84 gdt limit ff80 tss attributes ff7c tss base ff78 tss limit
amd-k5? processor 11 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information ff74 ldt attributes ff70 ldt base ff6c ldt limit ff68 gs attributes ff64 gs base ff60 gs limit ff5c fs attributes ff58 fs base ff54 fs limit ff50 ds attributes ff4c ds base ff48 ds limit ff44 ss attributes ff40 ss base ff3c ss limit ff38 cs attributes ff34 cs base ff30 cs limit ff2c es attributes ff28 es base ff24 es limit ff20 reserved ff1c reserved ff18 reserved ff14 cr2 ff10 cr4 ff0c i/o restart esi ff08 i/o restart ecx ff04 i/o restart edi ff02 halt restart slot ff00 i/o trap restart slot fefc smm revision identifier fef8 smm base address fe00Cfef4 reserved table 4. smm state-save area map (continued) offset (hex) contents
12 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information smm revision identifier the smm revision identifier at offset fefch in the smm state-save area specifies the version of smm and the extensions available on the processor. the smm revision identifier fields, shown in table 5, are as follows: n bits 31C18 reserved n bit 17 smm base address relocation (always 1 = enabled) n bit 16 i/o trap restart (always 1 = enabled) n bits 15C0 smm revision level = 0000 note: the i/o trap restart and the smm base address relocation functions are always enabled in the amd-k5 processor and do not need to be specifically enabled. smm base address during reset, the processor sets the code-segment (cs) base address for the smm memory areathe smm base address to its default, 0003_0000h. the smm base address at offset fef8h in the smm state-save area can be changed by the smm service routine to any address aligned to a 32-kbyte boundary. (locations not aligned to a 32-kbyte boundary cause the processor to enter the shutdown state when executing the rsm instruction.) in some operating environments it may be desirable to relocate the 64-kbyte smm memory area to a high memory area to provide more low memory for legacy software. during system initialization, the base of the 64-kbyte smm memory area is relocated by the bios. to relocate the smm base address, the system enters the smm handler at the default address. this handler changes the smm base address location in the smm state-save area, copies the smm handler to the new location, and exits smm. table 5. smm revision identifier fields bits 31C18 bit 17 bit 16 bits 15C0 reserved smm base relocation i/o trap extension smm revision level 0 1 1 0000
amd-k5? processor 13 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information the next time smm is entered, the processor saves its state at the new base address. this new address is used for every smm until the smm base address in the smm state-save area is changed or a hardware reset occurs. auto halt restart slot during entry into smm, the halt restart slot at offset ff02h in the smm state-save area indicates whether smm was entered from the halt state. before returning from smm, the halt restart slot can be written to by the smm service routine to specify whether the return from smm should take the processor back to the halt state or to the instruction-execution state specified by the smm state-save area. on entry into smm, the halt restart slot is configured as follows: n bits 15C1 undefined n bit 0 point of entry to smm: 1 = entered from halt state 0 = not entered from halt state after entry into the smi handler and before returning from smm, the halt restart slot can be written using the following definition: n bits 15C1 undefined n bit 0 point of return from smm 1 = return to halt state 0 = return to state specified by smm state-save area if the return from smm takes the processor back to the halt state, the hlt instruction is not re-executed, but the halt special bus cycle is driven on the bus after the return.
14 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information i/o trap dword if the assertion of smi is recognized on the boundary of an i/o instruction, the i/o trap dword at offset ffa4h in the smm state-save area contains information about the instruction. the fields of the i/o trap dword, shown in table 6, are configured as follows: n bits 31C16 i/o port address n bit 15 i/o string operation (1 = string, 0 = non-string) n bits 14C2 reserved n bit 1 valid i/o instruction (1 = valid, 0 = invalid) n bit 0 input or output instruction (1 = inx, 0 = outx) the i/o trap dword is related to the i/o trap restart slot, described below. bit 1 of the i/o trap dword (the valid bit) should be tested if the i/o trap restart slot is to be changed. i/o trap restart slot the i/o trap restart slot at offset ff00h in the smm state-save area specifies whether the trapped i/o instruction should be re-executed on return from smm. this slot in the state-save area is called the i/o instruction restart function. re-executing a trapped i/o instruction is useful, for example, if an i/o write occurs to a disk that is powered down. the system logic monitoring such an access can assert smi#. then the smm service routine can query the system logic, detect a failed i/o write, take action to power-up the i/o device, enable the i/o trap restart slot feature, and return from smm. table 6. i/o trap dword fields bits 31C16 bit 15 bit 14C2 bit 1 bit 0 i/o port address i/o string operation reserved valid i/o instruction input or output
amd-k5? processor 15 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information the fields of the i/o trap restart slot are defined as follows: n bits 31C16 reserved n bits 15C0 i/o instruction restart on return from smm: 0000h = execute the next instruction after the trapped i/o instruction 00ffh = re-execute the trapped i/o instruction table 7 shows the format of the i/o trap restart slot. the processor initializes the i/o trap restart slot to 0000h upon entry into smm. if smm is entered as a result of a trapped i/o instruction, the processor indicates the validity of the i/o instruction by setting or clearing bit 1 of the i/o trap dword at offset ffa4h in the smm state-save area. the smm service routine should test bit 1 of the i/o trap dword to determine if a valid i/o instruction was being executed when entering smm and before writing the i/o trap restart slot. if the i/o instruction is valid, the smm service routine can safely rewrite the i/o trap restart slot with the value 00ffh, causing the processor to re-execute the trapped i/o instruction when the rsm instruction is executed. if the i/o instruction is invalid, writing the i/o trap restart slot has undefined results. if a second smi# is asserted and a valid i/o instruction was trapped by the first smm handler, the cpu services the second smi# prior to re-executing the trapped i/o instruction. the second entry into smm never has bit 1 of the i/o trap dword set, and the second smm service routine must not rewrite the i/o trap restart slot. during a simultaneous smi# i/o instruction trap and debug breakpoint trap, the amd-k5 processor first responds to the smi# and postpones recognizing the debug exception until after returning from smm via the rsm instruction. if the debug registers dr3Cdr0 are used while in smm, they must be saved table 7. i/o trap restart slot 31C16 15C0 reserved i/o instruction restart on return from smm: n 0000h = execute the next instruction after the trapped i/o instruction n 00ffh = re-execute the trapped i/o instruction
16 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information and restored by the smm handler. the processor automatically saves and restores dr7Cdr6. if the i/o trap restart slot in the smm state-save area contains the value 00ffh when the rsm instruction is executed, the debug trap does not occur until after the i/o instruction is re-executed. exceptions and interrupts in smm when smm is entered, the processor disables both intr and nmi interrupts. the processor disables intr interrupts by clearing the if flag in the eflags register. to enable intr interrupts within smm, the smm handler must set the if flag to 1. generating an intr interrupt is a method for unmasking nmi interrupts in smm. the processor recognizes the assertion of nmi within smm immediately after the completion of an iret. the nmi can thus be enabled by using a dummy intr interrupt. once nmi is recognized within smm, nmi recognition remains enabled until smm is exited, at which point nmi masking is restored to the state it was in before entering smm. because the if flag is cleared when entering smm, the hlt instruction should not be executed in smm without first setting the if bit to 1. setting this bit to 1 enables the processor to exit the halt state by means of an intr interrupt. table 8 summarizes the behavior of all interrupts in smm.
amd-k5? processor 17 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information table 8. summary of interrupts and exceptions priority description type sampling 5 vector 1 acknowledgment point of interruptibility 6 1 intn instruc- tions and all other software exceptions exceptions internal 0C255 none entry to service routine 2 buschk# interrupt level-sensitive 18 2 none entry to service routine 2 3 r/s# interrupt level-sensitive none prdy negation of prdy 4 flush# interrupt edge-triggered 4 none flush#-acknowl- edge special bus cycle brdy# of flush# acknowledge bus cycle 5 smi# interrupt edge-triggered 4 smm 3 smiact# entry to smm service routine 7 6 init interrupt edge-triggered 4 bios none completion of initialization 7 nmi interrupt edge-triggered 4 2 none nmi interrupts: iret from service routine. all others: entry to service routine. 8 intr interrupt level-sensitive 0C255 interrupt acknowl- edge special bus cycle entry to service routine 9 stpclk# interrupt level-sensitive none stop-grant special bus cycle negation of stpclk# notes: 1. for interrupts with vectors, the processor saves its state prior to accessing the service routine and changing the program flow. interrupts without vectors do not change program flow; instead, they simply pause program flow for the duration of the interrupt function and return to where they left off. 2. if the machine check enable (mce) bit in cr4 is set to 1. 3. the entry point for the smi interrupt handler is at offset 8000h from the smm base address. 4. only the edge-triggered interrupts are latched when asserted. all interrupts are recognized at the next instruction retirement boundary. 5. if a bus cycle is in progress, ewbe must be asserted before the interrupt is recognized. 6. for external interrupts (most exceptions, by contrast, are recognized when they occur). external interrupts are recognized at instruction boundaries. when mov or pop instructions load ss, interruptibility is delayed until after the next instruction, thus allowing both ss and the corresponding sp to load. 7. after assertion of smi, subsequent assertions of smi are masked to prevent recursive entry into smm. however, other exceptions or interrupts (except init and nmi) are taken in the smm service routine.
18 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information amd-k5? processor reset state the state of all architecture registers and model-specific registers (msrs) after the amd-k5 processor has completed its initialization due to the recognition of the assertion of reset are shown in table 9. table 9. state of the amd-k5? processor after reset register reset state notes gdtr base:0000_0000 limit:0000h idtr base:0000_0000 limit:0000h tr 0000h ldtr 0000h eip ffff_fff0h eflags 0000_0002h eax 0000_0000h 1 ebx 0000_0000h ecx 0000_0000h edx 0000_05xxh 2 esi 0000_0000h edi 0000_0000h ebp 0000_0000h esp 0000_0000h cs f000h ss 0000h ds 0000h es 0000h fs 0000h gs 0000h fpu stack r7Cr0 0000_0000_0000_0000_0000h notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, then bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k5 processor signature, which is comprised of the instruction family, model, and stepping. 3. these msrs are described in amd-k5? processor x86 architecture extensions on page 57. 4. the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater.
amd-k5? processor 19 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information fpu control word 0040h fpu status word 0000h fpu tag word 5555h fpu instruction pointer 0000_0000_0000h fpu data pointer 0000_0000_0000h fpu opcode register 000_0000_0000b cr0 6000_0010h cr2 0000_0000h cr3 0000_0000h cr4 0000_0000h dr7 0000_0400h dr6 ffff_0ff0h dr3 0000_0000h dr2 0000_0000h dr1 0000_0000h dr0 0000_0000h mcar 0000_0000_0000_0000h mctr 0000_0000_0000_0000h tr12 0000_0000_0000_0000h tsc 0000_0000_0000_0000h aar 0000_0000_0000_0000h 3 hwcr 0000_0000_0000_0000h 3 watmcr 0000_0000_0000_0000h 3, 4 wapmrr 0000_0000_000f_000ah 3, 4 table 9. state of the amd-k5? processor after reset (continued) register reset state notes notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, then bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k5 processor signature, which is comprised of the instruction family, model, and stepping. 3. these msrs are described in amd-k5? processor x86 architecture extensions on page 57. 4. the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater.
20 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information segment register attributes the selector portion of all segment registers is cleared. the access rights and attribute fields are set up as shown in table 10. the limit fields are set to ffffh. for cs, the base address is set to ffff_0000h; for all others the base address is 0. note that idtr and gdtr consist of the just base and limit values, which are initialized to 0 and ffffh, respectively. s tate of the amd-k5? processor after init the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the smm base, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. table 10. segment register attribute fields initial values attribute field value description g 0 byte granularity d/b 0 16-bit p 1 present dpl 0 privilege level s 1 application segment (except ldtr) type 2 data, read-write
amd-k5? processor 21 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information amd-k5? processor test and debug the amd-k5 processor has the following modes in which processor and system operation can be tested or debugged: n hardware configuration register (hwcr) the hwcr is a msr that contains configuration bits that enable cache, branch tracing, debug, and clock control functions. n built-in self-test (bist) both normal and test access port (tap) bist. n output-float test a test mode that causes the amd-k5 processor to float all of its output and bidirectional signals. n cache and tlb testing the array access register (aar) supports writes and reads to any location in the tag and data arrays of the processors on-chip caches and tlbs. n debug registers standard 486 debug functions with an i/o-breakpoint extension. n branch tracing a pair of special bus cycles can be driven immediately after taken branches to specify information about the branch instruction and its target. the hardware configuration register (hwcr) provides support for this and other debug functions. n functional redundancy checking support for real-time testing that uses two processors in a master-checker relationship. n test access port (tap) boundary-scan testing the jtag test access functions defined by the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. n hardware debug tool (hdt) the hardware debug tool (hdt), sometimes referred to as the debug port or probe mode, is a collection of signals, registers, and processor microcode enabled when external debug logic drives r/s low or loads the amd-k5 processors test access port (tap) instruction register with the usehdt instruction.
22 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information the test-related signals are described in chapter 5 of the amd-k5? processor technical reference manual , order# 18524. the signals include the following: n flush n frcmc n ierr n init n prdy n r/s n reset n tck n tdi n tdo n tms n trst the sections that follow provide details on each of the test and debug features. hardware configuration register (hwcr) the hardware configuration register (hwcr) is a msr that contains configuration bits that enable cache, branch tracing, write allocation, debug, and clock control functions. the wrmsr and rdmsr instructions access the hwcr when the ecx register contains the value 83h, as described on page 90. figure 2 and table 11 show the format and fields of the hwcr.
amd-k5? processor 23 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 2. hardware configuration register (hwcr) table 11. hardware configuration register (hwcr) fields bit mnemonic description function 31C8 reserved 7 ddc disable data cache disables data cache 0 = enabled, 1 = disabled 6 dic disable instruction cache disables instruction cache 0 = enabled, 1 = disabled 5 dbp disable branch prediction disables branch prediction 0 = enabled, 1 = disabled 4 wa* enable write allocate enables write allocation 0 = disabled, 1 = enabled note: * the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater. 876543210 31 d i c d d c d b p d c d s p c reserved w a symbol description bits ddc disable data cache 7 dic disable instruction cache 6 dbp disable branch prediction 5 wa write allocate enable 4 dc debug control 3C1 000 off 001 enable branch trace usages dspc disable stopping processor clocks 0
24 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information built-in self-test (bist) the processor supports the following types of built-in self-test: n normal bist a built-in self-test mode typically used to test system functions after reset n test access port (tap) bist a self-test mode started by the tap instruction, runbist all internal arrays except the tlb are tested in parallel by hardware. the tlb is tested by microcode. the amd-k5 processor does not report parity errors on ierr for every cache or tlb access. instead, the amd-k5 fully tests its caches during the bist. eads should not be asserted during a bist. the amd-k5 accesses the physical tag array during bists, and these accesses can conflict with inquire cycles. 3C1 dc debug control debug control bits: 000 off (disable hwcr debug control) 001 enable branch-tracing messages. see branch tracing on page 39. 010 reserved 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved 0dspc disable stopping processor clocks disables stopping of internal processor clocks in the halt and stop grant states 0 = enabled, 1 = disabled table 11. hardware configuration register (hwcr) fields (continued) bit mnemonic description function note: * the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater.
amd-k5? processor 25 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information normal bist the normal bist is invoked if init is asserted at the falling edge of reset. the bist runs tests on the internal hardware that exercise the following resources: n instruction cache: ? linear tag directory ? instruction array ? physical tag directory n data cache: ? linear tag directory ? data array ? physical tag directory n entry-point and instruction-decode plas n microcode rom n tlb the bist runs a linear feedback shift register (lfsr) signature test on the microcode rom in parallel with a march c test on the instruction cache, data cache, and physical tags. this is followed by the march c test on the tlb arrays and an lfsr signature test on the pla, in that order. upon completion of the pla test, the processor transfers the test result from an internal hardware debug test (hdt) data register to the eax register for external access, resets the internal microcode, and begins normal code fetching. the result of the bist can be accessed by reading the lower 9 bits of the eax register. if the eax register value is 0000_0000h, the test completed successfully. if the value is not zero, the non-zero bits indicate where the failure occurred, as shown in table 12. the processor continues with its normal boot process after the bist is completed, whether the bist passed or failed. table 12. bist error bit definition in eax register bit number bit value 01 31C9 no error always 0 8 no error data path 7 no error instruction-cache instructions
26 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information test access port (tap) bist the tap bist performs all the functions of the normal bist, up to and including the pla signature test, in the exact manner as the normal bist. however, after the pla test, the test result is not transferred to the eax register. the tap bist is started by loading and executing the runbist instruction in the test access port, as described in boundary scan architecture support on page 41. when the runbist instruction is executed, the processor enters into a reset mode that is identical to that entered when the reset signal is asserted. upon completion of the tap bist, the result remains in the bist result register for shifting out through the tdo signal. the trst signal must be asserted, or the tap instruction must be changed, to exit tap bist and return to normal operation. output-float test the output-float test mode is entered if flush is asserted before the falling edge of reset. this causes the processor to place all of its output and bidirectional signals in the high-impedance state. in this isolated state, system board traces and connections can be tested for integrity and driveability. the output-float test mode can only be exited by asserting reset again. on the amd-k5 processor and pentium, flush# is an edge-triggered interrupt. on the 486 processor, however, the signal is a level-sensitive input. 6 no error instruction-cache linear tags 5 no error data-cache linear tags 4no errorpla 3 no error microcode rom 2 no error data-cache data 1 no error instruction cache physical tags 0 no error data-cache physical tags table 12. bist error bit definition in eax register (continued) bit number bit value 01
amd-k5? processor 27 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information cache and tlb testing the internal cache for the amd-k5 processor is divided into two cachesa 16-kbyte, 4-way, set-associative instruction cache and an 8-kbyte, 4-way, set-associative data cache. cache and tlb testing is often done by the bios or operating system during power-up. note: the amd-k6 mmx enhanced processor does not contain these features. it contains a built-in self-test for all internal memories. the individual locations of all sram arrays on the amd-k5 processor are accessible with the rdmsr and wrmsr instructions. to access an array location, set up the array access msr code (82h) in ecx, and the array pointer (see page 28) in edx. eax holds the data to be read or written. tests can be performed on the following arrays: n data cache 8-kbyte, 4-way, set-associative ? data array ? linear-tag array ? physical-tag array n instruction cache 16-kbyte, 4-way, set-associative ? instruction array ? linear-tag array ? physical-tag array ? valid-bit array ? branch-prediction bit array n 4-kbyte tlb 128-entry, 4-way, set-associative ? linear-tag array ? page array n 4-mbyte tlb 4-entry, fully associative ? linear-tag array ? page array
28 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information array access register (aar) the 64-bit array access register (aar) is a msr that contains a 32-bit array pointer that identifies the array location to be tested and 32 bits of array test data to be read or written. the wrmsr and rdmsr instructions access the aar when the ecx register contains the value 82h, as described on page 90. figure 3 shows the format of the aar. figure 3. array access register (aar) to read or write an array location, perform the following steps: 1. ecx enter 82h into ecx to access the 64-bit aar. 2. edx enter a 32-bit array pointer into edx, as shown in figures 4 through 12 (top). 3. eax read or write 32 bits of array test data to or from eax, as shown in figures 4 through 12 (bottom). array pointer the array pointers entered in edx (figures 4 through 12, top) specify particular array locations. for example, in the data- and instruction-cache arrays, the way (or column) and set (or index) in the array pointer specify a cache line in the 4-way, set-associative array. the array pointers for data-cache data and instruction-cache instructions also specify a dword location within that cache line. in the data cache, this dword is 32 bits of data; in the instruction cache, this dword is two instruction bytes plus their associated pre-decode bits. for the 4-kbyte tlb, the way and set specify one of the 128 tlb entries. in 4-mbyte tlb, one of only four entries is specified. bits 7C0 of every array pointer encode the array id , which identifies the array to be accessed, as shown in table 13. to simplify multiple accesses to an array, the contents of edx are msr 82h 0 31 0 31 array pointer (contents of edx) array data (contents of eax)
amd-k5? processor 29 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information retained after the rdmsr instruction executes (edx is normally cleared after a rdmsr instruction). array test data eax specifies the test data to be read or written with the rdmsr or wrmsr instruction (see figures 4 through 12). for example, in figure 4 (top) the array pointer in edx specifies a way and set within the data-cache linear tag array (e1h in bits 7C0 of the array pointer) or the physical tag array (ech in bits 7C0 of the array pointer). if the linear tag array (e1h) is accessed, the data read or written includes the tag and the status bits. the details of the valid fields in eax are proprietary. table 13. array ids in array pointers array pointer bits 7C0 accessed array e0h data cache: data e1h data cache: linear tag ech data cache: physical tag e4h instruction cache: instructions e5h instruction cache: linear tag edh instruction cache: physical tag e6h instruction cache: valid bits e7h instruction cache: branch-prediction bits e8h 4-kbyte tlb: page e9h 4-kbyte tlb: virtual tag eah 4-mbyte tlb: page ebh 4-mbyte tlb: virtual tag
30 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 4. test formats: dcache tags for the amd-k5? processor model 0 mesi state 00 = invalid, 01 = shared 10 = modified, 11 = exclusive dirty bit edx: array pointer 0 29 28 27 array id (e1h, ech) way set eax: test data (ech) physical tag 0 tag 87 12 13 18 19 31 23 22 tag 0 31 26 25 user/supervisor bit 24 r/w bit 23 0 22 linear valid bit 21 20 (e1h) linear tag 21 20
amd-k5? processor 31 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 5. test formats: dcache tags for the amd-k5? processor model 1 and greater mesi state 00 = invalid, 01 = shared 10 = modified, 11 = exclusive tag 0 31 28 27 p c d p w t dirty bit 26 25 user/supervisor bit 24 r/w bit 23 0 22 linear valid bit 21 20 (e1h) linear tag eax: test data (ech) physical tag 0 tag 31 23 22 0 31 30 29 28 27 array id (e1h, ech) way set 87 12 13 18 19 edx: array pointer 21 20
32 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 6. test formats: dcache data for all models of the amd-k5? processor edx: array pointer 0 31 30 29 28 27 array id (e0h) way data array index 7 18 19 98 10 12 13 dword index into block eax: test data (e0h) data 0 valid bits 31
amd-k5? processor 33 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 7. test formats: icache tags for the amd-k5? processor model 0 (e5h) linear tag edx: array pointer (e7h) branch-prediction bits 87 0 11 12 19 20 29 28 27 array id (e5h, edh, e6h, e7h) way icache index for all icache arrays icache word (2 instruction bytes + pre-decode) eax: test data (edh) physical tag (e6h) valid bits 0 19 20 31 linear address 0 31 tag (physical address 31C11) 20 21 0 31 byte valid bits 18 19 0 31 target byte 18 19 9 0 linear tag valid bit 17 user/ super- visor 16 15 pre- dicted taken 17 14 byte offset within block of last byte of predicted branch instruction 13 12 column of predicted target 11 index of predicted target 43 valid bit 19
34 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 8. test formats: icache tags for the amd-k5? processor model 1 and greater (e6h) valid bits 0 31 valid bits (e5h) linear tag 0 19 20 31 linear address 21 22 edx: array pointer (e7h) branch-prediction bits 87 0 13 12 19 20 29 28 27 array id (e5h, edh, e6h, e7h) way icache index for all icache arrays eax: test data (edh) physical tag 0 31 valid bits 20 21 0 31 target byte 18 19 17 pre- dicted taken 14 byte offset within block of last byte of predicted branch instruction 13 12 column of predicted target 11 index of predicted target 43 30 31 linear tag valid bit user/ super- visor valid bit 19
amd-k5? processor 35 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 9. test formats: icache instructions for the amd-k5? processor model 0 figure 10. test formats: icache instructions for the amd-k5? processor model 1 and greater edx: array pointer 0 31 30 29 28 27 array id (e4h) way set eax: test data (e4h) instruction bytes 7 20 19 98 11 12 opcode bytes 0 31 26 25 byte 0 map rops/mr om 7 8 9 10 op- code bit end bit start bit 11 12 prefix 0 byte 1 map rops/mr om op- code bit end bit start bit prefix 1 13 20 21 22 23 24 eax: test data (e4h) instruction bytes 0 31 26 25 byte (n) map rops/mr om 7 8 9 10 op- code bit end bit start bit 11 12 prefix 0 byte (n + 8) map rops/mr om op- code bit end bit start bit prefix 1 13 20 21 22 23 24 87 0 11 12 19 20 29 28 27 array id (e4h) way icache index for all icache arrays 30 31 edx: array pointer 0 10 byte packet:0/1>low/highlow: bytes 0C7 and 8C15 high: bytes 16C23 and 24C31
36 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 11. test formats: 4-kbyte tlb for all models of the amd-k5? processor edx: array pointer 0 31 30 29 28 27 array id (e8h, e9h) way tlb index eax: test data (e8h) 4-kbyte page and status (e9h) 4-kbyte virtual tag page frame address 0 tag (virtual address 31C17) 87 12 13 31 0 21 31 22 19 20 p c d p w t 20 19 18 17 16 15 14 symbol description bits gv global valid bit 19 d dirty bit 18 u/s user supervisor bit 17 r/w read or write bit 16 v valid bit 15 g v d u / s v r / w
amd-k5? processor 37 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 12. test formats: 4-mbyte tlb for all models of the amd-k5? processor edx: array pointer 0 31 30 29 28 27 array id (eah, ebh) entry eax: test data (eah) 4-mbyte page and status (ebh) 4-mbyte virtual tag valid bits 0 valid bits 87 31 0 11 12 31 14 15 13 12 11 10 9 10 symbol description bits gv global valid bit 14 d dirty bit 13 u/s user supervisor bit 12 r/w read or write bit 11 v valid bit 10 g v d u / s v r / w p c d p w t
38 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information debug registers the processor implements the standard debug functions and registersdr7Cdr6 and dr3Cdr0 (often called dr7Cdr0) available on the 486 processor, plus an i/o breakpoint extension. standard debug functions the debug functions make the processors state visible to debug software through four debug registers (dr3Cdr0) that are accessed by mov instructions. accesses to memory addresses can be set as breakpoints in the instruction flow by invoking one of two debug exceptions (interrupt vectors 1 or 3) during instruction or data accesses to the addresses. the debug functions eliminate the need to embed breakpoints in code and allow debugging of rom as well as ram. for details on the standard 486 debug functions and registers, see the amd documentation on the am486 ? processor or other commercial x86 literature. i/o breakpoint extension the processor supports an i/o breakpoint extension for breakpoints on i/o reads and writes. this function is enabled by setting bit 3 of cr4, as described in control register 4 (cr4) extensions on page 58. when enabled, the i/o breakpoint function is invoked by the following: n entering the i/o port number as a breakpoint address (zero-extended to 32 bits) in one of the breakpoint registers, dr3Cdr0 n entering the bit pattern, 10b, in the corresponding 2-bit read-write (r/w) field in dr7 all data breakpoints on the amd-k5 processor are precise, including those encountered in repeated string operations. the trap is taken after completing the iteration on which the breakpoint match occurs. enabled breakpoints slow the processor somewhat. when a data breakpoint is enabled, the processor disables its dual-issue load/store operations and performs only single-issue load/store operations. when an instruction breakpoint is enabled, instruction issue is completely serialized.
amd-k5? processor 39 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information debug compatibility with the pentium ? processor the differences in debug functions between the amd-k5 processor and pentium are described in appendix a of the amd-k5? processor technical reference manual, order# 18524. branch tracing branch tracing is enabled by writing bits 3C1 with 001b and setting bit 5 to 1 (disabling branch prediction) in the hardware configuration register (hwcr), as described on page 22. when thus enabled, the processor drives two branch-trace message special bus cycles immediately after each taken branch instruction is executed. both special bus cycles have a be7Cbe0 encoding of dfh (1101_1111b). the first special bus cycle identifies the branch source, the second identifies the branch target. the contents of the address and data bus during these special bus cycles are shown in table 14. the branch-trace message special bus cycles are different for the amd-k5 processor and pentium, although their be7Cbe0 encodings are the same. table 14. branch-trace message special bus cycle fields signals first special bus cycle second special bus cycle a31 0 = first special bus cycle (source) 1 = second special bus cycle (target) a30Ca29 not valid operating mode of target: 11 = virtual-8086 mode 10 = protected mode 01 = not valid 00 = real mode a28 not valid default operand size of target segment: 1 = 32-bit 0 = 16-bit a27Ca20 0 0 a19Ca4 code segment (cs) selector of branch source code segment (cs) selector of branch target a3 0 0 d31Cd0 eip of branch source eip of branch target
40 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information functional-redundancy checking when frcmc is asserted at reset, the processor enters functional-redundancy checking mode as the checker and reports checking errors on the ierr output. if frcmc is negated at reset, the processor operates normally, although it also behaves as the master in a functional-redundancy checking arrangement with a checker. in the functional-redundancy checking mode, two processors have their signals tied together. one processor (the master) operates normally. the other processor (the checker) has its output and bidirectional signals (except for tdo and ierr) floated to detect the state of the masters signals. the master controls instruction fetching and the checker mimics its behavior by sampling the fetched instructions as they appear on the bus. both processors execute the instructions in lock step. the checker compares the state of the masters output and bidirectional signals with the state that the checker itself would have driven for the same instruction stream. errors detected by the checker are reported on the ierr output of the checker. if a mismatch occurs on such a comparison, the checker asserts ierr for one clock, two clocks after the detection of the error. both the master and the checker continue running the checking program after an error occurs. no action other than the assertion of ierr is taken by the processor. on the amd-k5 processor, the ierr output is reserved solely for functional-redundancy checking. no other errors are reported on that output. functional-redundancy checking is typically implemented on single-processor, fault-monitoring systems (which have two processors). the master processor runs the operational programs and the checker processor is dedicated entirely to constant checking. in this arrangement, the accurate operation test consists solely of reporting one or more errors. the particular error type or the instruction causing an error is not reported. the arrangement works because the processor is entirely deterministic. speculative prefetching, speculative execution, and cache replacement all occur in identical ways and at identical times on both processors if their signals are tied together so that they run the same program.
amd-k5? processor 41 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information the functional-redundancy checking mode can only be exited by the assertion of reset. functional-redundancy checking cannot be performed in the hardware debug tool (hdt) mode. the assertion of frcmc is not recognized while prdy is asserted. boundary scan architecture support the amd-k5 processor provides test features compatible with the standard test access port (tap) and boundary scan test architecture as defined in the ieee 1149.1-1990 jtag specification. the subsections in this topic include: n boundary scan test functional description n boundary scan architecture n registers n the test access port (tap) controller n jtag register organization n jtag instructions the external tap interface consists of five pins: n tck: the test clock input provides the clock for the jtag test logic. n tms: the test mode select input enables tap controller operations. n tdi: the test data input provides serial input to registers. n tdo: the test data output provides serial output from the registers; the signal is tri-stated except when in the shift-dr or shift-ir controller states. n trst: the tap controller reset input initializes the tap controller when asserted low. the internal jtag logic contains the elements listed below: n the test access port (tap) controller decodes the inputs on the test mode select (tms) line to control test operations. the tap is a general-purpose port that provides access to the test support functions built into the amd-k5. n instruction registeraccepts instructions from the test data input (tdi) pin. the instruction codes select the specific test or debug operation to be performed or the test data register to be accessed.
42 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information n implemented test data registersboundary scan register, device identification register, and bypass register. see jtag register organization on page 44 for more information. note: see table 18 on page 49 for more information. boundary scan test functional description the boundary scan testing uses a shift register, contained in a boundary scan cell, located between the core logic and the i/o buffers adjacent to each component pin. signals at each input and output pin are controlled and observed using scan testing techniques. the boundary scan cells are interconnected to form a shift register chain. this register chain, called a boundary scan register (bsr), constructs a serial path surrounding the core logic, enabling test data to be shifted through the boundary scan path. when the system enters the boundary scan test mode, the bsr chain is directed by a test program to pass data along the shift register path. if all the components used to construct a circuit or pcb contain a boundary scan cell architecture, the resulting serial path can be used to perform component interconnect testing. boundary scan architecture boundary scan architecture has four basic elements: n test access port (tap) n tap controller n instruction register (ir). see instruction register on page 44 for more information. n test data registers. see registers on page 43 for more information. the instruction and test data registers have separate shift register access paths connected in parallel between the test data in (tdi) and test data out (tdo) pins. path selection and boundary scan cell operation is controlled by the tap controller. the controller initializes at start-up, but the test reset ( trst ) input can asynchronously reset the test logic, if required. all system integrated circuit (ic) i/o signals are shifted in and out through the serial test data in (tdi) and test data out (tdo) path. the tap controller is enabled by the test mode select (tms) input. the test clock (tck), obtained from a system level bus or automatic test equipment (ate), supplies
amd-k5? processor 43 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information the timing signal for data transfer and system architecture operation. the dedicated tck input enables the serial test data path between components to be used independently of component-specific system clocks. tck also ensures that test data can be moved to or from a chip without changing the state of the on-chip system logic. the tck signal is driven by an independent 50% duty cycle clock (generated by the automatic test equipment). if the tck must be stopped (for example, if the ate must retrieve data from external memory and is unable to keep the clock running), it can be stopped at 0 or 1 indefinitely, without causing any change to the test logic state. to ensure race-free operation, changes on the taps tms input are clocked into the test logic. changes on the taps tdi input are clocked into the selected register (instruction or test data register) on the rising edge of tck. the contents of the selected register are shifted out onto the tap output (tdo) on the falling edge of tck. registers boundary scan architectural elements include an instruction register (ir) and a group of test data registers (tdrs). these registers have separate shift-register-based serial access paths connected in parallel between the tdi and tdo pins. the tdrs are internal registers used by the boundary scan architecture to process the test data. each test data register is addressed by an instruction scanned into the instruction register. the amd-k5 processor includes the following tdrs: n bypass register (br). see bypass register on page 45. n boundary scan register (bsr). see boundary scan register on page 44. n device identification register (dir). see device identification register on page 45. n built-in self-test result register (bistrr). see runbist on page 48.
44 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information instruction register. the 5-bit instruction register (ir) is a serial-in parallel-out register that includes five shift register-based cells for holding instruction data. the instruction determines which test to run, which data register to access, or both. when the tap controller enters the capture-ir state, the processor loads the idcode instruction in the ir. executing shift-ir starts instructions shifting into the instruction register on the rising edge of tck. executing update-ir loads the instruction from the serial shift register to the parallel register. the tap controller is a synchronous, finite-state machine that controls the test and debug logic sequence of operations. the tap controller changes state in response to the rising edge of tck and defaults to the test logic reset state at power-up. reinitialization to the test logic reset state is accomplished by holding the tms pin high for five tck periods. jtag register organization all registers in the jtag logic consist of the following two register ranks: n shift register n parallel output register fed by the shift register parallel input data is loaded into the shift register when the tap controller exits the capture state (capture-dr or capture-ir). the shift register then shifts data from tdi to tdo when in the shift state (shift-dr or shift-ir). the output register holds the current data while new data is shifted into the shift register. the contents of the output register are updated when the tap controller exits the update state (update-dr or update-ir). the following three registers are described in this section: n boundary scan register n device identification register n bypass register boundary scan register. the boundary scan register (bsr) is a 261-bit shift register with cells connected to all input and output pins and containing cells for tri-state i/o control. this arrangement enables serial data to be loaded into or read from the processor boundary scan area.
amd-k5? processor 45 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information output cells determine the value of the signal driven on the corresponding pin. input cells only capture data. the extest and sample/preload instructions can operate the bsr. device identification register. the format of the device identification register (dir) is shown in table 15. the fields include the following values: n version number this field is incremented by amd manufacturing for each major revision of silicon. n bond option the two bits of the bond option depend on how the part is bonded at the factory. n part number this field identifies the specific processor model. n manufacturer this field is actually only 11 bits (11C1). the least-significant bit, bit 0, is always set to 1, as specified by the ieee standard. bypass register. the bypass register, a 1-bit shift register, provides the shortest path between tdi and tdo. when the component is not performing a test operation, this path is selected to allow transfer of test data to and from other components on the board. the bypass register is also selected during the highz, all1, all0, and bypass tests and for any unused instruction codes. public instructions the processor supports all three ieee-mandatory instructions (bypass, sample/preload, extest), three ieee-optional instructions (idcode, highz, runbist), and three instructions unique to the amd-k5 processor (all1, all0, usehdt). table 16 shows the complete set of public tap instructions supported by the processor. the amd-k5 also implements several private manufacturing test instructions. the ieee standard describes the mandatory and optional instructions. the all1 and all0 instructions simply force all outputs and bidirectionals high or low. the usehdt instruction is described on page 57. any instruction encodings not shown in table 16 select the bypass instruction. table 15. amd-k5? processor device identification register version (bits 31C28) bond option (bits 27C26) part number (bits 25C12) manufacturer (bits 11C1) lsb (bit 0) 0h x0b 051xh 00000000001b 1b
46 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information extest. the extest instruction permits circuits outside the component package to be tested. a common use of the extest instruction is the testing of board interconnects. boundary scan register cells at output pins are used to apply test stimuli, while those at input pins capture test results. depending on the value loaded into their control cells in the boundary scan register, the i/o pins are established as input or output. inputs to the core logic retain the logic value set prior to execution of the extest instruction. upon exiting extest, input pins are reconnected to the package pins. sample/preload. there are two functions performed by the sample/preload instruction, as follows: n capturing an instantaneous picture of the normal operation of the device being tested. this function occurs if the instruction is executed while the tap controller is in the capture-dr state and causes the boundary scan register to sample the values present at the device pins. n preloading data to the device pins to be driven to the board by the extest instruction. this function occurs if the instruction is executed while the tap controller is in the update-dr state and causes data to be preloaded to the device pins from the boundary scan register. table 16. public tap instructions instruction encoding register description extest 00000 bsr as defined by the ieee standard sample/preload 00001 bsr as defined by the ieee standard idcode 00010 dir as defined by the ieee standard highz 00011 br as defined by the ieee standard all1 00100 br forces all outputs and bidirectionals high all0 00101 br forces all outputs and bidirectionals low usehdt 00110 hdtr accesses the hardware debug tool (hdt) see page 57 runbist 00111 bistrr as defined by the ieee standard bypass 11111 br as defined by the ieee standard bypass undefined br undefined instruction encodings select the bypass instruction
amd-k5? processor 47 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information idcode. the execution of the idcode instruction connects the device identification register between tdi and tdo. upon such connection, the device identification code can be shifted out of the register. highz. this instruction forces all output and bidirectional pins into a tri-state condition. when this instruction is selected, the bypass register is selected for shifting between tdi and tdo. a signal called hizext is responsible for forcing the tri-state to occur. this signal is generated in the tap block, underneath jtag_bist, and goes to the pad_top block. all1. this instruction forces all output and bidirectional pins to a high logic level. the all1 instruction, like the highz instruction, selects the bypass register for shifting between tdi and tdo. a signal called all1 is responsible for forcing the pins to a high state. this signal is generated in the tap block underneath jtag_bist and goes to the pad_top block. in the pad_top block, this signal goes to boundary scan cells called bslcd_out. the dout pins of the bslcd_out cells are forced high when all1 is high. the selpdr signal selects the boundary scan cells as the source for driving the outputs if the selpdr signal is high. the selpdr signal is also generated in the tap block underneath jtag_bist and goes to the pad_top block. all0. this instruction forces all output and bidirectional pins to a low logic level. the all0 instruction, like the highz instruction, selects the bypass register for shifting between tdi and tdo. a signal called all0 is responsible for forcing the pins to a low state. this signal is generated in the tap block underneath jtag_bist and goes to the pad_top block. in the pad_top block, this signal goes to boundary scan cells called bslcd_out. the dout pins of the bslcd_out cells are forced low when all0 is high. the selpdr signal selects the boundary scan cells as the source for driving the outputs if the selpdr signal is high. the selpdr signal is also generated in the tap block underneath jtag_bist and goes to the pad_top block.
48 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information runbist. this version of bist is similar to the normal bist mode, except runbist is started by shifting in a tap instruction. this instruction should behave according to the rules of the ieee 1149.1 definition of runbist. when the runbist instruction is updated into the instruction register, a signal from the tap_rtl block called jtgbist is asserted high. this signal goes to the pad_top and testctrl blocks. in pad_top, this signal goes to the brnbist block and causes both init_samp and runbist to be asserted. to the rest of the processor, it looks like a normal bist operation is taking place. the jtgbist signal also goes to the testctrl block so the bist controller knows the bist operation was initiated from the tap controller. this operation is necessary because the bist results do not get transferred to the eax register in this mode of operation. the jtag_bist block also asserts the reset_tap pin to the clocks block for 15 system clock cycles in order to fake an external reset. the pattern that is shifted into the boundary scan ring prior to the selection of the runbist instruction is driven at output and bidirectional cells during the duration of the instruction. the results of the execution of runbist are saved in the bist results register, which is 9 bits long and looks like the least significant 9 bits in the eax register. this register is selected for shifting between tdi and tdo and can be shifted out after the completion of bist. bit 0 (icache data status) is shifted out first. the bist results should be independent of signals received at non-clock input pins (except for reset). bypass. the execution of the bypass instruction connects the bypass register between tdi and tdo, bypassing the test logic. because of the pull-up resistor on the tdi input, the bypass register is selected if there is an open circuit in the board-level test data path following an instruction scan cycle. any unused instruction bit patterns cause the bypass register to be selected for shifting between tdi and tdo.
amd-k5? processor 49 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information the control bits listed in table 18 have the characteristics described in table 17. table 17. control bit definitions bit definition 144 controls the direction of the data bus (d63Cd0). if the bit is set to 1, the bus acts as an input. if the bit is set to 0, the bus acts as an output. 213 controls the direction of the address bus (a31Ca3) and address parity (ap). if the bit is set to 1, the bus acts as an input. if the bit is set to 0, the bus acts as an output. 257 controls pins that can be tri-stated, but these pins never act as inputs. if the bit is set to 1, the pin is tri-stated. if the bit is set to 0, the pin acts as an output. table 18. boundary scan register bit definitions bit pin name comments 0 dp7 output cell: controlled by bit 144 1 dp7 input cell 2 d63 output cell: controlled by bit 144 3 d63 input cell 4 d62 output cell: controlled by bit 144 5 d62 input cell 6 d61 output cell: controlled by bit 144 7 d61 input cell 8 d60 output cell: controlled by bit 144 9 d60 input cell 10 d59 output cell: controlled by bit 144 11 d59 input cell 12 d58 output cell: controlled by bit 144 13 d58 input cell 14 d57 output cell: controlled by bit 144 15 d57 input cell 16 d56 output cell: controlled by bit 144 17 d56 input cell 18 dp6 output cell: controlled by bit 144 19 dp6 input cell
50 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information 20 d55 output cell: controlled by bit 144 21 d55 input cell 22 d54 output cell: controlled by bit 144 23 d54 input cell 24 d53 output cell: controlled by bit 144 25 d53 input cell 26 d52 output cell: controlled by bit 144 27 d52 input cell 28 d51 output cell: controlled by bit 144 29 d51 input cell 30 d50 output cell: controlled by bit 144 31 d50 input cell 32 d49 output cell: controlled by bit 144 33 d49 input cell 34 d48 output cell: controlled by bit 144 35 d48 input cell 36 dp5 output cell: controlled by bit 144 37 dp5 input cell 38 d47 output cell: controlled by bit 144 39 d47 input cell 40 d46 output cell: controlled by bit 144 41 d46 input cell 42 d45 output cell: controlled by bit 144 43 d45 input cell 44 d44 output cell: controlled by bit 144 45 d44 input cell 46 d43 output cell: controlled by bit 144 47 d43 input cell 48 d42 output cell: controlled by bit 144 49 d42 input cell 50 d41 output cell: controlled by bit 144 51 d41 input cell 52 d40 output cell: controlled by bit 144 53 d40 input cell table 18. boundary scan register bit definitions (continued) bit pin name comments
amd-k5? processor 51 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 54 dp4 output cell: controlled by bit 144 55 dp4 input cell 56 d39 output cell: controlled by bit 144 57 d39 input cell 58 d38 output cell: controlled by bit 144 59 d38 input cell 60 d37 output cell: controlled by bit 144 61 d37 input cell 62 d36 output cell: controlled by bit 144 63 d36 input cell 64 d35 output cell: controlled by bit 144 65 d35 input cell 66 d34 output cell: controlled by bit 144 67 d34 input cell 68 d33 output cell: controlled by bit 144 69 d33 input cell 70 d32 output cell: controlled by bit 144 71 d32 input cell 72 dp3 output cell: controlled by bit 144 73 dp3 input cell 74 d31 output cell: controlled by bit 144 75 d31 input cell 76 d30 output cell: controlled by bit 144 77 d30 input cell 78 d29 output cell: controlled by bit 144 79 d29 input cell 80 d28 output cell: controlled by bit 144 81 d28 input cell 82 d27 output cell: controlled by bit 144 83 d27 input cell 84 d26 output cell: controlled by bit 144 85 d26 input cell 86 d25 output cell: controlled by bit 144 87 d25 input cell table 18. boundary scan register bit definitions (continued) bit pin name comments
52 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information 88 d24 output cell: controlled by bit 144 89 d24 input cell 90 dp2 output cell: controlled by bit 144 91 dp2 input cell 92 d23 output cell: controlled by bit 144 93 d23 input cell 94 d22 output cell: controlled by bit 144 95 d22 input cell 96 d21 output cell: controlled by bit 144 97 d21 input cell 98 d20 output cell: controlled by bit 144 99 d20 input cell 100 d19 output cell: controlled by bit 144 101 d19 input cell 102 d18 output cell: controlled by bit 144 103 d18 input cell 104 d17 output cell: controlled by bit 144 105 d17 input cell 106 d16 output cell: controlled by bit 144 107 d16 input cell 108 dp1 output cell: controlled by bit 144 109 dp1 input cell 110 d15 output cell: controlled by bit 144 111 d15 input cell 112 d14 output cell: controlled by bit 144 113 d14 input cell 114 d13 output cell: controlled by bit 144 115 d13 input cell 116 d12 output cell: controlled by bit 144 117 d12 input cell 118 d11 output cell: controlled by bit 144 119 d11 input cell 120 d10 output cell: controlled by bit 144 121 d10 input cell table 18. boundary scan register bit definitions (continued) bit pin name comments
amd-k5? processor 53 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 122 d9 output cell: controlled by bit 144 123 d9 input cell 124 d8 output cell: controlled by bit 144 125 d8 input cell 126 dp output cell: controlled by bit 144 127 dp input cell 128 d7 output cell: controlled by bit 144 129 d7 input cell 130 d6 output cell: controlled by bit 144 131 d6 input cell 132 d5 output cell: controlled by bit 144 133 d5 input cell 134 d4 output cell: controlled by bit 144 135 d4 input cell 136 d3 output cell: controlled by bit 144 137 d3 input cell 138 d2 output cell: controlled by bit 144 139 d2 input cell 140 d1 output cell: controlled by bit 144 141 d1 input cell 142 d0 output cell: controlled by bit 144 143 d0 input cell 144 control direction control. see table 17. 145 stplk# input cell 146 frcmc# input cell 147 pen# input cell 148 ignne# input cell 149 bf input cell 150 init input cell 151 smi# input cell 152 r/s# input cell 153 nmi input cell 154 intr input cell 155 a21 output cell: controlled by bit 213 table 18. boundary scan register bit definitions (continued) bit pin name comments
54 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information 156 a21 input cell 157 a22 output cell: controlled by bit 213 158 a22 input cell 159 a23 output cell: controlled by bit 213 160 a23 input cell 161 a24 output cell: controlled by bit 213 162 a24 input cell 163 a25 output cell: controlled by bit 213 164 a25 input cell 165 a26 output cell: controlled by bit 213 166 a26 input cell 167 a27 output cell: controlled by bit 213 168 a27 input cell 169 a28 output cell: controlled by bit 213 170 a28 input cell 171 a29 output cell: controlled by bit 213 172 a29 input cell 173 a30 output cell: controlled by bit 213 174 a30 input cell 175 a31 output cell: controlled by bit 213 176 a31 input cell 177 a3 output cell: controlled by bit 213 178 a3 input cell 179 a4 output cell: controlled by bit 213 180 a4 input cell 181 a5 output cell: controlled by bit 213 182 a5 input cell 183 a6 output cell: controlled by bit 213 184 a6 input cell 185 a7 output cell: controlled by bit 213 186 a7 input cell 187 a8 output cell: controlled by bit 213 188 a8 input cell 189 a9 output cell: controlled by bit 213 table 18. boundary scan register bit definitions (continued) bit pin name comments
amd-k5? processor 55 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 190 a9 input cell 191 a10 output cell: controlled by bit 213 192 a10 input cell 193 a11 output cell: controlled by bit 213 194 a11 input cell 195 a12 output cell: controlled by bit 213 196 a12 input cell 197 a13 output cell: controlled by bit 213 198 a13 input cell 199 a14 output cell: controlled by bit 213 200 a14 input cell 201 a15 output cell: controlled by bit 213 202 a15 input cell 203 a16 output cell: controlled by bit 213 204 a16 input cell 205 a17 output cell: controlled by bit 213 206 a17 input cell 207 a18 output cell: controlled by bit 213 208 a18 input cell 209 a19 output cell: controlled by bit 213 210 a19 input cell 211 a20 output cell: controlled by bit 213 212 a20 input cell 213 control direction control. see table 17. 214 scyc output cell: controlled by bit 257 215 reset input cell 216 be7# output cell: controlled by bit 257 217 be6# output cell: controlled by bit 257 218 be5# output cell: controlled by bit 257 219 be4# output cell: controlled by bit 257 220 be3# output cell: controlled by bit 257 221 be2# output cell: controlled by bit 257 222 be1# output cell: controlled by bit 257 223 be0# output cell: controlled by bit 257 table 18. boundary scan register bit definitions (continued) bit pin name comments
56 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information 224 w/r# output cell: controlled by bit 257 225 hit# output cell 226 clk clock 227 adsc# output cell: controlled by bit 257 228 ads# output cell: controlled by bit 257 229 cache# output cell: controlled by bit 257 230 brdyc# input cell 231 brdy# input cell 232 eads# input cell 233 pwt output cell: controlled by bit 257 234 lock# output cell: controlled by bit 257 235 pcd output cell: controlled by bit 257 236 wb/wt# input cell 237 hitm# output cell 238 ken# input cell 239 ahold input cell 240 boff# input cell 241 hlda output cell 242 hold input cell 243 na# input cell 244 ewbe# input cell 245 m/io# output cell: controlled by bit 257 246 flush# input cell 247 a20m# input cell 248 buschk# input cell 249 ap output cell: controlled by bit 213 250 ap input cell 251 d/c# output cell: controlled by bit 257 252 breq output cell 253 smiact# output cell 254 pchk# output cell 255 apchk# output cell 256 prdy output cell 257 control direction control. see table 17. table 18. boundary scan register bit definitions (continued) bit pin name comments
amd-k5? processor 57 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information hardware debug tool (hdt) the hardware debug tool (hdt)sometimes referred to as the debug port or probe modeis a collection of signals, registers, and processor microcode that is enabled when external debug logic drives r/s low or loads the processors test access port (tap) instruction register with the usehdt instruction. amd-k5? processor x86 architecture extensions the amd-k5 processor is compatible with the instruction set, programming model, memory management mechanisms, and other software infrastructure supported by the 486 and pentium (735\90, 815\100) processors. operating system and application software that runs on pentium can be executed on the amd-k5. because the amd-k5 processor takes a significantly different approach to implementing the x86 architecture, some subtle differences from pentium may be visible to system and code developers. these differences are described in appendix a of the amd-k5? processor technical reference manual, order# 18524. call amd at 1-800-222-9323 to order amd-k5 support documents. before implementing the amd-k5 processor model-specific features, check cpuid for supported feature flags. see cpuid on page 86 for more information. 258 inv input cell 259 ferr# output cell 260 ierr# output cell table 18. boundary scan register bit definitions (continued) bit pin name comments
58 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information additions to the eflags register the eflags register on the amd-k5 processor defines new bits in the upper 16 bits of the register to support extensions to the operating modes. see virtual-8086 mode extensions (vme) on page 67 and cpuid on page 86 for additional information. control register 4 (cr4) extensions control register 4 (cr4) was added on the amd-k5. the bits in this register control the various architectural extensions. the majority of the bits are reserved. the default state of cr4 is all zeros. figure 13 shows the register and describes the bits. the architectural extensions are described in table 19. figure 13. control register 4 (cr4) symbol description bit gpe global page extension 7 mce machine check enable 6 pse page size extensions 4 de debugging extensions 3 tsd time stamp disable 2 pvi protected virtual interrupts 1 vme virtual-8086 mode extensions 0 76543210 31 p s e t s d m c e v m e d e p v i g p e reserved 8
amd-k5? processor 59 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information table 19. control register 4 (cr4) fields bit mnemonic description function 7gpe global page extension* enables retention of designated entries in the 4-kbyte tlb or 4-mbyte tlb during invalidations. 1 = enabled, 0 = disabled. see global pages on page 65 for details. 6 mce machine-check enable enables machine-check exceptions. 1 = enabled, 0 = disabled. see machine-check exceptions on page 60 for details. 4 pse page size extension enables 4-mbyte pages. 1 = enabled, 0 = disabled. see 4-mbyte pages on page 60 for details. 3de debugging extensions enables i/o breakpoints in the dr7Cdr0 registers. 1 = enabled, 0 = disabled. see debug registers on page 38 for details. 2 tsd time stamp disable selects privileged (cpl=0) or non-privileged (cpl>0) use of the rdtsc instruction, which reads the time stamp counter (tsc). 1 = cpl must be 0, 0 =any cpl. see time stamp counter (tsc) on page 81 for details. 1pvi protected virtual interrupts enables hardware support for interrupt virtualization in protected mode. 1 = enabled, 0 = disabled. see protected virtual interrupt (pvi) extensions on page 79 for details. 0vme virtual-8086 mode extensions enables hardware support for interrupt virtualization in virtual-8086 mode. 1 = enabled, 0 = disabled. see virtual-8086 mode extensions (vme) on page 67 for details. note: * the amd-k5 processor supports global paging only on models 1, 2, and 3, with a stepping of 4 or greater.
60 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information machine-check exceptions bit 6 in cr4, the machine-check enable (mce) bit, controls generation of machine-check exceptions (12h). if enabled by the mce bit, these exceptions are generated when either of the following occurs: n system logic asserts buschk to identify a parity or other type of bus-cycle error n the processor asserts pchk while system logic asserts pen to identify an enabled parity error on the d63Cd0 data bus whether or not machine-check exceptions are enabled, the processor performs the following functions when either type of bus error occurs: n latches the physical address of the failed cycle in its 64-bit machine-check address register (mcar) n latches the cycle definition of the failed cycle in its 64-bit machine-check type register (mctr) software can read the mcar and mctr registers in the exception handling routine with the rdmsr instruction, as described on page 90. the format of the registers is shown in figures 20 and 21. if system software has cleared the mce bit in cr4 to 0 before a bus-cycle error, the processor attempts to continue execution without generating a machine-check exception. the processor still latches the address and cycle type in mcar and mctr as described in this section. 4-mbyte pages the tlbs in the 486 and 386 processors support only 4-kbyte pages. however, large data structures, such as a video frame buffer or non-paged operating system code, can consume many pages and easily overrun the tlb. the amd-k5 processor accommodates large data structures by allowing the operating system to specify 4-mbyte pages as well as 4-kbyte pages, and by implementing a four-entry, fully-associative 4-mbyte tlb that is separate from the 128-entry, 4-kbyte tlb. from a given page directory, the processor can access both 4-kbyte pages and 4-mbyte pages, and the page sizes can be intermixed within a page directory. when the page size extension (pse) bit in cr4 is set, the processor translates linear addresses using either the 4-kbyte tlb or the 4-mbyte tlb, depending on the state of the page size (ps) bit in the page-directory entry. figures 14 and 15 show how 4-kbyte and 4-mbyte page translations work.
amd-k5? processor 61 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 14. 4-kbyte paging mechanism linear address page directory page table 4-kbyte page frame cr3 0 11 12 21 31 22 page-directory offset page-table offset page offset pde pte physical address
62 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 15. 4-mbyte paging mechanism to enable the 4-mbyte paging option: 1. set the page size extension (pse) bit in cr4 to 1. 2. set the page size (ps) bit in the page-directory entry to 1. 3. write the physical base addresses of 4-mbyte pages in bits 31C22 of page-directory entries. (bits 21C12 of these entries must be cleared to 0 or the processor generates a page fault.) 4. load cr3 with the base address of the page directory that contains these page-directory entries. linear address page directory 4-mbyte page frame cr3 0 21 31 22 page-directory offset page offset pde physical address
amd-k5? processor 63 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 13 and table 19 show the fields in cr4. figure 16 and table 20 show the fields in a page-directory entry. 4-kbyte page translation differs from 4-mbyte page translation in the following ways: n 4-kbyte paging (figure 14) bits 31C22 of the linear address select an entry in a 4-kbyte page directory in memory, whose physical base address is stored in cr3. bits 21C12 of the linear address select an entry in a 4-kbyte page table in memory, whose physical base address is specified by bits 31C22 of the page-directory entry. bits 11C0 of the linear address select a byte in a 4-kbyte page, whose physical base address is specified by the page-table entry. n 4-mbyte paging (figure 15) bits 31C22 of the linear address select an entry in a 4-mbyte page directory in memory, whose physical base address is stored in cr3. bits 21C0 of the linear address select a byte in a 4-mbyte page in memory, whose physical base address is specified by bits 31C22 of the page-directory entry. bits 21C12 of the page-directory entry must be cleared to 0. figure 16. page-directory entry (pde) 876543210 31 p c d u / s w / r g 9 10 11 12 a v l p s a p w t p table base address symbol description bits avl available to software 11C9 g global 8 ps page size 0 = 4 kbytes 7 reserved = 0 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0
64 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information table 20. page-directory entry (pde) fields bit mnemonic description function 31C12 base physical base address for 4-kbyte pages, bits 31C12 contain the physical base address of a 4-kbyte page table. for 4-mbyte pages, bits 31C22 contain the physical base address of a 4-mbyte page and bits 21C12 must be cleared to 0. (the processor generates a page fault if bits 21C12 are not cleared to 0.) 11C9 avl available to software software may use this field to store any type of information. when the page-directory entry is not present (p bit cleared), bits 31C1 become available to software. 8 g global* 0 = local, 1 = global. 7 ps page size 0 = 4-kbyte, 1 = 4-mbyte. 6ddirty for 4-kbyte pages, this bit is undefined and ignored. the processor does not change it. 0 = not written, 1 = written. for 4-mbyte pages, the processor sets this bit to 1 during a write to the page that is mapped by this page-directory entry. 0 = not written, 1 = written. 5 a accessed the processor sets this bit to 1 during a read or write to any page that is mapped by this page-directory entry. 0 = not read or written, 1 = read or written. 4 pcd page cache disable specifies cacheability for all pages mapped by this page-directory entry. whether a location in a mapped page is actually cached also depends on several other factors. 0 = cacheable page, 1 = non-cacheable. 3 pwt page writethrough specifies writeback or writethrough cache protocol for all pages mapped by this page-directory entry. whether a location in a mapped page is actually cached in a writeback or writethrough state also depends on several other factors. 0 = writeback page, 1 = writethrough page. 2 u/s user/supervisor 0 = user (any cpl), 1 = supervisor (cpl < 3). 1 w/r write/read 0 = read or execute, 1 = write, read, or execute. 0 p present 0 = not valid, 1 = valid. note: * the amd-k5 processor supports global paging only on models 1, 2, and 3, with a stepping of 4 or greater.
amd-k5? processor 65 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information global pages the amd-k5 processor supports global paging only on models 1, 2, and 3, with a stepping of 4 or greater. the processors performance can sometimes be improved by making some pages global to all tasks and procedures. this can be done for both 4-kbyte pages and 4-mbyte pages. the processor invalidates (flushes) both the 4-kbyte tlb and the 4-mbyte tlb whenever cr3 is loaded with the base address of the new tasks page directory. the processor loads cr3 automatically during task switches, and the operating system can load cr3 at any other time. unnecessary invalidation of certain tlb entries can be avoided by specifying those entries as global (a global tlb entry references a global page) . this improves performance after tlb flushes. global entries remain in the tlb and need not be reloaded. for example, entries may reference operating system code and data pages that are always required. the processor operates faster if these entries are retained across task switches and procedure calls. to specify individual pages as global: 1. set the global page extension (gpe) bit in cr4. 2. (optional) set the page size extension (pse) bit in cr4. 3. set the relevant global (g) bit for that page: for 4-kbyte pages set the g bit in both the page-directory entry (shown in figure 16 and table 20) and the page-table entry (shown in figure 17 and table 21). for 4-mbyte pages (optional) after the pse bit in cr4 is set, set the g bit in the page-directory entry (shown in figure 16 and table 20). 4. load cr3 with the base address of the page directory. the invlpg instruction clears both the v and g bits for the referenced entry. to invalidate all entries in both tlbs, including global-page entries: 1. clear the global page extension (gpe) bit in cr4. 2. load cr3 with the base address of another (or same) page directory.
66 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 17. page-table entry (pte) table 21. page-table entry (pte) fields bit mnemonic description function 31C12 base physical base address the physical base address of a 4-kbyte page. 11C9 avl available to software software may use the field to store any type of information. when the page-table entry is not present (p bit cleared), bits 31C1 become available to software. 8 g global* 0 = local, 1 = global. 7 ps page size this bit is ignored in page-table entries, although clearing it to 0 preserves consistent usage of this bit between page-table and page-directory entries. 6ddirty the processor sets this bit to 1 during a write to the page that is mapped by this page-table entry. 0 = not written, 1 = written. 5 a accessed the processor sets this bit to 1 during a read or write to any page that is mapped by this page-table entry. 0 = not read or written, 1 = read or written. 4 pcd page cache disable specifies cacheability for all locations in the page mapped by this page-table entry. whether a location is actually cached also depends on several other factors. 0 = cacheable page, 1 = non-cacheable. note: * the amd-k5 processor supports global paging only on models 1, 2, and 3, with a stepping of 4 or greater. 876543210 31 p c d u / s w / r g 9 10 11 12 a v l p s a p w t p physical page base address reserved 21 22 symbol description bits avl available to software 11C9 g global 8 ps page size 1 = 4 mbytes 7 reserved = 0 6 a accessed 5 pcd page cache disable 4 pwt page writethrough 3 u/s user/supervisor 2 w/r write/read 1 p present (valid) 0
amd-k5? processor 67 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information virtual-8086 mode extensions (vme) the virtual-8086 mode extensions (vme) bit in cr4 (bit 0) enable performance enhancements for 8086 programs running as protected tasks in virtual-8086 mode. these extensions include: n virtualizing maskable external interrupt control and notification via the vif and vip bits in eflags n selectively intercepting software interrupts (int n instructions) via the interrupt redirection bitmap (irb) in the task state segment (tss) interrupt redirection in virtual-8086 mode without vme extensions. 8086 programs expect to have full access to the interrupt flag (if) in the eflags register, which enables maskable external interrupts via the intr signal. when 8086 programs run in virtual-8086 mode on a 386 or 486 processor, they run as protected tasks and access to the if flag must be controlled by the operating system on a task-by-task basis to prevent corruption of system resources. without the vme extensions available on the amd-k5 processor, the operating system controls virtual-8086 mode access to the if flag by trapping instructions that can read or write this flag. these instructions include sti, cli, pushf, popf, int n , and iret. this method prevents changes to the real if when the i/o privilege level (iopl) in eflags is less than 3, the privilege level at which all virtual-8086 tasks run. the operating system maintains an image of the if flag for each virtual-8086 program by emulating the instructions that read or write if. when an external maskable interrupt occurs, the 3 pwt page writethrough specifies writeback or writethrough cache protocol for all loca- tions in the page mapped by this page-table entry. whether a location is actually cached in a writeback or writethrough state also depends on several other factors. 0 = writeback, 1 = writethrough. 2 u/s user/supervisor 0 = user (any cpl), 1 = supervisor (cpl < 3). 1 w/r write/read 0 = read or execute, 1 = write, read, or execute. 0 p present 0 = not valid, 1 = valid. note: * the amd-k5 processor supports global paging only on models 1, 2, and 3, with a stepping of 4 or greater. table 21. page-table entry (pte) fields (continued) bit mnemonic description function
68 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information operating system checks the state of the if image for the current virtual-8086 program to determine whether the program is allowing interrupts. if the program has disabled interrupts, the operating system saves the interrupt information until the program attempts to re-enable interrupts. the overhead for trapping and emulating the instructions that enable and disable interrupts and the maintenance of virtual interrupt flags for each virtual-8086 program can degrade the processors performance. this performance can be regained by running virtual-8086 programs with iopl set to 3, thus allowing changes to the real if flag from any privilege level, but with a loss in protection. in addition to the performance overhead caused by virtualization of the if flag in virtual-8086 mode, software interrupts (those caused by int n instructions that vector through interrupt gates) cannot be masked by the if flag or virtual copies of the if flag. these flags only affect hardware interrupts. software interrupts in virtual-8086 mode are normally directed to the real mode interrupt vector table (ivt), but it may be desirable to redirect interrupts for certain vectors to the protected mode interrupt descriptor table (idt). the processors virtual-8086 mode extensions support both of these caseshardware (external) interrupts and software interruptswith mechanisms that preserve high performance without compromising protection. virtualization of hardware interrupts is supported via the virtual interrupt flag (vif) and virtual interrupt pending (vip) flag in the eflags register. redirection of software interrupts is supported with the interrupt redirection bitmap (irb) in the tss of each virtual-8086 program. hardware interrupts and the vif and vip extensions. when vme extensions are enabled, the if-modifying instructions that are normally trapped by the operating system are allowed to execute, but they write and read the vif bit rather than the if bit in eflags. this operation leaves maskable interrupts enabled for detection by the operating system. it also indicates to the operating system whether the virtual-8086 program is able to, or expecting to, receive interrupts.
amd-k5? processor 69 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information when an external interrupt occurs, the processor switches from the virtual-8086 program to the operating system, in the same manner as on a 386 or 486 processor. if the operating system determines the interrupt is for the virtual-8086 program, it checks the state of the vif bit in the programs eflags image on the stack. if vif has been set by the processor (during an attempt by the program to set the if bit), the operating system permits access to the appropriate virtual-8086 handler via the interrupt vector table (ivt). if vif has been cleared, the operating system holds the interrupt pending. the operating system can do this by saving appropriate information (such as the interrupt vector), setting the program's vip flag in the eflags image on the stack, and returning to the interrupted program. when the program subsequently attempts to set if, the set vip flag causes the processor to inhibit the instruction and generate a general-protection exception with error code zero, thereby notifying the operating system that the program is now prepared to accept the interrupt. thus, when vme extensions are enabled, the vif and vip bits are set and cleared as follows: n vif this bit is controlled by the processor and used by the operating system to determine whether an external maskable interrupt should be passed on to the program or held pending. vif is set and cleared for instructions that can modify if, and it is cleared during software interrupts through interrupt gates. the original if value is preserved in the eflags image on the stack. n vip this bit is set and cleared by the operating system via the eflags image on the stack. it is set when an interrupt occurs for a virtual-8086 program whose vif bit is cleared. the bit is checked by the processor when the program subsequently attempts to set vif. figure 18 and table 22 show the vif and vip bits in the eflags register. the vme extensions support conventional emulation methods for passing interrupts to virtual-8086 programs, but they make it possible for the operating system to avoid time-consuming emulation of most instructions that write or read the if. the vif and if flags only affect the way the operating system deals with hardware interrupts (the intr signal). software interrupts are handled like machine-generated exceptions and
70 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information cannot be masked by real or virtual copies of if (see software interrupts and the interrupt redirection bitmap (irb) extension on page 75). the vif and vip flags only ease the software overhead associated with managing interrupts so that virtual copies of the if flag do not have to be maintained by the operating system. instead, each tasks tss holds its own copy of these flags in its eflags image. figure 18. eflags register 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 i o p l 31 30 29 28 27 26 25 24 23 22 a f p f z f s f i f d f t f o f n t r f v m a c v i f v i p i d c f reserved symbol description bits id id flag 21 vip virtual interrupt pending 20 vif virtual interrupt flag 19 ac alignment check 18 vm virtual-8086 mode 17 rf resume flag 16 nt nested task 14 iopl i/o privilege level 13C12 of overflow flag 11 df direction flag 10 if interrupt flag 9 tf trap flag 8 sf sign flag 7 zf zero flag 6 af auxiliary flag 4 pf parity flag 2 cf carry flag 0
amd-k5? processor 71 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information tables 23 through 27 show the effects, in various x86-processor modes, of instructions that read or write the if and vif flag. the column headings in this table include the following values: n pe protection enable bit in cr0 (bit 0) n vm virtual-8086 mode bit in eflags (bit 17) n vme virtual mode extensions bit in cr4 (bit 0) n pvi protected-mode virtual interrupts bit in cr4 (bit 1) n iopl i/o privilege level bits in eflags (bits 13C12) n handler cpl code privilege level of the interrupt handler n gp(0) general-protection exception, with error code = 0 n if interrupt flag bit in eflags (bit 9) n vif virtual interrupt flag bit in eflags (bit 19) table 22. virtual-interrupt additions to eflags register bit mnemonic description function 20 vip virtual interrupt pending set by the operating system (via the eflags image on the stack) when an external maskable interrupt (intr) occurs for a virtual-8086 program whose vif bit is cleared. the bit is checked by the processor when the program subsequently attempts to set vif. 19 vif virtual interrupt flag when the vme bit in cr4 is set, the vif bit is modified by the processor when a virtual-8086 program running at less privilege than the iopl attempts to modify the if bit. the vif bit is used by the operating system to determine whether a maskable interrupt should be passed on to the program or held pending. table 23. instructions that modify the if or vif flagsreal mode type pe vm vme pvi iopl gp(0) if vif cli 0000 noif ? 0 sti 0000noif ? 1 pushf 0000nopushed popf 0000nopopped iret 0000nopopped note: not applicable.
72 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information table 24. instructions that modify the if or vif flagsprotected mode type pe vm vme pvi iopl handler cpl gp(0) if vif cli 1 0 0 3 cpl no if ? 0 cli 1 0 0 < cpl yes sti 1 0 0 3 cpl no if ? 1 sti 1 0 0 < cpl yes pushf 1 0 0 3 cpl no pushed pushf 1 0 0 < cpl no pushed pushfd 1 0 0 3 cpl no pushed pushed pushfd 1 0 0 < cpl no pushed pushed popf 1 0 0 3 cpl no popped popf 1 0 0 < cpl no not popped popfd 1 0 0 3 cpl no popped not popped popfd 1 0 0 < cpl no not popped not popped iret 1 0 0 = 0 no popped iret 1 0 0 3 cpl > 0 no* popped iret 1 0 0 < cpl > 0 no* not popped iretd 1 0 0 = 0 no popped popped iretd 1 0 0 3 cpl > 0 no* popped not popped iretd 1 0 0 < cpl > 0 no* not popped not popped notes: * gp(0), if the cpl of the task executing iretd is greater than the cpl of the task to which it is returning. not applicable.
amd-k5? processor 73 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information table 25. instructions that modify the if or vif flagsvirtual-8086 mode type pe vm vme pvi iopl gp(0) if vif cli 110 3 no if ? 0no change cli 110 < 3yes sti 1 1 0 3 no if ? 1no change sti 1 1 0 < 3yes pushf 1 1 0 3 no pushed pushf 110 < 3yes pushfd 1 1 0 3 no pushed pushed pushfd 110 < 3yes popf 1 1 0 3 no popped popf 1 1 0 < 3yes popfd 1 1 0 3 no popped not popped popfd 1 1 0 < 3yes iretd 2 1 1 0 no popped popped notes: 1. all virtual-8086 mode tasks run at cpl = 3. 2. all protected virtual interrupt handlers run at cpl = 0. not applicable.
74 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information table 26. instructions that modify the if or vif flagsvirtual-8086 mode interrupt extensions (vme) 1 type pe vm vme pvi iopl gp(0) if vif cli 111 3noif ? 0 no change cli 111 < 3 no no change vif ? 0 sti 1 1 1 3 no if ? 1 no change sti 1 1 1 < 3 no 3 no change vif ? 1 pushf 1 1 1 3 no pushed not pushed pushf 111 < 3 no not pushed pushed into if pushfd 1 1 1 3 no pushed pushed pushfd 111 < 3yes popf 1 1 1 3 no popped not popped popf 1 1 1 < 3 no not popped popped from if popfd 1 1 1 3 no popped not popped popfd 1 1 1 < 3yes iret from v86 mode 1 1 1 3 no popped not popped iret from v86 mode 111 < 3 no 3 not popped popped from if iretd from v86 mode 1 1 1 3 no popped not popped iretd from v86 mode 111 < 3yes iretd from protected mode 2 111 no 3 popped popped notes: 1. all virtual-8086 mode tasks run at cpl = 3. 2. all protected virtual interrupt handlers run at cpl = 0. 3. gp(0) if an attempt is made to set vif when vip = 1. not applicable.
amd-k5? processor 75 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information software interrupts and the interrupt redirection bitmap (irb) extension. in virtual-8086 mode, software interrupts (int n exceptions that vector through interrupt gates) are trapped by the operating system for emulation because they would otherwise clear the real if. when vme extensions are enabled, these int n instructions are allowed to execute normally, vectoring directly to a virtual-8086 service routine via the virtual-8086 interrupt vector table (ivt) at address 0 of the task address space. however, it may still be desirable for security or performance reasons to intercept int n instructions on a vector-specific basis to allow servicing by protected-mode routines accessed through the interrupt descriptor table (idt). this is accomplished by an interrupt redirection bitmap (irb) in the tss, which is created by the operating system in a manner similar to the io permission bitmap (iopb) in the tss. table 27. instructions that modify the if or vif flagsprotected mode virtual interrupt extensions (pvi) 1 type pe vm vme pvi iopl gp(0) if vif cli 1 0 1 3noif ? 0no change cli 1 0 1 < 3 no no change vif ? 0 sti 1 0 1 3 no if ? 1no change sti 1 0 1 < 3 no 3 no change vif ? 1 pushf 1 0 1 3 no pushed not pushed pushf 1 0 1 < 3 no pushed not pushed pushfd 1 0 1 3 no pushed pushed pushfd 1 0 1 < 3 no pushed pushed popf 1 0 1 3 no popped not popped popf 1 0 1 < 3 no not popped not popped popfd 1 0 1 3 no popped not popped popfd 1 0 1 < 3 no not popped not popped iretd 2 101 no 3 popped popped notes: 1. all protected mode virtual interrupt tasks run at cpl = 3. 2. all protected mode virtual interrupt handlers run at cpl = 0. 3. gp(0) if an attempt is made to set vif when vip = 1. not applicable.
76 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 19 shows the format of the tss with the interrupt redirection bitmap near the top. the irb contains 256 bits, one for each possible software-interrupt vector. the most-significant bit of the irb is located immediately below the base of the iopb. this bit controls interrupt vector 255. the least-significant bit of the irb controls interrupt vector 0. the bits in the irb work as follows: n set if set to 1, the int n instruction behaves as if the vme extensions are not enabled. the interrupt vectors to a protected-mode routine if iopl = 3, or it causes a general-protection exception with error code zero if iopl<3. n cleared if cleared to 0, the int n instruction vectors directly to the corresponding virtual-8086 service routine via the virtual-8086 programs ivt. only software interrupts can be redirected via the irb to a real mode ivthardware interrupts cannot. hardware interrupts are asynchronous events and do not belong to any current virtual task. the processor thus has no way of deciding which ivt (for which virtual-8086 program) to direct a hardware interrupt to. hardware interrupts, therefore, always require operating system intervention. the vif and vip bits described in hardware interrupts and the vif and vip extensions on page 68 are provided to assist the operating system in this intervention.
amd-k5? processor 77 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 19. task state segment (tss) 31 interrupt redirection bitmap (irb) (eight 32-bit locations) 0 i/o permission bitmap (iopb) (up to 8 kbytes) operating system data structure base address of iopb ldt selector 0000h 0000h 0000h 0000h 0000h 0000h 0000h gs fs ds ss cs es edi esi ebp esp ebx edx ecx eax cr3 eflags eip 0000h 0000h 0000h 0000h ss2 ss1 ss0 link (prior tss selector) esp0 esp1 esp2 tss limit from tr 64h 0 t 0000h
78 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information table 28 compares the behavior of hardware and software interrupts in various x86-processor operating modes. it also shows which interrupt table is accessed: the protected-mode idt or the real- and virtual-8086-mode ivt. the column headings in this table include: n pe protection enable bit in cr0 (bit 0) n vm virtual-8086 mode bit in eflags (bit 17) n vme virtual mode extensions bit in cr4 (bit 0) n pvi protected-mode virtual interrupts bit in cr4 (bit 1) n iopl i/o privilege level bits in eflags (bits 13C12) n irb interrupt redirection bit for a task, from the interrupt redirection bitmap (irb) in the tasks tss n gp(0) general-protection exception, with error code = 0 n idt protected-mode interrupt descriptor table n ivt real- and virtual-8086 mode interrupt vector table table 28. interrupt behavior and interrupt-table access mode interrupt type pe vm vme pvi iopl irb gp(0) idt ivt real mode software 0 0 0 0 3 hardware 0 0 0 0 3 protected mode software 1 0 0 3 hardware 1 0 0 3 virtual-8086 mode* software 1 1 0 = 3 no 3 software 1 1 0 < 3 yes 3 hardware 1 1 0 no 3 virtual-8086 mode extensions (vme)* software 1 1 1 0 0 no 3 software 1 1 1 0 = 31 no 3 software 1 1 1 0 < 31 yes 3 hardware 1 1 1 0 no 3 protected virtual extensions (pvi) software 1 0 1 1 no 3 hardware 1 0 1 1 no 3 notes: * all virtual-8086 tasks run at cpl = 3. not applicable.
amd-k5? processor 79 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information protected virtual interrupt (pvi) extensions the protected virtual interrupts (pvi) bit in cr4 enables support for interrupt virtualization in protected mode. in this virtualization, the processor maintains program-specific vif and vip flags in a manner similar to those in virtual-8086 mode extensions (vme). when a program is executed at cpl = 3, it can set and clear its copy of the vif flag without causing general-protection exceptions. the only differences between the vme and pvi extensions are that, in pvi, selective int n interception using the interrupt redirection bitmap in the tss does not apply, and only the sti and cli instructions are affected by the extension. tables 23 through 28 show, among other things, the behavior of hardware and software interrupts as well as instructions that affect interrupts in protected mode with the pvi extensions enabled. model-specific registers (msrs) the processor supports msrs that can be accessed with the rdmsr and wrmsr instructions when cpl = 0. the following index values in the ecx register access specific msrs: n machine-check address register (mcar)ecx = 00h n machine-check type register (mctr)ecx = 01h n time stamp counter (tsc)ecx = 10h n array access register (aar)ecx = 82h n hardware configuration register (hwcr)ecx = 83h n write allocate top-of-memory and control register (watmcr)ecx = 85h n write allocate programmable memory range register (wapmrr)ecx = 86h note: the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater. the rdmsr and wrmsr instructions are described on page 90. the following sections describe the format of the registers.
80 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information machine-check address register (mcar) the processor latches the address of the current bus cycle in its 64-bit machine-check address register (mcar) when a bus-cycle error occurs. these errors are indicated either by (a) system logic asserting buschk, or (b) the processor asserting pchk while system logic asserts pen. the mcar can be read with the rdmsr instruction when the ecx register contains the value 00h. figure 20 shows the format of the mcar register. the contents of the register can be read with the rdmsr instruction. if system software has set the mce bit in cr4 before the bus-cycle error, the processor also generates a machine-check exception as described on page 60. figure 20. machine-check address register (mcar) machine-check type register (mctr) the processor latches the cycle definition and other information about the current bus cycle in its 64-bit machine-check type register (mcar) at the same times that the machine-check address register (mcar) latches the cycle addresswhen a bus-cycle error occurs. these errors are indicated either by (a) system logic asserting buschk, or (b) the processor asserting pchk while system logic asserts pen. the mctr can be read with the rdmsr instruction when the ecx register contains the value 01h. figure 21 and table 29 show the formats of the mctr register. the contents of the register can be read with the rdmsr instruction. the processor clears the chk bit (bit 0) in mctr when the register is read with the rdmsr instruction. if system software has set the mce bit in cr4 before the bus-cycle error, the processor also generates a machine-check exception as described on page 60. 0 63 physical address of last failed bus cycle
amd-k5? processor 81 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 21. machine-check type register (mctr) time stamp counter (tsc) with each processor clock cycle, the processor increments a 64-bit time stamp counter (tsc) msr. the counter can be written or read using the wrmsr or rdmsr instructions when the ecx register contains the value 10h and cpl = 0. the counter can also be read using the rdtsc instruction (see page 89), but the required privilege level for this instruction is determined by the time stamp disable (tsd) bit in cr4. with any of these instructions, the edx and eax registers hold the upper and lower doublewords (dwords) of the 64-bit value to be written to or read from the tsc, as follows: n edx upper 32 bits of tsc n eax lower 32 bits of tsc the tsc can be loaded with any arbitrary value. table 29. machine-check type register (mctr) fields bit mnemonic description function 4 lock locked cycle set to 1 if the processor was asserting lock# during the bus cycle. 3 m/io# memory or i/o 1 = memory cycle, 0 = i/o cycle 2 d/c# data or code 1 = data cycle, 0 = code cycle 1 w/r# write or read 1 = write cycle, 0 = read cycle 0chk valid machine-check data the processor sets the chk bit to 1 when both the mctr and mcar registers contain valid information. the processor clears the chk bit to 0 when software reads the mctr with the rdmsr instruction. symbol description bits lock locked cycle 4 m/io memory or i/o cycle 3 d/c data or code cycle 2 w/r write or read cycle 1 chk valid machine-check data 0 543210 63 c h k d / c w / r l o c k m /i o reserved
82 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information array access register (aar) the array access register (aar) contains pointers for testing the tag and data arrays for the instruction cache, data cache, 4-kbyte tlb, and 4-mbyte tlb. the aar can be written or read with the wrmsr or rdmsr instruction when the ecx register contains the value 82h. for details on the aar, see cache and tlb testing on page 27. hardware configuration register (hwcr) the hardware configuration register (hwcr) contains configuration bits that control miscellaneous debugging functions. the hwcr can be written or read with the wrmsr or rdmsr instruction when the ecx register contains the value 83h. for details on the hwcr, see hardware configuration register (hwcr) on page 22. write allocate registers the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater. use the cpuid instruction to determine if the proper revision of the processor is present (see the amd processor recognition application note , order# 20734, located at http://www.amd.com.). two msrs are defined to support write allocate. the msrs are accessed using the rdmsr and wrmsr instructions (see rdmsr and wrmsr of the amd-k5? processor software development guide , order# 20007). the following index values in the ecx register access the msrs: n write allocate top-of-memory and control register (watmcr)ecx = 85h n write allocate programmable memory range register (wapmrr)ecx = 86h for more information about write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326. three non-write-allocatable memory ranges are defined for use with the write allocate featureone fixed range and two programmable ranges.
amd-k5? processor 83 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information fixed range. the fixed memory range is 000a_0000hC 000f_ffffh and can be enabled or disabled. when enabled, write allocate can not be performed in this range. this region of memory, which includes standard vga and other peripheral and bios access, is considered non-cacheable. performing a write allocate in this area can cause compatibility problems. it is recommended that this bit be enabled (set to 1) to prevent write allocate to this range. set bit 16 of watmcr to enable protection of this range. programmable range. one programmable memory range is xxxx_0000hCyyyy_ffffh, where xxxx and yyyy are defined using bits 15C0 and bits 31C16 of wapmrr, respectively. set bit 17 of watmcr to enable protection of this range. when enabled, write allocate can not be performed in this range. this programmable memory range exists because a small number of uncommon memory-mapped i/o adapters are mapped to physical ram locations. if a card like this exists in the system configuration, it is recommended that the bios program the memory hole for the adapter into this non-write-allocatable range. top of memory. the other programmable memory range is defined by the top-of-memory field. the top of memory is equal to zzzz_0000h, where zzzz is defined using bits 15C0 of watmcr. addresses above zzzz_0000h are protected from write allocate when bit 18 of watmcr is enabled. once the bios determines the size of ram installed in the system, this size should also be used to program the top of memory. for example, a system with 32 mbytes of ram requires that the top-of-memory field be programmed with a value of 0200h, which enables protection from write allocate for memory above that value. set bit 18 of watmcr to enable protection of this range. caching and write allocate are generally not performed for the memory above the amount of physical ram in the system. video frame buffers are usually mapped above physical ram. if write allocate were attempted in that memory area, there could be performance degradation or compatibility problems.
84 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information bits 18C16 of watmcr control the enabling or disabling of the three memory ranges as follows: n bit 18: top-of-memory enable bit 0 = disabled (default) 1 = enabled (write allocate can not be performed above top of memory) n bit 17: programmable range enable bit 0 = disabled (default) 1 = enabled (write allocate can not be performed in this range) n bit 16: fixed range enable bit 0 = disabled (default) 1 = enabled (write allocate can not be performed in this range) figures 22 and 23 show the bit positions for these two new registers. figure 22. write allocate top-of-memory and control register (watmcr)msr 85h figure 23. write allocate programmable memory range register (wapmrr)msr 86h protection control bits top-of-memory enable tme 18 programmable range enable pre 17 fixed range enable fre 16 18 17 16 15 0 63 reserved f r e p r e t m e top of memoryzzzz 19 16 31 32 15 0 63 reserved programmable rangexxxx (low C xxxx_0000h) programmable rangeyyyy (high C yyyy_ffffh)
amd-k5? processor 85 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information enable write allocate write allocate is enabled by setting bit 4 (wa) of the hwcr to 1. for more information on the hwcr, see hardware configuration register (hwcr) on page 22. figure 2 on page 23 shows the revised definition of the hardware configuration register. n ew amd-k5? processor instructions in addition to supporting all the 486 processor instructions, the amd-k5 processor implements the following instructions: n cpuid n cmpxchg8b n mov to and from cr4 n rdtsc n rdmsr n wrmsr n rsm n illegal instruction (reserved opcode)
86 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information cpuid mnemonic opcode description cpuid 0f a2h identify processor and its feature set privilege: any level registers affected: eax, ebx, ecx, edx flags affected: none exceptions generated: none the cpuid instruction is an application-level instruction that software executes to identify the processor and its feature set. this instruction offers multiple functions, each providing a different set of information about the processor. the cpuid instruction can be executed from any privilege level. software can use the information returned by this instruction to tune its functionality for the specific processor and its features. not all processors implement the cpuid instruction. therefore, software must test to determine if the instruction is present on the processor. if the id bit (21) in the eflags register is writeable, the cpuid instruction is implemented. the cpuid instruction supports multiple functions. the information associated with each function is obtained by executing the cpuid instruction with the function number in the eax register. functions are divided into two types: standard functions and extended functions. standard functions are found in the low function space, 0000_0000hC7fff_ffffh. in general, all x86 processors have the same standard function definitions. extended functions are defined specifically for processors supplied by the vendor listed in the vendor identification string. extended functions are found in the high function space, 8000_0000hC8fff_ffffh. because not all vendors have defined extended functions, software must test for their presence on the processor. for more detailed information refer to the amd processor recognition application note , order# 20734, located at http://www.amd.com.
amd-k5? processor 87 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information cmpxchg8b mnemonic opcode description cmpxchg8b r/m64 0f c7h compare and exchange 8-byte operand privilege: any level registers affected: eax, ebx, ecx, edx flags affected: zf exceptions generated: the cmpxchg8b instruction is an 8-byte version of the 4-byte cmpxchg instruction supported by the 486 processor. cmpxchg8b compares a value from memory with a value in the edx and eax register, as follows: n edx upper 32 bits of compare value n eax lower 32 bits of compare value if the memory value matches the value in edx and eax, the zf flag is set to 1 and the 8-byte value in ecx and ebx is written to the memory location, as follows: n ecx upper 32 bits of exchange value n ebx lower 32 bits of exchange value exception real virtual 8086 protected description invalid opcode (6) x x x invalid opcode if destination is a register. stack exception (12) x during instruction execution, the stack segment limit was exceeded. general protection (13) x x x during instruction execution, the effective address of one of the segment registers used for the operand points to an illegal memory location. page fault (14) x x a page fault resulted from the execution of the instruction. alignment check (17) x x an unaligned memory reference resulted from the instruction execution, and the alignment mask bit (am) of the control register (cr0) is set to 1. (in protected mode, cpl = 3.)
88 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information mov to and from cr4 mnemonic opcode description mov cr4, r32 0f 22h move to cr4 from register mov r32 ,cr4 0f 20h move to register from cr4 privilege: cpl = 0 registers affected: cr4, 32-bit general-purpose register flags affected: of, sf, zf, af, pf, and cf are undefined exceptions generated: these instructions read and write control register 4 (cr4). exception real virtual 8086 protected description general protection (13) x x if 1 is written to any reserved bits. x executing this instruction in virtual 8086 mode. x if cpl not = 0.
amd-k5? processor 89 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information rdtsc mnemonic opcode description rdtsc 0f 31h read time stamp counter privilege: selectable by tsd bit in cr4 registers affected: eax, edx flags affected: none exceptions generated: t he amd-k5 processors 64-bit time stamp counter (tsc) increments on each processor clock. in real or protected mode, the counter can be read with the rdmsr instruction and written with the wrmsr instruction when cpl = 0. however, in protected mode, the rdtsc instruction can be used to read the counter at privilege levels higher than cpl = 0. the required privilege level for using the rdtsc instruction is determined by the time stamp disable (tsd) bit in cr4, as follows: n cpl = 0 set the tsd bit in cr4 to 1 n any cpl clear the tsd bit in cr4 to 0 the rdtsc instruction reads the counter value into the edx and eax registers as follows: n edx upper 32 bits of tsc n eax lower 32 bits of tsc the following example shows how the rdtsc instruction can be used. after this code is executed, eax and edx contain the time required to execute the rdtsc instruction. mov ecx,10h ;time stamp counter access via msrs mov eax,00000000h ;initialize the eax part of the counter to zero mov edx,00000000h ;initialize the edx part of the counter to zero db 0fh, 30h ;wrmsr db 0fh, 31h ;rdtsc db 0fh, 31h ;rdtsc exception real virtual 8086 protected description general protection (13) x executing this instruction in virtual 8086 mode. x if cpl not = 0 when tsd bit of cr4 = 1.
90 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information rdmsr and wrmsr mnemonic opcode description rdmsr 0f 32h read model-specific register (msr) wrmsr 0f 30h write model-specific register (msr) privilege: cpl=0 registers affected: eax, ecx, edx flags affected: none exceptions generated: the rdmsr or wrmsr instructions can be used in real or protected mode to access several 64-bit msrs. these registers are addressed by the value in ecx, as follows: n 00h: machine-check address register (mcar). this may contain the physical address of the last bus cycle for which the buschk or pchk signal was asserted. for details, see machine-check address register (mcar) on page 80. n 01h: machine-check type register (mctr). this contains the cycle definition of the last bus cycle for which the buschk or pchk signal was asserted. for details, see machine-check type register (mctr) on page 80. the processor clears the chk bit (bit 0) in mctr when the register is read with the rdmsr instruction. n 10h : time stamp counter (tsc). this contains a time value. the tsc can be initialized to any value with the wrmsr instruction, and it can be read with either the rdmsr or rdtsc instruction. for details, see time stamp counter (tsc) on page 81. n 82h : array access register (aar). this contains an array pointer and test data for testing the processors cache and tlb arrays. for details on the aar, see cache and tlb testing on page 27. n 83h : hardware configuration register (hwcr). this contains configuration bits that control miscellaneous debugging functions. for details, see hardware configuration register (hwcr) on page 22. n 85h : write allocate top-of-memory and control register (watmcr) n 86h : write allocate programmable memory range register (wapmrr) note: the amd-k5 processor supports write allocate only on models 1, 2, and 3, with a stepping of 4 or greater. exception real virtual 8086 protected description general protection (13) x for unimplemented msr address. x executing this instruction in virtual 8086 mode. x for unimplemented msr address or if cpl not = 0.
amd-k5? processor 91 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information the above values in ecx identify the register to be read or written. the edx and eax registers contain the msr values to be read or written, as follows: n edx upper 32 bits of msr. for the aar, this contains the array pointer and (in contrast to all other msrs) its contents are not altered by a rdmsr instruction. n eax lower 32 bits of msr. for the aar, this contains the data to be read/written. all msrs are 64 bits wide. however, the upper 32 bits of the aar are write-only and are not returned on a read. edx remains unaltered, making it more convenient to maintain the array pointer. if an attempt is made to execute either the rdmsr or wrmsr instruction when cpl is greater than 0, or to access an undefined msr, the processor generates a general-protection exception with error code zero. model-specific registers, as their name implies, may or may not be implemented by later models of the amd-k5 processor.
92 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information rsm mnemonic opcode description rsm 0f aah resume execution (exit system management mode) privilege: cpl = 0 registers affected: cs, ds, es, fs, gs, ss, eip, eflags, ldtr, cr3, eax, ebx, ecx, edx, esp, ebp, edi, esi flags affected: none exceptions generated: the rsm instruction should be the last instruction in an system management mode (smm) service routine. it restores the processor state that was saved when the smi interrupt was asserted. this instruction is only valid when the processor is in smm. it generates an invalid opcode exception at all other times. the processor enters the shutdown state if any of the following illegal conditions are encountered during the execution of the rsm instruction: n the smm base value is not aligned on a 32-kbyte boundary n any reserved bit of cr4 is set to 1 n the pg bit is set while the pe is cleared in cr0 n the nw bit is set while the cd bit is cleared in cr0 exception real virtual 8086 protected description invalid opcode (6) x x x invalid opcode if not in smm mode.
amd-k5? processor 93 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information illegal instruction (reserved opcode) mnemonic opcode description (none) 0f ffh illegal instruction (reserved opcode) privilege: any level registers affected: none flags affected: none exceptions generated: this opcode always generates an invalid opcode exception. the opcode will not be used in future amd k86 processors. exception real virtual 8086 protected description invalid opcode (6) x x x invalid opcode if executed.
94 amd-k5? processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information
amd-k6? mmx? enhanced processor 95 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information 4 amd-k6? mmx? enhanced processor the following sections describe additional information required by bios developers to properly incorporate the amd-k6 mmx enhanced processor into a system. the bios for the amd-k6 needs minimal changes in order to fully support the amd-k6 processor family. bios consideration checklist cpuid n use the cpuid instruction to properly identify the amd-k6 processor. n determine the processor type, stepping and features using functions 0000_0001h and 8000_0001h of the cpuid instruction. n boot-up display: the processor name should be displayed as amd-k6(tm)/xxx. see cpu identification algorithms on page 3 for more information.
96 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information cpu speed detection n use speed detection algorithms that do not rely on repetitive instruction sequences. n use the time stamp counter (tsc) to clock a timed operation and compare the result to the real time clock (rtc) to determine the operating frequency. see the example of frequency-determination assembler code available on the amd website at http://www.amd.com. n display the p-rating shown in table 2, summary of amd-k6? mmx? enhanced processor cpu ids and bios boot strings, on page 4. model-specific registers (msrs) n only access msrs implemented in the amd-k6 processor. n enable write allocation by programming the write handling control register (whcr). see write handling control register (whcr) on page 119 and the implementation of write allocate in the k86? processors application note , order# 21326 for more information. cache testing n use the amd-k6 processors bist function to test internal memories. see built-in self-test (bist) on page 106 for more information. the amd-k6 does not contain msrs to allow for cache testing. smm issues n the system management mode (smm) functionality of the amd-k6 processor is identical to pentium. n implement the amd-k6 processor smm state-save area in the same manner as pentium except for the idt base and possibly pentium-reserved areas. see amd-k6? processor system management mode on page 97 for more information.
amd-k6? mmx? enhanced processor 97 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information amd-k6? processor system management mode the system management mode (smm) in the amd-k6 mmx enhanced processor is similar to the amd-k5 processor. this section points out the differences. see amd-k5? processor system management mode (smm) on page 7 for details on the amd-k5 processor implementation of smm. initial register values the general purpose registers and dr6 are unmodified when entering smm. table 30 shows the default register values when entering smm. table 30. initial state of registers in smm register initial contents selector base limit cs 3000h 0003_0000h 4 gbytes ds 0000h 0000_0000h 4 gbytes es 0000h 0000_0000h 4 gbytes fs 0000h 0000_0000h 4 gbytes gs 0000h 0000_0000h 4 gbytes ss 0000h 0000_0000h 4 gbytes general-purpose registers unmodified eflags 0000_0002h eip 0000_8000h cr0 bits 0, 2, 3, and 31 cleared (pe, em, ts, and pg); remainder are unmodified. cr4 0000_0000h gdtr unmodified ldtr unmodified idtr unmodified tr unmodified dr7 0000_0400h dr6 unmodified
98 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information smm state-save area when the smi# is recognized the amd-k6 processor saves its state to the state-save area shown in table 31. if the smi# has been relocated, the state dump begins at cs base + 7fffh (8000 + 7fffh). the default cs base is 30000h. table 31. amd-k6? processor state-save map address offset amd-k5? amd-k6? fffch cr0 cr0 fff8h cr3 cr3 fff4h eflags eflags fff0h eip eip ffech edi edi ffe8h esi esi ffe4h ebp ebp ffe0h esp esp ffdch ebx ebx ffd8h edx edx ffd4h ecx ecx ffd0h eax eax ffcch dr6 dr6 ffc8h dr7 dr7 ffc4h tr tr ffc0h ldtr base ldtr base ffbch gs gs ffb8h fs fs ffb4h ds ds ffb0h ss ss ffach cs cs ffa8h es es ffa4h i/o trap dword i/o trap dword ffa0h CC ff9ch i/o trap eip * i/o trap eip * ff98h C C notes: C no dump at that address. * only contains information if smi# was asserted on a valid corresponding i/o.
amd-k6? mmx? enhanced processor 99 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information ff94h CC ff90h idt base idt base ff8ch idt limit idt limit ff88h gdt base gdt base ff84h gdt limit gdt limit ff80h tss attr tss attr ff7ch tss base tss base ff78h tss limit tss limit ff74h ldt attr C ff70h ldt base ldt low ff6ch ldt limit ldt high ff68h gs attr gs attr ff64h gs base gs base ff60h gs limit gs limit ff5ch fs attr fs attr ff58h fs base fs base ff54h fs limit fs limit ff50h ds attr ds attr ff4ch ds base ds base ff48h ds limit ds limit ff44h ss attr ss attr ff40h ss base ss base ff3ch ss limit ss limit ff38h cs attr cs attr ff34h cs base cs base ff30h cs limit cs limit ff2ch es attr es attr ff28h es base es base ff24h es limit es limit ff20h C C ff1ch C C table 31. amd-k6? processor state-save map (continued) address offset amd-k5? amd-k6? notes: C no dump at that address. * only contains information if smi# was asserted on a valid corresponding i/o.
100 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information smm revision identifier the smm revision identifier specifies the version of smm and the extensions available on the processor. table 32 defines the bits associated with this register. a 1 present in either the i/o trap extension or the smm base relocation indicates this feature is available for use. smm base address this feature is compatible with the amd-k5 processor and pentium. see smm base address on page 12. ff18h CC ff14h cr2 cr2 ff10h cr4 cr4 ff0ch i/o restart esi* i/o restart esi* ff08h i/o restart ecx* i/o restart ecx* ff04h i/o restart edi* i/o restart edi* ff02h halt restart slot halt restart slot ff00h i/o restart slot i/o restart slot fefch smm revid smm revid fef8h smm base smm base fef7Cfe00h C C table 31. amd-k6? processor state-save map (continued) address offset amd-k5? amd-k6? notes: C no dump at that address. * only contains information if smi# was asserted on a valid corresponding i/o. table 32. smm revision identifier 31C18 17 16 15C0 reserved smm base relocation i/o trap extension smm revision level 0 1 1 0002h
amd-k6? mmx? enhanced processor 101 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information auto halt restart this feature is compatible with the amd-k5 processor and the pentium processor. see auto halt restart slot on page 13. i/o trap dword if the assertion of smi# is recognized on the boundary of an i/o bus cycle, the i/o trap doubleword at offset ffa4h in the smm state-save area contains information about the associated i/o instruction. the amd-k6 processor provides additional information at this offset when compared to the amd-k5 processor. the amd-k6 processor provides a bit to determine if the i/o string operand is a rep string operation. the fields of the i/o trap dword are configured as shown in table 33. i/o trap restart this feature is compatible with the amd-k5 processor. see i/o trap restart slot on page 14. exceptions and interrupts within smm this feature is compatible with the amd-k5. see exceptions and interrupts in smm on page 16. table 33. amd-k6? processor i/o trap dword configuration 31C16 15C4 3 2 1 0 i/o port address reserved rep string operation i/o string operation valid i/o instruction input or output
102 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information amd-k6? processor reset state table 34 shows the state of all architecture registers and msrs after the processor has completed its initialization resulting from the recognition of the assertion of reset. table 34. state of the amd-k6? processor after reset register reset state notes gdtr base:0000_0000 limit:0ffffh idtr base:0000_0000 limit:0ffffh tr 0000h ldtr 0000h eip ffff_fff0h eflags 0000_0002h eax 0000_0000h 1 ebx 0000_0000h ecx 0000_0000h edx 0000_056xh 2 esi 0000_0000h edi 0000_0000h ebp 0000_0000h esp 0000_0000h cs f000h ss 0000h ds 0000h es 0000h fs 0000h gs 0000h fpu stack r7Cr0 0000_0000_0000_0000_0000h fpu control word 0040h fpu status word 0000h fpu tag word 5555h notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, then bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6 processor signature. 3. these model-specific registers are described in amd-k6? processor x86 architec- ture extensions on page 117.
amd-k6? mmx? enhanced processor 103 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information segment register attributes see table 10 on page 20 for segment register attribute initial values. fpu instruction pointer 0000_0000_0000h fpu data pointer 0000_0000_0000h fpu opcode register 000_0000_0000b cr0 6000_0010h cr2 0000_0000h cr3 0000_0000h cr4 0000_0000h dr7 0000_0400h dr6 ffff_0ff0h dr3 0000_0000h dr2 0000_0000h dr1 0000_0000h dr0 0000_0000h mcar 0000_0000_0000_0000h mctr 0000_0000_0000_0000h tr12 0000_0000_0000_0000h tsc 0000_0000_0000_0000h efer 0000_0000_0000_0000h 3 star 0000_0000_0000_0000h 3 whcr 0000_0000_0000_0000h 3 table 34. state of the amd-k6? processor after reset (continued) register reset state notes notes: 1. the contents of eax indicate if bist was successful. if eax = 0000_0000h, then bist was successful. if eax is non-zero, bist failed. 2. edx contains the amd-k6 processor signature. 3. these model-specific registers are described in amd-k6? processor x86 architec- ture extensions on page 117.
104 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information state of the amd-k6? processor after init the assertion of init causes the processor to empty its pipelines, initialize most of its internal state, and branch to address ffff_fff0hthe same instruction execution starting point used after reset. unlike reset, the processor preserves the contents of its caches, the floating-point state, the smm base, the mmx state, msrs, and the cd and nw bits of the cr0 register. the edge-sensitive interrupts flush# and smi# are sampled and preserved during the init process and are handled accordingly after the initialization is complete. however, the processor resets any pending nmi interrupt upon sampling init asserted. init can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode. amd-k6? processor cache the internal l1 cache of the amd-k6 mmx enhanced processor consists of two separate cachesa 32-kbyte instruction cache and a 32-kbyte data cache. the instruction cache also incorporates a 20-kbyte pre-decode cache in addition to a 64-entry tlb. the data cache utilizes a 128-entry tlb. the cache line is 32 bytes wide. two adjacent cache lines are associated with each tag (a 64-byte sector with two 32-byte cache lines). the amd-k5 processor uses the array access register (aar), a msr that allows for testing of the processor caches. the amd-k6 processor does not contain these features. the amd-k6 contains a built-in self-test (bist) for all internal memories. however, cache information can be provided by utilizing the cpuid instruction. for more detailed information refer to the amd processor recognition application note , order# 20734, located at http://www.amd.com.
amd-k6? mmx? enhanced processor 105 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information function 8000_0005h of the cpuid instruction returns processor cache information. table 35 shows the information returned by the cpuid instruction when eax = 8000_0005h. amd-k6? processor test and debug the amd-k6 mmx enhanced processor implements various test and debug modes to enable the functional and manufacturing testing of systems and boards that use the processor. in addition, the debug features of the processor allow designers to debug the instruction execution of software components. this section describes the following test and debug features: n built-in self-test (bist) the bist, which is invoked after the falling transition of reset, runs internal tests that exercise most on-chip ram and rom structures. n tri-state test mode a test mode that causes the processor to float its output and bidirectional pins. n boundary-scan test access port (tap) the joint test action group (jtag) test access function defined by the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. table 35. data returned by the cpuid instruction register field bits field description ebx 31C24 data tlbassociativity 23C16 data tlbnumber of entries 15C8 instruction tlbassociativity 7C0 instruction tlbnumber of entries ecx 31C24 l1 data cachesize (kbytes) 23C16 l1 data cacheassociativity 15C8 l1 data cachelines per tag 7C0 l1 data cacheline size (bytes) edx 31C24 l1 instruction cachesize (kbytes) 23C16 l1 instruction cacheassociativity 15C8 l1 instruction cachelines per tag 7C0 l1 instruction cacheline size (bytes) note: full associativity is indicated by a value of ffh.
106 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information n level-one (l1) cache inhibit a feature that disables the processors internal l1 instruction and data caches. n debug support consists of all x86-compatible software debug features, including the debug extensions. built-in self-test (bist) following the falling transition of reset, the processor unconditionally runs its bist. the internal resources tested during bist include the following: n l1 instruction and data caches n instruction and data translation lookaside buffers (tlbs) n microcode read-only memory (rom) n programmable logic arrays the contents of the eax general-purpose register after the completion of reset indicate if the bist was successful. if eax contains 0000_0000h, then bist was successful. if eax is non-zero, the bist failed. following the completion of the bist, the processor jumps to address ffff_fff0h to start instruction execution, regardless of the outcome of the bist. the bist takes approximately 295,000 processor clocks to complete. tri-state test mode the tri-state test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manufacturing testing. in this mode, the processor is electrically isolated from other components on a system board, allowing automated test equipment (ate) to test those components that drive the same signals as those the processor floats. if the flush# signal is sampled low during the falling transition of reset, the processor enters the tri-state test mode. see the amd-k6? mmx? enhanced processor data sheet , order# 20695, for more information.
amd-k6? mmx? enhanced processor 107 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information boundary-scan test access port (tap) the boundary-scan test access port (tap) is an ieee standard that defines synchronous scanning test methods for complex logic circuits, such as boards containing a processor. the amd-k6 processor supports the tap standard defined in the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification. boundary scan testing uses a shift register consisting of the serial interconnection of boundary-scan cells that correspond to each i/o buffer of the processor. this non-inverting register chain, called a boundary scan register (bsr), is used to capture the state of every processor pin and to drive every processor output and bidirectional pin to a known state. each bsr of every component on a board that implements the boundary-scan architecture can be serially interconnected to enable component interconnect testing. tap registers the amd-k6 processor provides an instruction register (ir) and three test data registers (tdr) to support the boundary-scan architecture. the ir and one of the tdrsthe boundary-scan register (bsr)consist of a shift register and an output register. the shift register is loaded in parallel in the capture states (see the ieee standard test access port and boundary-scan architecture (ieee 1149.1-1990) specification for more information). in addition, the shift register is loaded and shifted serially in the shift states. the output register is loaded in parallel from its corresponding shift register in the update states. instruction register (ir). the ir is a 5-bit register, without parity, that determines which instruction to run and which test data register to select. when the tap controller enters the capture-ir state, the processor loads the following bits into the ir shift register: n 01b loaded into the two least significant bits, as specified by the ieee 1149.1 standard n 000b loaded into the three most significant bits loading 00001b into the ir shift register during the capture-ir state results in loading the sample/preload instruction. for each entry into the shift-ir state, the ir shift register is serially shifted by one bit toward the tdo pin. during the shift, the most significant bit of the ir shift register is loaded from the tdi pin.
108 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information the ir output register is loaded from the ir shift register in the update-ir state, and the current instruction is defined by the ir output register. see tap instructions on page 111 for a list and definition of the instructions supported by the amd-k6. boundary scan register (bsr). the bsr is a test data register consisting of the interconnection of 152 boundary-scan cells. each output and bidirectional pin of the processor requires a two-bit cell, where one bit corresponds to the pin and the other bit is the output enable for the pin. when a 0 is shifted into the enable bit of a cell, the corresponding pin is floated, and when a 1 is shifted into the enable bit, the pin is driven valid. each input pin requires a one-bit cell that corresponds to the pin. the last cell of the bsr is reserved and does not correspond to any processor pin. the total number of bits that comprise the bsr is 281. table 36 on page 109 lists the order of these bits, where tdi is the input to bit 280, and tdo is driven from the output of bit 0. the entries listed as pin _e (where pin is an output or bidirectional signal) are the enable bits. if the bsr is the register selected by the current instruction and the tap controller is in the capture-dr state, the processor loads the bsr shift register as follows: n if the current instruction is sample/preload, then the current state of each input, output, and bidirectional pin is loaded. a bidirectional pin is treated as an output if its enable bit equals 1, and it is treated as an input if its enable bit equals 0. n if the current instruction is extest, then the current state of each input pin is loaded. a bidirectional pin is treated as an input, regardless of the state of its enable. while in the shift-dr state, the bsr shift register is serially shifted toward the tdo pin. during the shift, bit 280 of the bsr is loaded from the tdi pin. the bsr output register is loaded with the contents of the bsr shift register in the update-dr state. if the current instruction is extest, the processors output pins, as well as those bidirectional pins that are enabled as outputs, are driven with their corresponding values from the bsr output register.
amd-k6? mmx? enhanced processor 109 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information table 36. boundary scan register bit definitions bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable 280 d35_e 247 d21 214 d4_e 181 a3 148 a20 115 a16 279 d35 246 d18_e 213 d4 180 a31_e 147 a13_e 114 ferr_e 278 d29_e 245 d18 212 dp0_e 179 a31 146 a13 113 ferr# 277 d29 244 d19_e 211 dp0 178 a21_e 145 dp7_e 112 hit_e 276 d33_e 243 d19 210 hold 177 a21 144 dp7 111 hit# 275 d33 242 d16_e 209 boff# 176 a30_e 143 be6_e 110 be7_e 274 d27_e 241 d16 208 ahold 175 a30 142 be6 109 be7 273 d27 240 d17_e 207 stpclk# 174 a7_e 141 a12_e 108 na# 272 dp3_e 239 d17 206 init 173 a7 140 a12 107 adsc_e 271 dp3 238 d15_e 205 ignne# 172 a24_e 139 clk 106 adsc# 270 d25_e 237 d15 204 bf1 171 a24 138 be4_e 105 be5_e 269 d25 236 dp1_e 203 bf2 170 a18_e 137 be4 104 be5# 268 d0_e 235 dp1 202 reset 169 a18 136 a10_e 103 wb/wt# 267 d0 234 d13_e 201 bf0 168 a5_e 135 a10 102 pwt_e 266 d30_e 233 d13 200 flush# 167 a5 134 d63_e 101 pwt 265 d30 232 d6_e 199 intr 166 a22_e 133 d63 100 be3_e 264 dp2_e 231 d6 198 nmi 165 a22 132 be2_e 99 be3# 263 dp2 230 d14_e 197 smi# 164 eads# 131 be2 98 breq_e 262 d2_e 229 d14 196 a25_e 163 a4_e 130 a15_e 97 breq 261 d2 228 d11_e 195 a25 162 a4 129 a15 96 pcd_e 260 d28_e 227 d11 194 a23_e 161 hitm_e 128 brdy# 95 pcd 259 d28 226 d1_e 193 a23 160 hitm# 127 be1_e 94 w_e 258 d24_e 225 d1 192 a26_e 159 a9_e 126 be1 93 w/r# 257 d24 224 d12_e 191 a26 158 a9 125 a14_e 92 smiact_e 256 d26_e 223 d12 190 a29_e 157 scyc_e 124 a14 91 smiact# 255 d26 222 d10_e 189 a29 156 scyc 123 brdyc# 90 ewbe# 254 d22_e 221 d10 188 a28_e 155 a8_e 122 be0_e 89 dc_e 253 d22 220 d7_e 187 a28 154 a8 121 be0 88 d/c# 252 d23_e 219 d7 186 a27_e 153 a19_e 120 a17_e 87 apchk_e 251 d23 218 d8_e 185 a27 152 a19 119 a17 86 apchk# 250 d20_e 217 d8 184 a11_e 151 a6_e 118 ken# 85 cache_e 249 d20 216 d9_e 183 a11 150 a6 117 a20m# 84 cache# 248 d21_e 215 d9 182 a3_e 149 a20_e 116 a16_e 83 ads_e
110 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information device identification register (dir). the dir is a 32-bit test data register selected during the execution of the idcode instruction. the fields of the dir and their values are shown in table 37 and are defined as follows: n version code this 4-bit field is incremented by amd manufacturing for each major revision of silicon. n part number this 16-bit field identifies the specific processor model. n manufacturer this 11-bit field identifies the manufacturer of the component (amd). n lsb the least significant bit (lsb) of the dir is always set to 1, as specified by the ieee 1149.1 standard. bypass register (br). the br is a test data register consisting of a 1-bit shift register that provides the shortest path between tdi and tdo. when the processor is not involved in a test 82 ads# 68 dp6_e 54 d53_e 40 d43_e 26 d38_e 12 d3_e 81 ap_e 67 dp6 53 d53 39 d43 25 d38 11 d3 80 ap 66 d54_e 52 d47_e 38 d62_e 24 d58_e 10 d39_e 79 inv 65 d54 51 d47 37 d62 23 d58 9 d39 78 hlda_e 64 d50_e 50 d59_e 36 d49_e 22 d42_e 8 d32_e 77 hlda 63 d50 49 d59 35 d49 21 d42 7 d32 76 pchk_e 62 d56_e 48 d51_e 34 dp4_e 20 d36_e 6 d5_e 75 pchk# 61 d56 47 d51 33 dp4 19 d36 5 d5 74 lock_e 60 d55_e 46 d45_e 32 d46_e 18 d60_e 4 d37_e 73 lock# 59 d55 45 d45 31 d46 17 d60 3 d37 72 m_e 58 d48_e 44 d61_e 30 d41_e 16 d40_e 2 d31_e 71 m/io# 57 d48 43 d61 29 d41 15 d40 1 d31 70 d52_e 56 d57_e 42 dp5_e 28 d44_e 14 d34_e 0 reserved 69 d52 55 d57 41 dp5 27 d44 13 d34 table 36. boundary scan register bit definitions (continued) bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable bit pin/enable table 37. amd-k6? processor device identification register version code (bits 31C28) part number (bits 27C12) manufacturer (bits 11C1) lsb (bit 0) xh 0560h 00000000001b 1b
amd-k6? mmx? enhanced processor 111 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information operation, the br can be selected by an instruction to allow the transfer of test data through the processor without having to serially scan the test data through the bsr. this functionality preserves the state of the bsr and significantly reduces test time. the br register is selected by the bypass and highz instructions as well as by any instructions not supported by the amd-k6. tap instructions the processor supports the three instructions required by the ieee 1149.1 standardextest, sample/preload, and bypassas well as two additional optional instructions idcode and highz. table 38 shows the complete set of tap instructions supported by the processor along with the 5-bit instruction register encoding and the register selected by each instruction. extest. when the extest instruction is executed, the processor loads the bsr shift register with the current state of the input and bidirectional pins in the capture-dr state and drives the output and bidirectional pins with the corresponding values from the bsr output register in the update-dr state. table 38. supported tap instructions instruction encoding register description extest 1 00000b bsr sample inputs and drive outputs sample / preload 00001b bsr sample inputs and outputs, then load the bsr idcode 00010b dir read dir highz 00011b br float outputs and bidirectional pins bypass 2 00100b C11110b br undefined instruction, execute the bypass instruction bypass 3 11111b br connect tdi to tdo to bypass the bsr notes: 1. following the execution of the extest instruction, the processor must be reset in order to return to normal, non-test operation. 2. these instruction encodings are undefined on the amd-k6 processor and default to the bypass instruction. 3. because the tdi input contains an internal pullup, the bypass instruction is executed if the tdi input is not connected or open during an instruction scan operation. the bypass instruction does not affect the normal operational state of the processor.
112 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information sample/preload. the sample/preload instruction performs two functions. these functions are as follows: n during the capture-dr state, the processor loads the bsr shift register with the current state of every input, output, and bidirectional pin. n during the update-dr state, the bsr output register is loaded from the bsr shift register in preparation for the next extest instruction. the sample/preload instruction does not affect the normal operational state of the processor. bypass. the bypass instruction selects the br register, which reduces the boundary-scan length through the processor from 281 to one (tdi to br to tdo). the bypass instruction does not affect the normal operational state of the processor. idcode. the idcode instruction selects the dir register, allowing the device identification code to be shifted out of the processor. this instruction is loaded into the ir when the tap controller is reset. the idcode instruction does not affect the normal operational state of the processor. highz. the highz instruction forces all output and bidirectional pins to be floated. during this instruction, the br is selected and the normal operational state of the processor is not affected. l1 cache inhibit purpose the amd-k6 mmx enhanced processor provides a means for inhibiting the normal operation of its l1 instruction and data caches while still supporting an external level-two (l2) cache. this capability allows system designers to disable the l1 cache during the testing and debug of an l2 cache. if the cache inhibit bit (bit 3) of test register 12 (tr12) is set to 0, the processors l1 cache is enabled and operates as described in the cache organization section of the amd-k6? mmx? enhanced processor data sheet , order# 20695. if the cache inhibit bit is set to 1, the l1 cache is disabled and no new cache lines are allocated. even though new allocations do not occur, valid l1 cache lines remain valid and are read by the
amd-k6? mmx? enhanced processor 113 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information processor when a requested address hits a cache line. in addition, the processor continues to support inquire cycles initiated by the system logic, including the execution of writeback cycles when a modified cache line is hit. while the l1 is inhibited, the processor continues to drive the pcd output signal appropriately, which system logic can use to control external l2 caching. in order to completely disable the l1 cache so no valid lines exist in the cache, the cache inhibit bit must be set to 1 and the cache must be flushed in one of the following ways: n by asserting the flush# input signal n by executing the wbinvd instruction n by executing the invd instruction (modified cache lines are not written back to memory) debug the amd-k6 processor implements the standard x86 debug functions, registers, and exceptions. in addition, the processor supports the i/o breakpoint debug extension. the debug feature assists programmers and system designers during software execution tracing by generating exceptions when one or more events occur during processor execution. the exception handler, or debugger, can be written to perform various tasks, such as displaying the conditions that caused the breakpoint to occur, displaying and modifying register or memory contents, or single-stepping through program execution. the following sections describe the debug registers and the various types of breakpoints and exceptions supported by the processor. for more details on the register definitions see the test and debug chapter in the amd-k6? mmx? enhanced processor data sheet , order# 20695. debug registers figures 24 through 27 show the 32-bit debug registers supported by the processor. table 39 provides len and rw information for dr7 as displayed in figure 24.
114 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 24. debug register dr7 . table 39. dr7 len and rw definitions len bits 1 rw bits breakpoint 00b 00b 2 instruction execution 00b 01b one-byte data write 01b two-byte data write 11b four-byte data write 00b 10b 3 one-byte i/o read or write 01b two-byte i/o read or write 11b four-byte i/o read or write 00b 11b one-byte data read or write 01b two-byte data read or write 11b four-byte data read or write notes: 1. len bits equal to 10b is undefined. 2. when rw equals 00b, len must be equal to 00b. 3. when rw equals 10b, debugging extensions (de) must be enabled (bit 3 of cr4 must be set to 1). if de is set to 0, rw equal to 10b is undefined. 9876543210 10 11 12 13 14 15 l 2 l 1 l 3 g 3 g e l e l 0 reserved g 0 g 1 l 2 g d 25 24 23 22 21 20 19 18 17 16 26 27 28 29 30 31 r/w 3 len 3 r/w 2 len 2 r/w 1 len 1 r/w 0 len 0 symbol description bits len 3 length of breakpoint #3 31C30 r/w 3 type of transaction(s) to trap 29C28 len 2 length of breakpoint #2 27C26 r/w 2 type of transaction(s) to trap 25C24 len 1 length of breakpoint #1 23C22 r/w 1 type of transaction(s) to trap 21C20 len 0 length of breakpoint #0 19C18 r/w 0 type of transaction(s) to trap 17C16 symbol description bit gd general detect enabled 13 ge global exact breakpoint enabled 9 le local exact breakpoint enabled 8 g3 global exact breakpoint # 3 enabled 7 l3 local exact breakpoint # 3 enabled 6 g2 global exact breakpoint # 2 enabled 5 l2 local exact breakpoint # 2 enabled 4 g1 global exact breakpoint # 1 enabled 3 l1 local exact breakpoint # 1 enabled 2 g0 global exact breakpoint # 0 enabled 1 l0 local exact breakpoint # 0 enabled 0
amd-k6? mmx? enhanced processor 115 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 25. debug register dr6 figure 26. debug registers dr5 and dr4 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 b 1 b 2 b s b 0 reserved b t b d symbol description bit bt breakpoint task switch 15 bs breakpoint single step 14 bd breakpoint debug access detected 13 b3 breakpoint #3 condition detected 3 b2 breakpoint #2 condition detected 2 b1 breakpoint #1 condition detected 1 b0 breakpoint #0 condition detected 0 b 3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr5 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 reserved dr4
116 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information figure 27. debug registers dr3, dr2, dr1, and dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 3 32-bit linear address dr3 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 0 32-bit linear address dr0 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 2 32-bit linear address dr2 9876543210 10 11 12 13 14 15 16 17 18 19 20 21 31 30 29 28 27 26 25 24 23 22 breakpoint 1 32-bit linear address dr1
amd-k6? mmx? enhanced processor 117 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information amd-k6? processor x86 architecture extensions this section documents the extensions that have been added to the amd-k6 mmx enhanced processor. model-specific registers (msr) the amd-k6 processor provides the following six msrs. the contents of ecx selects the msr to be addressed by the rdmsr and wrmsr instruction. n machine-check address register (mcar)ecx = 00h n machine-check type register (mctr)ecx = 01h n test register 12 (tr12)ecx = 0eh n time stamp counter (tsc)ecx = 10h n extended feature enable register (efer)ecx = c000_0080h n syscall target address register (star)ecx = c000_0081h n write handling control register (whcr)ecx = c000_0082h these six msrs are read and written by the rdmsr and wrmsr instructions. (the tsc can also be read by the rdtsc instruction.) the target register for the rdmsr and wrmsr instructions is addressed by the contents of ecx. the only values allowed in ecx by the amd-k6 processor are 00h, 01h, 0eh, 10h, c000_0080h, c000_0081h, and c000_0082h for the mcar, mctr, tr12, tsc, efer, star and whcr registers respectively. the usage of any other reserved value in ecx results in a general protection exception. machine-check address register (mcar) see figure 20 on page 80 and machine check exception on page 122. machine-check type register (mctr) see figure 21 on page 81 and machine check exception on page 122.
118 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information test register 12 (tr12) the amd-k6 processor also provides the 64-bit test register 12 (tr12), but only the function of the cache inhibit (ci) bit (bit 3 of tr12) is supported. all other bits in tr12 have no effect on the processors operation. the i/o trap restart function (bit 9 of tr12) is always enabled on the amd-k6. time stamp counter (tsc) see time stamp counter (tsc) on page 81. extended feature enable register (efer) the extended feature enable register (efer) contains the control bits that enable the extended features of the amd-k6 processor. figure 28 shows the format of the efer register, and table 40 defines the function of each bit of the efer register. the efer register is msr c000_0080h. figure 28. extended feature enable register (efer) syscall target address register (star) the syscall target address register (star) contains the target eip address used by the syscall instruction, and contains the 16-bit selector base used by the syscall and sysret instructions. figure 29 shows the format of the star register, and table 41 defines the fields of the star register. the star register is msr c000_0081h. table 40. extended feature enable register (efer) definition bit description r/w function 63C1 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 0 system call extension (sce) r/w sce must be set to 1 to enable the usage of the syscall and sysret instructions. 10 63 s c e reserved symbol description bit sce system call extension 0
amd-k6? mmx? enhanced processor 119 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information figure 29. syscall target address register (star) write handling control register (whcr) the amd-k6 processor contains a split level-one (l1) 64-kbyte writeback cache organized as a separate 32-kbyte instruction cache and a 32-kbyte data cache with two-way set associativity. the cache line size is 32 bytes, and lines are read from memory using an efficient pipelined burst read cycle. further performance gains are achieved by the implementation of a write allocation scheme. for more information about write allocate, see the implementation of write allocate in the k86? processors application note , order# 21326. write allocate, if enabled, occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the l1 cache. in this case, the processor performs a burst read cycle to fetch the cache line addressed by the pending write cycle. the data associated with the pending write cycle is merged with the recently-allocated data-cache line and stored in the processors l1 data cache. the table 41. syscall target address register (star) definition bit description r/w function 31C0 target eip address r/w this address is copied into the eip and points to the new starting address. 47C32 cs and ss selector base r/w during the syscall instruction, this field is copied into the cs register and the contents of this field, plus 8, are copied into the ss register. during the sysret instruction, this field, plus 16, is copied into the ss register, and bits 1C0 of the ss register are set to 11b. 63C48 reserved r writing a 1 to any reserved bit causes a general protection fault to occur. all reserved bits are always read as 0. 31 0 63 target eip address reserved 32 47 48 cs selector and ss selector base
120 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information final mesi state of the cache line depends on the state of the wb/wt# and pwt signals during the burst read cycle and the subsequent cache write hit. write handling control register (whcr). the write handling control register (whcr) is an msr that contains three fieldsthe wcde bit, the write allocate enable limit (waelim) field, and the write allocate enable 15-to-16-mbyte (wae15m) bit (see figure 30). figure 30. write handling control register (whcr)msr c000_0082h write cacheability detection enable. when the write cacheability detection enable (wcde) bit (bit 8) of the write handling control register (whcr) msr is set to 1, this write allocate mechanism is enabled. for more details on the write cacheability detection mechanism, see the cache organization chapter in the amd-k6? mmx? enhanced processor data sheet , order# 20695. if the address is cacheable, support of the write cacheability detection mechanism requires the system logic to assert ken# during a write cycle. some chipsets assert ken# during a write cycle and some chipsets do not assert ken# during a write cycle. (triton chipsets eventually generate a correct value for ken#, but not during the sample point. therefore do not enable wcde in systems that use the triton chipset.) if write cacheability detection is enabled, ken# is sampled during write cycles in the same manner it is sampled during read cycles (ken# is sampled on the clock edge on which the first brdy# or na# of a cycle is sampled asserted). future chipsets may take advantage of this mechanism, but currently amd recommends setting this bit to zero (disabled). 710 63 reserved waelim 8 w c d e note : hardware reset initializes this msr to all zeros. w a e 1 5 m symbol description bits wcde write cacheability detection enable 8 waelim write allocate enable limit 7C1 wae15m write allocate enable 15-to-16-mbyte 0
amd-k6? mmx? enhanced processor 121 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information write allocate enable limit. the waelim field is 7 bits wide. this field, multiplied by 4 mbytes, defines an upper memory limit. any pending write cycle that addresses memory below this limit causes the processor to perform a write allocate. write allocate is disabled for memory accesses at and above this limit unless the processor determines a pending write cycle is cacheable by means of one of the other write cacheability detection mechanisms. the maximum value of this limit is ((2 7 C1) 4 mbytes) = 508 mbytes. when all the bits in this field are set to 0, all memory is above this limit and the write allocate mechanism is disabled. write allocate enable 15-to-16-mbyte. the wae15m bit is used to enable write allocations for the memory write cycles that address the 1 mbyte of memory between 15 mbytes and 16 mbytes. this bit must be set to 0 to prevent write allocates in this memory area. this sub-mechanism of the waelim provides a memory hole to prevent write allocates. this memory hole is provided to account for a small number of uncommon memory-mapped i/o adapters that use this particular memory address space. if the system contains one of these peripherals, the bit should be set to 0. the wae15m bit is ignored if the value in the waelim field is set to less than 16 mbytes. by definition, write allocations in the amd-k6 processor are never performed in the memory area between 640 kbytes and 1 mbyte. it is not safe to perform write allocations between 640 kbytes and 1 mbyte (000a_0000h to 000f_ffffh) because it is considered a non-cacheable region of memory. see the software environment section of the amd-k6? mmx? enhanced processor data sheet , order# 20695, for more information. note: the bios should enable the write allocate mechanisms only after performing any memory sizing and typing algorithms.
122 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information machine check exception the amd-k6 processor does not support the generation of a machine check exception. the processor provides a 64-bit machine check address register (mcar) and a 64-bit machine check type register (mctr), but because the processor does not support machine check exceptions, the contents of the mcar and mctr are only affected by the wrmsr instruction and by reset being sampled asserted (where all bits in each register are reset to 0). the processor also provides the machine check exception (mce) bit in control register 4 (cr4, bit 6) as a read-write bit. however, the state of this bit has no effect on the operation of the processor. the processor does not provide the buschk and pen signals provided by pentium. new amd-k6? processor instructions this section documents and explains the new instructions added to the amd-k6 processor above and beyond the amd-k5 processor. n syscall n sysret n mmx? instructions57 new instructions for multimedia software. see mmx? instructions on page 127. system call extensions setting bit 0 (sce) in the extended feature enable register (see extended feature enable register (efer) on page 118) enables the system call extensions. the system call extensions consist of two new instructions, syscall and sysret, that allow os vendors fast protection-level switching to and from cpl0.
amd-k6? mmx? enhanced processor 123 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information syscall mnemonic opcode description syscall 0f05h call operating system privilege: none registers affected: ecx, eip, cs, ss flags affected: if, vm machine state affected: cpl, cs (base, limit, attr), ss (base, limit, attr) exceptions generated: the syscall instruction provides a fast method for transferring control to a fixed entry point in an operating system. the eip register is copied into the ecx register. bits 31C0 of the 64-bit syscall target address register (see syscall target address register (star) on page 118) are copied into the eip register. (the star register is model-specific register c000_0081h.) the if and vm flags are set to 0 to disable interrupts and force the processor out of virtual-8086 mode. new selectors are loaded with no checking performed as follows: n bits 47C32 of the star register are copied into the cs register n (bits 47C32 of the star register) + 8 are copied into the ss register the cs and ss registers must not be modified by the operating system between the execution of the syscall instruction and its corresponding sysret instruction. the processors cpl is set to 0 regardless of the value of bits 33C32 of the star register. there are no permission checks of the cpl, real mode, or virtual-8086 mode. exception real virtual 8086 protected description invalid opcode (6) x x x the system call extension bit (sce) of the extended feature enable register (efer) is set to 0. (the efer register is msr c000_0080h.)
124 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information the following descriptors are loaded to specify fixed 4-gbyte flat segments as follows: n the cs_base and the ss_base are both set to zero n the cs_limit and the ss_limit are both set to 4-gbyte n the cs segment attributes are set to read-only n the ss segment attributes are set to read-write and expand-up the operating system must set the star register and the appropriate descriptor table entries to reflect the values loaded by the processor during the syscall instruction. related instructions see the sysret instruction.
amd-k6? mmx? enhanced processor 125 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information sysret mnemonic opcode description sysret 0f07h return from operating system privilege: cpl = 0 registers affected: eip, cs, ss flags affected: if machine state affected: cpl, cs (base, limit, attr) exceptions generated: the sysret instruction is the return instruction used in conjunction with the syscall instruction to provide fast entry/exit to an operating system. the ecx register, which points to the next sequential instruction after the corresponding syscall instruction, is copied into the eip register. the if flag is set to 1 in order to enable interrupts. new selectors are loaded without any checking as follows: n bits 47C32 of the star register are copied into the cs register n bits 1C0 of the cs register are set to 11b (cpl of 3), regardless of the value of bits 33C32 of the star register n (bits 47C32 of the star register) + 16 are copied into the ss register n bits 1C0 of the ss register are set to 11b (rpl of 3), regardless of the value of bits 33C32 of the star register the cs and ss registers must not be modified by the operating system between the execution of the syscall instruction and its corresponding sysret instruction. if the cpl is not equal to 0 when the sysret instruction is executed, a general protection fault exception is generated with an error code of 0. exception real virtual 8086 protected description invalid opcode (6) x x x the system call extension bit (sce) of the extended feature enable register (efer) is set to 0. (the efer register is msr c000_0080h.) general protection (13) x x x the cpl is not equal to 0.
126 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information a new descriptor is loaded for cs to specify a fixed 4-gbyte flat segment as follows: n the cs_base is set to zero n the cs_limit is set to 4-gbyte n the cs segment attributes are set to read-only the operating system must set the star register and the appropriate descriptor table entries to reflect the values loaded by the processor during the syscall instruction. related instructions see the syscall instruction.
amd-k6? mmx? enhanced processor 127 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information mmx? instructions the amd-k6 mmx enhanced processor implements the complete mmx instruction set. for a detailed description refer to amd-k6? mmx? enhanced processor multimedia technology , order# 20726, located at http://www.amd.com. table 42 lists the mmx instructions. table 42. mmx? instructions and descriptions instruction description emms empty mmx state movd move 32 bits movq move 64 bits packsswb /packssdw pack with signed saturation packuswb pack with unsigned saturation paddb/paddw/paddd packed add paddsb/paddsw packed add with saturation paddusb/paddusw packed add unsigned with saturation pand bitwise logical and pandn bitwise logical and not pxor bitwise logical exclusive or por bitwise logical or pcmpeqb/pcmpeqw/pcmpeqd packed compare for equal pcmpgtb/pcmpgtw/pcmpgtd packed compare for greater than pmaddwd packed multiply and add pmullw packed multiply low pmulhw packed multiply high psllw/pslld/psllq packed shift left logical psraw/psrad packed shift right arithmetic psrlw/psrld/psrlq packed shift right logical psubb/psubw/psubd packed subtract psubsb/psubsw packed subtract with saturation psubusb/psubsw packed subtract unsigned with saturation punpckhbw/punpckhwd/punpckhdq unpack high packed data punpcklbw/punpcklwd/punpckldq unpack low packed data
128 amd-k6? mmx? enhanced processor amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information
index 129 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information index numerics 4-kbyte paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4-mbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 64 4-mbyte paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 a additions to the eflags register. . . . . . . . . . . . . . . . . . . . 58 all0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 all1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 amd-k5 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 cpu ids and bios boot strings . . . . . . . . . . . . . . . . . . . . . . 4 device identification register . . . . . . . . . . . . . . . . . . . . . . 45 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 state-save area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 system management mode (smm) . . . . . . . . . . . . . . . . . . . 7 test and debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 x86 architecture extensions. . . . . . . . . . . . . . . . . . . . . . . . 57 amd-k6 mmx enhanced processor . . . . . . . . . . . . . . . . . . . 95 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 cpu ids and bios boot strings . . . . . . . . . . . . . . . . . . . . . . 4 device identification register . . . . . . . . . . . . . . . . . . . . . 110 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 state-save area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 system management mode (smm) . . . . . . . . . . . . . . . . . . 97 test and debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 x86 architecture extensions. . . . . . . . . . . . . . . . . . . . . . . 117 array access register (aar) . . . . . . . . . . . . . . . . . . . . . 28 , 82 array ids in array pointers . . . . . . . . . . . . . . . . . . . . . . . . . 29 array pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 array test data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 C 29 auto halt restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 , 101 b bios consideration checklist . . . . . . . . . . . . . . . . . . . . . . 5 , 95 bist error bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 bits dbp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 de. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 dic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dspc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 gpe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 mce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 C 60 ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 pse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 pvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 79 tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 tsd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 81 vif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 vip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 vme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 67 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 register (bsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 108 register bit definitions . . . . . . . . . . . . . . . . . . . . . . . 49 , 109 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 test functional description . . . . . . . . . . . . . . . . . . . . . . . . 42 branch tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 built-in self-test (bist) . . . . . . . . . . . . . . . . . . . . . . . . 24 , 106 buschk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bypass instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 , 112 bypass register (br). . . . . . . . . . . . . . . . . . . . . . . . . . . 45 , 110 c cache testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 27 , 96 clocks, disable stopping . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cmpxchg8b instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 control bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 control register 4 (cr4) . . . . . . . . . . . . . . . . . . . . . . . . 58 C 59 cpu identification algorithms . . . . . . . . . . . . . . . . . . . . . . . 3 cpu speed detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 96 cpuid instruction . . . . . . . . . . . . . . . . . . . . . . . . 5 , 86 , 95 , 105 cr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 d dbp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ddc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 de . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 branch tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 compatibility with the pentium processor . . . . . . . . . . . 39 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 i/o breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 , 113 C 116 device identification register (dir) . . . . . . . . . . . . . 45 , 110 dic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable branch prediction . . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable instruction cache. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable stopping processor clocks . . . . . . . . . . . . . . . . . . . 24 dspc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 e eflags register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 enable write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 in smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 , 101 machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 extensions extended feature enable register (efer) . . . . . . . . . . 118 vif and vip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 extest instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 111
130 index amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information f flags vif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 vip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 float test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 flush# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 functional-redundancy checking . . . . . . . . . . . . . . . . . . . . 40 g g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 global page extension . . . . . . . . . . . . . . . . . . . . . . . .59 , 64 C 66 global pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C 66 gpe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 h halt restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 , 101 halt state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 hardware configuration register (hwcr). . . . . . .22 C 23 , 82 hardware debug tool (hdt) . . . . . . . . . . . . . . . . . . . . . . . . 57 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 hdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 , 112 hwcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 C 23 , 82 i i/o breakpoint extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 , 101 trap restart slot. . . . . . . . . . . . . . . . . . . . . . . . . . .14 C 15 , 101 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 , 112 illegal instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 initial register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 97 instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . 44 , 107 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 85 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 cmpxchg8b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 cpuid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 , 86 , 95 extest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 111 highz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 , 112 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 , 112 illegal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 modification of the if or vif flags . . . . . . . . . . . . . . . 71 C 75 mov to/from cr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 public tap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 C 46 rdmsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 rdtsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 rsm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 runbist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sample/preload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 syscall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 C 123 sysret . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 , 125 usehdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 wrmsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 interrupt redirection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interrupt redirection bitmap (irb) . . . . . . . . . . . . . . . . 68 , 75 interrupts hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 in smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 , 101 interrupt-table access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 irb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 , 75 software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 virtual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 intr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 irb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 75 j jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 105 l l1 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 m machine check exception . . . . . . . . . . . . . . . . . . . . . . . . . 122 machine-check address register (mcar). . . . . . 60 , 80 , 117 machine-check enable . . . . . . . . . . . . . . . . . . . . . . . . . . 59 C 60 machine-check exception . . . . . . . . . . . . . . . . . . . . . . . . . . 60 machine-check type register (mctr) . . . . . 60 , 80 C 81 , 117 mmx instructions and descriptions . . . . . . . . . . . . . . . . . 127 mode, operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 model-specific registers (msrs). . . . . . . . . . . . 6 , 79 , 96 , 117 mov to/from cr4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 msrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 79 , 96 , 117 multimedia software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 n nmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 normal bist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 o opcodes, reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 output-float test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 p page size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 page size extension. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 C 60 page-directory entry (pde) . . . . . . . . . . . . . . . . . . . . . . 63 C 64 pages, 4-mbyte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 64 page-table entry (pte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 paging global. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C 66 page size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 page-directory entry . . . . . . . . . . . . . . . . . . . . . . . . . . 63 C 64 page-table entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 pde . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 C 64 probe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 protected mode instructions that modify the if or vif flags . . . . . . . . . . 72 virtual interrupt extensions . . . . . . . . . . . . . . . . . . . . . . . 75
index 131 21062e/0june 1997 amd k86? family bios and software tools developers guide preliminary information protected virtual interrupts . . . . . . . . . . . . . . . . . . . . . . 59 , 79 ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 pse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 pte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 public instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 public tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 pvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 79 r r/s# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 rdmsr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 rdtsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 real mode, instructions that modify the if or vif flags . 71 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 msr 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 msr 86h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 aar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 br . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 , 110 cr4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 C 59 , 88 debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 , 113 C 116 default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 dir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 , 110 dr0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 dr1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 dr2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 dr3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 dr4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 dr5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 dr6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 dr7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 dr7Cdr0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 efer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 eflags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 hwcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 C 23 , 82 ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 , 107 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 mcar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 80 , 117 mctr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 80 , 117 model-specific . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 79 , 96 , 117 msrs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 79 , 96 , 117 smm initial values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 97 star . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 tr12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 wapmrr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 watmcr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 whcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 C 120 reserved opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 102 rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 runbist instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 s sample/preload instruction . . . . . . . . . . . . . . . . . . 46 , 112 segment register attributes . . . . . . . . . . . . . . . . . . . . . 20 , 103 signals buschk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 flush# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 init . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 intr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 nmi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 r/s# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 , 102 smi# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 smm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 100 exceptions and interrupts in smm. . . . . . . . . . . . . . 16 , 101 halt restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i/o restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 C 15 , 101 i/o trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 , 101 initial state of registers . . . . . . . . . . . . . . . . . . . . . . . . . 9 , 97 issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 , 96 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 , 100 rsm instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 C 10 , 98 software extensions 4-mbyte pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 , 66 branch tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 debug control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 debugging extensions (de). . . . . . . . . . . . . . . . . . . . . . . . 59 disable branch prediction . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable data cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable instruction cache . . . . . . . . . . . . . . . . . . . . . . . . . 23 disable stopping processor clocks . . . . . . . . . . . . . . . . . . 24 global page extension (gpe) . . . . . . . . . . . . . . . . 59 , 64 C 66 i/o breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 interrupt redirection bitmap (irb) . . . . . . . . . . . . . . . . . 75 machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 machine check enable (mce). . . . . . . . . . . . . . . . . . . . . . 60 page size extension (pse) . . . . . . . . . . . . . . . . . . . . . . 59 C 60 protected virtual interrupts (pvi) . . . . . . . . . . . . . . . 59 , 79 system call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 122 time stamp disable (tsd) . . . . . . . . . . . . . . . . . . 59 , 81 , 118 virtual-8086 mode extension (vme) . . . . . . . . . . . . . 59 , 67 software interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 standard debug functions . . . . . . . . . . . . . . . . . . . . . . . . . . 38 state halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 stop-grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 state of the amd-k5 processor after init. . . . . . . . . . . . . 20 state of the amd-k5 processor after reset . . . . . . . . . . 18 state of the amd-k6 processor after init. . . . . . . . . . . . 104 state of the amd-k6 processor after reset . . . . . . . . . 102 stop-grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 stpclk# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 syscall instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 syscall target address register (star). . . . . . . 118 C 119 sysret instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 system call. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 , 122 system management mode. see smm t tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 , 112 highz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 , 112 idcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 , 112 runbist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sample/preload . . . . . . . . . . . . . . . . . . . . . . . . . 46 , 112 tap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 tap registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 task state segment (tss) . . . . . . . . . . . . . . . . . . . . . . . . . . 77
132 index amd k86? family bios and software tools developers guide 21062e/0june 1997 preliminary information test aar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 float . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 functional redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 hdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 hwcr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 C 23 , 82 tlb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 test access port (tap) bist . . . . . . . . . . . . . . . . . . . . . . . . . 26 test formats 4-kbyte tlb for all models of the amd-k5 processor. . 36 4-mbyte tlb for all models of the amd-k5 processor . 37 dcache data for all models of the amd-k5 processor . 32 dcache tags for the amd-k5 processor model 0 . . . . . . 30 dcache tags for the amd-k5 processor model 1 and greater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 icache instructions for the amd-k5 processor model 0. 35 icache instructions for the amd-k5 processor model 1 and greater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 icache tags for the amd-k5 processor model 0 . . . . . . . 33 icache tags for the amd-k5 processor model 1 and greater. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 test register 12 (tr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 time stamp counter (tsc) . . . . . . . . . . . . . . . 59 , 81 , 89 , 118 time stamp disable . . . . . . . . . . . . . . . . . . . . . . . . 59 , 81 , 118 tlb testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 top of memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 tristate test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 tri-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 tsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 81 , 89 , 118 tsd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 81 u usehdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 v vif. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 vip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 , 71 virtual interrupt flag (vif). . . . . . . . . . . . . . . . . . . . . . 68 , 71 virtual interrupt pending (vip) flag. . . . . . . . . . . . . . . 68 , 71 virtual-8086 mode extensions (vme). . . . . . . . . . . . . . 59 , 67 virtual-8086 mode interrupt extensions (vme) . . . . . . . . 74 virtual-interrupt additions to eflags register . . . . . . . 71 vme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 , 67 w write allocate enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 enable 15-to-16-mbyte. . . . . . . . . . . . . . . . . . . . . . . . . . . 121 enable limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 fixed range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 programmable memory range register (wapmrr) . . . 84 programmable range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 , 119 top-of-memory and control register (watmcr) . . . . . . 84 write cacheability detection enable . . . . . . . . . . . . . . . 120 write handling control register (whcr) . . . . . . . . 119 C 120 wrmsr instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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