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1 of 21 rev: 010804 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . features integrated nv sram, real-time clock (rtc), crystal, power-fail control circuit, and lithium energy source clock registers are accessed identically to the static ram; these registers reside in the 16 top ram locations century byte register (i.e., y2k compliant) totally nonvolatile with over 10 years of operation in the absence of power precision power-on reset programmable watchdog timer and rtc alarm bcd-coded year, month, date, day, hours, minutes, and seconds with automatic leap- year compensation valid up to the year 2100 battery voltage-level indicator flag power-fail write protection allows for 10% v cc power-supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time also available in industrial temperature range: -40c to +85c pin configurations DS1554 256k, nonvolatile, y2k-compliant timekeeping ram www.maxim-ic.com encapsulated dip rs t 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc n.c. i r q / ft we a 13 a 8 a 9 a 11 oe a 10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 n.c. a12 a6 dq2 gnd 15 16 18 17 dq4 dq3 dallas semiconductor DS1554 1 irq / ft 2 3 n.c. n.c. rs t v cc w e o e c e dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c. a 14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 n.c. x1 gnd v bat x2 powercap? module board (uses ds9034pcx powercap) dallas semiconductor DS1554 top view powercap is a registered trademark of dallas semiconductor.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 2 of 21 pin description a0?a14 - address inputs dq0?dq7 - data input/outputs irq /ft - interrupt, frequency test output (open drain) rst - power-on reset output (open drain) ce - chip enable oe - output enable we - write enable v cc - power-supply input gnd - ground n.c. - no connection x1, x2 - crystal connection v bat - battery connection ordering information part temp range pin-package top mark DS1554-70 0c to +70c 32 edip (0.740a) DS1554-070 DS1554-70ind -40c to +85c 32 edip (0.740a) DS1554-070 ind DS1554p-70 0c to +70c 34 powercap DS1554p-070 DS1554p-70ind -40c to +85c 34 powercap DS1554p-070 ind DS1554w-120 0c to +70c 32 edip (0.740a) DS1554w-120 DS1554w-120ind -40c to +85c 32 edip (0.740a) DS1554w-120 ind DS1554wp-120 0c to +70c 34 powercap DS1554wp-120 DS1554wp-120ind -40c to +85c 34 powercap DS1554wp-120 ind
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 3 of 21 description the DS1554 is a full-function, year 2000-compliant (y 2kc), real-time clock/cal endar (rtc) with an rtc alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 nonvolatile static ram. user access to all registers within the DS1554 is accomplishe d with a byte-wide interface as shown in figure 1. the rtc registers contain century, year, month, date , day, hours, minutes, and seconds data in 24-hour binary-coded decimal (bcd) format. corrections for da y of month and leap year are made automatically. the rtc registers are double-buffered into an internal an d external set. the user has direct access to the external set. clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of extern al registers settings to guarantee that accurate rtc information is always maintained. the DS1554 has interrupt ( irq /ft) and reset ( rst ) outputs which can be used to control cpu activity. the irq /ft interrupt output can be used to generate an external interrupt when the rtc register values match user programmed alarm values. the interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery-backed state to serve as a system wakeup. either the irq /ft or rst outputs can also be used as a cpu watchdog timer, cpu activity is monitored and an interrupt or reset output will be activated if the correct activity is not detected within programmed limits. the DS1554 power-on re set can be used to detect a system power down or failure and hold the cpu in a safe reset state until normal power returns and stabilizes; the rst output is used for this function. the DS1554 also contains its own power-fail circuitry, which automatically deselects the device when the v cc supply enters an out of tolerance condition. this feature provides a high de gree of data security during unpredictable system operation brought on by low v cc levels. packages the DS1554 is available in two packages (32-pin dip and 34-pin powercap module). the 32-pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the DS1554p after the completion of the surface mount pr ocess. mounting the powercap after the surface mount process prevents damage to the crystal and batte ry due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shippe d in separate containers. the pa rt number for the powercap is ds9034pcx.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 4 of 21 figure 1. block diagram table 1. operating modes v cc ce oe we dq0?dq7 mode power v ih x x high-z deselect standby v il x v il d in write active v il v il v ih d out read active v cc > v pf v il v ih v ih high-z read active v so < v cc DS1554
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 5 of 21 data-read mode the DS1554 is in the read mode whenever ce (chip enable) is low and we (write enable) is high. the device architecture allows ripple-through access to any valid address location. valid data will be available at the dq pins within t aa after the last address input is stable, providing that ce and oe access times are satisfied. if ce or oe access times are not met, valid data will be available at the latter of chip enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. data-write mode the DS1554 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the addresses must be he ld valid throughout the cycle. ce and we must return inactive for a minimum of t wr prior to the initiation of a subsequent read or write cycle. data in must be valid t ds prior to the end of the write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low, the data bus can become active w ith read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active. data-retention mode the 5v device is fully accessible and data can be written and read only when v cc is greater than v pf . however, when v cc is below the power-fail point v pf (point at which write protection occurs) the internal clock registers and sram are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), devi ce power is switched from the v cc pin to the internal backup lithium battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and da ta can be written and read only when v cc is greater than v pf . when v cc falls below v pf , access to the device is inhibited. if v pf is less than v so , the device power is switched from v cc to the internal backup lithium battery when v cc drops below v pf . if v pf is greater than v so , the device power is switched from v cc to the internal backup lithium battery when v cc drops below v so . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. all control, data, and address sign als must be powered down when v cc is powered down.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 6 of 21 battery longevity the DS1554 has a lithium power source that is designed to provide energy for the clock activity, and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the DS1554 continuously for the life of the equipment in which it is installed. for specification purposes, th e life expectancy is 10 years at 25 c with the internal clock oscillator running in the absence of v cc . each DS1554 is shipped from dallas semiconduct or with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup ope ration. actual life expectancy of the DS1554 will be much longer than 10 years since no internal battery energy is consumed when v cc is present. internal battery monitor the DS1554 constantly monitors the ba ttery voltage of the internal ba tter. the battery low flag (blf) bit of the flags register (b4 of 7fff0h) is not writ eable and should always be a 0 when read. if a 1 is ever present, an exhausted lithium energy source is indicated and both the contents of the rtc and ram are questionable. power-on reset a temperature compensated comparator circuit monitors the level of v cc . when v cc falls to the power- fail trip point, the rst signal (open drain) is pulled low. when v cc returns to nominal levels, the rst signal continues to be pulled low for a period of 40 ms to 200 ms. the power-on reset function is independent of the rtc oscillator and thus is operational whether or not the oscillator is enabled. clock operations table 2 and the following paragraphs describe th e operation of rtc, alarm, and watchdog functions.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 7 of 21 table 2. register map data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 7fffh 10 year year year 00-99 7ffeh x x x 10 month month month 01-12 7ffdh x x 10 date date date 01-31 7ffch x ft x x x day day 01-07 7ffbh x x 10 hour hour hour 00-23 7ffah x 10 minutes minutes minutes 00-59 7ff9h osc 10 seconds seconds seconds 00-59 7ff8h w r 10 century century control 00-39 7ff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog ? 7ff6h ae y abe y y y y y interrupts ? 7ff5h am4 y 10 date date alarm date 01-31 7ff4h am3 y 10 hours hours alarm hours 00-23 7ff3h am2 10 minutes minutes alarm minutes 00-59 7ff2h am1 10 seconds seconds alarm seconds 00-59 7ff1h y y y y y y y y unused ? 7ff0h wf af 0 blf 0 0 0 0 flags ? x = unused, read/writeable under write and read bit control ae = alarm flag enable y = unused, read/writeable without write and read bit control abe = alarm in battery-backup mode enable ft = frequency test bit am1-am4 = alarm mask bits osc = oscillator start/stop bit wf = watchdog flag w = write bit af = alarm flag r = read bit 0 = 0 (read only) wds = watchdog steering bit blf = battery low flag bmb0 to bmb4 = watchdog multiplier bits rb0 to rb1 = watchdog resolution bits clock oscillator control the clock oscillator may be stopped at any time. to increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb of the seconds register (b7 of 7ff9h). setting it to a 1 stops the oscillator, setting to a 0 starts the oscillator. the DS1554 is shipped from dallas semic onductor with the clock oscillator turned off, osc bit set to a 1. reading the clock when reading the rtc data, it is recommended to ha lt updates to the external set of double-buffered rtc registers. this puts the external registers into a sta tic state allowing data to be read without register values changing during the read process. normal update s to the internal registers continue while in this state. external updates are halted when a 1 is written into the read bit, b6 of the control register (7ff8h). as long as a 1 remains in the control register read bit, updating is halted. after a halt is issued, the registers reflect the rtc count (d ay, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of regi sters will resume within 1 second after the read bit is set to a 0 for a minimum of 500 s. the read bit must be a zero for a minimum of 500 s to ensure the external registers will be updated.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 8 of 21 setting the clock the 8th bit, b7 of the control register is the write bit. setting the write bit to a 1, like the read bit, halts updates to the DS1554 (7ff8h-7fffh) registers. after se tting the write bit to a 1, rtc registers can be loaded with the desired rtc count (day, date, and time) in 24-hour bcd format. setting the write bit to a 0 then transfers the values written to the internal rtc registers and allows normal operation to resume. clock accuracy (dip module) the ds1553 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. the rtc is calibrated at the factory by dalla s semiconductor using nonvola tile tuning elements and does not require additional calibration. for this r eason, methods of field clock calib ration are not available and not necessary. the electrical environmen t also affects clock accuracy. caution should be taken to place the rtc in the lowest-level emi section of the pc board layout. for additional information, refer to application note 58 . clock accuracy (powercap module) the DS1554 and ds9034pcx are each i ndividually tested for accuracy. once mounted together, the module is will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25c. the electrical environment aff ects clock accuracy. caution should be taken to place the rtc in the lowest- level emi section of the pc board lay out. for additional information, refer to application note 58 . frequency test mode the DS1554 frequency test mode uses the open drain irq /ft output. with the oscillator running, the irq /ft output will toggle at 512 hz when the ft bit is a 1, the alarm flag enable bit (ae) is a 0, and the watchdog steering bit (wds) is a 1 or the watchdog register is reset (register 7ff7h = 00h). the irq /ft output and the frequency test mode can be used as a measure of the actual frequency of the 32.768 khz rtc oscillator. the irq /ft pin is an open drain output wh ich requires a pullup resistor for proper operation. the ft bit is cleared to a 0 on power-up. using the clock alarm the alarm settings and control for the DS1554 reside within registers 7ff2h-7ff5h. register 7ff6h contains two alarm enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go off while the DS1554 is in the battery-backed state of operation to serve as a system wakeup. alarm mask bits am1 to am4 control the alarm mode. table 3 shows the possible settings. configura tions not listed in the table defau lt to the once per second mode to notify the user of an incorrect alarm setting.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 9 of 21 table 3. alarm mask bits am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match when the rtc register values match alarm register settings, the alarm flag bit (af) is set to a 1. if alarm flag enable (ae) is also set to a 1, the alarm condition activates the irq /ft pin. the irq /ft signal is cleared by a read or write to the flags register (address 7ff0h) as shown in figure 2 and 3. when ce is active, the irq /ft signal may be cleared by having the address stable for as short as 15 ns and either oe or we active, but is not guaranteed to be cleared unless t rc is fulfilled. the alarm flag is also cleared by a read or write to the flags register but the flag will not change states until the end of the read/write cycle and the irq /ft signal has been cleared. figure 2. clearing irq waveforms figure 3. clearing irq waveforms the irq /ft pin can also be activated in the battery backed mode. the irq /ft will go low if an alarm occurs and both abe and ae are set. the abe and ae bits are cleared during the power-up transition, however an alarm generated during pow er-up will set af. therefore, the af bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. figure 4 illustrates alarm timing during the battery-backup mode and power-up states. 0v ce, ce=0
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 10 of 21 figure 4. backup mode alarm waveforms using the watchdog timer the watchdog timer can be used to detect an out-of-control processor. the user programs the watchdog timer by setting the desired amount of time-out into the 8-bit watchdog register (address 7ff7h). the five watchdog register bits bmb4 to bmb0 store a binary multiplier and the two lower order bits rb1-rb0 select the resolution, where 00=1/16 se cond, 01=1/4 second, 10=1 second, and 11=4 seconds. the watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (for example: writing 00001110 in the watchdog register = 3 x 1 second or 3 seconds.) if the processor does not reset the timer within the specified period, the watchdog flag (wf) is set and a processor interrupt is generated and stays active until either the watchdog flag (wf) is read or the watchdog register (7ff7) is read or written. the most significant bit of the watchdog register is the watchdog steering bit (wds). when set to a 0, the watchdog will activate the irq /ft output when the watchdog times out. when wds is set to a 1, the watchdog will output a negative pulse on the rst output for a duration of 40 ms to 200 ms. the watchdog register (7ff7) and th e ft bit will reset to a 0 at the end of a watchdog time-out when the wds bit is set to a 1. the watchdog timer resets when the processor performs a read or write of the watchdog register. the timeout period then starts over. writing a value of 00h to the watchdog register disables the watchdog timer. the watchdog function is automatically disa bled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft output and the frequency test function is activated, the watchdog function prevails a nd the frequency test function is denied. power-on default states upon application of power to the device, th e following register bits are set to 0: wds = 0, bmb0 to bmb4 = 0, rb0 to rb1 = 0, ae = 0, and abe = 0.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 11 of 21 absolute maximum ratings voltage range on any pin relative to ground????????..???????????????-0.3v to +6.0v storage temperature range??????????????????????????????...-40c to +85c soldering temperature???????????????????.see ipc/jedec standard j-std-020a (note 8) for surface-mount devices this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. operating range range temp range v cc commercial 0c to +70c 3.3v 10% or 5v 10% industrial -40c to +85c 3.3v 10% or 5v 10% recommended dc operating conditions (over the operating range) parameter symbol conditions min typ max units v ih v cc = 5v 10% 2.2 v cc + 0.3v v logic 1 voltage all inputs (note 1) v ih v cc = 3.3v 10% 2.0 v cc + 0.3v v v il v cc = 5v 10% -0.3 +0.8 logic 0 voltage all inputs (note 1) v il v cc = 3.3v 10% -0.3 +0.6 dc electrical characteristics (v cc = 5.0v 10%, over the operating range.) parameter symbol conditions min typ max units active supply current i cc (notes 2, 3) 40 75 ma ttl standby current ( ce = v ih ) i cc1 (notes 2, 3) 3 6 ma cmos standby current ( ce v cc - 0.2v) i cc2 (notes 2, 3) 2 6 ma input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh (note 1) 2.4 v v ol1 i out = 2.1 ma, dq0?7 outputs (note 1) 0.4 v output logic 0 voltage v ol2 i out = 7.0 ma, irq /ft, and rst outputs (notes 1, 5) 0.4 v write protection voltage v pf (note 1) 4.20 4.50 v battery switchover voltage v so (notes 1,4) v bat v
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 12 of 21 dc electrical characteristics ( v cc = 3.3v 10% , over the operating range.) parameter symbol conditions min typ max units active supply current i cc (notes 2, 3) 10 30 ma ttl standby current ( ce = v ih ) i cc1 (notes 2, 3) 0.7 6 ma cmos standby current ( ce v cc - 0.2v) i cc2 (notes 2, 3) 0.7 4 ma input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0 ma) v oh (note 1) 2.4 v v ol1 i out = 2.1 ma, dq0?7 outputs (note 1) 0.4 v output logic 0 voltage v ol2 i out = 7.0 ma, irq /ft and rst outputs (notes 1, 5) 0.4 v write protection voltage v pf (note 1) 2.75 2.97 v battery switchover voltage v so (notes 1,4) v bat or v pf v figure 5. read cycle timing diagram
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 13 of 21 ac characteristics?read cycle (over the operating range) v cc = 5.0v 10% v cc = 3.3v 10% parameter symbol min max min max units read cycle time t rc 70 120 ns address access time t aa 70 120 ns ce to dq low-z t cel 5 5 ns ce access time t cea 70 120 ns ce data off time t cez 25 40 ns oe to dq low-z t oel 5 5 ns oe access time t oea 35 100 ns oe data off time t oez 25 35 ns output hold from address t oh 5 5 ns ac characteristics?write cycle (over the operating range) v cc = 5.0v 10% v cc = 3.3v 10% parameter symbol min max min max units write cycle time t wc 70 120 ns address access time t as 0 0 ns we pulse width t wew 50 100 ns ce pulse width t cew 60 110 ns data setup time t ds 30 80 ns data hold time (note 9) t dh1 5 5 ns data hold time (note 10) t dh2 5 5 ns address hold time (note 9) t ah1 5 0 ns address hold time (note 10) t ah2 5 5 ns we data off time t wez 25 40 ns write recovery time t wr 5 10 ns
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 14 of 21 figure 6. write cycle timing, write-enable controlled figure 7. write cycle timing, chip-enable controlled
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 15 of 21 power-up/down characteristics?5v (v cc = 5.0v 10%, over the operating range.) parameter symbol conditions min typ max units ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 40 200 ms expected data-retention time (oscillator on) t dr (notes 6, 7) 10 years figure 8. power-up/down waveform timing (5v device )
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 16 of 21 power-up/down characteristics?3.3v (v cc = 3.3v 10%, over the operating range.) parameter symbol conditions min typ max units ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 40 200 ms expected data-retention time (oscillator on) t dr (notes 6, 7) 10 years figure 9. power-up/down waveform timing (3.3v device) capacitance (t a = +25c) parameter symbol conditions min typ max units capacitance on all input pins c in (note 1) 14 pf capacitance on irq /ft, rst , and dq pins c io (note 1) 10 pf
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 17 of 21 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1) voltage referenced to ground. 2) typical values are at +25 c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lowe r of either the battery voltage or v pf . 5) the irq /ft and rst outputs are open drain. 6) data-retention time is at +25 c. 7) each DS1554 has a built-in switch th at disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined for dip modules and powerc ap modules as a cumulative time in the absence of v cc starting from the time power is first applied by the user. 8) rtc modules (dip) can be successfully processe d through conventional wave-soldering techniques as long as temperature exposure to the lithium en ergy source contained within does not exceed +85 c. post-solder cleaning with water-washing techniques is accept able, provided that ultrasonic vibration is not used. in addition, for the powercap: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or a pply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. 9) t ah1 , t dh1 are measured from we going high. 10) t ah2 , t dh2 are measured from ce going high.
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 18 of 21 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg 32-pin dim min max a in. mm 1.670 38.42 1.690 38.93 b in. mm 0.715 18.16 0.740 18.80 c in. mm 0.335 8.51 0.365 9.27 d in. mm 0.075 1.91 0.105 0.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.45 k in. mm 0.015 0.38 0.025 0.64
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 19 of 21 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c ? ? 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: dallas semiconductor recommends that powercap module bases experience one pass through solder reflo w oriented with the label side up (?live-bug?). hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than 3 seconds. to solder, a pply flux to the pad, heat the lead frame pad, and appl y solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to remove solder. d s 1 55 4p
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram 20 of 21 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) DS1554p with ds9034pcx attached
DS1554 256k, nonvolatile, y2k-compliant timekeeping ram maxim/dallas semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specification s without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2004 maxim integrated products printed usa 21 of 21 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .) recommended powercap module land pattern

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