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1/12 author: c.ruggieri april 2002 AN1525 application note i 2 c communication between st52x520 and eeprom 1 introduction this an shows an example of how to interface style i 2 c eeprom with an st52x520 microcontroller using an i 2 c protocol. an st24c04 (4kbit) memory is used for this example, although similar thoughts are also true for any other type of eeprom that uses an i 2 cbus. the software that is proposed uses a read/write routine that performs random access to a certain number of user defined eeprom memory locations with the st52x520 microcontroller configured in master mode. 2 communication protocol the i 2 c standard protocol defines every device that sends data in the bus as a transmitter and every device that reads data as receiver. the device that controls data transfer is defined as master, while all the others are defined as slave. the standard i 2 c protocol uses a bidirectional data line (sda) and a clock line (scl) generated by the master device, which in this specific case has to necessarily be the microcontroller, since eeprom only works as slave. start conditon: start is recognized when the sda line switches from high to low, while the scl line is stable in high state. start has to precede every data transfer command. stop condition: stop is recognized when the sda line switches from high to low during a stable phase of the scl line in high state. the stop condition ends communication. acknowledge bit (ack): the ack signal is used to indicate that the data transfer was successful. the bus transmitter (both master and slave) will release the sda line after having sent an 8 bit byte. during the 9th clock cycles, the receiver places the sda line in low in order to indicate that it has received the 8 bits of data. eeprom addressing: in order to begin the communication between the bus master and the slave memory, the master has to begin with a start condition. afterwards, the master serially sends 8 bits to the sda line (msb the first), which corresponds to the device select code (7 bits) and to one read or write bit. the device select code is composed of the first four bits equal to 1010 (unique device iden- tification code), which correspond to the specifications of the i 2 c protocol. the three successive bits iden- tify the chip enable inputs that allow the same bus to interface with other memories. figure 1. i 2 c bus protocol
AN1525 - application note 2/12 3 hardware description the electrical schematic of the circuit, which the proposed program refers to is shown in figure 2. the pa0/scl pin of the microcontroller is connected to the scl line and the pa1/sda pin is connected with the sda line for bus synchronization. the pushbutton is connected with pin pa7 (external interrupt, int) in order to select the reading and writing phase. in this scheme, the e1 and e2 enable pins are set as vss. in order to address up to a maximum of 4 mem- ories, st24c04 is required to dynamically drive the two e1 and e2 pins from other i/o pins of the micro- controller. the other devices will be addressed by setting the corresponding bits of the device select code, which will be a0h for writing and a1h for reading. the first time the button is pressed, the microcon- troller will start sending data in a sequence, beginning from the address that is indicated by the program user. once the button is pushed again, the microcontroller will request the memory to send the data that was previously written. figure 2. st52x520 eeprom i 2 c schematics 3.1 page write mode the program performs 8 byte memory writing, equal to the dimensions of the sequential writing page for st24c04. in page write mode, after having sent the start condition, the i 2 c peripheral of st52x520 sends the device select code with the rw bit reset to 0 (see figure 3) in the bus. the memory sends an ack and waits for the initial address writing location to be sent. upon receipt of the address, the mem- ory sends another ack. after the memory sends the ack, st52x520 will send the 8 bytes of data (maximum limit) to be written on the memory. the memory will send an ack after every byte and will automatically increment the last three bits of the internal address counter. after the last byte has been sent and after having waited for the last ack, the microcontroller will send the stop condition. figure 3. page write mode
3/12 AN1525 - application note 3.2 random address read mode in order to read a series of data from a memory address, empty writing (dummy write) must be performed to set the memory address location where to start reading. as shown in figure 4, after the start condi- tion, the microcontroller sends the device select code with the rw bit reset to 0 (as in the writing oper- ation). after receiving the ack, the microcontroller sends the address of the memory location where to begin reading. then, after receiving the ack from the memory, the microcontroller sends another start condition followed by a new device select code, but this time with the rw bit set to 1. after receiving an ack, the memory begins transmitting data that will be received sequentially by the st52x520, which is each followed by an ack. the microcontroller wont have to send an ack after receiving the last byte. receiving will end with a stop condition. figure 4. random address read mode 4 software description the following section describes the software to communicate with the st52x520 via an i 2 c type eeprom st24c04. the software is developed with visual five and allows sequential writing of a maximum of 8 bytes (for st24c04) to a certain memory address and the reading, afterwards, of the same amount of bytes. the software that is proposed can be found in file i2cgp.fs4 (see file AN1525.fs4 in the applica- tion note page at the following web site: http://www.st.com/five ). figure 5. i 2 c device configuration window
AN1525 - application note 4/12 in the example that has been proposed, bit b1 (that represents bit a8 of the memory address) wasnt used in the device select code. the user can select only one range of addresses, which range from 0 to 255. in order to address memory locations that exceed the quantity indicated, the program has to be modified. the reading and writing phases are alternated based on the pressure exerted on the pushbutton (see fig- ure 2). during the reading phase, data read is seen in port b of the st52x520 microcontroller. seeing that this is a demonstration program, the user will be responsible for adequately managing the program in the data reception phase. in the example, the micro clock frequency is set to 5 mhz, all port b pins are con- figured as out, pa7 as int and pin pa0 and pa1, respectively as scl and sda (pins of the i 2 c periph- eral of the st52x520 microcontroller). figure 5 shows the device configuration window for the configuration of the i 2 c peripheral of the micro- controller, where both the acknowledgment generation and the interrupt generation are set, in order to allow the program to synchronize various events. moreover, the clock divider value (prescaler) is set to 14 in order to obtain a transmission frequency of approximately 98 khz. the st52x520 micro can also be configured for communications in fast mode (400khz). 4.1 main program window the window of the main program flow is shown in figure 6. in the user_var block, which is shown be- side it, the user will be able to define the apposite variable memory address where to begin data writing (w_add), reading (r_add), as well as the number of data to write and read (byte_n) and the initial val- ue to be written in the first location (base). base will be incremented automatically by the program before writing in the next location. figure 6. main window the st52x520 ports and the indexes k and p are initialized in the init block. these indexes are used to determine the inhibition of the last ack during the reading phase and generate the stop condition cor- rectly, in accordance with the specifications of the i 2 c interface of the st52x520 microcontroller. in case the number of bytes to write and read (byte_n) is equal to one, the read/write operations in eeprom will be respectively that of byte write operation and random address read. the flag variable is used to establish exactly which phases the micro st52x520 has to read or write each time. all of these phases are performed in the interrupt routine of the i 2 c described further ahead. the meaning of the single bits of the flag variable is shown in figure 7.
5/12 AN1525 - application note figure 7. program flag definition the use of a register with various flags is necessary in this program, seeing that within a sole routine (i 2 c interrupt) the program manages all phases of sequential writing, random reading and all interrupt events generated during the various steps of every phase (see figure 8). the program flow begins by enabling the interrupt of the i 2 c peripheral and afterwards enables the pe- ripheral iteself (irqmask_0, i2c_en controls). the program flow is interrupted immediately after the wait0 block. once the pushbutton is pressed, the status of bit b0 of the flag register is inverted. this occurs via an xor operation on the b0 bit of the flag register. initially, as flag = 1, b0 will be reset to 0. this last operation is performed by the external interrupt routine, which sets bit 7 of the flag register to 1. in this manner, the external interrupt routine will be executed again only at the end of reading or writing to the memory. after exiting the routine via the ret10 control, the start condition will be activated through the i 2 c pe- ripheral of the st52x520 micocontroller and bit 6 will be set to 1 in the flag register. this flag bit is nec- essary since the start condition begins at the main program level, while the communication management occurs after each event generated by the i 2 c interrupt routine. in the norm_op block, a code can be inserted to perform operations while the microcontroller communi- cates with the memory. finally, the pb_0 block resets the value of port b to 0. figure 8 represents the sequence to be followed to receive and transmit data to an i 2 c peripheral, configuring the st52x520 mi- crocontroller as master (receiver and transmitter) with the addressing mode of 7 bits (refer to the st52x520 datasheet for the complete diagram of the sequences, relative to the i 2 c peripheral of the mi- crocontroller). figure 8. 7 bit master transfer sequencing
AN1525 - application note 6/12 figure 9. external interrupt window 4.2 i 2 c interrupt window the routine of the interrupt window of the i 2 c peripheral (represented in figure 10) manages all the phases that are necessary for the correct reading and writing sequence. as can be seen in figure 8, each time a start condition begins or data begins, the i 2 c peripheral of the microcontroller sends an interrupt re- quest that will have to be managed by the user (evx events). 4.2.1 common steps in reading and writing. when the i 2 c peripheral of the microcontroller has sent the start condition, the i 2 c routine will be called. block rd_sr1_sr2 is the first block that will be executed (this will occur at every call of the routine). the status register of the i 2 c peripheral is read in this block (sr1-other than the status register sr2, which can be used to manage eventual transmission or reception erros, errors which are not managed in this example) via the instruction sr1 = _inpreg_07 (and sr2=_inpreg_08). figure 10. i 2 c interrupt window
7/12 AN1525 - application note this operation is indispensable, seeing that the i 2 c peripheral will not continue operations requested if sr1 is not read. in fact, only by reading this register the microcontroller resets the event flag bit (evf) to 0. the first conditional block (sb) verifies if the start condition was just generated. in fact, bit 0 of register sr1 is set to 1 only after a start condition. when an interrupt is generated following a start condition, the program verifies if start is the initial one, or the one that follows the address location where to begin reading (random address read mode, see figure 4). in this last case, bit 3 of the flag register will be set to 1, otherwise it will be reset to 0. when the first start occurs, the value transferred to the i2cdata (used by the program to transfer data to/from memory via the send and receive controls of visual five) will be 160 (corresponding to the value of the select code with bit 7 - rw - reset to 0 for writing operations) if bit 3 of the register flag is 0. the address transferred to the variable slaveadd will be that of writing, w_add. if, on the other hand, bit 3 of flag register is 1 (value that is modified after the second start has been sent), the value trans- ferred to the i2cdata register will be 161 (rw bit = 1). control is performed through the conditional block add_or_r. figure 11. write and read block windows in case the start condition occurs after the initial address has been sent (in the random address read mode), the program sets bit 2 of the flag register to 1. this indicates that the device select code for reading has already been sent to the memory and from this point on, sequential reading may be per- formed. lastly, the cb_w control transfers the i2cdata variable to the i 2 c peripheral of the microcontroller and the routine ends via the retl1 control. at the end of the process in which the contents of the i2cdata have been sent to the memory, the micro- controller will generate a new interrupt. however, bit 0 of register sr1 will be reset to 0. the program will examine the condition of the add_wr block, which verifies bit 2 of the flag register. if this bit is still reset to 0, the memory address to begin writing/reading data must be sent to the ee- prom. the i2c_add block transfers the value of the slaveadd, which contains this address (address previously transferred by the write block, figure 11) in the i2cdata variable. in this phase, other than reading the sr1 register, which is guaranteed by the rd_sr1_sr2 block performed at every entry of the interrupt of the i 2 c routine, writing on the control register (cr) of the i2c peripheral (see figure 8, ev6) is indespensable. this operation is performed by the wr_cr_fb2 block via the cr=cnfreg_16 and_cnfreg_16=cr instructions, which simply read, then rewrite the cr register without modifications. in this block, bit 2 of the flag register is set to 1 in order to inform the program that the memory address where to read or write data was sent to eeprom. after the address has been sent to the i 2 c peripheral of the microcontroller (control w_slad), the routine terminates via the retl1 control. at the end of the transfer process, the micro will generate a new interrupt and a new i 2 c routine will be called. this time, due to a 1 value of the bit 2 of the flag register, control will pass to the conditional block btf10, which determines if the operation to be performed is that of reading or writing (operation which is established by the value of bit 0 of the flag register, modified with every exterted pressure on the pushbutton).
AN1525 - application note 8/12 4.2.2 writing block. if writing is to be performed, the program will execute the instructions of the block shown in figure 12 (bit 0 of the flag register = 0). the conditional buffer block verifies when the number of bytes sent from the i 2 c peripheral of the st52x520 microcontroller to the memory has achieved the number of bytes indicated bytheuserinthebyte_nvariable. figure 12. write flow blocks in case the result is positive (i>bufl[=byte_n-1]) the stop condition is sent, ending communication (see figure 3) and the re_init (2) block is executed, which sets all the bits in the flag register to the initial conditions once again (see figure 13). if the number of bytes sent still hasnt reached the limit, the value of the variable index i in the i2cdata_i block is incremented by one each time. in the same block the initial data defined by the user in the base variable is assigned to the i2cdata_i variable. the base variable is incremented by the instructions i2cdata = base+i and i++ contained in the i2cdata_i block. in this m anner, the function of the writing routine is that of sending the growing numeric values that begin with the value specified by the base vari- able, written in the memory locations that begin with the address specified by the w_add variable. the snd_pb block simply sends the byte transferred to the i 2 c peripheral of the microcontroller, from the w_slad control to port b of the microcontroller. after each byte is sent (since there is no variation of the value of the flag register), the program returns the control to the main program window through the retl1 control, and each time an interrupt is generated the i 2 c routine will return in the writing block (see figure 12).
9/12 AN1525 - application note figure 13. initialization blocks 4.2.3 reading block. if, on the other hand, the operation set by the pushbutton is that of reading (flag, bit b0=1) the program flow is different: before reading a memory location, as represented in figure 4, a dummy write must be performed. meaning that, writing mode must be set with the rw bit of the device select code reset to 0, the address where to begin reading must be sent, a start condition must be sent, the device select code (this time with the rw bit set to 1) must be resent and reading may begin. after the start condition has been sent in the main program window, the microcontroller generates an interrupt that will service the i 2 c routine. after each start, bit 0 of the sr1 register is set to 1 and the conditional expression specified in the sb block will become true. the operations performed by the pro- gram from this point on are those described in paragraph 4.2.1: common steps in reading and writing where a description is provided on how the program sends to the memory the initial address where to be- gin reading. once the btf10 block condition is performed, seeing that bit0 of register flag is set to 1, the program will perform the reading block represented by figure 14. figure 14. read flow blocks
AN1525 - application note 10/12 the first conditional block (r_ _or_w) verifies if bit 3 of the flag register has already been set to 1. in case it is negative, the routine sets this bit to 1 and sends the start condition, exiting immediately after the i 2 c routine via the retl1 control. when the start condition has been generated by the peripheral, the microcontroller will generate an in- terrupt, which will allow the program to perform the add_or_r conditional block, seeing that at every start bit, b0 of the sr1 register is set to 1. this time, seeing that bit 3 of the flag register is set to 1, the program will perform the read block, which via the cb_w control will send the device select code to the memory with the rw bit set to 1 (see figure 10). at the end of the transmission of the i 2 c peripheral, the microcontroller will generate an interrupt. at this point, two operations will have to be performed: reading the sr1 register (operation performed every- time the i 2 c is called by the rd_sr1_sr2 block) and writing on the cr register (for example pe=1), as per the specifications of the i2c peripheral that are found on the st52x520 microcontroller datasheet. its important to notice that as soon as the set_fb1_cr block writes on the cr register, the i 2 c peripheral immediately begins to generate the clock signals on the scl line to receive data, generating a second interrupt. only at this time may the receiving register be read through the r_dr control. if reading occurs immediately after writing on the cr register (before the peripheral completes reading data), the micro would return the value previously memorized in the data register (dr) of the i 2 c peripheral, which in this example, is the value of the device select code with the rw bit set to 1 (a1h). this is the reason why bit 1 of the register flag was used: when this bit is reset to 0, it means that the routine is serving an interrupt generated, following the completion of the device select code being sent with the rw bit set to 1. the int_cb condition becomes true and the program follows the set_fb1_cr block, exiting the i 2 c routine via the retl1 control, right after having set bit 1 of the flag register to 1. as soon as the peripheral has finished receiving the first data and the data is ready in the reading register dr of the i 2 c peripheral of the microcontroller, a second interrupt is generated. the program within the i2c window will restart from the conditional block no_ack, since at this point bit 1 of the flag register is set to 1. two conditional blocks are present in the program flow of data reception (as shown in figure 14), which verify the transmission both of the next to last and of the last data. this is necessary seeing that the mi- crocontroller wont have to generate the ack after receiving the last data, in order to allow the memory to close communication. this control is performed by the conditional block no_ack which, when index i (this index specifies the number of bytes that have already been sent) achieves the value of variable k (=bufl- 1), it inhibits the generation of the acknowledgement via the instructions cr =_cnfreg_16 and _cnfreg_16 = cr & 251 of the no_ack_g block, resetting bit 2 (=ack) of the control register (cr) of the i 2 c peripheral of the st52x520 microcontroller to 0. instead, the second conditional buffer block (2) verifies reading of the last byte by performing a confron- tation of the index with variable p, and in case it is positive it generates a stop condition before reading the last data byte that is sent, via the r_dr control. the use of the two variables k and p is necessary in this program in order to anticipate if the user wants to write or read only one data, which in this case, ack inhibition and the stop condition must be sent contemporaneously. if the value of byte_n is equal to 1, both the variable p and k will have the value 0 (see figure 6) and both conditions of the two conditional blocks no_ack and buffer (2) will be true. finally, the snd_pb1_i block allows data read by the memory to be sent to port b of the st52x520 micro- controller and increments the value of the index variable i. after receiving the last byte and before exiting the interrupt routine via the retl1 condtion, the program returns to the initial conditions of the bit in the flag register in order to retransmit or be able to receive once again via the re-init (1) block (as represented in figure 13).
11/12 AN1525 - application note 5test the graphics represented in figure 15 are those obtained by the logical states analyzer and they regard the writing and reading phase, obtained by slightly modifying the program in order to introduce the refer- ence signals indicated (pc0->pc4), to view the synchronization of the data of port b with the various phas- es. figure 15. write and read blocks in this test, the initial memory location address where reading and writing will begin is 16. the number of bytes written in the memory is 8 and the initial value written is 5. this value will be incremented every time writing in the memory occurs. this data is specified in the user_var block (see figure 6). the pc0 signal changes state everytime the start condition is sent. on the other hand, the pc1 signal changes state every time the cb_w control is executed, which sends the device select code to the mem- ory. the pc2 signal changes its state of performance of the w_slad control, which sends to the memory (eeprom) the address of the location where reading or writing will be performed. the pc3 signal chang- es state before sending or receiving every byte of data from the memory. lastly, the pc4 signal changes state everytime the stop condition is sent. references [1] st52x520 - datasheet, stmicroelectronics, 2001 [2] st24c0z1 - datasheet, stmicroelectronics, 1999 [3] visual five 5.0 - user manual, stmicroelectronics, 2002
AN1525 - application note 12/12 full product information at http://www.st.com/five information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - china - canada - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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