www.powerint.com design idea DI-25 dpa-switch 30 w dc-dc converter with synchronous rectification december 2004 DI-25 application dc-dc converter dpa425r 5 v power output 30 w input voltage output voltage topology device 36-75 vdc forward figure 1. dpa-switch 30 w, 5 v, 6 a dc-dc converter. design highlights extremely low component count high efficiency ?90% using synchronous rectification accurate uv/ov allows self-driven synchronous rectification no current sense resistor or current transformer required output overload, open loop and thermal protection 300 khz switching frequency ?optimizes efficiency when simple self-driven synchronous rectification is used operation dpa-switch greatly simplifies the deisign compared to a discrete implementation. resistor r1 programs the input under/over voltages to 33 v and 86 v, respectively, and linearly reduces the maximum duty cycle with input voltage to prevent core saturation during load transients. tight tolerances of the uv/ov thresholds determine the secondary mosfets gate voltage range, allowing low cost, self-driven synchronous rectification. resistor r3 programs the internal current limit of the dpa425r to 45% of nominal. the larger dpa-switch selection reduces conduction losses, raising efficiency without design or overload penalty. drain voltage clamping and core reset is provided by vr1 and the gate capacitance of q1. the bias supply for u1 is generated from an auxiliary winding on l2, providing higher efficiency than a winding on t1. capacitor c17 and r15 drive the gate of q2, c17 providing dc isolation to prevent q1 gate overstress during power down. diode d4 resets the voltage on c17 before the next switching cycle. resistor r17 filters voltage spikes at the gate of q1 and d2 prevents the body diode of q1 from conducting. mosfets q1 and q2 are connected as self-driven synchronous rectifiers. key design points for nominal undervoltage set point v uv : r1 = (v uv -2.35 v)/50 a. v ov = (r1 135 a) + 2.5 v. select time constant of r16 and c17 to be much longer than the period of one switching cycle. zener vr1 safely limits the drain voltage below bv dss and guarantees transformer reset. opto u2 should have a ctr range of 100% to 200% for optimum loop stability. u1 dpa425r d1 bav 19ws d2 c5 220 nf vr1 smbj 150 c6 68 f 10 v c7 1 nf 1.5 kv r14 10 ? t1 r3 18.2 k ? 1% r1 619 k ? 1% r4 1.0 ? c10 100 f 10 v c11 100 f 10 v c12 1 f 10 v 3 6-75 vdc l1 1 h 2.5 a l2 c1, c2 & c3 1 f 100 v dl sxf c control control u2 pc357n1t pi 3472 040903 dpa-switch 5 v, 6 a rtn q2 si4888 dy r15 10 ? r16 10 k ? d4 bav19ws r17 10 ? q1 si4888 dy c4 4.7 f 20 v u2 d3 bav19ws u3 lm431aim3 r9 220 ? r11 10.0 k ? 1% r10 10.0 k ? 1% r12 5.1 ? r7 10 k ? c14 1 f c13 10 f 10 v c16 100 nf r6 150 ? v in + v in c17 3300 pf
www.powerint.com d 12/04 DI-25 power integrations 5245 hellyer avenue san jose, california 95138 main phone number applications hotline applications fax for a complete listing of worldwide sales offices, +1 408-414-9200 +1 408-414-9660 +1 408-414-9760 please visit www.powerint.com the pi logo, topswitch , tinyswitch , linkswitch , dpa-switch and ecosmart are registered trademarks of power integrations. pi expert and pi facts are trademarks of power integrations. ? copyright 2004, power integrations power integrations may make changes to its products at any time. power integrations has no liability arising from your use of a ny information, device or circuit described herein nor does it convey any license under its patent rights or the rights of others. power integrations makes no warranties h erein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular pur pose, and non-infringement of third party rights. the products and applications illustrated herein (including circuits external to th e products and transformer construction) may be covered by one or more u.s. and foreign patents or potentially by pending u.s. and foreign patent applicat ions assigned to power integrations. a complete list of power integrations' patents may be found at www.powerint.com . for the latest updates, visit www.powerint.com at zero load, maximum input voltage, the bias voltage across c4 should be 8 v (12 v to 15 v under nominal conditions). good layout practices should be followed: - locate c5, c6 and r4 close to u1 with grounds returned to the source pin. - primary return should be connected to the dpa-switch tab, not the source pin. - minimize the primary and secondary loop areas to reduce parasitic leakage inductance. consult an-31 for additional design tips and information. choose c17 to provide adequate gate charge to q2 at low line (typically 5 v) and to limit q2 gate to a safe voltage at high line (typically less than 20 v). core bobbin winding detail winding order (pin numbers) inductance primary resonant frequency transformer parameters efd20 ungapped ferroxcube efd20-3f3 efd20 10 pin (b&b b-052 or equivalent) primary: 8t + 8t, 25 awg secondary: 4t, 0.002" cu foil primary (5-3), tape, secondary (6,7-9,10), tape, primary (3-1), tape primary: 307 h 25%, leakage: 1 h (max.) 3 mhz (minimum) core winding details bobbin winding order (pin numbers) inductance output inductor parameters rm6ilp ferroxcube 3f3 material gap for a lg of 278 nh/t 2 main: 6t, 4x26 awg bias: 15t, 32 awg rm6ilp 8 pin (epcos b-65821-a6008-t1 or equivalent) bias (1-2), tape, main winding (7,8-5,6), tape 8 h 10% table 2. output inductor construction information. table 1. transformer construction information. 010152025 530 output power (w) efficiency (%) 70 60 50 80 90 100 pi-3489-040303 v in = 36 vdc v in = 48 vdc v in = 72 vdc figure 2. dpa-switch 30 w, 5 v synchronous rectifier efficiency vs. output power.
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