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| ETHERNET-10 core order number r14006 technical manual february 1997
ii february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. ETHERNET-10 (e-10) core technical manual iii february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. this document is preliminary. as such, it contains data derived from functional simulations and performance estimates. lsi logic has not veri?ed either the functional descriptions, or the electrical and mechanical speci?cations using production parts. document db14-000063-00, first edition (february 1997) this document describes revision a of lsi logic corporations ETHERNET-10 (e-10) core and will remain the of?cial reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, call us at 1.800.574.4286 (u.s. and canada); +32.11.300.531 (europe); 408.433.7700 (outside u.s., canada, and europe) and ask for department jds; or visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. copyright ? 1994-1997 by lsi logic corporation. all rights reserved. trademark acknowledgment lsi logic logo design, coreware, are registered trademarks and g10, and right- first-time are trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. iv february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. ETHERNET-10 (e-10) core technical manual v february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. contents preface chapter 1 introduction 1.1 coreware program 1-1 1.2 local area networks overview 1-3 1.2.1 ethernet standards 1-3 1.3 general description 1-4 1.4 features 1-8 1.4.1 general features and bene?ts 1-8 1.4.2 media access control (mac) features 1-8 1.4.3 encoder/decoder (endec) features 1-9 1.4.4 twisted-pair transceiver interface features 1-9 1.4.5 attachment unit interface features 1-10 1.5 other key e-10 features 1-10 chapter 2 signal descriptions 2.1 logic symbol 2-1 2.2 transceiver interface signals 2-3 2.3 receiver signals 2-6 2.4 receiver status signals 2-8 2.5 multicast filter signals 2-9 2.6 transmitter signals 2-10 2.7 transmitter status signals 2-13 2.8 general mac signals 2-15 2.9 timing and test signals 2-17 chapter 3 e-10 functional description 3.1 media access control (mac) 3-1 vi contents february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. 3.1.1 frame data encapsulation and decapsulation 3-1 3.1.2 frame transmission 3-4 3.1.3 frame reception 3-9 3.2 encoder/decoder (endec) 3-13 3.2.1 pll characteristics 3-13 3.3 twisted-pair interface 3-14 3.3.1 4-wire twisted-pair interface 3-14 3.3.2 8-wire twisted-pair interface 3-16 3.3.3 squelch 3-19 3.3.4 link test function 3-20 3.3.5 polarity detection and correction 3-20 3.4 attachment unit interface (aui) 3-20 3.4.1 6-wire aui interface 3-21 3.4.2 9-wire aui interface 3-23 3.4.3 signal quality error (sqe) function (heartbeat) 3-25 chapter 4 functional timing 4.1 mac transmission and reception timing 4-1 4.1.1 mac transmission timing 4-1 4.1.2 mac reception timing 4-5 4.1.3 endec timing 4-9 4.2 e-10 clock timing 4-10 4.3 multiple core clocking 4-11 4.3.1 core clocks 4-11 4.3.2 80-mhz clock 4-11 4.3.3 10- and 20-mhz clocks 4-12 4.3.4 e-10 testing 4-12 chapter 5 speci?cations 5.1 derivation of ac timing and loading 5-1 5.2 ac timing 5-1 5.3 pin summary 5-4 appendix a glossary customer feedback ETHERNET-10 (e-10) core technical manual vii february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. figures 1.1 ETHERNET-10 mac relationship to the osi model 1-3 1.2 e-10 block diagram 1-7 2.1 e-10 logic symbol 2-2 3.1 mac frame format 3-2 3.2 alternate one-zero manchester encoding 3-3 3.3 host multicast filter implementation 3-11 3.4 4-wire twisted-pair interface using mixed signal cores 3-15 3.5 8-wire twisted-pair interface 3-17 3.6 manchester encoding 3-18 3.7 squelch signal 3-19 3.8 10base-5 aui connection 3-21 3.9 aui 6-wire interface 3-22 3.10 aui 9-wire interface 3-24 4.1 successful transmission 4-2 4.2 transmission aborted by a collision 4-3 4.3 transmission aborted by tabortp 4-4 4.4 successful reception 4-5 4.5 reception with no individual address filter match 4-6 4.6 reception with external multicast filter match 4-7 4.7 reception with no external multicast filter match 4-8 4.8 twisted pair serial output data 4-9 4.9 twisted pair link integrity pulses 4-9 4.10 e-10 clock buffers 4-10 4.11 multiple-core clock multiplexing 4-13 5.1 e-10 core setup and hold timing diagram 5-4 5.2 e-10 core reset timing diagram 5-4 a.1 router osi interconnect level a-7 tables 5.1 e-10 core ac timing parameters 5-2 5.2 e-10 pin summary 5-5 viii contents february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. ETHERNET-10 (e-10) core technical manual ix february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. preface this book is the primary reference and technical manual for the ETHERNET-10 core. it contains a complete functional description for the e-10 core and includes complete physical and electrical speci?cations. audience this document assumes that you have some familiarity with microprocessors and related support devices. the people who bene?t from this manual are: engineers and managers who are evaluating the e-10 core for possible use in value-added local area network (lan) applications, such as network hubs, routers, and adapter cards engineers with motherboard designs requiring system integration of an ethernet core function organization this document has the following chapters and appendixes: chapter 1, introduction , describes the general characteristics and capabilities of the e-10 core. chapter 2, signal description s, describes each of the input and output signals of the e-10 core. chapter 3, e-10 functional description , provides information on the architecture and functional blocks of the e-10 core. chapter 4, functional timing , provides a detailed description of the e-10 media access control (mac) timing and the e-10 clock timing. chapter 5, speci?cations , contains the complete electrical and mechanical speci?cations of the e-10 core. x preface february 1997 - rev. a copyright ? 1994-1997 by lsi logic corporation. all rights reserved. appendix a, glossary , gives a list of terms applicable to the e-10 core. appendix b, customer feedback , includes a form that you may use to fax us your comments about this document. related publications ieee standard 802.3 10 mbits/s ethernet speci?cation coreware? mixed signal 10 mbits/s ethernet transceiver for 10base-t and aui datasheet , order number r15003 conventions used in this manual the ?rst time a word or phrase is used in this manual, it is italicized. see the glossary at the end of this manual for de?nitions of italicized words. the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. the following signal naming conventions are used throughout this manual: a signal whose name ends wit h a p (positive) is true or valid when the signal is high. a signal whose name ends in an n (negative) is true or valid when the signal is low. if a signal can be either active-high or active-low and is an input, the signal name ends in i (input). if a signal can be either active-high or active-low and is an output, the signal name ends in o (output). the following register bit conventions are used throughout this manual: a register bit that is set has a binary value of one. a register bit that is cleared has a binary value of zero. hexadecimal numbers are indicated by the pre?x 0x before the numberfor example, 0x32cf. binary numbers are indicated by the pre?x 0b before the numberfor example, 0b0011.0010.1100.1111. ETHERNET-10 (e-10) core technical manual 1-1 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. chapter 1 introduction lsi logics coreware? library consists of leading-edge microprocessors, ?oating-point processors, digital signal processing (dsp) functions, and peripheral functions. designers can combine coreware building blocks with other lsi logic library elements to implement highly integrated systems in silicon for a wide variety of applications. this document describes the function, operation, and features of the ETHERNET-10 (e-10) building block that is part of the coreware library. this chapter provides an overview of lsi logics coreware program and the coreware building blocks, introduces some networking concepts, describes in general terms the e-10 core, and then provides a summary of the cores features. the chapter contains the following sections: section 1.1, coreware program section 1.2, local area networks overview section 1.3, general description section 1.4, features 1.1 coreware program an lsi logic core is a fully de?ned, optimized, and reusable block of logic. it supports industry-standard functions and has prede?ned timing and layout. the core is also an encrypted rtl simulation model for a wide range of vhdl and verilog simulators. the coreware library contains an extensive set of complex cores for the communications, consumer, and computer markets. the library consists of high-speed interconnect functions such as the gigablaze g10?-p core, mips embedded microprocessors, mpeg-2 decoders, a pci core, and many more. 1-2 introduction february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the library also includes megafunctions or building blocks, which provide useful functions for developing a system on a chip. through the coreware program, you can create a system on a chip uniquely suited to your applications. each core has an associated set of deliverables, including: rtl simulation models for the verilog and hdl environments a system veri?cation environment (sve) for rtl-based simulation synthesis and timing shells netlists for full timing simulation complete documentation lsi logic toolkit support lsi logic's toolkit provides seamless connectivity between products from leading electronic design automation (eda) vendors and lsi logic's manufacturing environment. standard interfaces for formats and languages such as vhdl, verilog, waveform generation language (wgl), physical design exchange format (pdef), and standard delay format (sdf) allow a wide range of tools to interoperate within the lsi logic toolkit environment. in addition to design capabilities, full scan automatic test pattern generation (atpg) tools and lsi logic's specialized test solutions can be combined to provide high-fault coverage test programs that assure a fully functional design. because your design requirements are unique, lsi logic is ?exible in working with you to develop your system-on-a-chip coreware design. three different work relationships are available: you provide lsi logic with a detailed speci?cation and lsi logic does all of the design you design some functions while lsi logic provides you with the cores and megafunctions, and lsi logic completes the integration you perform the entire design and integration, and lsi logic provides the core and associated deliverables whatever the working relationship, lsi logics advanced coreware methodology and asic process technologies consistantly produce right-first-time? silicon. ETHERNET-10 (e-10) core technical manual 1-3 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 1.2 local area networks overview if you are already familiar with networking and local area networks, you may skip this section and proceed directly to section 1.3 on page 1-4. 1.2.1 ethernet standards standards organizations govern the development of speci?cations for ethernet lan technology. the standard having the greatest in?uence over lan design and speci?cations is the ansi/ieee 802.3 ethernet standard, which is available from the ieee in published form. each major lan system technology has gained acceptance by the ieee 802 standards committee. the ieee 802 standards are compati- ble with the international standards organizations (iso) open system interconnect (osi) reference model, shown in figure 1.1. figure 1.1 ETHERNET-10 mac relationship to the osi model application presentation session transport data link physical osi reference model layers lan csma/cd layers higher layers llc - logical link mac - media access reconciliation control control mii pcs pma pmd medium phy mdi mdi = media-dependent interface mii = media-independent interface pcs = physical coding sublayer pma = physical medium attachment phy = physical layer device pmd = physical medium dependent network e-10 core 1-4 introduction february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the e-10 core complies with the media access control (mac) sublevel within the data link layer of the osi reference model and also contains a manchester encoder/decoder (endec) and transceivers for 10base-t or aui interfaces. the endec and transceivers are part of the physical layer of the osi model. 1.3 general description the ieee 802.3 e-10 core provides the designer ?exibility in integrating an ethernet port into an lsi logic application-speci?c design. an ethernet port includes the following: media access control (mac) manchester encoder/decoder (endec) network transceivers the e-10 core is part of the lsi logic coreware library. the coreware program provides the critical building blocks, cad tools, and applications support necessary to achieve high levels of system integration and product differentiation using lsi logics right-first-time asic design methodology. as a coreware product, the e-10 core provides a highly-integrated ethernet core implementation using submicron cmos process technology. this optimization of size and functionality enables designers to easily integrate multiple ethernet cores onto a single chip. the e-10 core is fully synchronous, therefore providing predictable and reliable operation. the e-10 core processes data at 10 mbit/s at half-duplex and 10 mbit/s simultaneously in each direction in full-duplex mode, provides a comprehensive solution for 10base-t based systems, and is designed for easy interface to 10base-2, 10base-5 ,or 10base-f (?ber) media through an attachment unit interface (aui) . the e-10 core engine gives the designer a very effective systems integration building block for developing next-generation networking products for switched hub or router applications. the e-10 core also enables the highest form of system integration for workstation or high-end pcs by converting all the i/o and system logic into a single-chip motherboard solution. ETHERNET-10 (e-10) core technical manual 1-5 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the functional blocks within the e-10 core are: media access control (mac). the media access control function provides simple and independent frame transmission and reception control by means of parallel eight-bit data interfaces. manchester encoder/decoder (endec). the e-10 core contains an integrated endec function that performs manchester encoding and decoding and utilizes a digital phase-locked loop for decoding data at 10 mbit/s. network transceivers. lsi logic provides two methods for integrating aui/tp transceivers: C lsi library cells (best for single-port applications) C mixed signal cells (best for multiport applications) 1-6 introduction february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. lsi logic provides the following mixed signal cores for interfacing to a network: C 10base-t/aui driver C 10base-t/aui receiver C bias generator. these cores perform all the analog interface functions for a 10base-t four-wire twisted pair or aui six-wire connection, reduce requirements for external components, and reduce emissions, which is especially useful for multiport devices. the e-10 core provides inputs and outputs that are easily connected to the mixed signal cores, which are compatible with ieee 802.3 networks. the core has pins that can be connected to an 8-wire twisted-pair interface or a 9-wire aui interface using transmit drivers and differential receivers. figure 1.2 is a block diagram of the e-10 core. ETHERNET-10 (e-10) core technical manual 1-7 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 1.2 e-10 block diagram attachment unit interface (aui) squelch and link integrity detection phase-locked loop data recovery unit 802.3 receive engine - crc and other error checking - collision detection unit 802.3 transmit engine - crc generation - deferral and collision backoff control predistort shaping and link integrity generation manchester encoder control manchester encoder/decoder (endec) function media access control (mac) function host interface unit e-10 core medium attachment unit (mau) 10base-2, 10base-5, or 10base-f 1 network 10base-t network 1. with the proper transceiver implementation, the e-10 can be compatible with 10base-f, 10base-fl and 10base-fx. transceivers transceivers 1-8 introduction february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 1.4 features this section summarizes the key features of the e-10 core. 1.4.1 general features and bene?ts the e-10 core contains the following general features and associated bene?ts: certi?cation to ieee 802.3 ethernet requirements by a recognized ethernet interoperability lab. compliance with other ethernet products at the mac and phy layers of the osi model is assured. deep submicron cmos process technology. submicron technology allows optimized core size and functionality, which enables integration of multiple cores. system veri?cation environment (sve) for e-10 simulation. verilog sve allows designers to rapidly simulate with the e-10 core, and includes an ethernet emulator, packet analyzer, and host interface bus emulator for performing system analysis. vhdl and verilog hdl simulation model support. lsi logic-created core test vectors. the core test vectors are guaranteed to provide a minimum 95% fault coverage. coreware engineering support for applications, development, and test needs. expert engineering assistance is available for integrating the e-10 core into an asic design. 1.4.2 media access control (mac) features the mac contains the following features: ieee 802.3 ethernet standards compliance functionality at the mac sublevel of osi layer 2 support for an external multicast hash ?lter automatic internal frame check sequence (fcs) generator and checker ETHERNET-10 (e-10) core technical manual 1-9 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. programmable source address insertion programmable pad insertion separate, parallel eight-bit host interfaces for transmit and receive data 1.4.3 encoder/decoder (endec) features the endec contains the following features: manchester encoding/decoding C 10 mbit/s receive or transmit (half-duplex) C 10 mbit/s receive and transmit (full-duplextwisted-pair mode only) frame decoding up to 4,500 bytes digital phase-locked loop with synchronous data recovery manchester data decoding of incoming signals containing up to 18 ns of jitter pll with fast lock time (seven bit times)one bit at 10 mbit/s equals 100 ns randomized collision backoff algorithm 1.4.4 twisted-pair transceiver interface features the e-10 twisted-pair transceiver interface has the following features: integrated transceiver, which provide: C transmitter and receiver (four-wire or eight-wire interface) for 10base-t C collision detection C link integrity test internal loopback test capability link polarity detection and correction smart receive squelch for receive data 1-10 introduction february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 1.4.5 attachment unit interface features the e-10 aui interface contains the following features: signal quality error test ( heartbeat ) smart receive squelch for receive data smart sqe squelch for collision detection 10base-2, 10base-5, or 10base-f interface 1.5 other key e-10 features following are some additional key features of the e-10 core: three address filtering modes: C individual address ?ltering (matches 48-bit destination address to 48-bit host-supplied address) C multicast address ?ltering (provides nine-bit polynomial output for matching by an external multicast hashing table) C promiscuous address ?ltering (matches to any individual address) status pins C frame size checking/ runt frame detection C dribble bit error C frame check sequence error C phase-locked loop error ETHERNET-10 (e-10) core technical manual 2-1 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. chapter 2 signal descriptions this chapter provides detailed descriptions of the e-10 signals. these descriptions are useful for designers who are interfacing the e-10 core with other core logic or logic external to the core. this chapter contains the following sections: section 2.1, logic symbol section 2.2, transceiver interface signals section 2.3, receiver signals section 2.4, receiver status signals section 2.5, multicast filter signals section 2.6, transmitter signals section 2.7, transmitter status signals section 2.8, general mac signals section 2.9, timing and test signals please see the subsection entitled conventions used in this manual, in the preface of this manual for a description of how signals are named. 2.1 logic symbol the logic diagram for the e-10 core is shown in figure 2.1. 2-2 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 2.1 e-10 logic symbol e-10 core transceiver interface datap datai datan datatp preep datatn preen collinp collinn lpbadp lcorpp lpassp lforcep rlockedp renabp rcvngp rmcenp rstartp rpmenp rdonep rcleanp rbytep rdatao[7:0] rspllep rsfcsep rsdrblep rsmatip rsmatmp mstartp mdonep mindexo[8:0] mbitp trnsmtp tavailp tstartp tfinishp tdonep tdatai[7:0] treaddp tlastp tsecolp tabortp tslcolp tctri[3:0] tsmcolp tsocolp tssqeep tsnclbp tsidefp colloutp noaddri[47:0] tp/aui duplexp loopbkp clk80i clk20o clk20i clk10o clk10i resetn test1n test2n receiver multicast filter status transmitter status general mac functions timing/test functions rsnoopenp driveenn selio tmode testsep testsip testso fastestn vcc gndn ETHERNET-10 (e-10) core technical manual 2-3 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 2.2 transceiver interface signals the e-10 transceiver interface signals connect to ethernet transceivers or transceiver control lines that are external to the e-10 core. the descriptions of each individual signal are given below. collinn negative collision threshold input collinn is one of two pins (the other is collinp) used to detect collisions . it is used for the aui mode only and must be connected to the negative threshold output of the off-core collision differential receiver. collinp positive collision threshold input collinp is one of two pins (the other pin is collinn) used to detect collisions. it is used for the aui mode only and must be connected to the positive threshold output of the off-core collision differential receiver. datai data in input this input pin receives the serial data from the network and is used by the e-10 endec pll logic for data recovery. it should be connected to the zero offset output of the off-core differential input data receiver. datap data positive output the e-10 core endec transmits positive manchester- encoded data on the datap pin. datap is used in conjunction with the preep signal and operates in both aui and tp modes. datap must be connected to the data input of the off-core transmit driver. datan data negative output the e-10 core endec transmits negative manchester- encoded data on the datan pin. datan is used in test mode and is not needed for interfacing to the mixed signal transmit driver. datatn data threshold negative input datat n i s used in conjunction with d atat p t o control the e-10 core endec squelch function and link integrity pulse detection. it should be connected to the negative threshold output of the off-core differential input data receiver. 2-4 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. datatp data threshold positive input datat p i s o n e o f t w o pins (the other pin is d atatn) that control the e-10 core endec squelch function and link integrity pulse detection. it should be connected to the positive threshold output of the off-core differential input data receiver. driveenn drive enable output driveenn is the enable output signal needed for enabling the mixed signal drivers in a four-wire solution when frame data or link pulses are to be transmitted from the e-10 core. driveen is an active-low signal and must be connected to the enable input of the driver. lcorpp link correct polarity input lcorpp is used in the twisted-pair mode only. when this input is high in twisted-pair mode and the polarity of the link integrity pulses is inverted, the received data is inverted to correct for inverted wiring. the e-10 core endec monitors link integrity pulses, which may be sent on a regular basis from any other device on the network when the channel is idle. the link integrity pulses received by the core normally must be positive- going pulses spaced from 6 to 96 milliseconds apart. if the e-10 core endec detects eight consecutive pulses of the wrong polarity and the lcorpp pin is high, the e-10 core endec inverts the received data. when lcorpp is low, the e-10 core endec does not correct for inverted wiring. lforcep link control force input lforcep is used in the twisted-pair mode only. when lforcep is asserted high, the e-10 core endec allows a transmission even in a link integrity fail situation (occurs when link pulses are not present due to a broken or missing wire). lpassp link state pass output lpassp is used in the twisted-pair mode only to indicate the link status. lpassp is high when the link is active (data or link integrity pulses received). lpassp is low when there is a link failure (no data or link integrity pulses received for more than 96 milliseconds). when in the link fail state (lpassp is low), the transmit function within the e-10 core endec is disabled. the disabling of the ETHERNET-10 (e-10) core technical manual 2-5 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. receive operation has to be done in the mac logic, using this output. the collision output is invalid during the link fail state. lpbadp link polarity bad output lpbadp is used in the twisted-pair mode only to indicate the link polarity status. lpbadp is high when eight consecutive link integrity pulses of inverted polarity are received. if lcorpp is high, the e-10 core endec automatically inverts the data coming from the link to compensate for inverted wiring. preep positive data pre-emphasis output this pin is used in twisted-pair mode only and is the positive pre-emphasis output from the core. the purpose of preep is to increase the amplitude of the higher frequencies in the output signal. data pre-emphasis guarantees that twisted-pair mode can drive signals properly at 10 mbit/s on cable up to 100 meters long. preep is used in conjunction with datap and must be connected to the pre-emphasis input of the off-core mixed signal transmit driver. the mixed signal cell uses datap with preep to generate the proper transmit signals. preen negative data pre-emphasis output this pin is used in twisted-pair mode only and is the negative pre-emphasis output from the core. the purpose of preen is to increase the amplitude of the higher frequencies in the output signal. it is used in test mode and is not needed for interfacing to the mixed sig- nal transmit driver. 2-6 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 2.3 receiver signals the receiver signals connect to the parallel interface and the control circuitry of the system. the description of each signal follows. rlockedp receiver locked output the e-10 core endec asserts this output high when the receiver phase-locked loop is locked onto an input signal and is receiving frame bits. it takes a minimum of six bits and a maximum of eight bits for lock to occur. at least three bits are required for the smart squelch operation and the remaining bits are required for the pll to operate. rbytep received byte output a 100-ns positive pulse on this pin indicates that a new receive data byte is valid and available on the rdatao[7:0] pins. rbytep pulses for 100 ns every 800 ns (a byte time) as long as the e-10 core is receiving data. rcleanp receiver cleanup output the e-10 core drives rcleanp with a 100-ns positive pulse when the end of an invalid frame is encountered. an invalid frame is a frame that failed the address filter or was shorter than a minimum length frame. rcleanp indicates to the host that the bytes received and stored by the host since the last rstartp pulse can be discarded. rcvngp receiving output the e-10 core asserts rcvngp high when the receiver is receiving valid manchester-encoded input data. every valid manchester-encoded bit contains a transition (either high-to-low or low -to-high) in the middle of the 100-ns bit time. the e-10 core asserts rcvngp high directly following the start of frame delimiter and deasserts it low when a bit cell is received without a transition in the center of the bit time. rdatao[7:0] received data output the e-10 core drives the rdatao[7:0] receive data bus with a new data byte when the rbytep pin is pulsed high. the data on these pins is valid and stable for 800 ns until the next rbytep pulse is received. ETHERNET-10 (e-10) core technical manual 2-7 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. rdonep receiver done output the e-10 core drives rdonep with a 100-ns positive pulse after the reception of a complete frame. the rdonep pulse indicates that all data bytes have been written and all receive status bits are valid. renabp receive enable input when renabp is high, the receive engine is enabled, frames are able to be received, and address checking is performed. rmcenp receive multicast enable input when rmcenp is high and the multicast ?lter logic external to the e-10 receiver is enabled, the e-10 core continues to receive the frame. multicast addressing is used when it is necessary to transmit to a selected group of destinations with a single individual address. the ?rst bit of a multicast address is always a one. however, even if rmcenp is high, an individual address (?rst address bit is a zero) can still be recognized. the external multicast ?lter logic supplied by the host uses the nine-bit polynomial supplied on the mindexo[8:0] e-10 pins to create an index into a hash table. the nine bits are the nine msbs of the e-10 linear feedback shift register (lfsr), which generates the 32-bit fcs. the host hash table result (mbitp, mdonep) determines whether or not the e-10 core should continue to receive the frame. rpmenp receive promiscuous mode enable input when this input is high, the e-10 core disables individual address checking. all frames with an individual address are accepted. the least-significant bit of the most- significant byte of an individual address is always a zero. rsnoopenp receiver lookback enable input when rsnoopenp is high, all transmitted frames are routed back through the receiver. operation is similar to that of loopback except that the phase-locked loop is bypassed. a lookback frame is indicated when both the rsmatip and rsmatmp receiver output pins are asserted high. 2-8 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 2.4 receiver status signals the e-10 receiver status signals may be used by the host to monitor various conditions regarding the reception of a data frame. rsdrblep receive status dribble bits output when rsdrblep is high, the number of bits in the received frame was not a multiple of eight, or contained dribble bits. rsfcsep receive status frame check sequence error output when this signal is high, the frame check sequence (fcs), which consists of the last four bytes of the received frame, did not correspond with the expected value. the fcs is also known as a cyclic redundancy check (crc) . the e-10 core preloads a 32-bit lfsr with all ones. it then uses the incoming source address, destination address, length, data, pad, and fcs ?elds to update the 32-bit lfsr. if the contents of the 32-bit lfsr are incorrect after all bits are received, the e-10 core asserts rsfcsep high. rsmatip receive status match individual address output when this signal is high, all 48 destination address bits of the received frame matched the 48 bits of the node or individual address. in promiscuous mode, rsmatip goes high only if the address received matches the individual address. rsmatip is not asserted for multicast addresses. rsmatmp receive status match multicast address output when this signal is high, the frame was received because the external multicast ?lter logic accepted the frame. rsmatmp is not asserted for individual or promiscuous address modes. rspllep receive status phase-locked loop (pll) output error when this pin is high, the phase-locked loop encountered a clock rate error during the reception of the frame. the state of rspllep is a dont care prior to the time that the pll acquires phase-lock. ETHERNET-10 (e-10) core technical manual 2-9 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. a phase-locked loop error signals that the data recovery circuit ran out of elasticity during the reception of the frame. elasticity is a measure of the tolerance of the phase-locked loop to the cumulative bit shift due to small differences in the free-running clock oscillator frequencies of the transmitting source and receiving destination. if the oscillator frequencies are not exactly the same, it is possible that the centers of the bits during lengthy frames will drift apart so much that the phase-locked loop cannot properly recover the data. the pll runs out of elasticity after a bit shift between the transmitter and receiver of exactly six bit times or a clock period difference of .05%. for more information on elasticity, see the subsection entitled pll characteristics on page 3-13. rstartp receiver start output the e-10 core drives this pin with a 100-ns positive pulse immediately following the start of frame delimiter. the pulse may be used to prepare the external logic for the reception of data. 2.5 multicast filter signals the multicast ?lter signals connect to the parallel interface and the control circuitry of the system. the description of each signal follows. mbitp multicast hash table bit input while the mdonep pulse is asserted high, the mac samples mbitp. when mbitp is high, it indicates that the external logic has determined that the destination multicast address is valid. mdonep multicast filter done input external host logic must examine the e-10 mindexo[8:0] lines to determine if a destination multicast address is valid. the host may use mindexo[8:0] as an index into a multicast hash lookup table. when the external logic decides to accept or reject the multicast message based on the hash table results, the logic indicates it to the e-10 receive engine by asserting the mbitp pin high (if the multicast address is accepted) or by deasserting the mbitp pin low (if the multicast address is rejected) and asserting a 100-ns positive pulse on the mdonep pin. 2-10 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. mindexo[8:0] multicast hash function output these nine output pins contain the nine-bit hash function computed from the destination address. the e-10 core uses the nine msbs of the 32-bit lfsr that is used to generate the fcs to create the nine-bit hash function. the nine-bit hash function is generated after the ?nal destination address bit is received. mstartp multicast filter start output when multicast is enabled (rmcenp is high) and a frame is received with a destination multicast address, the e-10 core places a 100-ns pulse on mstartp to indicate to the external logic that a new nine-bit hash function has been computed from the destination address. 2.6 transmitter signals the mac transmitter signals connect to the parallel interface and the control circuitry of the system. the description of each signal follows. tabortp transmit abort input the host asserts tabortp to indicate that an under?ow condition exists, which signi?es that the host is not supplying transmit data fast enough to the core. the host is responsible for detecting the under?ow condition. assertion of tabortp forces an invalid end to the frame. the host may assert tabortp for any reason in order to stop transmission of data. as soon as tabortp is received, the e-10 core transmits 32 bits of alternating ones and zeros, starting with a one, before stopping transmission. tavailp transmit packet available input tavailp should be asserted high when the host has one or more data packets available to be transmitted. this signal is sampled only once per frame, so it can be deasserted low by the host after the e-10 core asserts the trnsmtp and tstartp output pins. the e-10 core continues to attempt to transmit the frame until it is transmitted successfully, an error occurs, or the transmission is aborted. ETHERNET-10 (e-10) core technical manual 2-11 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. after the tavailp signal is ?rst sampled, it is not sampled again until a minimum of 800 ns after the tdonep pulse, to give external logic time to do buffer housekeeping, and to determine whether or not another buffer is ready to be transmitted. tctri[3:0] transmit control input the bits in this four-bit control bus are described in the following table. the tctri[3:0] signals come from the host. they are normally static signals that the e-10 core uses to determine transmission operation. tctri[0] is the insert source address enable signal. when tctri[0] is high, the e-10 core inserts the source address into a transmitted frame from the 48-bit noaddri[47:0] bus supplied at the e-10 input pins by the host. if tctri[0] is low, the host itself must place the source address in the transmitted frame. tctri[1] is the insert fcs field enable signal. when tctri[1] is high, the e-10 core computes a four-byte fcs and appends it to the end of a transmitted frame. when tctri[1] is low, the host must generate and append the fcs ?eld to the frame. tctri[2] is the automatic frame padding enable signal. when tctri[2] is high, the e-10 core examines the data ?eld supplied by the host. if the data ?eld contains less than 46 bytes (46 bytes is the minimum amount of data required for a minimum frame length), the e-10 core supplies enough bytes ?lled with zeroes to make a 46-byte data ?eld. if tctri[2] is low, the e-10 core does not automatically append any bytes to the data ?eld. tctri[3] is the sqe test enable signal. when tctri[3] is high, the e-10 core expects to receive a heartbeat on the collinp and collinn signal inputs after each frame is transmitted. the heartbeat is a 10-mhz burst bit description 0 insert source address enable 1 insert fcs field enable 2 automatic frame padding enable 3 sqe test enable 2-12 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. and starts six to 16 bit times (0.6 m sto1.6 m s) after the last transition of the transmitted signal and lasts for a duration of ?ve to 15 bit times. if tctri[3] is low, the e-10 core expects no such signalling. the sqe test enable signal is not applicable to twisted-pair mode. tdatai[7:0] transmit data input the data on this eight-bit transmit data bus is sampled on the low-to-high transition of clk10i when treaddp is asserted. after treaddp is asserted high, the external logic has up to 800 ns to place the next data byte onto the tdatai[7:0] bus. tdonep transmit done output the e-10 core puts a 100-ns positive pulse on the tdonep pin to indicate either the end of a transmission, the frame was transmitted successfully, excessive collisions are detected, or the signals tfinishp or tabortp are asserted. when this signal is asserted, the transmit status pins are valid. section 2.7, transmitter status signals, de?nes the transmit status pins. tfinishp transmit finish input when tfinishp is asserted high during a transmission, the current transmission attempt is completed, no retry is attempted, and a tdonep pulse generated even if the transmission attempt is not successful. tlastp transmit last byte input the host asserts tlastp high to indicate that tdatai[7:0] contains the last byte of data in the frame. treaddp transmitter read data output a high pulse on this output pin indicates that the data byte previously placed on the tdatai[7:0] lines by the host is going to be read into the e-10 core on the next low-to-high transition of clk10i. after the data is read, the host can remove the data from the tdatai[7:0] pins. the host should put the next data byte on the tdatai[7:0] pins within 800 ns. ETHERNET-10 (e-10) core technical manual 2-13 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. trnsmtp transmitting output a high on trnsmtp indicates to external logic for both the aui and tp modes that the mac is in transmit mode and is putting manchester-encoded data on the e-10 pins that drive the off-core transceivers. tstartp transmit start output the e-10 core asserts a 100-ns positive pulse on the tstartp pin to indicate the start of a transmission (or retransmission). the host should supply data on the tdatai[7:0] pins within 6.4 m s of the tstartp pulse. external logic may use this signal to reset the data pointer to the beginning of the transmit data buffer. 2.7 transmitter status signals the e-10 transmitter status signals may be used by the host to monitor various conditions regarding the transmission of a data frame. tsecolp transmit status excessive collisions output this signal is asserted high when the frame could not be transmitted after 16 attempts. the transmission will then be aborted with no further retry attempts. tsidefp transmit status initially deferred output this signal is asserted high when the ?rst transmission attempt of a frame is deferred because of activity on the network and the frame was transmitted without a collision. the core keeps the tsidefp signal asserted during any subsequent transmission attempt and does not deassert the tsidefp signal until after the end of the transmission. tslcolp transmit status late collision output this signal is asserted high when a collision is detected more than 512 bits into the frame. the transmit engine continues to retry. the time period corresponding to 512 bits is a slot time (51.2 m s), and is considered to be the maximum time necessary to transmit data on an ethernet channel so that all nodes detect activity. if a late collision (after 512 bit times) occurs, it indicates that the ethernet connection is out of speci?cation and corrective action should be taken. 2-14 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. when the e-10 core detects a collision less than 512 bits into the frame, the tsecolp, tsmcolp, or tsocolp signals are asserted high, depending on the circumstances surrounding the collision (see the individual signal descriptions for more details). tsmcolp transmit status multiple collisions output this signal is asserted high when more than one transmission attempt resulted in a collision during the transmission of the frame. this signal is also asserted when the transmission is terminated due to the assertion of tabortp. tsnclbp transmit status no carrier loopback output in aui mode, tsnclbp is asserted high when a transmission results in a transmit carrier loopback or transmit carrier dropout error . if the e-10 core does not detect a signal within 512 bit times from the time it was transmitted, the error condition exists. a transmit dropout condition could result from a broken or missing coaxial cable. in twisted-pair mode tsnclbp is asserted high if a frame is transmitted while the transceiver is in the link-fail state. link pulses are 100-ns in duration and are transmitted every 16.384 ms in the absence of transmit data. a link fail state could result from a broken or missing receive wire pair. tsocolp transmit status one collision output this signal is asserted high when the frame was transmitted after exactly one collision. this signal is also asserted when the transmission was terminated due to the assertion of tabortp. tssqeep transmit status sqe error output a high on this output pin indicates a sqe test error. ETHERNET-10 (e-10) core technical manual 2-15 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 2.8 general mac signals the general mac signals connect to the parallel interface and the control system circuitry. the description of each signal follows. colloutp transmit collision output colloutp is asserted (high) when a collision is encountered during a transmission. colloutp is valid for aui mode and twisted-pair half duplex mode. colloutp is not valid for twisted-pair full duplex mode. in aui mode, the collision signal coming from the external media attachment unit (mau) at the collision input pins causes the colloutp signal to be asserted. in twisted- pair mode, when simultaneous transmit and receive activity takes place, the e-10 core asserts colloutp. the host must take the operational mode into account when interpreting this signal. duplexp full duplex select input when this input is asserted, the mac is in full duplex mode. full duplex mode is applicable only in the twisted- pair mode of operation. in twisted-pair full duplex mode, collision detection is not valid. the host must take the operating mode into account when interpreting the collision output signal (colloutp). loopbkp diagnostic loopback enable input when loopbkp is high, the e-10 core endec is in the diagnostic loopback mode and the transmitter output is fed back to the receiver input inside the core. loopback mode allows testing the e-10 transmitter and receiver up to but not including the off-core transceivers under program control without the need of an external loopback connector. this diagnostic loopback capability is applicable to both the aui and twisted-pair modes. it does not represent the standard loopback function in twisted-pair mode (as the core presents an internal on-chip mau for twisted-pair mode) 2-16 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. noaddri[47:0] node address input this 48-bit node address bus is driven with the individual address of the station. it is up to the host to provide the appropriate levels on noaddri[47:0] to con?gure the address. selio 4-wire and 8-wire mixed signal cell select input selio must be asserted for four-wire twisted-pair mode and deasserted for eight-wire twisted-pair mode. when selio is asserted, the core does not use the preep, preen, or datan signals. for more information on the four-wire and eight-wire modes, see section 3.3, twisted-pair interface on page 3-14. tp/aui twisted-pair/aui select input when tp/aui is deasserted (low), the mac core is in aui mode. when the signal is asserted (high), twisted- pair mode is selected. below are listed the principal differences in the way the e-10 core operates in these two modes: it makes no difference to the core if the aui interface is 6-wire or 9-wire. the transceivers and external circuitry used in either 6-wire or 9-wire aui operation present the same signals to the mac core. for more information on the aui mode of operation, see section 3.4, attachment unit interface (aui) on page 3-20. for more information on the twisted-pair mode of operation, see section 3.3, twisted-pair interface on page 3-14. feature tp mode aui mode sqe test no yes link pulse detection yes no link pulse polarity detection and correction ye s n o link integrity pulses generated yes no collision pair pins (collinp, collinn) are used no yes cause of loopback transmit carrier error link fail no carrier loopback ETHERNET-10 (e-10) core technical manual 2-17 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 2.9 timing and test signals the timing and test signals connect to the parallel interface and the control circuitry of the system. in multiple-core environments, only one core may be the clock master. all other cores must be slaves. for clock duty cycles and tolerances, see section 4.2, e-10 clock timing, on page 4-10. the description of each signal follows. clk10i 10-mhz clock in input the e-10 core endec uses clk10i for mac and bus interface timing. clk10i should be driven by the clk10o output pin through a buffer external to the e-10 core. clk10o 10-mhz clock out output this 10-mhz output is derived from the 80-mhz input signal, clk80i. clk20i 20-mhz clock in input the e-10 core uses clk20i for timing and for the manchester encoder clocking. clk20i should be driven by the clk20o output pin through a buffer external to the e-10 core. clk20o 20-mhz clock out output this 20-mhz output is derived from the 80-mhz input signal, clk80i. clk80i 80-mhz clock in input clk80i is the master clock source provided to the e-10 core endec. it is the only external timing signal used by the e-10 core endec. clk80i may be provided as an external oscillator or it may be provided with a pll circuit as part of some chip logic surrounding the e-10 core. fastestn fast test input fastestn is used for chip testing purposes only (fast test) and must be left high during normal operation. gndn ground input the gnd signal must be asserted (low) during normal core operation. it is used for testing the core. 2-18 signal descriptions february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. resetn core reset input after power is applied to the chip, resetn should be asserted low for a minimum of 200 ns (at least 100 ns after test1n goes high) to force initialization. testsep scan enable input testsep is the scan enable pin for testing the module in the endec. the endec has a full-scan test chain built into it. testsip scan input input testsip is the scan input pin for full scan testing. testsop scan output output testsop is the scan output pin for full scan testing. test1n test 1 input test1n is for chip testing purposes only (fast test) and must be left high in normal operation. test2n test 2 input test2n must be left high in normal operation. it must be asserted low for 100 ns to initialize the endec core logic. the clk10o and clk20o outputs become operational only after the tes2n signal is deasserted (high) during initialization resetn is then asserted (low) for an additional 100 ns to initialize the rest of the endec logic. in test mode, test2n is used for testing the endec core. tmode test mode input tmode must be left deasserted (low) during normal operation and asserted (high) in test mode. tmode is used during scan testing. vcc positive voltage input the vcc pin should be asserted (high) during normal operation. it is used for core testing. ETHERNET-10 (e-10) core technical manual 3-1 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. chapter 3 e-10 functional description this chapter provides a functional description of the e-10 core and contains the following sections: section 3.1, media access control (mac) section 3.2, encoder/decoder (endec) section 3.3, twisted-pair interface section 3.4, attachment unit interface (aui) 3.1 media access control (mac) the mac is the portion of the e-10 core that handles the carrier sense multiple access with collision detection ( csma/cd ) protocol for trans- mission and reception of frames. the mac performs the following func- tions: frame data encapsulation and decapsulation frame transmission frame reception 3.1.1 frame data encapsulation and decapsulation the format of the frame generated by the ansi/ieee ethernet 802.3 protocol consists of several ?elds, as explained in the following subsections. figure 3.1 shows the overall structure and order of transmission of bits and octets of a frame. 3-2 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 3.1 mac frame format 3.1.1.1 preamble field the preamble ?eld is a 7-octet (56-bit) alternating one-zero pattern (starting with a one), which is manchester-encoded before being transmitted onto the media. the alternating one-zero pattern ensures that there are no transitions between bits in the manchester-encoded signal, which results in a 5-mhz signal (see figure 3.2). because the twisted-pair ethernet cable attenuates higher frequencies, the 5-mhz signal creates a perfect signal for acquisition by the digital phase-locked loop (pll). any pattern other than an alternating one-zero pattern would create a higher-frequency signal and make acquisition more dif?cult. in addition, an alternating one-zero data pattern, when manchester- encoded, has data transitions at the same clock edge, which makes it easier for the pll to achieve lock. 7 octets 1 octet 6 octets 6 octets 2 octets 4 octets lsb preamble sfd destination address source address length/type frame check data pad sequence msb bit 0 bit 7 bits within each octet are transmitted left-to-right octets within a frame are transmitted top-to-bottom 1 frame ETHERNET-10 (e-10) core technical manual 3-3 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 3.2 alternate one-zero manchester encoding 3.1.1.2 start frame delimiter (sfd) field the eight-bit start of frame delimiter ?eld contains the 10101011 2 bit pattern. this bit pattern allows alignment of the data received in the rest of the frame. 3.1.1.3 address fields the frame has two 48-bit address ?elds. the ?rst ?eld contains the destination address and speci?es the address(es) for which the frame is intended. if the ?rst bit of the destination address is a zero, the address is an individual address. a one in the ?rst bit indicates a multicast or group address. the second address is the source address and should contain the individual address of the station from which the message originated. 3.1.1.4 length/type field the two-byte length ?eld indicates the number of data bytes in the data ?eld. the mac does not interpret the data in the length ?eld and does not treat it any differently than the data ?eld. 3.1.1.5 data and pad field the data ?eld contains a sequence of fully transparent data bytes; that is, the data bytes are not analyzed or interpreted in any way by the mac. the size of the data ?eld may be between zero and 1,500 bytes, but can be extended up to 4,500 bytes or more, depending on the clock accuracy of the transmitting and receiving stations. 10-mhz clock 1 bit alternate ones and zeroes data (5 mhz) 010 101 010 010 101 alternate ones and zeroes data manchester-encoded 1 3-4 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the function of the pad ?eld is to ensure minimum frame size. if the supplied data ?eld contains less than 46 bytes of data, the mac can add a pad ?eld to make the sum of bytes in the data and pad ?eld equal to 46. appended pad data consists of bytes ?lled with zeroes. 3.1.1.6 frame check sequence (fcs) field the transmit and receive algorithm uses the standard 802.3 four-byte frame check sequence (fcs) ?eld to ensure data integrity. the e-10 core uses a linear feedback shift register to compute the value in the fcs ?eld. the fcs is a function of the content of the source address, destination address, length, data, and pad ?elds. the generating polynomial shown in equation 3.1 de?nes the encoding. the nine msbs of the fcs may be used by an external hashing table function to perform multicast address ?ltering. equation 3.1 fcs encoding 3.1.2 frame transmission frame transmission is enabled with the tavailp signal. tavailp indicates that at least one frame is ready to be transmitted. all transmissions start by complying with the rules of deference; that is, they monitor the physical medium for activity. if no activity exists, the transmit cycle starts. during the start of a transmission, the transmitter asserts a 100-ns positive start of transmission pulse (tstartp). the start pulse resets the transmit pointer to the beginning of the transmit buffer. when the treaddp signal is pulsed (high), it indicates to the external control logic that data is read on the low-to-high transition of the clk10i input. if a collision is detected during a transmission, the collision enforcement rules are followed, and the transmission is aborted. if the signals tabortp and tfinishp are not asserted, and the frame was not retried 15 times, backoff and deference rules are followed and the frame transmission is retried. the external control logic asserts the tlastp signal to indicate that the last byte of data to be transmitted is present at the tdatai[7:0] pins. when a frame is transmitted successfully, or when a serious error is gx () x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 3 x 2 x1 ++++++++++ ++ + ++ = ETHERNET-10 (e-10) core technical manual 3-5 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. detected during the transmission, the transmitter asserts the transmitter done (tdonep) pulse. the tdonep pulse indicates to the external logic that either the transmission is complete, or the tabortp or tfinishp signals were asserted before the end of the transmission, or that the transmitter exhausted its ability to transmit the frame successfully. external logic has a minimum of 800 ns to deassert or assert tavailp indicating whether or not a new frame is ready for transmission. 3.1.2.1 carrier deference rules even when it has nothing to transmit, the transmit portion of the mac monitors the traf?c on the physical medium. when there is no traf?c (a carrier is not detected by the mac and the mac is not transmitting) the mac starts a 9.6 m s interframe timer. the interframe timer is reset if the mac senses a carrier during the ?rst 5.6 m s of the interframe gap after a reception. during the time from 5.6 m s to 9.6 m s, the interframe timer is not reset, to ensure fair access to the medium. if, at the end of the interframe gap, a frame is waiting to be transmitted, transmission is started regardless of the presence of a carrier. if a carrier is present, a collision occurs so that a node constantly transmitting is forced to back off. if, at the end of the interframe gap, there is no frame waiting to be transmitted, the mac starts monitoring for a carrier again, and resets the interframe timer as soon as it detects a carrier. 3.1.2.2 interframe spacing the carrier deference method described above ensures that the e-10 provides an interframe gap of 9.6 m s. the interframe gap ensures fair arbitration among all sources trying to transmit and prevents one transmitter from dominating the transmission channel. 3.1.2.3 collision enforcement rules when a collision is detected during a frame transmission (for the definition of a frame, see the subsection entitled frame data encapsulation and decapsulation on page 3-1), the transmission is not terminated immediately. the preamble and start of frame delimiter (sfd) are transmitted unmodified regardless of the collision state. if a collision is detected before the preamble and sfd have finished transmitting, a 32-bit jam pattern of alternating ones and zeros is transmitted immediately after the sfd and then the transmission ends. if the collision is detected after 3-6 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the preamble and sfd, while data is being transmitted, the data transmitted changes to a jam pattern of alternating ones and zeros for 32 bits before the transmission is terminated. 3.1.2.4 transmission backoff algorithm when a transmission attempt has terminated due to a collision, the transmission is retried until either it is successful or 15 retries (16 attempts total) have been terminated due to collisions. a controlled randomization process called truncated binary exponential backoff schedules the retransmission. at the end of enforcing a collision (jamming), the transmit engine delays before attempting to retransmit the frame. the delay is in 51.2 m s increments, or slot times . the number of slot times to delay before the nth retransmission attempt is chosen as a uniformly distributed random integer r in the range: -1 3-8 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. transmit carrier loopback error (tsnclbp). in aui mode, when an error is detected in the receive carrier signal that is required to be fed back during the transmission of a frame, the e-10 core asserts the transmit carrier loopback error pin (tsnclbp) high. two different conditions can cause the transmit carrier loopback error pin to be asserted in aui mode: C during transmission, no carrier is received during the ?rst 512 bit times (51.2 m s) of the transmission. C during transmission, carrier was received but was interrupted before transmission stopped. the transmit carrier loopback error has no effect on the transmission/ retransmission process, but no sqe test is performed. in twisted-pair mode, the e-10 core asserts the transmit carrier loopback pin high to indicate a link failure during the transmission of the frame. a link failure can be caused by a twisted-pair transceiver failure or by a broken twisted-pair cable. in the link fail state, the e-10 core does not route the manchester-encoded data to the transmitter pins, but it still transmits link integrity pulses. sqe error (tssqeep). the e-10 core asserts the signal quality error pin (tssqeep) high when the mac detects all the following conditions: C the e-10 core is in aui mode C the e-10 core is in half-duplex mode C sqe testing is enabled (tctri[3] pin is high) C the late collision status pin (tslcolp) is not high C the excessive collisions status pin (tsecolp) is not high C the transmit carrier loopback error status pin (tsnclbp) is not high C no sqe signal was received in the first 5.6 m s of the interframe gap one collision (tsocolp). the e-10 core asserts the one collision status pin (tsocolp) high when the frame is transmitted after exactly one collision. if more than one collision occurred before the frame was transmitted, the tsmcolp pin is asserted (high) and the tsocolp pin is deasserted (low). assertion of the tsocolp pin is not an error indication, but is intended only for information, and ETHERNET-10 (e-10) core technical manual 3-9 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. can be used to update network statistics counters. when the transmission of a frame is terminated with the signal tabortp, the e-10 core asserts the tsocolp signal (together with tsmcolp) to indicate this fact to external logic. section 2.6, transmitter signals, contains a description of the tabortp signal. tsocolp is valid when the tdone pin pulses. multiple collisions (tsmcolp). the e-10 core asserts the multiple collision status pin (tsmcolp) high when the frame is transmitted after more than one collision. this pin is not an error indication, but is intended only for information, and can be used to update network statistical counters. when the transmission of a frame was terminated with the signal tabortp, the e-10 core asserts the tsmcolp signal (together with tsocolp) to indicate this fact to external logic. tsmcolp is valid when the tdonep pin pulses. 3.1.3 frame reception frame reception is allowed after the receiver enable signal (renabp) is asserted. after the transceiver squelch circuitry detects a valid signal, and the receiver pll locks onto the incoming signal as indicated by assertion of the rlockedp signal, the receiver starts searching for a valid start of frame delimiter. the pll takes a minimum of six and a maximum of eight bit times (600 to 800 ns) to achieve lock. a valid start of frame delimiter is de?ned as 0b10101011. when the start of frame delimiter is detected, the receiver pulses the rstartp pin. a pulse on the rstartp pin informs the external logic to make available a new receive buffer, because received data will start arriving in 800 ns. every time a new byte of received data is available on the rdatao[7:0] bus, the e-10 receiver pulses the rbytep pin. the ?rst 48 bits of the frame contain the destination address. the mac receiver portion of the e-10 core compares the destination address bits with the data on the 48-bit node address bus (noaddri[47:0]), and when the bits are equal, allows the continued reception of the frame. when the receiver promiscuous mode pin (rpmenp) is asserted, any individual destination address validates the frame, and allows the reception process to continue. when the destination address is a multicast address, including the broadcast address (the address contains all ones), the receiver computes a nine-bit hash function from the destination address, and leaves the decision to accept or reject the frame to external logic. 3-10 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. when an end-of-frame delimiter is detected, the receiver accepts the frame and generates a 100-ns pulse on the rdonep pin when all the following conditions are true: at least one address ?lter passed the frame was at least 64 bytes in length the receiver is still enabled when the end-of-frame delimiter does not generate an rdonep pulse, the receiver instead pulses the rcleanp pin, which indicates to the external logic that it must ignore the data received. it is then up to the host logic to manage the receive buffer space properly (either give up the buffer space so it can be used for other transmit or receive data or allocate another buffer). 3.1.3.1 address filtering three address ?lter mechanisms are present in the receiver, two for individual addresses, and one for multicast addresses. at least one of these address ?lters must pass to accept the received frame. the address ?lters are listed below: individual address filter . the ?rst bit of an individual address is a zero. the incoming destination address is compared with the data from the individual address pins. when all 48 bits match and the receiver is enabled (renabp pin asserted high), the address ?lter passes. individual address promiscuous mode . when the external logic asserts the individual address promiscuous mode enable pin (rpmen) high and the destination address is an individual address, the address ?lter always passes, and the incoming frame is received. multicast address filter . the ?rst bit of an multicast address is a one. when the destination address bits that are received in the frame contain a multicast address, the e-10 core uses its built-in fcs generator to compute a nine-bit polynomial (the nine msbs of the 32-bit fcs generator) from the incoming address. the value of this polynomial can be used as an index into an external multicast ?lter hash table. external logic can decide to either accept or reject the incoming frame. the external logic asserts the rmcenp pin (high) to enable the multicast address ?lter. figure 3.3 shows the general ETHERNET-10 (e-10) core technical manual 3-11 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. host implementation of a multicast ?lter. section 2.5, multicast filter signals, in chapter 2, signal descriptions, explains the functions of the individual signals shown in the ?gure. when the destination address is all ones, it indicates a broadcast address. when the e-10 core detects a broadcast address, it receives the incoming frame. figure 3.3 host multicast filter implementation 3.1.3.2 fcs checking during reception, the fcs value is checked against the value computed by the receive crc checker. if the two values do not match, the frame is received and the e-10 core asserts the fcs error pin (rsfcsep) high to indicate data corruption in the frame. the decision to accept or reject the frame is left to external logic. 3.1.3.3 frame size checking frame size checking is performed on every received frame. if a frame is less then 64 bytes in length, the receiver cleanup pulse (rcleanp) discards the received data (collision fragment). ieee 802.3 speci?es a maximum frame size of 1,518 bytes, but the mac does not do any maximum length checking, and much larger frames (for instance 4,500 bytes) can be received, as long as care is taken not to exceed pll elasticity. the application is responsible for checking the maximum frame size and reporting any errors. e-10 core rmcenp (high to enable e-10 multicast filter logic) multicast filter hash table mindex8 mindex0 mindex8 mindex0 mdonep mbitp 32-bit lfsr bit 32 bit 24 register mstartp 3-12 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 3.1.3.4 start of frame delimiter checking the start of frame delimiter, a bit sequence of 0b10101011 that occurs following the preamble, starts the reception of bytes. 3.1.3.5 receive status indications the ?ve e-10 pins listed below indicate the status of ethernet reception with regard to collisions and errors. frame check error (rsfcsep). the e-10 core asserts the frame check error pin (rsfcsep) high when bits of the incoming frame do not generate a crc identical to the one in the received fcs ?eld, indicating data corruption has occurred in the received frame. dribble bit error (rsdrblep). the e-10 core asserts the dribble bit error pin (rsdrblep) high at the end of a frame when less than a complete byte has been received, indicating the reception of from one to seven dribble bits. the e-10 core asserts the rsdrblep pin high independently of the frame check error bit. rsdrblep can be ignored if the rsfcsep pin is not set. the reason rsdrblep can be ignored is that the fcs is updated every eight bits. if there are less than eight dribble bits (from one to seven bits) at the end of the frame and the current fcs is correct, any extra dribble bits (less than eight) do not matter. however, if there are eight or more dribble bits, the fcs will be updated and will most likely be wrong due to the dribble bits. in this case, rsdrbel should not be ignored. phase-locked loop error (rspllep). the e-10 core asserts the phase-locked loop error pin (rspllep) when, during reception of a frame, the digital phase-locked data recovery circuit elasticity is exhausted. the elasticity becomes exhausted due to drift between the 10-mhz clock frequency of the device sending the data and the endec 10-mhz clock frequency. see the subsection entitled pll characteristics on page 3-13 for an explanation of elasticity. rspllep is asserted when a frame is received with a transmit clock error suf?ciently larger than the ieee 802.3 requirement of 0.01% that the pll elasticity is exhausted within a normal frame, or when a frame length suf?ciently larger than that speci?ed in ieee 802.3 has caused the elasticity to be exhausted even when the clock is within tolerance. ETHERNET-10 (e-10) core technical manual 3-13 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. match individual address (rsmatip). the e-10 core asserts the match individual address pin (rsmatip) high when the destination address matches the node address. match multicast address (rsmatmp). the e-10 core asserts the match multicast address pin (rsmatmp) high or deasserts it low as a result of the decision of the external multicast ?lter logic to accept or reject the multicast address. 3.2 encoder/decoder (endec) the endec consists of the manchester encoder, manchester decoder, and the digital phase-locked loop. 3.2.1 pll characteristics the digital phase-locked loop used for data recovery has the following characteristics: sampling C sampling frequency: 160 mhz C sampling interval: 6.25 ns with the above sampling parameters, each bit of 100 ns is sampled 16 times. jitter tolerance: 18.00 ns this parameter indicates that the incoming data bits may have a jitter up to 18.00 ns and the digital pll will still work acceptably. tracking speed C initial (?rst 4.8 m s): 0.39% C steady-state (after 4.8 m s): 0.098% when ?rst attempting to lock on to an oncoming data stream (during the ?rst 4.8 m s), the pll looks every 16 bits to see if a bit transition is occurring in the center of the sampling window. dividing the sampling interval of 6.25 ns by the 16-bit interval (1600 ns) yields 0.0039 or 0.39%. 3-14 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. after the ?rst 4.8 m s, the pll maintains a window of 64 bits for ?nding a transition. dividing the sampling interval of 6.25 ns by the 64-bit interval (6400 ns) yields 0.00098 or 0.098%. elasticity C maximum clock drift time 600 ns (6 bit times) C maximum clock error @ 1518 byte frame: 0.05% C maximum clock error @ 4500 byte frame: 0.016% elasticity indicates the tolerance of the pll to slightly different clock rates between a transmitter and a receiver. the e-10 core allocates a buffer of 13 bits to accommodate clock drift. the 13-bit buffer allows a clock drift of six bits (600 ns) from center in either direction during a frame transfer. for a 1518-byte frame, consisting of six bytes of destination address, six bytes of source address, two bytes of length, 1500 bytes of data, and four bytes of fcs (6 + 6 + 2 + 1500 + 4 = 1518), the maximum clock drift allowed is 0.05% (0.05% x 1518 bytes x 8 bits/byte = 6 bits). for a 4500 byte frame, the maximum clock drift allowable during frame transfer is 0.016% (0.016% x 4500 bytes x 8 bits/byte = 6 bits). 3.3 twisted-pair interface the e-10 core supports two twisted-pair con?gurations: four-wire eight-wire 3.3.1 4-wire twisted-pair interface the four-wire e-10 twisted-pair interface is shown in figure 3.4. the four-wire interface implements coreware mixed signal transmitter and receiver cores to prepare the e-10 cores i/o signals for connection to the network. an asic implementation of an ethernet port using the e-10 core and mixed signal i/o cores provides a simple interface to the network. ETHERNET-10 (e-10) core technical manual 3-15 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. a four-wire interface is usually best for multiport applications. the mixed signal i/o cores reduce the number of asic device pins and external passive components. figure 3.4 4-wire twisted-pair interface using mixed signal cores 3.3.1.1 4-wire twisted-pair transmit interface with the four-wire twisted-pair interface, the e-10 core outputs a single manchester-encoded transmit signal, datap, to a mixed signal differential driver core. the driver produces low common-mode noise differential outputs, which provide the desired output swing to the magnetics (transformer). the mixed signal driver reduces the generation of high-frequency signal components, thereby minimizing external ?ltering requirements and reducing external component costs. 3.3.1.2 4-wire twisted-pair receive interface the four-wire receiver interface complies with the receiver speci?cations of the ieee 802.3 10base-t standard, including noise immunity, propagation delays, jitter requirements, and received signal rejection criteria (smart squelch). e-10 core datap datatp datatn asic drivers receivers rj-45 connector 10base-t data i passive components tx+ tx- rx+ rx- magnetics and 3-16 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the four-wire twisted pair receive interface has three signals at the e-10 core interface: d atat p, datat n , a n d data i . t h e three signals are inputs to the e-10 core and come from a two-input differential mixed signal receiver. the receiver converts the two differential analog data signals from the network to d atat p, datat n , a n d data i , which are cmos-level single-ended digital outputs. the three signals switch in such a way that the e-10 core can properly perform data detection, reverse polarity detection, and smart squelch. 3.3.2 8-wire twisted-pair interface the eight-wire e-10 twisted-pair interface is shown in figure 3.5. this interface uses data pre-emphasis on data transmitted from the core and threshold detection circuitry on the data being received by the core. ETHERNET-10 (e-10) core technical manual 3-17 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 3.5 8-wire twisted-pair interface 3.3.2.1 8-wire twisted-pair transmit interface with the eight-wire twisted-pair interface, the core outputs four transmit signals, the true and complemented (differential) manchester-encoded data (datap and datan) and those signals delayed by 50 ns (preep and preen). these four signals are sent through four individual transmit buffers and resistively combined (datap with preep and datan with preen). the technique of resistively combining the signals is known as digital pre-emphasis and provides the necessary electrical driving capability and predistortion control for transmitting signals over a maximum length twisted-pair cable, as speci?ed by the ieee 802.3 10base-t standard. digital pre-emphasis compensates for the twisted- pair cable, which acts like a low-pass ?lter and causes greater attenuation to the 10-mhz (50-ns) pulses of the manchester encoded waveform than the 5-mhz (100-ns) pulses. when a data stream of all ones or all zeroes is present, manchester encoding causes a transition e-10 core datap preep datan preen datai datatp datatn asic rj-45 connector 10base-t drivers receivers passive components magnetics and tx+ tx- pre+ pre- rx+ rx- ref ref 3-18 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. every bit time, which creates a 10-mhz bitstream. with a data stream of alternate ones and zeroes, manchester encoding causes a transition every other bit time, which creates a 5-mhz bitstream. figure 3.6 shows how different data patterns are manchester encoded. the differential manchester-encoded signal is passed to an external transmit ?lter. the transmit function meets the propagation delays and jitter speci?ed by the standard. figure 3.6 manchester encoding 3.3.2.2 8-wire twisted-pair receive interface the eight-wire receiver interface complies with the receiver speci?cations of the ieee 802.3 10base-t standard, including noise immunity, propagation delays, jitter requirements, and received signal rejection criteria (smart squelch). with the eight-wire twisted-pair receive interface, there are three input signals at the e-10 core interface: d atat p, datat n , a n d data i . these input signals are the outputs from three distinct differential receivers. in a similar fashion to the four-wire interface, the three input signals switch in such a way that the e-10 core can properly perform data detection, reverse polarity detection, and smart squelch. 10-mhz clock 1 bit all ones all zeroes 111 111 111 111 111 1 000 000 000 000 000 0 alternate ones and zeroes data (5 mhz) 010 101 010 010 101 00 10 1 1 11 0 1 1 0 1 1 1 0 random data data (10 mhz) data (10 mhz) ETHERNET-10 (e-10) core technical manual 3-19 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. following is a functional description of the twisted-pair interface. it includes these sections: squelch link test function polarity detection and correction 3.3.3 squelch an intelligent (smart) receive squelch is implemented on the receiver differential inputs to ensure that impulse noise on the receiver inputs is not mistaken for a valid signal. the smart squelch logic uses a combination of amplitude and timing measurements to determine the validity of data on the twisted-pair inputs. the squelch circuitry operation is illustrated in figure 3.7. squelching determination starts when the input signal crosses the positive or negative threshold (a). to continue a valid signal sequence, the signal then has to cross the other threshold (b) within 150 ns. to complete the valid signal process, the input signal has to cross the original threshold (c) again within 150 ns. if the signal proves to be valid, the smart squelch logic does not suppress the signal. however, if not all of the conditions just outlined are met, the signal is suppressed. figure 3.7 squelch signal < 150 ns < 150 ns a b c positive negative threshold threshold (+ 585 mv ) (- 585 mv) 3-20 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 3.3.4 link test function the link test function is implemented as speci?ed by the ieee 802.3 10base-t standard. during periods of transmit pair inactivity, link test pulses are periodically sent from any transmitting device over the twisted- pair medium to allow constant monitoring of medium integrity. link pulses, which are 100 ns wide, are transmitted from the e-10 core every 16.384 ms in the absence of transmit data. the core expects to receive a link pulse every 96 ms. the absence of serial link integrity pulses on the receiver inputs causes a link fail state to occur. in the link fail state, data transmission, data reception, and the collision detection functions are disabled and remain disabled until valid data or eight consecutive link test pulses appear on the receiver inputs. when the e-10 core identi?es the link as functional, the e-10 core asserts the lpassp pin high to indicate that the link status is good. 3.3.5 polarity detection and correction the receive function includes the ability to invert the polarity of the signals appearing at the receiver pair if the polarity of the received signal is reversed, as in the case of a wiring error. this feature allows frames received from a reversed twisted-pair interface to be corrected prior to transfer to the e-10 core. the function uses link pulses to determine polarity of the received signal. a reversed polarity condition is detected when seven consecutive opposite-polarity receive link pulses are detected without receipt of a link pulse of the expected polarity. 3.4 attachment unit interface (aui) an aui provides the link from a 10base-t network to a 10base-5, 10base-2, or 10base-f network. as shown in figure 3.8, an aui provides the appropriate interface to a medium attachment unit (mau) so that the mau can interface to a variety of physical media. ETHERNET-10 (e-10) core technical manual 3-21 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 3.8 10base-5 aui connection auis provide transmit, receive, and collision control functions. the e-10 core supports two different attachment unit interface (aui) configurations: six-wire nine-wire 3.4.1 6-wire aui interface the six-wire e-10 aui interface shown in figure 3.9 implements coreware mixed signal transmitter and receiver cores to prepare the e-10 cores i/o signals for connection to the network. an asic implementation of an ethernet port using the e-10 core and mixed signal cores, along with a few discrete components provide impedance matching, isolation, filtering and electromagnetic interference (emi) suppression. dte (pc) mau aui endec transceiver coaxial cable 3-22 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 3.9 aui 6-wire interface without the integrated mixed signal i/o cores, multiple-port interfaces produce high common-mode coherent noise, which requires the use of expensive ?ltering to meet fcc requirements. 3.4.1.1 6-wire aui transmit interface with the six-wire aui interface, the e-10 core outputs a single manchester-encoded signal, datap, to a mixed signal differential driver core. the driver produces low common-mode noise differential outputs. using controlled impedance voltage, the driver produces the desired output swing to the magnetics (transformer). asic e-10 core datap datatp datai datatn collinp collinn 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 aui db-15 connector driver receiver receiver passive components magnetics and tx+ tx- rx+ rx- coll+ coll- collision data data ETHERNET-10 (e-10) core technical manual 3-23 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. using mixed signal drivers reduces the generation of high-frequency signal components, which propagate easily and cause interference. high- frequency components must otherwise be eliminated with external filtering. using mixed signal drivers minimizes external filtering requirements and thereby reduces the associated external component costs. 3.4.1.2 6-wire aui receive interface the six-wire twisted pair receive interface provides a receiver for data and a receiver for collision control. the data receiver has three signals at the e-10 core interface: d atat p, datatn, and datai. the three signals are inputs to the e-10 core and come from a two-input differential mixed signal receiver. the data receiver converts the two differential analog data signals from the network to d atat p, datat n , a n d data i . t h e three signals switch in such a way that the e-10 core can properly perform data detection, reverse polarity detection, and smart squelch. the collision receiver has two signals at the e-10 core interface: collinp and collinn. these two signals are inputs to the core and come from a two-input differential mixed signal receiver 3.4.2 9-wire aui interface the nine-wire e-10 aui interface is shown in figure 3.10. 3-24 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 3.10 aui 9-wire interface 3.4.2.1 9-wire aui transmit interface with the nine-wire aui interface, the e-10 core outputs two transmit signals, the true and complemented (differential) manchester-encoded data signals datap and datan. the transmit circuitry sends these differential signals to the aui cable through a transformer. a transformer isolates the transmit pins from the transceiver cable, achieving system isolation. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 aui db-15 connector asic e-10 core data p datatp data i datat n collinp collinn driver receiver receiver collision data data datan passive components magnetics and ETHERNET-10 (e-10) core technical manual 3-25 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 3.4.2.2 9-wire aui receive interface the nine-wire twisted pair receive interface provides a receiver for data and a receiver for collision control. the data receiver has three signals at the e-10 core interface: d atat p, datatn, and datai. the data receiver converts the two differential analog data signals from the network to d atat p, datat n , a n d data i . t h e three signals switch in such a way that the e-10 core can properly perform data detection, reverse polarity detection, and smart squelch. the collision receiver has two signals at the e-10 core interface: collinp and collinn. 3.4.3 signal quality error (sqe) function (heartbeat) the signal quality error (sqe) diagnostic feature has been speci?ed for the mau in the ieee 802.3 standard. the feature is supported by the e-10 core when it operates in the aui mode with an external mau (see figure 3.8). the sqe test is a self-test feature supported in the mau that is invoked after the end of each transmission by the dte, where the e-10 core is located. when enabled, the sqe test consists of a 10-mhz burst sent from the mau over the collision pair and starts six to 16 bit times (0.6 m s to 1.6 m s) after the last transition of the transmitted signal and lasts for a duration of ?ve to 15 bit times. this test is an indication to the e-10 core that the mau has recognized the end of the transmission and the mau collision circuitry is intact and operational. 3-26 e-10 functional description february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. ETHERNET-10 (e-10) core technical manual 4-1 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. chapter 4 functional timing this chapter describes the media access controller (mac) and e-10 clock timing and contains the following sections: section 4.1, mac transmission and reception timing section 4.2, e-10 clock timing section 4.3, multiple core clocking 4.1 mac transmission and reception timing this section explains mac transmission and reception timing, and manchester encoder-decoder (endec) timing. 4.1.1 mac transmission timing figure 4.1 shows the mac transmission timing. the transmission process starts with external logic asserting tavailp to indicate that a complete frame is ready to be transmitted (a). the transmitter starts transmitting (the e-10 core asserts trnsmtp high) as soon as it is ?nished deferring, and then waits an additional 9.6 m s for the interframe gap (b). at this time, the e-10 core pulses the tstartp pin to indicate that transmit data is needed within 6.4 m s on the transmit data bus (tdatai[7:0]). at this point, the e-10 core pulses the treaddp pin every 800 ns for every byte of transmit data read from the transmit data bus. there are gaps in the stream of treaddp pulses when the transmitter does an automatic insertion of the source address, pad ?eld, or frame check sequence. external logic asserts the tlastp signal, accompanied by the last byte of transmit data. 4-2 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the e-10 core stops transmission after the optional autoinsertion of the pad and fcs ?elds and after all data has been transmitted to the network (c). as soon as all transmit status bits are valid, the e-10 core pulses the tdonep pin to indicate that transmission of the frame is complete (d). the tavailp signal is not sampled again until a minimum of 800 ns after the tdonep pulse, to give external logic time to do buffer housekeeping, and to determine whether or not another buffer is ready to be transmitted. figure 4.1 successful transmission d4 tavailp trnsmtp tstartp treaddp tdonep tsxxxx (status) tdatai[7:0] a tlastp b cd d1 d2 d3 dl note: tsecolp, tsidefp, tslcolp, tsmcolp, tsnclbp, tsocolp, and tssqeep tsxxxx consists of the following transmit status signals: ETHERNET-10 (e-10) core technical manual 4-3 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.1.1 transmission aborted by a collision a collision can abort a transmission. the timing for this condition is shown in figure 4.2. the transmission starts normally as shown in (a) and (b). the transmitter transmits the complete preamble and start of frame delimiter while it latches any collision. as soon as the transmitter detects the presence of a collision after the sfd is transmitted (c), it stops requesting additional transmit data bytes, transmits four bytes of alternating ones and zeros and then terminates the transmission without asserting a tdonep pulse (d). after the transmission is terminated, the transmitter starts the backoff algorithm, and then, after deferring, starts a frame retransmission. figure 4.2 transmission aborted by a collision 4.1.1.2 retransmission the host asserts availp to the e-10 core when the host has one or more frames available to be transmitted. a transmission that was aborted by a collision initiates a retransmission. after the backoff algorithm and deferral, the e-10 core starts the retransmission. the e-10 core does not sample the tavailp signal during a retransmission, but the rest of the timing is identical to any normal transmission. the host asserts the tlastp signal to indicate to the core that the tdata[7:0] signals from the host contain the last byte of data in the frame. tavailp trnsmtp tstartp treaddp tdonep tsxxxx (status) tdatai[7:0] a tlastp bcd d1 d2 d3 note: tsecolp, tsidefp, tslcolp, tsmcolp, tsnclbp, tsocolp, and tssqeep tsxxxx consists of the following transmit status signals: 4-4 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.1.3 transmission aborted by tabortp when external logic decides it wants to terminate a transmission (for example, after a transmission data underrun), it can assert the signal tabortp instead of sending a new transmit data byte. the timing for this condition is shown in figure 4.3. the transmission starts normally as shown in (a) and (b). the transmitter terminates the transmission when it detects the assertion of tabortp (c) after transmitting four bytes of alternating ones and zeros (d). this operation is identical to a transmission aborted by a collision. figure 4.3 transmission aborted by tabortp 4.1.1.4 transmission terminated with tfinishp when the signal tfinishp is asserted at the end of a transmission, the mac terminates the transmission with the assertion of tdonep, independent of the detection of a collision. the frame is not retried, even if it normally would have been. assertion of tfinishp can prevent a frame from being retried independent of the normal default conditions. for example, the transmit status pin tslcolp can be connected to tfinishp to prevent frames with a late collision from being retried. tavailp trnsmtp tstartp treaddp tdonep tsxxxx (status) tdatai[7:0] a tabortp b cd d1 d2 xx note: tsecolp, tsidefp, tslcolp, tsmcolp, tsnclbp, tsocolp, and tssqeep tsxxxx consists of the following transmit status signals: ETHERNET-10 (e-10) core technical manual 4-5 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.2 mac reception timing mac reception timing is shown in figure 4.4. when the e-10 core receives a frame from the network, the data recovery digital pll locks onto the transitions of the preamble. phase-lock occurs within six to eight bit times (three bits for intelligent squelch operation and the remainder for the pll to operate). when phase-lock occurs, the e-10 core asserts the rlockedp pin (a). the receiver then goes into receiving mode and asserts rcvngp (b) when the start of frame delimiter is detected (b). the beginning of a reception is marked with an rstartp pulse, which prepares the off-core logic for the arrival of new data. the off-core logic has 800 ns to make a new receive buffer available before new data bytes start arriving (indicated by rbytep pulses). reception is stopped when the end of frame delimiter is detected and the receive status pins (rsxxxx) are valid. section 2.4, receiver status signals, lists the individual receive status pins. the rdonep pulse indicates to external logic that the received frame is complete (c). figure 4.4 successful reception rlockedp rcvngp rstartp rdatao[7:0] rcleanp rsxxxx (status) rdonep a rbytep b c dl-1 dl d1 d2 d3 note: rsdrblep, rsfcsep, rsmatip, rsmatmp and rspllep rsxxxx consists of the following transmit status signals: 4-6 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.2.1 reception with no individual address filter match figure 4.5 shows the timing of the address ?lters during reception. packet reception begins at (a). when all address ?lters do not match during a reception of a frame from the network (b), the receiver stops transferring received data to the host. when reception stops, the receiver terminates with the assertion of the rcleanp pulse (c). figure 4.5 reception with no individual address filter match rcvngp rstartp rbytep rdonep rsxxxx (status) rcleanp a rdatao[7:0] b c d4 d6 d1 d2 d3 d5 note: rsdrblep, rsfcsep, rsmatip, rsmatmp and rspllep rsxxxx consists of the following transmit status signals: ETHERNET-10 (e-10) core technical manual 4-7 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.2.2 reception with external multicast filter match figure 4.6 shows the external multicast filter match timing. packet reception begins at (a). when multicast is enabled, and a multicast frame is received from the network, the receive engine calculates a nine-bit hash function (mindexo[8:0]) from the 48-bit multicast destination address. the receiver indicates to external logic to either accept or reject the message with the mstartp pulse (b). external logic has until the end of a minimum length frame (51.2 m s from the sfd) to make a decision. when the external logic decides to accept the frame, it asserts the mbitp signal and pulses the mdonep input (c). the receiver now permanently asserts the rsmatmp signal and accepts the rest of the frame, and when the receiver is finished, it asserts the rdonep pulse (d). figure 4.6 reception with external multicast filter match rcvngp rstartp rbytep mstartp mindexo[8:0] a rdatao[7:0] b c d4 d1 d2 d3 d5 mdonep mbitp rsmatmp rdonep d d6 d7 d8 dl dl-1 4-8 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.2.3 reception with no external multicast filter match figure 4.7 shows the no external multicast filter match timing. packet reception begins at (a). a pulse on mstartp (b) indicates to the external logic that a new nine-bit hash function has been computed from the destination address. when the external logic decides to reject the frame, it deasserts the mbitp signal and pulses the mdonep input to indicate to the receiver that it has made the decision (c). the receiver now deasserts the rsmatmp signal and rejects the rest of the frame. when the receiver is finished, the e-10 core pulses the rcleanp pin (d). figure 4.7 reception with no external multicast filter match rcvngp rstartp rbytep mstartp mindexo[8:0] a rdatao[7:0] b c d4 d1 d2 d3 d5 mdonep mbitp rsmatmp rcleanp d d6 d7 ETHERNET-10 (e-10) core technical manual 4-9 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.1.3 endec timing examples of endec timing are shown in figure 4.8 and figure 4.9. the bit times shown in the diagrams are 100 ns in duration. figure 4.8 twisted pair serial output data figure 4.9 twisted pair link integrity pulses 1 0 1 1 0 0 eof (300 ns) idle data p data n preep preen externally combined signal idle pulse idle idle datap datan preep preen externally combined signal 100-ns 4-10 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.2 e-10 clock timing this section explains the e-10 clock, receiver, and transmitter timing. the input clock to the e-10 core is 80 mhz. the duty cycle should have a nominal duty cycle of 50/50, with a worst-case duty cycle of 60/40 because both the low-to high and the high-to-low transitions of this signal are used in the digital phase-locked loop that samples the input data. the mac timing logic divides the 80 mhz down to 20 mhz and 10 mhz. these derived frequencies are available on the e-10 output pins. noninverting buffers have to be put outside of the e-10 core. the outputs of these buffers have to be routed back to the e-10 input pins as shown in figure 4.10. the e-10 core expects all input signals from the host to be synchronous with its own 10-mhz clock rate. this requirement for synchronism dictates that the external logic use the same synchronous 10-mhz clock driver that e-10 uses. if more than one e-10 core resides on the same chip, only the clock drivers from a single e-10 core can drive all clock inputs and the external logic. figure 4.10 e-10 clock buffers because the transmit clock is derived from the 80 mhz input clock, the maximum clock error has to comply with the ieee 802.3 maximum error of 0.01% or 100 ppm. clk20o clk10o clk20i clk10i e-10 core clk20 clk10 clk80 from clock_driver or pll clk80 ETHERNET-10 (e-10) core technical manual 4-11 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.3 multiple core clocking multiple e-10 cores can be used in an asic. this section describes how multiple e-10 core clocking can best be accomplished. 4.3.1 core clocks the e-10 core uses three different clocks: 80 mhz. this clock is used as the primary timing input, and is used in several places, as follows: C clocking the data recovery digital pll C clocking the ethernet signal squelch circuits C generating the lower frequency clocks (20 and 10 mhz) 20 mhz. this clock is used for the manchester encoding. 10 mhz. this main clock drives the mac, endec, and transceiver state machines. the e-10 core does not contain any clock drivers. the designer should add two clock buffers (see figure 4.10) of suf?cient strength to drive all e-10 cores in parallel. the 10- and 20-mhz clock buffers should be driven by the 10- and 20-mhz output pins of only one of the e-10 cores. 4.3.2 80-mhz clock the 80-mhz clock can be generated by a phase-locked loop (pll), which consists of a phase comparator, external loop ?lter, and voltage- controlled oscillator (see figure 4.11). the reference input can be a 10- or 20-mhz clock or can be driven by an on chip 10- or 20-mhz crystal oscillator. generating the 80-mhz clock on the chip reduces the higher frequencies on the printed circuit board and should allow for easier passing of the fcc emissions test. 4-12 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 4.3.3 10- and 20-mhz clocks the 10- and 20-mhz inputs should be synchronized to the 80-mhz input clock. the e-10 core generates 20- and 10-mhz clocks and makes these three signals available on core output pins. the 20- and 10-mhz output pins of only one of the e-10 cores should be used to drive all e-10 cores on the chip. most of the input signals of the e-10 core are synchronous and should be clocked with the same 10-mhz clock as is used by the cores. the 10- and 20-mhz clock buffers should be strong enough to allow for a delay of no more than 9 ns from clk80 input to the clk10 and clk20 inputs. 4.3.4 e-10 testing to allow testing of the e-10 cores, the three clocks used by the cores should be multiplexed with three signals coming directly from the input pins. the e-10 test vectors need direct control over the three test inputs plus the multiplexer control input. the clock multiplexing scheme is shown in figure 4.11. ETHERNET-10 (e-10) core technical manual 4-13 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 4.11 multiple-core clock multiplexing e-10 core #1 e-10 core #2 e-10 core #n clk80i clk20i clk10i clk80i clk20i clk10i clk80i clk20i clk10i clk20o clk10o clk20o clk10o clk20o clk10o clock buffers multiplexers clocks for synchronous interface 10- or 20-mhz external clock clock reference 10- or 20-mhz test_enable test_clk80 test_clk20 test_clk10 loop filter 80-mhz vco phase compare not connected not connected not connected not connected 4-14 functional timing february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. ETHERNET-10 (e-10) core technical manual 5-1 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. chapter 5 speci?cations this chapter provides speci?cations for the e-10 core, including the ac timing as well as input and output loading, driver type, and power consumption. this chapter has three sections: section 5.1, derivation of ac timing and loading section 5.2, ac timing section 5.3, pin summary 5.1 derivation of ac timing and loading every customer that buys a core from lsi logic for incorporation into an asic also receives delay predictor software, which gives you an input loading report so you can plan for buffer strengths that drive core inputs. when you integrate the core into the rest of your logic and run other simulation software, you get a ramptime violation report that indicates if a core output is too heavily loaded. you can then adjust buffering, wire length, and other parameters to eliminate the violation. as a result, there are no speci?c numbers in this chapter for ac timing and loading, because the numbers depend on the technology you use and the design layout. 5.2 ac timing this section gives a list of the signals that must operate properly with respect to the clk10i and clk20o signals. the relationship between the signals is depicted in figure 5.1 and figure 5.2. 5-2 speci?cations february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. the numbers in figure 5.1 and figure 5.2 refer to the ac timing parameters listed in the ?rst column of table 5.1. the core has been veri?ed under worst-case process voltage and ambient temperature. table 5.1 e-10 core ac timing parameters parameter description 1. tfinishp setup to clk10i 2. tfinishp hold from clk10i 3. tavailp setup to clk10i 4. tavailp hold from clk10i 5. tdatai[7:0] setup to clk10i 6. tdatai[7:0] hold from clk10i 7. tabortp setup to clk10i 8. tabortp hold from clk10i 9. tlastp setup to clk10i 10. tlastp hold from clk10i 11. renabp setup to clk10i 12. renabp hold from clk10i 13. mdonep setup to clk10i 14. mdonep hold from clk10i 15. mbitp setup to clk10i 16. mbitp hold from clk10i 17. tstartp delay from clk10i 18. tdonep delay from clk10i 19. treaddp delay from clk10i 20. trnsmtp delay from clk10i 21. rstartp delay from clk10i ETHERNET-10 (e-10) core technical manual 5-3 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 22. rdonep delay from clk10i 23. rcleanp delay from clk10i 24. rbytep delay from clk10i 25. rdatao[7:0] delay from clk10i 26. rcvngp delay from clk10i 27. rlockedp delay from clk10i 28. datap delay from clk20o 29. datan delay from clk20o 30. preep delay from clk20o 31. preen delay from clk20o 32. lpassp delay from clk10i 33. lpbadp delay from clk10i 34. colloutp delay from clk10i 35. mstartp delay from clk10i 36. mindexo[8:0] delay from clk10i 37. resetn pulse width 38. resetn low before clk10i rise 39. resetn high before clk10i rise table 5.1 (cont.) e-10 core ac timing parameters parameter description 5-4 speci?cations february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. figure 5.1 e-10 core setup and hold timing diagram figure 5.2 e-10 core reset timing diagram 5.3 pin summary table 5.2 summarizes the e-10 core input and output signals. the table provides the signal names and types for both outputs and inputs. 1, 3, 5, 7, 9, 11, 13, 15 2, 4, 6, 8, 10, 12, 14, 16 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 32, 33, 34, 35, 36 clk10i 28, 29, 30, 31 clk20o inputs valid outputs valid outputs valid 37 38 39 clk10o resetn ETHERNET-10 (e-10) core technical manual 5-5 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. table 5.2 e-10 pin summary mnemonic description type active clk80i 80-mhz clock input C clk10i 10-mhz clock input C clk20i 20-mhz clock input C clk10o 10-mhz clock output C clk20o 20-mhz clock output C collinn negative collision threshold input C collinp positive collision threshold input C colloutp transmit collision output high datai data input from network input C datap positive data output C datan negative data output C datat p p ositive data threshold input C datat n negative data threshold input C driveenn drive enable output low duplexp full duplex select input high fastestn fast test input low lcorpp link correct polarity input high lforcep force link input high loopbkp loopback enable input high lpassp link pass output high lpbadp link polarity bad output high mbitp multicast hash table bit input high mdonep multicast filter done input high (sheet 1 of 3) 5-6 speci?cations february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. mindexo[8:0] multicast hash function output C mstartp multicast filter start output high noad- dri[47:0] node address input C preep positive data pre-emphasis output C preen negative data pre-emphasis output C rbytep received byte output high rcleanp receiver cleanup output high rcvngp receiving output high rdatao[7:0] received data output C rdonep receiver done output high renabp receive enable input high resetn reset input low rlockedp receiver locked output output high rmcenp receive multicast enable input high rpmenp receive promiscuous mode enable input high rsdrblep receive status dribble bits output high rsfcsep receive status frame check sequence error output high rsmatip receive status match individual address output high rsmatmp receive status match multicast address output high rspllep receive status phase-locked loop error output high rstartp receiver start output high rsnoopenp receiver lookback enable input high selio 4-wire/8-wire mixed signal cell select input C table 5.2 (cont.) e-10 pin summary mnemonic description type active (sheet 2 of 3) ETHERNET-10 (e-10) core technical manual 5-7 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. tabortp transmit abort input high tavailp transmitter packet available input high tctri[3:0] transmit control input C tdatai[7:0] transmit data input C tdonep transmit done output high testse scan enable input high testsi scan input input C testso scan output output C test1n fast test input low test2n reset b input low tfinishp transmit finish input high tlastp transmit last byte input high tmode test mode input high tp/aui twisted-pair/aui select input C treaddp transmitter read control output high trnsmtp transmitting output high tsecolp transmit status excessive collisions output high tsidefp transmit status initially deferred output high tslcolp transmit status late collision output high tsmcolp transmit status multiple collision output high tsnclbp transmit status no carrier loopback output high tsocolp transmit status one collision output high tssqeep transmit status sqe error output high tstartp transmit start output high table 5.2 (cont.) e-10 pin summary mnemonic description type active (sheet 3 of 3) 5-8 speci?cations february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. ETHERNET-10 (e-10) core technical manual a-1 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. appendix a glossary address filtering (individual, multicast, promiscuous) C address ?ltering is the process the e-10 core performs to match a destination address within a received frame with an address derived at the receiving station. three common types of address ?ltering are: individualthe ?rst bit of an individual address is a zero. the incoming destination address is compared with the data from the individual address pins. when all 48 bits match and the receiver is enabled, the address ?lter passes. multicastthe ?rst bit of an multicast address is a one. when the destination address bits that are received in the frame contain a multicast address, the e-10 core uses its built-in fcs generator to compute a nine-bit polynomial (the nine msbs of the 32-bit fcs generator) from the incoming address. the value of this polynomial can be used as an index into an external multicast ?lter hash table. external logic can decide to either accept or reject the incoming frame. the external logic enables the multicast address ?lter. promiscuouswhen the external logic asserts the individual address promiscuous mode enable pin (rpmen) high and the destination address is an individual address, the address ?lter always passes, and the incoming frame is received. attachment unit interface (aui) C the aui is the interface between the medium attachment unit (mau) and the data terminal equipment (dte) device or repeater. a typical aui interface consists of a 15-pin d connector. backoff C in ieee 802.3 networks, backoff occurs when two or more nodes attempt a transmission and collide. the function of stopping transmission, and waiting a speci?ed random time before retrying the transmission is considered backoff. in ieee 802.3 networks a truncated binary exponential backoff algorithm is employed. a-2 glossary february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. coaxial cable C coaxial cable is a transmission medium with a central copper-wire conductor surrounded by concentric layers of plastic/polyvinyl chloride, aluminum or aluminized mylar and a copper tube that acts as an insulator (ground) and source of shielding from electromagnetic and radio frequency interference (cmi/rfi). two types of coaxial cable known as thick and thin for their respective diametersare used in ethernet data transmissions. collision C when an ethernet station is operating in the aui mode, it can sense a change in the energy level of the communication channel and interpret the phenomenon as a collision. a collision is caused by two stations attempting to transmit at the same time. collision detection C collision detection is the ability of a transmitting node on an ethernet lan to sense a change in the energy level of the channel and to interpret the phenomenon as a collision crc (cyclic redundancy check) C crc is a basic error-checking mechanism for link-level data transmission; a characteristic link-level feature of (typically) bit-oriented data communications protocols. the data integrity of a received frame or packet is checked via a polynomial algorithm based on the content of the frame and then matched with the result that is performed by the sender and included in a (most often, 16-bit) ?eld appended to the frame. csma/cd (carrier sense multiple access with collision detection) C csma/cd is a lan protocol access method where the nodes are attached to a cable. when a node transmits data onto the network and raises the carrier, the remaining nodes detect the carrier (carrier sense) and listen for the information to detect if it is intended for them. the nodes have network access (multiple access) and can send if no other transmission is taking place. if two nodes attempt to send simultaneously, a collision takes place (collision detection) and both nodes must retry at random intervals. data recovery C the data sent over an ethernet lan is manchester- encoded and must be recovered by the receiving station. in the e-10 core, a digital phase-locked loop recovers the data through a sampling process and has the necessary elasticity to allow for the bit drift that occurs over lengthy frame sizes. ETHERNET-10 (e-10) core technical manual a-3 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. dribble bit C a dribble bit is a bit that is extra and occurs when, at the end of a frame, less than a complete byte is received. it is possible to have from one to seven dribble bits at the end of a frame if a complete byte is not received. dropout error C a dropout error occurs when the carrier on a transmission channel stops due to a broken or missing cable. elasticity C elasticity is a measure of the tolerance of the phase-locked loop to the cumulative bit shift due to small differences in the free running clock oscillator frequencies of the transmitting source and receiving destination. end-of-frame delimiter C an end-of-frame delimiter is a series of three bits of ones at the end of a frame that are not manchester-encoded; that is, they are non-return-to-zero bits that do not contain a transition in the middle of the bit time. the purpose of the end-of-frame delimiter is to cause the pll at the receiving station to lose lock so the host can be noti?ed that the frame has ended. when a receiving node detects a bit that is not manchester-encoded, it considers the previous four bytes to be the fcs. endec C endec is short for encoder/decoder and is a functional block within network adapters that performs two basic functions. first, this function encodes the data from the controller to be transmitted over the network. second, it decodes the data on the network to a form suitable for the network controller chip. in the case of ethernet, the endec converts nrz controller data to manchester data (and back again). ethernet local area network (lan) C an ethernet lan is a branching broadcast communications system for carrying digital data packets among locally distributed computing stations. ethernet is a 10 mbit/s baseband, local area network that has evolved into the ieee 802.3 speci?cation and is de?ned by a data-link protocol that speci?es how data is placed on and retrieved from a common transmission medium. ethernet is used as the underlying transport vehicle by several upper level protocols, including tcp/ip and xerox network system (xns). see ieee 802.3. a-4 glossary february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. frame C an ethernet frame contains the following eight ?elds: preamble start-of-frame delimiter destination address source address length data pad (if necessary) frame check sequence frame check sequence (fcs) C the ethernet transmit and receive algorithm uses the standard ieee 802.3 four-byte frame check sequence (fcs) ?eld to ensure data integrity. during data transmission, the e-10 core uses a 32-bit linear feedback shift register (lfsr) to compute the value that will be sent in the fcs ?eld. the fcs value is a function of the content of the source address, destination address, length, data, and pad ?elds. on data reception, the e-10 core preloads the lfsr with all ones and updates this value with each byte received, including the received fcs. if the ?nal value in the lfsr does not match a predetermined value after all bytes including the fcs are received, the e-10 core ?ags an fcs error. heartbeat C in ieee 802.3 networks, a heartbeat is a short burst of collision signal that is transmitted from the mau to the dte after every packet. see signal quality error (sqe) test. hub C the e-10 core operating in 10base-t mode uses a hub to concentrate connections to multiple terminals. hubs come in various sizes, with 4-port, 8-port, and 12-port being the most common. the number of ports indicates the number of terminals that can be connected to the hub. most hubs have built-in transceivers and network management features. hubs are mainly used in star topology lans. the e-10 core is speci?cally designed for multiple-core integration, especially for hub-on-a-chip implementations. ETHERNET-10 (e-10) core technical manual a-5 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. ieee 802.3 C ieee 802.3 is a standard set by the ieee for csma/cd network protocol, which is a physical layer de?nition including speci?cations for cabling in addition to transmitting data and controlling cable access. see ethernet lan. jam C in ieee 802.3 networks, when a collision occurs the colliding nodes ensure that the collision is seen by the entire network by continuing to transmit for a minimum time during a collision. this occurrence is known as jamming. jitter C jitter is the slight movement of a transmission signal in time or phase that can introduce errors and loss of synchronization in high- speed synchronous communications. lan (local area network) C a lan is a communications system linking computers together to form a network whose dimensions typically are less than ?ve kilometers. transmissions within a local area network generally are digital, carrying data among stations at rates usually above one megabit per second. a lan is an assembly of computing resources such as microcomputers (for example, pcs), printers, minicomputers and mainframes linked by a common transmission medium, including coaxial cable or twisted-pair wiring. link failure C in the twisted-pair mode, a link failure can be caused by a twisted-pair transceiver failure or by a broken twisted-pair receive cable. a link failure occurs when there are eight consecutive missing link integrity pulses. link integrity pulses C the e-10 core monitors link integrity pulses, which may be sent on a regular basis from any other device on the network when the channel is idle. the purpose of the pulses is to ensure that the channel is functional even in the absence of active data. the link integrity pulses should be positive-going pulses spaced approximately 50 milliseconds apart. link polarity detection/correction C link integrity pulses should be positive-going pulses. if they are not, it is an indication that the wiring is inverted. the e-10 core can optionally, under control of the host, invert the data on the receive pair when it detects that eight consecutive link integrity pulses have been received with inverted polarity. a-6 glossary february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. lock time C lock time is the amount of time it takes the receiver phase- locked loop to achieve phase lock with an input signal, which may be either data bits or preamble bits. it takes approximately six to eight bits for the e-10 digital phase-locked loop circuit to achieve lock. three bits are required for the smart squelch operation and the remaining bits are required for the pll to operate. loopback C when the e-10 core is in loopback mode, the transmitter output is fed back to the receiver input inside the chip. loopback mode allows testing of the e-10 transmitter and receiver up to but not including the off-core transceivers under program control without the need of an external loopback connector. loopback is applicable to both the aui and twisted-pair modes. another loopback mode is known as lookback. when the e-10 core is in lookback mode, all transmitted frames are routed back through the receiver. operation is similar to that of normal loopback described in the previous paragraph except that the phase-locked loop is bypassed. mac (media access control) C the data link sublayer that is responsible for transferring data to and from the physical layer. manchester encoding/decoding C a manchester-encoded bit contains a transition (either high-to-low or low-to-high) in the center of the bit time. having a transition every bit time allows a phase-locked loop at a receiving station to maintain lock and extract both data and clock from the waveform. with manchester encoding, each bit is divided into two complementary halves. a low-to-high voltage transition in the middle of the bit period designates a binary one, while a high-to-low transition represents a binary zero. mau (media attachment unit) C an mau is the physical and electrical component that provides the means of attaching a terminal to a local area network medium. multicast hash function C see address ?ltering (multicast). packet C a packet is data sent in the data ?eld of an ethernet frame. ETHERNET-10 (e-10) core technical manual a-7 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. phase-locked loop circuit C a phase-locked loop circuit operates from a local free-running oscillator and is able to achieve and maintain phase and frequency with a signal received from a source that is operating on a different free-running oscillator. the purpose of a phase- locked loop is to provide a clock source that is synchronous with data that is derived from a different clock source. such a circuit is used commonly in telecommunications systems where data is transmitted without an accompanying clock. pre-emphasis C the purpose of pre-emphasis is to increase the amplitude of the higher frequencies in an output signal. data pre-emphasis guarantees that an ethernet system operating twisted-pair mode can drive signals properly at 10 mbit/s on cable up to 100 meters long. router C a router is similar to a bridge but has the ability to connect networks at the osi network level, as shown in figure a.1. figure a.1 router osi interconnect level a router is an intelligent device that plans the most ef?cient route for data to move between networks. routers generally have the ability to recover lost data packets. the end user must address the router to send data through it. routers are slower in the transfer of data than bridges and are more expensive to purchase. for this reason, routers are not used to connect lans (although it is possible) but are more commonly used to connect lans to wide area networks. application presentation session transport network physical data link mac sublevel llc sublevel application presentation session transport network physical data link router source: in-stat a-8 glossary february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. runt packet C in ieee 802.3 networks, a runt packet is a special case of a fragment packet where the length of the packet is less than 512 bit times. signal quality error (sqe) test C the signal quality error (sqe) test is a self-test feature supported in the mau that is invoked after the end of each transmission by the station. when enabled, the sqe test consists of a 10-mhz burst and starts six to sixteen bit times (0.6 m sto 1.6 m s) after the last transition of the transmitted signal and lasts for a duration of ?ve to 15 bit times. this test is an indication to the station that the mau has recognized the end of the transmission and the mau collision circuitry is intact and operational. slot time C a slot time is 512 bit times (51.2 m s), and is the time it takes to ?ll up an ethernet cable with data. in aui mode, if the receive circuitry of a station does not detect a carrier within one slot time from the initiation of transmission (preamble start), it is an indication of trouble on the cable. smart receive squelch C an intelligent (smart) receive squelch is implemented on the receiver differential inputs to ensure that impulse noise on the receive inputs is not mistaken for a valid signal. the smart squelch logic uses a combination of amplitude and timing measurements to determine the validity of data. sqe burst (heartbeat) C see signal quality error (sqe) test. start of frame delimiter (sfd) C the eight-bit start of frame delimiter ?eld follows the seven-octet preamble at the beginning of a frame and contains the 10101011 2 bit pattern. this pattern allows synchronization of the data received in the rest of the frame. tracking speed C tracking speed refers to the speed with which a pll responds to changes in the incoming signal. in the e-10 core, when ?rst attempting to lock on to an oncoming data stream (during the ?rst 4.8 m s), the pll looks every 16 bits (1.6 m s) to see if a bit transition is occurring in the center of the sampling window. after the ?rst 4.8 m s, the pll maintains a window of 64 bits (6.4 m s) for ?nding a transition. ETHERNET-10 (e-10) core technical manual a-9 february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. transceiver C a transceiver is a combined transmitter and receiver and is an essential element of all lan networks. when an ethernet lan operates in the 10base-2 or 10base-5 mode, the transceivers are generally located in the mau and connect directly to the coaxial cable. in the twisted-pair mode, the transceivers are generally located in the data terminal equipment and connect directly to the twisted-pair cable. transmit carrier loopback C transmit carrier loopback occurs in the aui mode. when a station transmits onto the wire, it should detect its own activity on the line within 512 bit times (51.2 m s), which is the maximum amount of time to ?ll the wire under normal circumstances. transmit carrier loopback error C transmit carrier loopback error occurs when a station does not detect its own activity on the line within 512 bit times (51.2 m s). transmit carrier dropout error C a transmit carrier dropout error occurs when the carrier on a transmission channel stops due to a broken or missing cable, or bad transceivers. twisted-pair transmission system C in 10base-t terminology, this term refers to the twisted-pair wire link and its two attached maus. twisted-pair wire C twisted-pair wire is a cable comprised of two 18 to 24 awg (american wire gauge) solid copper strands twisted around each other. the twisting provides a measure of protection from electromagnetic and radio-frequency interference (emi/rfi). two types are available: shielded and unshielded. the former is wrapped inside a metallic sheath that provides protection from emi/rfi. the latter, also known as telephone wire, is covered with plastic or pvc, which provides no protection from emi/rfi. 10base-2 C 10base-2 is the ieee 802.3 physical layer standard for thin wire ethernet (sometimes called cheapernet). this standard uses rg58 standard coaxial cable. 10base2 stands for: 10 = 10 mbit/s data rate, base = baseband, 2 = 185 meter segment length. 10base-5 C 10base-5 is the ieee 802.3 physical layer standard for thick cable ethernet, utilizing thick double shielded coaxial cable. 10base-5 stands for: 10 = 10 mbit/s data rate, base = baseband, 5 = 500 meters segment length. a-10 glossary february 1997 - rev. a copyright ? 1996, 1997 by lsi logic corporation. all rights reserved. 10base-f C 10base-f is the ieee 802.3 physical layer standard for ?ber-based ethernet. 10base-f stands for; 10 = 10 mbit/s data rate, base = baseband, f= ?ber. 10base-t C 10base-t is the ieee 802.3 physical layer standard for the new twisted-pair ethernet in a star topology. 10base-t stands for; 10 = 10 mbit/s data rate, base = baseband, t = twisted-pair over 100 meters nominal segment length. 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