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dual channel line receiver hermetically sealed optocoupler technical data hcpl-1930 hcpl-1931 hcpl-193k 5962-89572 caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the hcpl-193x devices are dual channel, hermetically sealed, high cmr, line receiver optocoup- lers. the products are capable of operation and storage over the full military temperature range and can be purchased as either a standard product or with full mil-prf-38534 class level h or k testing, or from the dscc standard microcircuit drawing (smd) 5962-89572. this is a sixteen pin dip which may be purchased with a variety of lead bend and plating options. see selection guide table for details. standard microcircuit drawing (smd) parts are available for each lead style. functional diagram truth table features ? dual marked with device part number and dscc standard microcircuit drawing ? manufactured and tested on a mil-prf-38534 certified line ? qml-38534, class h and class k ? hermetically sealed 16-pin dual in-line package ? performance guaranteed over -55 c to +125 c ? high speed C 10 mb/s ? accepts a broad range of drive conditions ? adaptive line termination included ? internal shield provides excellent common mode rejection ? external base lead allows "led peaking" and led current adjustment ? 1500 vdc withstand test voltage ? high radiation immunity ? hcpl-2602 function compatibility ? reliability data available applications ? military and space ? high reliability systems ? isolated line receiver ? simplex/multiplex data transmission ? computer-peripheral interface ? microprocessor system interface ? harsh environmental environments ? digital isolation for a/d, d/a conversion ? current sensing ? instrument input/output isolation ? ground loop elimination ? pulse transformer replacement the connection of a 0.1 m f bypass capacitor between pins 15 and 10 is recommended.
2 dc specifications are compatible with ttl logic and are guaranteed from -55 c to +125 c allowing trouble-free interfacing with digital logic circuits. an input current of 10 ma will sink a six gate fan-out (ttl) at the output with a typical propagation delay from input to output of only 45 nsec. all devices are manufactured and tested on a mil-prf-38534 certified line and are included in the dscc qualified manufac- turers list qml-38534 for hybrid microcircuits. each unit contains two indepen- dent channels, consisting of a gaasp light emitting diode, an input current regulator, and an integrated high gain photon detector. the input regulator serves as a line termination for line receiver applications. it clamps the line voltage and regulates the led current so line reflections do not interfere with circuit performance. the regulator allows a typical led current of 12.5 ma before it starts to shunt excess current. the output of the detector ic is an open collector schottky clamped transistor. an enable input gates the detector. the internal detector shield provides a guaranteed common mode transient immunity specifi- cation of +1000 v/ m sec. selection guideCpackage styles and lead configuration options agilent part # and options commercial hcpl-1930 mil-prf-38534 class h hcpl-1931 mil-prf-38534 class k hcpl-193k standard lead finish gold solder dipped option #200 butt joint/gold plate option #100 gull wing/soldered option #300 crew cut/gold plate option #600 class h smd part # prescript for all below 5962- either gold or soldered 8957201ex gold plate 8957201ec solder dipped 8957201ea butt joint/gold plate 8957201yc butt joint/soldered 8957201ya gull wing/soldered 8957201xa crew cut/gold plate available crew cut/soldered available class k smd part # prescript for all below 5962- either gold or soldered 8957202kex gold plate 8957202kec solder dipped 8957202kea butt joint/gold plate 8957202kyc butt joint/soldered 8957202kya gull wing/soldered 8957202kxa
3 outline drawings 16 pin dip through hole, 2 channels device marking 4.45 (0.175) max. 20.06 (0.790) 20.83 (0.820) 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 0.89 (0.035) 1.65 (0.065) 8.13 (0.320) max. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) note: dimensions in millimeters (inches). 3.81 (0.150) min. compliance indicator,* date code, suffix (if needed) a qyywwz xxxxxx xxxxxxx xxx xxx 50434 country of mfr. agilent cage code* agilent designator dscc smd* pin one/ esd ident agilent p/n dscc smd* * qualified parts only
4 option description hermetic optocoupler options 100 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this option is available on commercial and hi-rel product. 200 lead finish is solder dipped rather than gold plated. this option is available on commercial and hi-rel product. dscc drawing part numbers contain provisions for lead finish. 300 surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. this option is available on commercial and hi-rel product. this option has solder dipped leads. 600 surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. this option is available on commercial and hi-rel product. contact factory for the availability of this option on dscc part types. note: dimensions in millimeters (inches). 3.81 (0.150) min. 1.14 (0.045) 1.25 (0.049) 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 1.40 (0.055) 1.65 (0.065) 4.57 (0.180) max. 0.51 (0.020) max. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) min. 9.65 (0.380) 9.91 (0.390) 0.20 (0.008) 0.33 (0.013) 5?max. 4.57 (0.180) max.
5 absolute maximum ratings storage temperature ................................................. -65 c to +150 c operating temperature ............................................... -55 c to +125 c lead solder temperature ................................................ 260 c for 10 s 1.6 mm below seating plane forward input current C i i (each channel) ................................. 60 ma 2 reverse input current ................................................................. 60 ma supply voltage C v cc ....................................... 7 v (1 minute maximum) enable input voltage C v e (each channel) ...................................... 5.5 v not to exceed v cc by more than 500 mv output collector current C i o (each channel) ............................. 25 ma output collector power dissipation (each channel) ................... 40 mw output collector voltage C v o (each channel) ................................... 7 v total package power dissipation .............................................. 564 mw input power dissipation (each channel) ................................... 168 mw parameter symbol min. max. units input current, low level i il 0 250 m a input current, high level* i ih 12.5 60 ma supply voltage, output v cc 4.5 5.5 v high level enable voltage v eh 2.0 v cc v low level enable voltage v el 0 0.8 v fan out (@ r l = 4 k w ) n 5 ttl loads operating temperature t a -55 125 c *12.5 ma condition permits at least 20% guardband for optical coupling variation. initial switching threshold is 10 ma or less. recommended operating conditions esd classification (mil-std-883, method 3015) .............................................. ( d ), class 1 schematic a 0.1 m f bypass capacitor must be connected between pins 10 and 15 (see note 1).
6 group a limits sub- parameter symbol test conditions groups min. typ.* max. units fig. note high level output i oh v cc = 5.5 v, v o = 5.5 v 1, 2, 3 20 250 m a3 3 current i i = 250 m a, v e = 2.0 v low level v ol v cc = 5.5 v; i i = 10 ma output voltage v e = 2.0 v, 1, 2, 3 0.3 0.6 v 1 3 i ol (sinking) = 10 ma i i = 10 ma 2.2 2.6 input voltage v i 1, 2, 3 v 2 3 i i = 60 ma 2.35 2.75 input reverse v r i r = 10 ma 1, 2, 3 0.8 1.10 v 3 voltage low level enable i el v cc = 5.5 v, v e = 0.5 v 1, 2, 3 -1.45 -2.0 ma 3 current high level enable v eh 1, 2, 3 2.0 v 3, 12 voltage low level enable v el 1, 2, 3 0.8 v 3 voltage high level i cch v cc = 5.5 v; i i = 0, 1, 2, 3 21 28 ma supply current v e = 0.5 v both channels low level i ccl v cc = 5.5 v; i i = 60 ma, 1, 2, 3 27 36 ma supply current v e = 0.5 v both channels input-output relative humidity = 45% insulation i i-o t = 5 s, 1 1 m a4 leakage current v i-o = 1500 vdc propagation delay 9 55 100 time to high t plh r l = 510 w ; c l = 50 pf, ns 4, 5 3, 5 output level i i = 13 ma,v cc = 5.0 v 10, 11 140 propagation delay 9 60 100 time to low t phl r l = 510 w ; c l = 50 pf, ns 4, 5 3, 6 output level i i = 13 ma, v cc = 5.0 v 10, 11 120 common mode v cm = 50 v (peak), transient |cm h |v o (min.) = 2 v, 9, 10, 11 1000 10,000 v/ m s 8, 9 3, 9, immunity at r l = 510 w ; i i = 0 ma, 14 high output level v cc = 5.0 v common mode v cm = 50 v (peak), transient |cm l |v o (max.) = 0.8 v, 9, 10, 11 1000 10,000 v/ m s 8, 9 3, 10, immunity at r l = 510 w ; i i = 10 ma, 14 low output level v cc = 5.0 v *all typical values are at v cc = 5 v, t a = 25 c. electrical specifications t a = -55 c to 125 c unless otherwise stated. see note 15.
7 parameter symbol typ. units test conditions fig. note resistance (input-output) r i-o 10 12 w v i-o = 500 v dc 3, 13 capacitance (input-output) c i-o 1.7 pf f = 1 mhz 3, 13 input-input insulation i i-i 0.5 na 45% relative humidity, 11 leakage current v i-i = 500 vdc, t = 5 s resistance (input-input) r i-i 10 12 w v i-i = 500 vdc 11 capacitance (input-input) c i-i 0.55 pf f = 1 mhz 11 propagation delay time of enable t elh 35 ns 6, 7 3, 7 from v eh to v el r l = 510 w , c l = 15 pf, propagation delay time of enable t ehl 35 ns i i = 13 ma, v eh = 3 v, v el = 0 v 6, 7 3, 8 from v el to v eh output rise time (10-90%) t r 30 ns 3 r l = 510 w , c l = 15 pf, i i = 13 ma output fall time (90-10%) t f 24 ns 3 input capacitance c i 60 pf f = 1 mhz, v i = 0, 3 pins 1 to 2 or 5 to 6 typical specifications t a = 25 c, v cc = 5 v notes: 1. bypassing of the power supply line is required, with a 0.1 m f ceramic disc capacitor adjacent to each isolator. the power supply bus for the isolators should be separate from the bus for any active loads, otherwise additional bypass capacitance may be needed to suppress regenerative feedback via the power supply. 2. derate linearly at 1.2 ma/ c above t a = 100 c. 3. each channel. 4. device considered a two terminal device: pins 1 through 8 are shorted together, and pins 9 through 16 are shorted together. 5. the t plh propagation delay is measured form the 6.5 ma point on the trailing edge of the input pulse to the 1.5 v point on the trailing edge of the output pulse. 6. the t phl propagation delay is measured from the 6.5 ma point on the leading edge of the input pulse to the 1.5 v point on the leading edge of the output pulse. 7. the t elh enable propagation delay is measured from the 1.5 v point on the trailing edge of the enable input pulse to the 1.5 v point on the trailing edge of the output pulse. 8. the t ehl enable propagation delay is measured from the 1.5 v point on the leading edge of the enable input pulse to the 1.5 v point on the leading edge of the output pulse. 9. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state, i.e. v out > 2.0 v. 10. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state, i.e. v out < 0.8 v. 11. measured between adjacent input leads shorted together, i.e. between 1, 2 and 4 shorted together and pins 5, 6 and 8 shorted together. 12. no external pull up is required for a high logic state on the enable input. 13. measured between pins 1 and 2 or 5 and 6 shorted together, and pins 10 through 15 shorted together. 14. parameters shall be tested as part of device initial characterization and after process changes. parameters shall be guaranteed to the limits specified for all lots not specifically tested. 15. standard parts receive 100% testing at 25 c (subgroups 1 and 9). hi-rel and smd parts receive 100% testing at 25, 125, and -55 c (subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
8 figure 3. high level output current vs. temperature. figure 2. input characteristics. figure 1. input-output characteristics. figure 4. propagation delay vs. temperature. figure 5. test circuit for t phl and t plh . figure 6. enable propagation delay vs. temperature. figure 7. test circuit for t ehl and t elh .
9 1 3 2 4 510 w 5 6 7 8 16 14 15 13 12 11 10 9 gnd v cc 5 v output v o monitoring node 0.01 ? bypass v cm pulse gen. + v in i in a b figure 10. burn in circuit. 100 w 100 w 200 w 200 w v in +5.0 v 0.01 ? v cc +5.5 v v out +2.6 v t a = +125 ? + conditions: i i = 30 ma i o = 10 ma v cc = 5.5 v 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 figure 9. test circuit for common mode transient immunity and typical waveforms. figure 8. typical common mode transient immunity.
10 application circuits* figure a 1 . polarity non-reversing. figure a 2 . polarity reversing, split phase. hcpl-193x hcpl-193x
11 mil-prf-38534 class h, class k, and dscc smd test program agilent technologies hi-rel optocouplers are in compliance with mil-prf-38534 class h and k. class h and class k devices are also in compliance with dscc drawing 5962-89572. testing consists of 100% screen- ing and quality conformance inspection to mil-prf-38534. figure a 3 . flop-flop configurations.
www.semiconductor.agilent.com data subject to change. copyright ? 2000 agilent technologies obsoletes 5967-5809e 5968-9401e (4/00)

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