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order number: 314822-03 december 2007 numonyx? serial flash memory (s33) 16-, 32-, and 64-mbit datasheet product features ? architecture ? spi-compatible serial interface ? eight 8-kbyte parameter blocks; configurable as one 64-kbyte main memory sector ? 64-kbyte main memory sectors ? 16 mbit (31 sectors) ? 32 mbit (63 sectors) ? 64 mbit (127 sectors) ? voltage and power ? vcc = 2.7 v to 3.6 v ? standby current: 15 a (typ) ? read current: 3 ma (typ) at 33.3 mhz; 6 ma (typ) at 68 mhz ? performance ? 68-mhz fast read; 33.3 mhz standard read ? 256-byte program buffer ? software ? driver and file manager ? security ? one-time programmable space ? 64 unique factory device identifier bits ? 64 user-programmable otp bits ? additional 3920 user-programmable otp bits ? quality and reliability ? operating temperature: -40 c to +85 c ? 100k minimum erase cycles per sector (block) ? 0.13 m etox? viii process ? density and packaging ? 16, -32, -64-mbit densities in soic-16 package ? 16-mbit density in soic-8 package ? industry standard packaging and pinout
datasheet december 2007 2 order number: 314822-03 legal lines and disc laim ers legal lines and disc laim ers information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear f acility applications. numonyx b.v. may make changes to specifications and product descriptions at any time, without notice. numonyx b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights tha t relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implie d, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx, the numonyx logo, and strataflash are trademarks or registered trademarks of numonyx b.v. or its subsidiaries in other countries. *other names and brands may be claimed as the property of others. copyright ? 2007, numonyx b.v., all rights reserved.
december 2007 datasheet order number: 314822-03 3 numonyx? serial flash memory (s33) contents 1.0 introduction .............................................................................................................. 6 1.1 nomenclature ..................................................................................................... 6 1.2 acronyms........................................................................................................... 6 1.3 conventions ....................................................................................................... 6 2.0 functional overview .................................................................................................. 8 2.1 memory maps ..................................................................................................... 8 3.0 package information ............................................................................................... 10 3.1 soic-8 package ................................................................................................ 10 3.2 soic-16 package .............................................................................................. 11 4.0 pinouts and signal descriptions ............................................................................... 12 4.1 soic-8 pinout (16-mbit)..................................................................................... 12 4.2 soic-16 package pinout..................................................................................... 12 4.3 signal descriptions ............................................................................................ 13 5.0 maximum ratings and operating conditions ............................................................ 14 5.1 absolute maximum ratings................................................................................. 14 5.2 operating conditions ......................................................................................... 14 5.3 power supply.................................................................................................... 14 5.3.1 power-up/down characteristics................................................................ 14 5.3.2 power supply decoupling ........................................................................ 15 6.0 electrical characteristics ......................................................................................... 16 6.1 dc current specifications ................................................................................... 16 6.2 dc voltage specifications ................................................................................... 16 6.3 capacitance...................................................................................................... 17 7.0 ac characteristics ................................................................................................... 18 7.1 ac test conditions ............................................................................................ 18 7.2 ac timing characteristics ................................................................................... 19 7.2.1 serial input characteristics ...................................................................... 19 7.2.2 write protect setup and hold timing ......................................................... 20 7.2.3 output timing........................................................................................ 20 7.2.4 hold timing ........................................................................................... 21 7.2.5 other timings ........................................................................................ 22 8.0 device operations ................................................................................................... 23 8.1 spi bus operations............................................................................................ 23 8.1.1 spi modes ............................................................................................. 23 8.1.2 the hold state ....................................................................................... 24 8.2 spi command set ............................................................................................. 25 8.2.1 write spi sr command (01h) .................................................................. 26 8.2.2 page program command (02h) ................................................................ 26 8.2.3 read data bytes command (03h)............................................................. 27 8.2.4 write disable command (04h) ................................................................. 27 8.2.5 read spi sr command (05h) .................................................................. 27 8.2.6 write enable command (06h) .................................................................. 27 8.2.7 fast read data bytes command (0bh) ...................................................... 28 8.2.8 clear sr fail flags command (30h) .......................................................... 28 8.2.9 parameter block erase command (40h) .................................................... 28 8.2.10 otp program command (42h) ................................................................. 29 8.2.11 read otp data bytes command (4bh) ...................................................... 29 8.2.12 read id command (9fh)......................................................................... 29
numonyx? serial flash memory (s33) datasheet december 2007 4 order number: 314822-03 8.2.13 release from dpd command (abh) ...........................................................29 8.2.14 deep power-down command (b9h) ..........................................................29 8.2.15 bulk erase command (c7h) .....................................................................29 8.2.16 sector erase command (d8h) ..................................................................30 8.3 status register definition ...................................................................................30 8.3.1 main memory protection ..........................................................................31 8.4 spi instruction cycle examples............................................................................32 8.4.1 fast read ..............................................................................................32 8.4.2 page program ........................................................................................33 8.4.3 write enable ..........................................................................................34 9.0 security features .....................................................................................................36 9.1 otp memory space ............................................................................................36 9.1.1 programming otp address space .............................................................36 9.1.2 reading otp data...................................................................................36 9.1.3 lock protection registers .........................................................................36 10.0 numonyx? serial flash memory (s33) id codes ......................................................38 a write state machine (wsm) .....................................................................................39 b ordering information ...............................................................................................41
december 2007 datasheet order number: 314822-03 5 numonyx? serial flash memory (s33) revision history date revision description august 2006 001 initial release january 2007 002 revised soic-8 pinout, 16-mbit ( figure 3, ?soic-8 pinout (16-mbit)? on page 12 ) in section 4.0, ?pinouts and signal descriptions? on page 12 . november 2007 03 applied numonyx template.
numonyx? serial flash memory (s33) datasheet december 2007 6 order number: 314822-03 1.0 introduction this document describes the numonyx? serial flash memory (s33) device features, operation, and specifications. the s33 device provides superior performanc e with enhanced security features, taking advantage of the high quality and reliability of the nor-based intel 0.13 m etox* viii process technology. offered in 16-mbit, 32-mbit, and 64-mbit densities, the s33 device is hardware and software compatible with existing industry offerings to ensure ease of design. the s33 device takes advantage of more than one billion units of flash manufacturing experience and is ideal for code and data applications where simplified interface and low cost are the primary requirements. ex amples include pcs and notebooks, wlan and dsl cards and routers, printers, tvs, dvd/cd players and recorders, and other consumer electronic devices. 1.1 nomenclature 1.2 acronyms 1.3 conventions block: a group of flash cells that share common erase circuitry and erase simultaneously. for serial flash devices, blocks are more commonly referred to as sectors. cleared: indicates a logic zero (0). page: a 256-byte main memory segment that is aligned to a 256-byte boundary. parameter block: an 8-kb memory segment that can be erased independently. program: a data write operation to the flash array. sector: a single 64-kb main block, or all eight of the 8-kb parameter blocks combined. set: indicates a logic one (1). lsb: least significant bit msb: most significant bit otp: one-time programmable pr: protection register prd: protection register data rfu: reserved for future use sr: status register wel: write enable latch wsm: write state machine 0x: hexadecimal prefix 0b: binary prefix k: 1,000 m: 1,000,000 nibble: 4 bits
december 2007 datasheet order number: 314822-03 7 numonyx? serial flash memory (s33) byte: 8 bits word: 16 bits kword: 1,024 words kb: 1,024 bits kb: 1,024 bytes mb: 1,048,576 bits mb: 1,048,576 bytes brackets: square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e. a[21:1], sr[4,1] and d[15:0]). 00ffh: denotes 16-bit hexadecimal numbers 00ff 00ffh: denotes 32-bit hexadecimal numbers
numonyx? serial flash memory (s33) datasheet december 2007 8 order number: 314822-03 2.0 functional overview this section provides an overview of the features and capabilities of the name of product. the s33 device is available in 16-, 32-, and 64-mbit densities with a common spi interface. the spi interface consists of 8 pins. six of these pins are signals; the other two are vcc and ground. the s33 device contains eight 8-kbyte parameter blocks and up to 127 64-kbyte main memory sectors. the eight 8-kbyte parameter blocks can be treated as one 64-kbyte main memory sector. the s33 device includes new security features. two 8-byte, thirty 16-byte, and one 10- byte individually-lockable otp protection registers can support multiple uses, including unique flash device identification. a sector erase operation erases one of the device?s 64-kbyte main memory sectors or all eight 8-kbyte parameter blocks in parallel, independent of other memory sectors. a parameter block erase operation erases the specified parameter block; the operation is ignored when the address is outside the parameter block space. each block or memory sector can be independently erased 100,000 times. a bulk erase operation erases the entire chip. each device incorporates a write buffer of 256 bytes (128 words) to allow optimum programming performance. page program operation uses the write buffer to program up to 256-bytes within a 256-byte-aligned main memory region. a given page can be programmed multiple times between erase cycles. 2.1 memory maps table 1: bottom boot memory map (sheet 1 of 2) size (kb) sector memory addressing (hex) memory addressing (hex) memory addressing (hex) 64-mbit 32-mbit 16-mbit 64 127 7f0000 - 7fffff 64 126 7e0000 - 7effff ... ... ... 64 64 400000 - 40ffff 64 63 3f0000 - 3fffff 3f0000 - 3fffff 64 62 3e0000 - 3effff 3e0000 - 3effff ... ... ... ... 64 32 200000 - 20ffff 200000 - 20ffff 64 31 1f0000- 1fffff 1f0000- 1fffff 1f0000- 1fffff 64 30 1e0000 - 1effff 1e0000 - 1effff 1e0000 - 1effff ... ... ... ... ... 64 16 100000 - 10ffff 100000 - 10ffff 100000 - 10ffff 64 15 f0000 - fffff f0000 - fffff f0000 - fffff 64 14 e0000 - effff e0000 - effff e0000 - effff ... ... ... ... ... 64 4 40000 - 4ffff 40000 - 4ffff 40000 - 4ffff
december 2007 datasheet order number: 314822-03 9 numonyx? serial flash memory (s33) 64 3 30000 - 3ffff 30000 - 3ffff 30000 - 3ffff 64 2 20000 - 2ffff 20000 - 2ffff 20000 - 2ffff 64 1 10000 - 1ffff 10000 - 1ffff 10000 - 1ffff 8 0-h e000 - ffff e000 - ffff e000 - ffff 8 0-g c000 - dfff c000 - dfff c000 - dfff 8 0-f a000 - bfff a000 - bfff a000 - bfff 8 0-e 8000 - 9fff 8000 - 9fff 8000 - 9fff 8 0-d 6000 - 7fff 6000 - 7fff 6000 - 7fff 8 0-c 4000 - 5fff 4000 - 5fff 4000 - 5fff 8 0-b 2000 - 3fff 2000 - 3fff 2000 - 3fff 8 0-a 0 - 1fff 0 - 1fff 0 - 1fff table 1: bottom boot memory map (sheet 2 of 2)
numonyx? serial flash memory (s33) datasheet december 2007 10 order number: 314822-03 3.0 package information 3.1 soic-8 package figure 1: soic-8 package drawing and specifications
december 2007 datasheet order number: 314822-03 11 numonyx? serial flash memory (s33) 3.2 soic-16 package figure 2: soic-16 package drawing and specifications
numonyx? serial flash memory (s33) datasheet december 2007 12 order number: 314822-03 4.0 pinouts and signal descriptions the numonyx? serial flash memory (s33) device is available in two package types. the 16-mbit density is supported with soic-8 and soic-16 packages as shown in figure 3 and figure 4 . the 32- and 64-mbit densities are supported by the soic-16 package as shown in figure 4 . 4.1 soic-8 pinout (16-mbit) 4.2 soic-16 package pinout figure 3: soic-8 pinout (16-mbit) figure 4: soic-16 package pinout q s# w# vss hold# vcc c d 18 7 6 5 4 3 2 8 lead soic top view 16 lead soic top view 1 8 7 6 5 4 3 2 hold# s# q nc vcc nc nc nc c vss w# nc d nc nc nc 16 9 10 11 12 13 14 15
december 2007 datasheet order number: 314822-03 13 numonyx? serial flash memory (s33) 4.3 signal descriptions table 2: signal descriptions symbol type name and function cinput spi clock: provides the timing of the spi interface. op codes, addresses, and data are latched in on the rising edge. spi output data transitions after the falling edge. dinput spi data input: shifts all data (including op codes, address bytes, as well as data bytes) into the device. all data is clocked in on the rising edge of ?c?, starting with the msb. the rising edge input applies to modes 0 & 3 as depicted in figure 12, ?supported spi bus operation modes? on page 24 . qoutput spi data output: shifts all data out of the device. all output data is clocked out after the falling edge of ?c?, starting with the msb. the falling edge output applies to modes 0 & 3 as depicted in figure 12, ?supported spi bus operation modes? on page 24 . s# input spi select: falling s# edge triggers command writes to the spi interface. rising s# edge completes (or terminates) the spi command cycle. when s# is high, ?q? is at high-z. hold# input spi hold: internally freezes the synchronization clock and sets ?q? to high-z. to enter the hold condition, s# must be low. refer to section 8.1.2, ?the hold state? on page 24 for details. w# input write protect: enables write protection. refer to table 18 on page 32 for details. vcc power power supply: source voltage. writes to the flash array are inhibited when v cc v lko . operations at invalid v cc should not be attempted. vss power ground: connect to system ground. do not float vss.
numonyx? serial flash memory (s33) datasheet december 2007 14 order number: 314822-03 5.0 maximum ratings and operating conditions 5.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. 5.2 operating conditions warning: operation beyond the ?operating conditions? is not recommended. extended exposure beyond the ?operating conditions? may affect device reliability. 5.3 power supply this section provides an overview of system-level considerations with regards to the flash device. it includes a brief description of power-up, power-down and decoupling design considerations. 5.3.1 power-up/down characteristics the device is protected against accidental block erasure or programming during power transitions. after power-up, a t vsl latency is required before s# can be brought low to issue a command. note: this document contains information available at the time of its release. the specifications are subject to change without notice. verify with your local numonyx sales office that you have the latest datasheet before finalizing a design. table 3: absolute maximum ratings parameter min max unit notes temperature under bias expanded (t a , ambient) ?40 +85 c 4 storage temperature ?65 +125 c ? v cc voltage ?2.0 +5.6 v 1, 2 i sh output short circuit current ? 100 ma 3 notes: 1. voltage is referenced to v ss . during infrequent non-periodic transitions, the voltage potential between v ss and input/ output pins may undershoot to ?2.0 v for periods < 20 ns or overshoot to v ccq (max) + 2.0 v for periods < 20 ns. 2. during infrequent non-periodic transitions, the voltage potential between v cc and the supplies may undershoot to ?2.0 v for periods < 20 ns or v supply (max) + 2.0 v for periods < 20 ns. 3. output is shorted for no more than one second. no more than one output shorted at a time 4. temperature specified is at ambient (t a ) and not the package (t c ). table 5: temperature and vcc operating condition symbol parameter min nom max unit notes t c operating temperature (case) ?40 +25 +85 c 1 v cc v cc supply voltage 2.7 3.0 3.6 v note: 1. temperature specified is at case (t c ) and/or ambient (t a ).
december 2007 datasheet order number: 314822-03 15 numonyx? serial flash memory (s33) 5.3.2 power supply decoupling flash memory devices require careful power supply decoupling. the basic power supply considerations are as follows: 1. standby current levels 2. active current levels 3. transient peaks produced when the device is enabled when the device is accessed, many internal conditions change. circuits within the device enable charge-pumps, and internal logic states change at high speed. all of these internal activities produce transient signals. transient current magnitudes depend on the capacitive and inductive loading at the device output. two-line control and correct de-coupling capacitor selection suppress transient voltage peaks. additionally, for every eight devices used in the system, a 4.7 f electrolytic capacitor should be placed between power and ground close to the devices. the bulk capacitor is meant to overcome voltage droop caused by pcb trace inductance.
numonyx? serial flash memory (s33) datasheet december 2007 16 order number: 314822-03 6.0 electrical characteristics 6.1 dc current specifications 6.2 dc voltage specifications table 6: dc current characteristics symbol parameter typ max unit test conditions notes i li input load current ? 2 av cc = v cc max; v in = v cc or v ss 3 i lo output leakage current ? 2 av cc = v cc max; v in = v cc or v ss ? i ccs v cc standby current 15 70 a s# = v cc ; v in = v cc or v ss 4,6 i dpd v cc deep power-down current 15 70 a s# = v cc ; v in = v cc or v ss 4 i ccr v cc read current 24 ma 20 mhz; no load ? 3 5 33.3 mhz; no load 7 5 8 50 mhz; no load 6 10 68 mhz; no load i ccp page program current 18 25 ma s# = v cc ; 256-byte page 2,5 i cce parameter block erase current 16 45 ma s# = v cc 2.5 sector erase current 16 45 ma s# = v cc 2,5 i ccb bulk erase current 16 45 ma s# = v cc 2.5 notes: 1. all currents are rms unless noted. typical values at typical v cc , t c = +25 c. 2. sampled, not 100% tested. 3. if v in > v cc the input load current increases to 10 a max. 4. i ccs and i dpd is the average current measured over any 5 ms time interval 5 s after a s# de-assertion. 5. i ccp , i cce measured over typical or max times. 6. i ccs will increase substantially if w# or hold# is toggled while in standby mode. 7. i ccr will increase if d is toggled during read. table 7: dc voltage characteristics symbol parameter min max unit test conditions notes v il input low voltage 0 0.3 * v cc v? 1 v ih input high voltage 0.7 * v cc v cc v? 1 v ol output low voltage ? 0.1 v v cc = v cc min i ol = 100 a v oh output high voltage v cc ? 0.1 ? v v cc = v cc min i oh = ?100 a ? v lko v cc lockout voltage 2.0 ? v ? ? note: 1. v il can undershoot to ?1.0 v for periods <2 ns and v ih may overshoot to a maximum of v cc +1.0 v for periods < 2 ns.
december 2007 datasheet order number: 314822-03 17 numonyx? serial flash memory (s33) 6.3 capacitance table 8: device capacitance symbol parameter 1 type max unit condition 2 c in input capacitance 6 8 pf v in = 0.0 v v cc = 0 v ?or? v cc =v cc max c out output capacitance 8 12 pf v out = 0.0 v v cc = 0 v ?or? v cc =v cc max notes: 1. sampled, not 100% tested. 2. t a = +25 c, f = 1 mhz.
numonyx? serial flash memory (s33) datasheet december 2007 18 order number: 314822-03 7.0 ac characteristics 7.1 ac test conditions note: c l includes jig capacitance figure 5: transient equivalent testing load circuit table 9: ac measurement conditions parameter min max unit load capacitance (c l )?30 1 pf input rise and fall times 0.3 3 ns input v il timing reference voltages ? 0.3*vcc v input v ih timing reference voltages 0.7*vcc ? v input drive voltages 0 for v il , vcc for v ih v input timing reference voltages 0.3 v cc to 0.7 v cc v output timing reference voltages v cc /2 v note: 1. output hi-z is defined as the point where data output is no longer driven. device under test c l out
december 2007 datasheet order number: 314822-03 19 numonyx? serial flash memory (s33) 7.2 ac timing characteristics 7.2.1 serial input characteristics table 10: serial input characteristics sym parameter min max unit notes f c clock frequency for all instructions except read d.c. 68.0 mhz ? f r clock frequency for read d.c. 33.3 mhz ? t ch clock high time 7 ? ns 1 t cl clock low time 7 ? ns 1 t clch clock rise time (peak to peak) 0.1 ? v/ns 2, 3,4 t chcl clock fall time (peak to peak) 0.1 ? v/ns 2, 3,4 t chsl s# active setup time (relative to preceding c edge) 5 ? ns ? t slch s# active setup time (relative to subsequent c edge) 5 ? ns ? t chsh s# inactive hold time (relative to c) 5 ? ns ? t shch s# inactive setup time (relative to c) 5 ? ns ? t shsl s# deselect time 100 ? ns ? t dvch data input setup time 2 ? ns ? t chdx data input hold time 5 ? ns ? notes: 1. t ch + t cl must be greater than or equal to 1/f c (max). 2. sampled, not 100% tested. 3. expressed as a slew-rate. ? minimum clock rise/fall times guarantee functionality. clock rise/fall times must fall within the range specified in figure 9, ?ac measurement conditions? on page 18 for compliance to timing specs. figure 6: serial input timing msb lsb tchdx tdvch tshsl tshsl tshch tchsh tslch tchsl c s# d q
numonyx? serial flash memory (s33) datasheet december 2007 20 order number: 314822-03 7.2.2 write protect setup and hold timing 7.2.3 output timing table 11: write protect setup and hold timing sym parameter min max unit notes t whsl w# setup time 20 ? ns 1 t shwl w# hold time 100 ? ns 1 note: 1. only applicable as a constraint for a wrsr instruction when srwd is set to 1. figure 7: write protect setup and hold timing during wrsr when srwd=1 table 12: output timing sym parameter min max unit notes t clqv clock low to output valid (30 pf, 2.7 v to 3.6 v) ? 8 ns ? t clqv clock low to output valid (10 pf, 3.0 v to 3.6 v) ? 6 ns ? t clqx output hold time 0 ? ns ? t shqz output disable time ? 8 ns 1 note: 1. sampled, not 100% tested. figure 8: output timing tshwl twhsl c s# w# lsb out tshqz tclqv tclqx tclqv tclqx tch tch tcl tcl c s# q
december 2007 datasheet order number: 314822-03 21 numonyx? serial flash memory (s33) 7.2.4 hold timing table 13: hold timing sym parameter min max unit notes t chhl hold# assertion hold time (relative to c) 5 ? ns ? t hlch hold# assertion setup time (relative to c) 5 ? ns ? t hlqz hold# assertion to output high-z ? 8 ns 1 t chhh hold# de-assertion hold time (relative to c) 5 ? ns ? t hhch hold# de-assertion setup time (relative to c) 5 ? ns ? t hhqx hold# de-assertion to output low-z ? 8 ns 1 note: 1. sampled, not 100% tested. figure 9: hold timing - standard usage figure 10: hold timing - non-standard usage thhqx thlqz thhch tchhh thlch tchhl c s# q hold# thhqx thlqz thhch tchhh thlch tchhl c s# q hold#
numonyx? serial flash memory (s33) datasheet december 2007 22 order number: 314822-03 7.2.5 other timings d table 14: other timings sym parameter min typ max unit notes t pp page program time ? 1.4 10 ms 1 t bp byte otp program time ? 40 175 s1 t se parameter block erase time (8 kb) ? 0.3 2.5 s 1 sector erase time (64 kb) ? 0.7 4.0 s 1 t be bulk erase time (64 m) ? 89.6 512 s 1 bulk erase time (32 m) ? 44.8 256 s 1 bulk erase time (16 m) ? 22.4 128 s 1 t vsl v cc power valid to s# assertion (low) 60 ? ? s? t rdp release from dpd mode into standby mode 60 ? ? s? figure 11: t vsl power-up timing v cc time v cc(max) v cc(min) t vsl chip selection not allowed v cc time v cc(max) v cc(min) t vsl chip selection not allowed
december 2007 datasheet order number: 314822-03 23 numonyx? serial flash memory (s33) 8.0 device operations this section provides an overview of the numonyx? serial flash memory (s33) device operations. 8.1 spi bus operations the spi instruction cycle begins with a byte-wide op code that is initiated with the falling edge of s#. the 8-bit instruction is latched into "d" (data input), msb first, on the rising edge of "c" (clock). some op codes are followed by an additional address and dummy and/or data bytes, msb first. the number of input instruction bytes depends upon the op code. refer to table 15, ?spi command set? on page 25 for the instruction protocols. address and dummy bytes are input through "d" on the rising "c" edge. depending upon the op code, the data bytes are either input data through "d", or they are output data from "q". on cycles that input data through ?d?, the output signal ?q? is at high-z. for instructions that change the memory co ntents or device configuration (such as a status register write command), the rising s# edge must occur on a whole-byte increment, otherwise the command will be ignored. for read operations, the instruction sequence can be botched (ignored) only if s# is raised before the input sequence is complete. after the required number of input bits is clocked into the device, a data stream is clocked out of "q"; each bit is shifted out after the falling edge of ?c? (msb first). when data is streaming from "q", raising s# will terminate the data stream and bring this output to high-z. the rising s# edge always resets the spi command interpreter and places the output in high-z. it also does one of the following actions: ? terminates the output data stream (read operations) ? kicks off program/erase algorithms ? initiates changes to the sr ? botches an spi command when s# is raised too early (or too late for commands that alter the array or device configuration) ? terminates a command and puts the device in standby mode (not in the case of a program or erase operation) when s# is high and the internal algorithms are completed, the device will go into standby mode. 8.1.1 spi modes this device supports spi bus operations mode 0 and mode 3, as depicted in figure 12, ?supported spi bus operation modes? on page 24 . the difference between the two modes is the default state of the clock signal (c) when the spi bus master is in standby. for mode 0, the ?c? is normally low; for mode 3, ?c? is normally high. for both modes, input data (d) is sampled on the rising edge of ?c?, and output data (q) is updated on the falling edge of ?c.?
numonyx? serial flash memory (s33) datasheet december 2007 24 order number: 314822-03 8.1.2 the hold state the hold# input signal freezes the internal clock (c) without resetting the device's clocking sequence. however, taking hold# to v il does not terminate any program or erase operation that is currently in progress. to enter the hold state, the device must be selected (s# at v il ). the hold state starts on the falling edge of the hold# signal, provided that it coincides with the clock at v il as shown in figure 13 on page 24 . the hold state ends on the rising edge of hold#, provided that it coincides with the spi clock at v il . if the falling hold# edge does not coincide with the clock at v il , the hold state starts after the next falling edge of the clock as shown in figure 14 on page 25 . similarly, if the rising edge does not coincide with the clock at v il , the hold state ends after the next falling edge of the clock. the command sequence will not necessarily botch if s# is raised to v ih while hold# is at v il . raising s# will complete the command sequence, regardless of the state of hold#. if a proper sequence was inputted prior to dropping hold# to v il , the input data stream will be recognized as a valid command sequence. during the hold state, the data output (q) is at high impedance. the clock input and the data input (d) are don't care. figure 12: supported spi bus operation modes data data address address instruction instruction a23 a22 a21 d7 d6 a0 a1 a2 d1 d0 s# c - mode 0 c - mode 3 d q figure 13: hold state ? standard usage hold state hold state standard usage s# c hold#
december 2007 datasheet order number: 314822-03 25 numonyx? serial flash memory (s33) 8.2 spi command set the spi command set is found in ta b l e 1 5 . this table defines the commands (and the op codes) that are supported by the spi interface. all other op codes will be ignored. all commands support frequencies up to 68 mhz except for the read data bytes command (03h). the read data bytes command (03h) supports up to 33.3 mhz. figure 14: hold state ? non-standard usage hold state inactive hold state active hold state hold state non-standard usage delay delay s# c hold# table 15: spi command set (sheet 1 of 2) instruction op code addr bytes dummyb ytes data bytes name and function write spi sr 01h ? ? 1 overwrites sr[7, 4:2] and (bp[2:0] srwd). when w# = v il & srwd = 1, the values of bp[2:0] & srwd cannot be changed. page program 02h 3 ? 1 to 256 programs up to 256 bytes within a 256-byte- aligned main memory region. read data bytes 03h 3 ? 1 to infinite supports up to 33.3 mhz clock. write disable 04h ? ? - clears the wel bit (sr1) read sr 05h ? ? 1 to infinite continuously polls the sr write enable 06h ? ? - sets the wel bit (sr1). fast read data bytes 0bh 3 1 1 to infinite supports up to a 68 mhz clock; protocol uses a dummy byte. clear sr fail flags 30h ? ? ? resets the erase fail flag and the program fail flag (sr5 and sr6, respectively) parameter block erase 40h 3 ? ? erases the specified parameter block; it is ignored when the address is outside parameter block space. otp program 42h 3 ? 1 programs one byte of data in the otp memory space. read otp data bytes 4bh 3 1 1 to infinite reads data in the otp memory space. for details refer to section 9.1.2, ?reading otp data? on page 36 . read id 9fh ? ? 1 to 3 device id: 1st byte = mfg id 2nd byte = upper byte, 3rd byte = lower byte release from dpd only abh ? ? ? brings the device out of dpd mode into standby mode after the t rdp latency.
numonyx? serial flash memory (s33) datasheet december 2007 26 order number: 314822-03 8.2.1 write spi sr command (01h) the write sr command allows the user to write to the writable status register bits (that is, sr[7, 4:2]. as with any command that writes to the device, the write enable command must be executed prior to the write sr command to set the wel bit. if the wel bit is not set, the write sr command will be ignored. if the device is in hardware protect mode, the write sr command will be ignored and the wel bit will be unchanged. assuming the wel bit is set and the device is not in hardware protect mode, the rising edge of s# updates the sr within the t shsl specification time. if the write sr command is botched (rising s# edge does not occur after exactly sixteen clock cycles), the writable sr bits and the wel bit will remain unchanged. 8.2.2 page program command (02h) the page program command programs 1 bit to 256 bytes of data within a 256-byte- aligned memory segment. this command is used for programming the main array; it is not used for otp programming. the command sequence consists of an 8-bit op code, followed by a 24-bit address, and then by the data bytes to be programmed. the data to be programmed must be in whole-byte granularity. otherwise, the command sequence will be ignored. to program in bit granularity, the remainder of the bits within the data byte must be set to "1". the input data stream is loaded into a 256-byte program buffer. the starting address of the program buffer is a[7:0] of the user-supplied address, and all subsequent bytes from the input data stream are loaded sequentially into the program buffer. if the program buffer reaches its maximum address, it wraps over, and subsequent data bytes are sequentially loaded starting at the beginning of the program buffer. if more than 256 bytes of data are provided in the command input stream, the program buffer will be over-written, replacing the data that was previously loaded. the command sequence ends when s# goes high. when the command sequence ends, the data in the program buffer is programmed in the 256-byte-aligned memory segment defined by a[23:8] of the user-supplied address. a byte count is not required with this command. the end of the data stream is identified with the rising edge of s#. deep power-down b9h ? ? ? puts device in dpd mode, whereby all commands are ignored except the release from dpd command (abh). bulk erase c7h ? ? ? serially erases all main memory sectors including the eight parameter blocks. sector erase d8h 3 ? ? erases a 64 kb memory sector; when addressing a parameter block, it will erase all eight 8 kb parameter blocks. table 15: spi command set (sheet 2 of 2) instruction op code addr bytes dummyb ytes data bytes name and function
december 2007 datasheet order number: 314822-03 27 numonyx? serial flash memory (s33) as with any command that writes to the device or changes the memory contents, the write enable command must be executed prior to the page program command in order to set the wel bit. if the wel bit is not set, the page program command will be ignored. if the wel bit is set and the address is protected, the program operation will not occur. instead, the p_fail flag of the status register will set and the wel bit will clear. the page program command can be botched (cancelled) by failing to raise the s# edge on a whole-byte increment. the following occur if the page program command is botched: ? the wel bit will not be cleared. ? sr fail flags (described in ta b l e 1 6 ) will not be set. ? none of the bytes written into the program buffer will be programmed into the flash array. assuming the wel bit is set, the address is unprotected, and the command is not botched, the rising edge of s# initiates the program operation. this program operation cannot be terminated without powering off the device, and doing so will result in unexpected data. 8.2.3 read data bytes command (03h) the read data bytes command requires a 3-byte address. after the last address byte is clocked in (on the rising clock edge), the first data bit is clocked out on the subsequent falling clock edge. data clocks out continuously and sequentially as long as s# remains low. when the address reaches its maximum, it wraps back to zero. the read data byte command supports up to 33.3 mhz. 8.2.4 write disable command (04h) the write disable command clears the wel bit, which corresponds to bit sr1. clearing the wel bit disables the following commands: ?write sr ?page program ?otp program ?bulk erase ? parameter block erase ?sector erase these commands can be re-enabled by executing the write enable command as described in section 8.2.6 . the wel bit is cleared at power-up. 8.2.5 read spi sr command (05h) the read sr command continuously polls the spi status register. as long as s# remains low, a refreshed version of the status register is continuously clocked out. the read sr command does not require address bytes, data bytes or dummy bytes. 8.2.6 write enable command (06h) the write enable command sets the wel bit, which corresponds to bit sr1. setting the wel bit enables the following commands: ?write sr
numonyx? serial flash memory (s33) datasheet december 2007 28 order number: 314822-03 ?page program ?otp program ?bulk erase ? parameter block erase ?sector erase these commands can be disabled by executing the write disable command as described in section 8.2.4 . the wel bit is cleared at power-up. 8.2.7 fast read data bytes command (0bh) the fast read data bytes command requires a 3-byte address. after the last address byte is clocked in (on the rising clock edge), a dummy byte latency occurs (8 clock cycles) before the first data bit is clocked out on the falling clock edge. data clocks out continuously and sequentially as long as s# remains low. refer to section section 8.4.1, ?fast read? on page 32 for a detailed description of the fast read data bytes command. when the address reaches its maximum, it wraps back to zero. the fast read data bytes command supports up to 68 mhz, but it requires a dummy byte to allow time for the first read latency. 8.2.8 clear sr fail flags command (30h) the clear sr fail flags command resets bit sr5 (erase fail flag) and bit sr6 (program fail flag). it is not necessary to set the wel bit before the clear sr fail flags command is executed. the wel bit will be unchanged after this command is executed. 8.2.9 parameter block erase command (40h) the parameter block erase command is used to erase an 8-kb parameter block. the command sequence consists of the op code followed by an address within the targeted block. as with any command that writes to the device or changes the memory contents, the write enable command must be executed prior to the parameter block erase command in order to set the wel bit. the parameter block erase command will be ignored if the wel bit is not set. if the wel bit is set and one of the following is true: ? the address is not an 8-kb parameter block address ? the address is protected, the erase operation will not occur. instead, the e_fail flag of the status register will set and the wel bit will clear. the parameter block erase command can be botched (cancelled) by failing to raise the s# edge after exactly thirty-two clock cycles. if the parameter block erase command is botched, the wel bit will not clear and the e_fail flag will not set. assuming the wel bit is set, the address is an unprotected 8-kb parameter block address, and the command is not botched, the rising edge of s# initiates the erase operation. this erase operation cannot be terminated without powering off the device, and doing so will result in unexpected data.
december 2007 datasheet order number: 314822-03 29 numonyx? serial flash memory (s33) 8.2.10 otp program command (42h) the otp program command programs data in the otp region, which is in a different address space from the main array data. refer to section 9.1, ?otp memory space? on page 36 for details on the otp region. the protocol of the otp program command is the same as the page program command, except that the otp program command requires exactly one byte of data; otherwise, the command will be ignored. to program the otp in bit granularity, the rest of the bits within the data byte can be set to "1". if the wel bit is set and the address is not a valid otp address, the program operation will not occur. instead, the f_fail flag of the status register will set and the wel bit will clear. the otp memory space can be programmed one or more times, provided that the otp memory space is not locked (as described in section 9.1.3, ?lock protection registers? on page 36 ). subsequent otp programming can be performed only on the unprogrammed bits (that is, ?1? data). 8.2.11 read otp data bytes command (4bh) the read otp data bytes command reads data from the otp region. refer to section 9.1, ?otp memory space? on page 36 for details on the otp region. the protocol of the read otp data bytes command is the same as the fast read data bytes command except that it will not wrap to the starting address after the otp address is at its maximum; instead, the data will be indeterminate. 8.2.12 read id command (9fh) the read id command reads three bytes of data. it does not require any address bytes, data bytes or dummy bytes. after inputting the op code, three bytes are clocked out of the device: the mfg id, the first byte of the device id, and the second byte of the device id. refer to table 19, ?device id codes? on page 38 for the mfg id and device ids of the s33 device. if s# is held low after the third byte of data, the subsequent data is indeterminate. 8.2.13 release from dpd command (abh) in deep power-down mode, the only command that the spi interface recognizes is the release from dpd command. after issuing this command, the t rdp latency is required before s# can go low to initiate another command. the only other way to release the device from dpd mode is to power it off and on. when issuing a release from dpd command, it is not necessary to raise s# after exactly eight clock cycles. after inputting the 8-bit op code, all subsequent bits in the command sequence will be ignored. 8.2.14 deep power-down command (b9h) the deep power-down command puts the device in dpd mode, whereby all commands are ignored except the release from dpd command (abh). 8.2.15 bulk erase command (c7h) the bulk erase command serially erases the entire main array. including the parameter blocks (but excluding the otp memory space).
numonyx? serial flash memory (s33) datasheet december 2007 30 order number: 314822-03 as with any command that writes to the device or changes the memory contents, the write enable command must be executed prior to the bulk erase command to set the wel bit. the bulk erase command will be ignored if the wel bit is not set. if the wel bit is set and there is at least one memory sector that is protected, the erase operation will not occur. instead, the e_fail flag of the status register will set and the wel bit will clear. the bulk erase command can be botched (cancelled) by failing to raise the s# edge after exactly eight clock cycles. if the bulk erase command is botched, the wel bit will not clear and the e_fail flag will not set. assuming the wel bit is set, all memory sectors are unprotected, and the command is not botched, the rising edge of s# initiates the erase operation. this erase operation cannot be terminated without powering off the device, and doing so will result in unexpected data. 8.2.16 sector erase command (d8h) the sector erase command is used to erase a 64-kb memory sector. the command sequence consists of an 8-bit op code followed by a 24-bit address. if the address is within the parameter block address range (a[max:16]=0), all eight parameter blocks will be erased. (with this characteristic, the device behaves as a symmetrically blocked device.) as with any command that writes to the device or changes the memory contents, the write enable command must be executed prior to the sector erase command in order to set the wel bit. if the wel bit is not set, the sector erase command will be ignored. if the wel bit is set and the address is protected, the erase operation will not occur. instead, the e_fail flag of the status register will set and the wel bit will clear. the sector erase command can be botched (cancelled) by failing to raise the s# edge after exactly 32 clock cycles. if the sector erase command is botched, the wel bit will not clear and the e_fail flag will not set. assuming the wel bit is set, the address is an unprotected, and the command is not botched, the rising edge of s# initiates the erase operation. the erase operation cannot be terminated without powering off the device, and doing so will result in unexpected data. 8.3 status register definition the status register bit definition can be found in ta b l e 1 6 . the status register has program/erase fail flags, and it contains writeable bits that define the program/erase protection within the flash array. all status register bits are volatile.
december 2007 datasheet order number: 314822-03 31 numonyx? serial flash memory (s33) 8.3.1 main memory protection main memory program/erase protection is defined by three status register bits (sr[4:2]) and the w# input signal. ta b l e 1 7 defines the memory protection regions. ta b l e 1 8 defines the sr and w# configurations for software protection mode and hardware protection mode. table 16: status register bit definition sr bit bit name bit description power- up state write/read capability 7srwd status register write disable - when this writeable bit is set and w# is low, none of the writable sr bits can be changed including these bits (that is, sr7, 4:2). for details, refer to ta b l e 1 8 , ? m a i n a r ra y p r o t e c t i o n m o d e s ? on page 32 . this bit is volatile. 0read/write (1) 6p_fail program fail flag - when set, this bit indicates that a program failure occurred. this bit will also be set when the user attempts to program a protected main memory region or a locked otp region. however, the program fail flag will not be set under the following scenarios: ? botched command sequence (that is, s# edge not raised on a whole-byte increment) ? write enable latch bit is reset (that is, sr1 = 0) after a series of program operations, this bit indicates whether one or more of these operations failed. once set, this bit is reset with the clear sr fail flag command. 0read only (2) 5e_fail erase fail flag - when set, this bit indicates that an erase failure occurred. this bit will also be set when the user attempts to erase a protected main memory region. however, the erase fail flag will not be set under the following scenarios: ? botched command sequence (that is, s# edge not raised on a whole-byte increment). ? write enable latch bit is reset (that is, sr1 = 0) after a series of erase operations, this bit indicates whether one or more of the operations failed. once set, this bit is reset with the clear sr fail flag command. 0read only (2) 4bp2 sector protect bits - these bits define the lock region of the main memory. a locked region is one or more adjacent memory sectors that are protected from program or erase. for further details, refer to ta b l e 1 7 . when all three of these bits are ?0?, the entire main array is unlocked. these bits are volatile; at power-up, these bits are set to ?1?. 1read/write (1) 3bp1 1read/write (1) 2bp0 1read/write (1) 1wel write enable latch - this bit must be set prior to the following spi commands: ? write spi sr ?page program ? otp program ?bulk erase ? parameter block erase ?sector erase after issuing one of these commands, the wel bit will clear when the command is completed. the wel bit will not be cleared if the command is botched by not raising s# on a whole-byte increment. 0read only (3) 0wip write in process - when a program, erase, or write to the sr is in process (busy), the wip reads as ?1?. when the wip bit is zero, the spi interface is in its ready state. 0read only notes: 1. refer to table 18, ?main array protection modes? on page 32 for writable conditions. 2. the program and erase fail flags are not directly writable, but they can be reset with the clear sr fail flag command. this is true regardless of the protection modes described in ta b l e 1 8 . 3. the wel bit is not directly writable but it can be set with the write enable command and reset with the write disable command. this is true regardless of the protection modes described in ta b l e 1 8 .
numonyx? serial flash memory (s33) datasheet december 2007 32 order number: 314822-03 8.4 spi instruction cycle examples in this section, two spi instruction cycles are explained in detail to provide a thorough understanding of spi instruction cycles in general. the intent of these examples is to provide a foundation for all spi instructions. 8.4.1 fast read a fast read instruction uses 0bh as an op code. after clocking in the op code, a 3- byte address is clocked in (starting with the msb), followed by a dummy byte. the output serial data stream is clocked out on the falling edge of "c", one-half cycle after the last dummy bit is clocked in. the timing diagram for a fast read command sequence can be found in figure 15, ?timing diagram for spi fast read command sequence? on page 33 . within the spi interface, the address is automatically incremented internally as the data is clocked out continuously and sequentially, as long as s# remains low. the output data stream can be paused by bringing hold# low, and it can be continued by table 17: main array protection regions - bottom boot status register bits protected main memory sectors bp2 bp1 bp0 64 m 32 m 16 m 0 0 0 none none none 00 1 sectors 126 - 127 (upper 1/64) sector 63 (upper 1/64) sector 31 (upper 1/32) 01 0 sectors 124 - 127 (upper 1/32) sectors 62 - 63 (upper 1/32) sectors 30 - 31 (upper 1/16) 01 1 sectors 120 - 127 (upper 1/16) sectors 60 - 63 (upper 1/16) sectors 28 - 31 (upper 1/8) 10 0 sectors 112 - 127 (upper 1/8) sectors 56 - 63 (upper 1/8) sectors 24 - 31 (upper 1/4) 10 1 sectors 96 - 127 (upper 1/4) sectors 48 - 63 (upper 1/4) sectors 16 - 31 (upper 1/2) 11 0 sectors 64 - 127 (upper 1/2) sectors 32 - 63 (upper 1/2) all sectors 1 1 1 all sectors all sectors all sectors table 18: main array protection modes w# signal srwd bit (sr7) mode protection of sr v il 0 software protect the srwd bit (sr7) and the bp bits (sr[4:2]) are writable. v il 1 hardware protect the srwd bit (sr7) and the bp bits (sr[4:2]) are not writable. these bits cannot be altered without raising w# to v ih or device power-up. in this configuration, the main array protection regions cannot be changed. v ih 0 software protect the srwd bit (sr7) and the bp bits (sr[4:2]) are writable. v ih 1 software protect the srwd bit (sr7) and the bp bits (sr[4:2]) are writable.
december 2007 datasheet order number: 314822-03 33 numonyx? serial flash memory (s33) bring it high again. when the internal address reaches the last address within the device?s range, it will wrap to address 0h. when the user brings s# high, the instruction cycle is terminated, and the data output (q) becomes tri-stated. 8.4.2 page program a page program instruction consists of an op code (02h) followed by a 3-byte address and a variable number of data bytes, up to the size of the program buffer (page). assuming s# goes high on a whole-byte increment, the spi module will instruct the wsm to initiate programming, otherwise the page program instruction will botch (and nothing will be programmed). the timing diagram for a page program command sequence can be found in figure 16, ?timing diagram for spi page program command sequence? on page 34 . to monitor when the program algorithm is complete, a read sr command must be issued. the read sr command is the only instruction that the device will recognize while a write is in process. figure 15: timing diagram for spi fast read command sequence address address instruction instruction 1/fc 1/fc 01 a23a22a21a2a1a0 234567 293031 s# c d q data byte data byte dummy byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d s# c d q data byte (addr+2) data byte (addr+2) data byte (addr+1) data byte (addr+1) d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 s# c d q
numonyx? serial flash memory (s33) datasheet december 2007 34 order number: 314822-03 8.4.3 write enable for write operations such as the page program operation, the single-byte write enable command sequence must be issued to set the wel bit prior to issuing the page program operation. without setting the wel bit, the subsequent page program operation will be ignored. just as with any other command that alters the configuration, the write enable command is completed on the rising edge of s#. the timing diagram for a write enable command sequence can be found in figure 17, ?timing diagram for write enable command sequence? on page 35 . figure 16: timing diagram for spi page program command sequence address address instruction instruction 1/fc 1/fc 01 a23 a22 a21 a2 a1 a0 234567 293031 d d7 32 s# c d q data byte 2 data byte 2 data byte 1 data byte 1 1/fc 1/fc d6 d2 d1 d0 d4 d5 d3 d7 d6 d5 d4 d3 d2 d1 d0 d7 d 40 48 s# c d q data byte 256 data byte 256 data byte 3 data byte 3 1/fc 1/fc d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 2072 s# c d q
december 2007 datasheet order number: 314822-03 35 numonyx? serial flash memory (s33) figure 17: timing diagram for write enable command sequence instruction instruction 1/fc 1/fc 01234567 s# c d q
numonyx? serial flash memory (s33) datasheet december 2007 36 order number: 314822-03 9.0 security features this section describes the security features of the s33 device that go beyond the typical spi flash feature set. 9.1 otp memory space the s33 device contains two 8-byte, thirty 16-byte, and one 10-byte individually- lockable otp regions (protection registers) within an address space that is separate from the main array. refer to figure 18, ?otp memory map? on page 37 for a pictorial representation of the otp memory space. the two 8-byte protection registers are intended for increased system security. protection register values can ?mate? a flash component with system cpu/asic to prevent device substitution. the numonyx factory programs the lower 8-byte protection register with a unique, unchangeable 64-bit number. the other 64 bits (upper 8-byte) are blank so customers can program them for a similar purpose. once programmed, each customer segment (one of the 8-byte segment, thirty 16-byte segments, and one 10-byte segment) can be locked to prevent further reprogramming. 9.1.1 programming otp address space for the description and spi protocol of the otp program command, refer to table 15, ?spi command set? on page 25 . the protocol of this command is the same as page program. the otp program command can be issued multiple times to any given otp address, but this address space can never be erased. after a given otp segment is programmed, it can be locked to prevent further programming with the lock protection registers, which are describe in section 9.1.3 . the valid address range for otp program is depicted in figure 18, ?otp memory map? on page 37 . otp program operations outside the valid otp address range will be ignored. 9.1.2 reading otp data for the description and spi protocol of the otp read command, refer to ta b l e 1 5 , ? s p i command set? on page 25 . the protocol of this command is the same as fast read. the valid address range for otp reads is depicted in figure 18, ?otp memory map? on page 37 . otp read operations outside the valid otp address range will yield indeterminate data. 9.1.3 lock protection registers the lock protection registers (pr-lock1, pr-lock2, and pr-lock3) are illustrated in figure 18, ?otp memory map? on page 37 . pr-lock1 is used to permanently lock otp addresses 0x102 through 0x111; pr-lock2 is used to permanently lock otp addresses 0x114 through 0x213; pr-lock3 is used to permanently lock otp addresses 0x216 through 0x2ff.
december 2007 datasheet order number: 314822-03 37 numonyx? serial flash memory (s33) note: otp bytes 0x102 through 0x109 will be programmed at numonyx?s factory with an unchangeable, unique identifier, and bit 0 of pr-lock1 register will be programmed to 0. figure 18: otp memory map pr -lo c k1 r egister 8 b ytes (64 bits) 8 b ytes (64 bits) 0x100 0x102 0x109 0x10a 0x111 0x101 reserved: { locked w ith bit 1 locked w ith bit 0 pr-lo c k2a r egister: 16 b ytes (128 bits) 16 b ytes (128 bits) 0x112 0x114 0x123 0x204 0x213 0x113 { locked w ith pr -lo c k2a, bit 0 ? pr-lo c k2b r egister: { locked w ith pr -lo c k2b, bit 7 pr-lo c k3a r egister: 16 b ytes (128 bits) 16 b ytes (128 bits) 0x214 0x216 0x225 0x2e 6 0x2f 5 0x215 { locked w ith pr -lo c k3a, bit 0 ? pr-lo c k3b r egister: { locked w ith pr -lo c k3b, bit 5 10 b ytes (80 bits) 0x2f 6 0x2f f { locked w ith pr -lo c k3b, bit 6 {
numonyx? serial flash memory (s33) datasheet december 2007 38 order number: 314822-03 10.0 numonyx? serial flash memory (s33) id codes the manufacturer id is 89h, and the device ids are found in ta b l e 1 9 . through the spi command set, op code 9fh is required. the first byte of data read is the manufacturer id (89h); the second byte is the upper byte of the device id, and the third byte is the lower byte of the device id. table 19: device id codes device device id mode numonyx? serial flash memory (s33) 64m 8913 bottom boot numonyx? serial flash memory (s33) 32m 8912 bottom boot numonyx? serial flash memory (s33) 16m 8911 bottom boot
december 2007 datasheet order number: 314822-03 39 numonyx? serial flash memory (s33) appendix a write state machine (wsm) ta b l e 2 0 and ta b l e 2 1 shows the command state transitions (next state table) based on incoming commands. table 20: chip state and output state transitions (sheet 1 of 2) current chip state command input to chip and resulting chip next state (1 of 2) write sr page program read data bytes write disable read sr write enable fast read data bytes clear sr fail flags param block erase 01h 02h 03h 04h 05h 06h 0bh 30h 40h ready, wel bit =0 ready, wel bit = 0 (command ignored) ready, wel bit does not change (array data output) ready, wel=0 ready, wel bit does not change (sr output) ready, wel=1 ready, wel bit does not change (array data output) ready, wel bit does not change ready, wel bit = 0 (command ignored) ready, wel bit =1 ready. if software protected, sr write occurs and wel=0. else, command is ignored and wel=1. (see note 1) if targeted address is protected, device is ready and wel=1. else, device is busy and wel=x. (see note 2) if the targeted address is protected and a valid parameter block address, device is ready and wel bit = 1. else, device is busy and wel bit = x (see note 2) dpd, wel bit =x dpd, wel bit does not change (command ignored) busy busy (command ignored) busy (sr output) busy (command ignored) notes: 1. refer to ta b l e 1 8 for details on hw/sw protection. 2. refer to ta b l e 1 8 for details on address protection. 3. refer to section 9.0, ?security features? for details on otp protection. 4. refer to ta b l e 1 6 for details on the status register.
numonyx? serial flash memory (s33) datasheet december 2007 40 order number: 314822-03 table 21: chip state and output state transitions (sheet 2 of 2) current chip state command input to chip and resulting chip next state (2 of 2) otp program read otp data bytes read jedec id release from dpd deep power- down bulk erase sector erase power cycle (off, then on) program or erase operation completes 42h 4bh 9fh abh b9h c7h d8h ready, wel bit =0 ready, wel bit = 0 (command ignored) ready, wel bit does not change (otp data output) ready, wel bit does not change (id output) ready, wel bit does not change dpd, wel bit does not change ready, wel=0 (command ignored) ready, sr = 1ch (see note 4) n/a ready, wel bit =1 if targeted address is protected, device is ready and wel bit = 1. else, device is busy and wel bit = x. (see note 3) if any main memory is protected, device is ready and wel bit =1. else, device is busy and wel bit = x. (see note 2) if targeted address is protected, device is ready and wel bit =1. else, device is busy and wel bit =x. (see note 2) dpd, wel bit =x dpd, wel bit does not change (command ignored) dpd, wel bit does not change (command ignored) busy busy (command ignored) ready, wel bit = 0 notes: 1. refer to ta b l e 1 8 for details on hw/sw protection. 2. refer to ta b l e 1 8 for details on address protection. 3. refer to section 9.0, ?security features? for details on otp protection. 4. refer to ta b l e 1 6 for details on the status register.
december 2007 datasheet order number: 314822-03 41 numonyx? serial flash memory (s33) appendix b ordering information figure 19: ordering information table 22: valid combinations for numonyx? serial flash memory (s33) 32 mbit 16 mbit 64 mbit qb25f320s33b8 qb25f016s33b8/qb25f160s33b8 qb25f640s33b8 QH25F320S33B8 qh25f016s33b8/qb25f160s33b8 qh25f640s33b8 f 3 2 s 3 3 b 5 b 2 q 0 product line designator package designator device density product family intel ? s33 v cc = 2.7 ? 3.6 v access speed 8 ns (t clqv ) parameter location b = bottom parameter t = top parameter 8 016 = 16 mbit, soic-8 160 = 16 mbit, soic-16 320 = 32 mbit 640 = 64 mbit qb = soic-8/soic-16, leaded qh = soic-8/soic-15, lead free 25f = intel ? s33 fpg_a0019-01

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