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1. general description the SSTUB32868 is a 1.8 v 28-bit 1 : 2 register specifically designed for use on two rank by four (2r 4) and similar high-density double data rate 2 (ddr2) memory modules. it is similar in function to the jedec-standar d 14-bit ddr2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommoda te high-density dual in-line memory module (dimm) designs. the SSTUB32868 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the d-inputs and indicates whether a parity error has occurred on its open-drain ptyerr pin (active low). it further offers added features over the jedec standard register in that it can be configured for normal or high output drive st rength, simply by tying input pin seldr either high or low as needed. this allows use in different module designs varying from low to high density designs by picking the appropri ate drive strength to match net loading conditions. furthermore, the SSTUB32868 feat ures two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. both added features (drive strength and chip selects) are fully backward compatible to the jedec standard register. the SSTUB32868 is packaged in a 176-ball, 8 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (tfbga) package, which (while requiring a minimum 6mm 15 mm of board space) allows for adeq uate signal routing and escape using conventional card technology. 2. features and benefits ? 28-bit data register supporting ddr2 ? supports 2 rank by 4 dimm density by in tegrating equivalent functionality of two jedec-standard ddr2 re gisters (that is, 2 sstua32864 or 2 sstua32866) ? parity checking function across 22 input data bits ? parity out signal ? controlled multi-impedance output impedance drivers enable optimal signal integrity and speed ? meets or exceeds SSTUB32868 jedec standard speed performance ? supports up to 450 mhz clock frequency of operation ? programmable for normal or high output drive ? optimized pinout for high-density ddr2 module design ? chip-selects minimize power consumption by gating data outputs from changing state SSTUB32868 1.8 v 28-bit 1 : 2 configurable registered buffer with parity for ddr2-800 rdimm applications rev. 04 ? 22 april 2010 product data sheet
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 2 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity ? two additional chip select inputs allo w optional flexible e nabling and disabling ? supports stub series terminated logic sstl_18 data inputs ? differential clock (ck and ck ) inputs ? supports low voltage complementary metal-oxide semiconductor (lvcmos) switching levels on the control and reset inputs ? single 1.8 v supply operation (1.7 v to 2.0 v) ? available in 176-ball 6 mm 15 mm, 0.65 mm ball pitch tfbga package 3. applications ? 400 mt/s to 800 mt/s high-density (for exampl e, 2 rank by 4) ddr2 registered dimms ? ddr2 registered dimms (rdimm) desiring parity checking functionality 4. ordering information 4.1 ordering options table 1. ordering information type number solder process package name description version SSTUB32868et/g pb-free (snagcu solder ball compound) tfbga176 plastic thin fine-pitch ball grid array package; 176 balls; body 6 15 0.7 mm sot932-1 SSTUB32868et/s pb-free (snagcu solder ball compound) tfbga176 plastic thin fine-pitch ball grid array package; 176 balls; body 6 15 0.7 mm sot932-1 table 2. ordering options type number temperature range SSTUB32868et/g t amb = 0 c to +70 c SSTUB32868et/s t amb = 0 c to +85 c
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 3 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 5. functional diagram (1) register a configuration (c = 0): d2 to d5, d7, d9 to d12, d17 to d28 register b configuration (c = 1): d2 to d12, d17 to d20, d22, d24 to d28 fig 1. logic diagram of SSTUB32868 (positive logic) d q r vref dcke0, dcke1 reset ck ck qcke0a, qcke1a qcke0b, qcke1b 002aac33 6 2 2 SSTUB32868 clk 2 2 2 d q r dodt0, dodt1 qodt0a, qodt1a qodt0b, qodt1b 2 2 clk 2 2 2 d q r dcs0 qcs0a qcs0b clk csgen d q r dcs1 qcs1a qcs1b clk d q r d1 q1a q1b clk one of 22 channels to 21 other channels (1) ce dcs2 dcs3
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 4 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity (1) register a configuration (c = 0): d1 to d5, d7, d9 to d12, d17 to d28 register b configuration (c = 1): d1 to d12, d17 to d20, d22, d24 to d28 (2) register a configuration (c = 0): q1a to q5a, q7a, q9a to q12a, q17a to q28a register b configuration (c = 1): q1a to q12a, q17a to q20a, q22a, q24a to q28a (3) register a configuration (c = 0): q1b to q5b, q7b, q9b to q12b, q17b to q28b register b configuration (c = 1): q1b to q12b, q17b to q20b, q22b, q24b to q28b fig 2. parity logic diagram (positive logic) d q r vref dn (1) reset ck ck qna (2) qnb (3) 002aac49 7 22 22 clk 22 22 22 csgen ce d q r par_in clk ce parity generator and error check 22 qerr d q r dcs0 clk qcs0a qcs0b d q r dcs1 clk qcs1a qcs1b dcs2 dcs3
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 5 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 6. pinning information 6.1 pinning fig 3. pin configuration for tfbga176 002aac33 7 transparent top view 2468 1357 SSTUB32868et/ g SSTUB32868et/ s ab aa y w v u r n t p m l k j h f d g e c b a ball a1 index area
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 6 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 176-ball, 8 22 grid; top view. fig 4. ball mapping (1 : 2 register a; c = 0) d2 d1 c gnd vref gnd 123456 d4 d3 v dd v dd v dd v dd a b d6 (dcke1) d5 c d8 (dcke0) d7 v dd v dd v dd d d9 q6a (qcke1a) gnd gnd gnd e d10 q8a (qcke0a) v dd v dd f d11 q10a gnd gnd g d12 q12a v dd v dd h gnd gnd j v dd v dd k csgen gnd gnd l ck reset v dd v dd m d15 (dodt0) q15a (qodt0a) gnd gnd n d16 (dodt1) q16a (qodt1a) v dd v dd v dd p d17 q17a gnd gnd gnd r d18 q19a t 002aac49 8 q1a q1b 78 q2a q2b q4a q4b q5a q5b q6b (qcke1b) q7b q8b (qcke0b) q9b q11b q16b (qodt1b) q18b q19b q20b q18a q21b d19 q21a gnd gnd gnd gnd u d20 q23a v dd v dd v dd v dd v q22a q23b q24a q24b ck d21 d22 gnd gnd gnd w d23 d24 y q25a q25b d25 d26 gnd gnd gnd gnd aa d27 d28 seldr v dd vref v dd ab q27a q27b q28a q28b gnd gnd gnd gnd q3a q3b v dd q7a gnd q9a v dd q11a gnd q10b v dd q12b gnd q14b (qcs0b) v dd q15b (qodt0b) gnd q17b v dd gnd v dd gnd v dd gnd dcs2 par_in qerr gnd dcs3 gnd v dd v dd v dd q20a q22b v dd v dd v dd v dd q26a q26b gnd v dd q13b (qcs1b) dcs1 (d13) dcs0 (d14) qcs1a (q13a) qcs0a (q14a)
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 7 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 176-ball, 8 22 grid; top view. fig 5. ball mapping (1 : 2 register b; c = 1) d2 d1 c gnd vref gnd 123456 d4 d3 v dd v dd v dd v dd a b d6 d5 c d8 d7 v dd v dd v dd d d9 q6a gnd gnd gnd e d10 q8a v dd v dd f d11 q10a gnd gnd g d12 q12a v dd v dd h q13a (qodt1a) gnd gnd j d14 (dodt0) q14a (qodt0a) v dd v dd k csgen gnd gnd l ck reset v dd v dd m d15 (dcs0) q15a (qcs0a) gnd gnd n d16 (dcs1) q16a (qcs1a) v dd v dd v dd p d17 q17a gnd gnd gnd r d18 q19a t 002aac49 9 q1a q1b 78 q2a q2b q4a q4b q5a q5b q6b q7b q8b q9b q11b q16b (qcs1b) q18b q19b q20b q18a q21b (qcke0b) d19 q21a (qcke0a) gnd gnd gnd gnd u d20 q23a (qcke1a) v dd v dd v dd v dd v q22a q23b (qcke1b) q24a q24b ck d21 (dcke0) d22 gnd gnd gnd w d23 (dcke1) d24 y q25a q25b d25 d26 gnd gnd gnd gnd aa d27 d28 seldr v dd vref v dd ab q27a q27b q28a q28b gnd gnd gnd gnd q3a q3b v dd q7a gnd q9a v dd q11a gnd q10b v dd q12b gnd q14b (qodt0b) v dd q15b (qcs0b) gnd q17b v dd gnd v dd gnd v dd gnd dcs2 par_in qerr gnd dcs3 gnd v dd v dd v dd q20a q22b v dd v dd v dd v dd q26a q26b gnd v dd d13 (dodt1) q13b (qodt1b)
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 8 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 6.2 pin description table 3. pin description symbol pin type description 1 : 2 register a (c = 0) 1 : 2 register b (c = 1) ungated inputs dcke0 d1 w1 sstl_18 the outputs of this register will not be suspended by the dcs0 and dcs1 control. dcke1 c1 y1 dodt0 n1 k1 sstl_18 the outputs of this register will not be suspended by the dcs0 and dcs1 control. dodt1 p1 j1 chip select gated inputs d1 to d28 a2, a1, b2, b1, c2, c1, d2, d1, e1, f1, g1, h1, n1, p1, r1, t1, u1, v1, w1, w2, y1, y2, aa1, aa2, ab1, ab2 a2, a1, b2, b1, c2, c1, d2, d1, e1, f1, g1, h1, j1, k1, n1, p1, r1, t1, u1, v1, w1, w2, y1, y2, aa1, aa2, ab1, ab2 sstl_18 data inputs, clocked in on the crossing of the rising edge of cd and the falling edge of ck . chip select inputs dcs0 k1 n1 sstl_18 chip select inputs. these pins initiate dram address/command decodes, and as such at least one will be low when a valid address/command is present. the register can be programmed to re-drive all d-inputs (csgen = high) only when at least one chip select input is low. if csgen, dcs0 and dcs1 inputs are high, d1 to d28 [1] inputs will be disabled. dcs1 j1 p1 dcs2 k3 k3 dcs3 p3 p3 configuration control inputs ca3 a3 lvcmos input configuration control inputs; register a or register b re-driven outputs q1a to q28a a7, b7, c7, d7, e7, e2, f7, f2, g7, g2, h7, h2, n2, p2, r2, r7, t2, t7, u2, u7, v2, v7, w7, y7, aa7, ab7 a7, b7, c7, d7, e7, e2, f7, f2, g7, g2, h7, h2, j2, k2, n2, p2, r2, r7, t2, t7, u2, u7, v2, v7, w7, y7, aa7, ab7 1.8 v cmos outputs data outputs [2] that are suspended by the dcs0 and dcs1 control. q1b to q28b a8, b8, c8, d8, e8, f8, g8, h8, j8, j7, k8, k7, l8, l7, m7, m8, n7, n8, p7, p8, r8, t8, v8, u8, w8, y8, aa8, ab8 a8, b8, c8, d8, e8, f8, g8, h8, j8, j7, k8, k7, l8, l7, m7, m8, n7, n8, p7, p8, r8, t8, u8, v8, w8, y8, aa8, ab8 qcs0a k2 n2 1.8 v cmos outputs data outputs that will not be suspended by the dcs0 and dcs1 control. qcs0b l7 m7 qcs1a j2 p2 qcs1b l8 m8 qcke0a f2 u2 1.8 v cmos outputs data outputs that will not be suspended by the dcs0 and dcs1 control. qcke0b h8 r8 qcke1a e2 v2 qcke1b f8 u8
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 9 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity qodt0a n2 k2 1.8 v cmos outputs data outputs that will not be suspended by the dcs0 and dcs1 control. qodt0b m7 l7 qodt1a p2 j2 qodt1b m8 l8 output error qerr m3 m3 open-drain output output error bit; generated on clock cycle after the corresponding data output. parity input par_in l3 l3 sstl_18 parity input. arrives one clock cycle after the corresponding data input. program inputs csgenl2l2lvcmos input chip select gate enable. when high, the d1 to d28 [1] inputs will be latched only when at least one chip select input is low during the rising edge of the clock. when low, the d1 to d28 [1] inputs will be latched and re-driven on every rising edge of the clock. clock inputs ck l1 l1 differential input positive master clock input. ck m1 m1 differential input negative master clock input. miscellaneous inputs reset m2 m2 lvcmos input asynchronous reset in put. resets registers and disables vref data and clock differential-input receivers. vref a5, ab5 a5, ab5 0.9 v nominal input reference voltage. v dd b3, b4, b5, b6, d3, d4, d5, d6, f3, f4, f5, f6, h3, h4, h5, h6, k4, k5, k6, m4, m5, m6, p4, p5, p6, t3, t4, t5, t6, v3, v4, v5, v6, y3, y4, y5, y6, ab4, ab6 b3, b4, b5, b6, d3, d4, d5, d6, f3, f4, f5, f6, h3, h4, h5, h6, k4, k5, k6, m4, m5, m6, p4, p5, p6, t3, t4, t5, t6, v3, v4, v5, v6, y3, y4, y5, y6, ab4, ab6 1.8 v nominal power supply voltage. gnd a4, a6, c3, c4, c5, c6, e3, e4, e5, e6, g3, g4, g5, g6, j3, j4, j5, j6, l4, l5, l6, n3, n4, n5, n6, r3, r4, r5, r6, u3, u4, u5, u6, w3, w4, w5, w6, aa3, aa4, aa5, aa6 a4, a6, c3, c4, c5, c6, e3, e4, e5, e6, g3, g4, g5, g6, j3, j4 , j5, j6, l4, l5, l6, n3, n4, n5, n6, r3, r4, r5, r6, u3, u4, u5, u6, w3, w4, w5, w6, aa3, aa4, aa5, aa6 ground input ground. seldr ab3 ab3 lvcmos input with weak pull-up selects output drive strength: ?high? for normal drive; ?low? for high drive. this pin will default high if left open-circuit (built-in weak pull-up resistor). table 3. pin description ?continued symbol pin type description 1 : 2 register a (c = 0) 1 : 2 register b (c = 1)
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 10 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity [1] data inputs = d1 to d5, d7, d9 to d12, d17 to d28 when c = 0. data inputs = d1 to d12, d17 to d20, d22, d24 to d28 when c = 1. [2] data outputs = q1x to q5x, q7x, q9x to q12x, q17x to q28x when c = 0. data outputs = q1x to q12x, q17x to q20x, q22x, q24x to q28x when c = 1. 7. functional description 7.1 function table [1] q 0 is the previous state of the associated output. [2] dcs2 and dcs3 operate identically to dcs0 and dcs1 , except they do not have corresponding re-driven (qcs) outputs. table 4. function table (each flip-flop) inputs outputs [1] reset dcs0 [2] dcs1 [2] csgen ck ck dn, dodtn, dcken qn qcs0x qcs1x qodtn, qcken hll x lllll hll x hhllh h l l x l or h l or h x q 0 q 0 q 0 q 0 hlh x lllhl hlh x hhlhh h l h x l or h l or h x q 0 q 0 q 0 q 0 hhl x llhll hhl x hhhlh h h l x l or h l or h x q 0 q 0 q 0 q 0 hhh l llhhl hhh l hhhhh h h h l l or h l or h x q 0 q 0 q 0 q 0 hhh h lq 0 hh l hhh h hq 0 hh h h h h h l or h l or h x q 0 q 0 q 0 q 0 lx or floating x or floating x or floating x or floating x or floating x or floating l l l l
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 11 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity [1] dcs2 and dcs3 operate identically to dcs0 and dcs1 with regard to the parity function. [2] par_in arrives one clock cycle after the data to which it applies. [3] this transition assumes qerr is high at the crossing of ck going high and ck going low. if qerr is low, it stays latched low for two clock cycles or until reset is driven low. [4] qerr 0 is the previous state of output qerr . [5] if dcs0 , dcs1 , dcs2 , dcs3 and csgen are driven high, the device is placed in low-power mode (lpm). if a parity error occurs on the clock cycle before the device enters the lpm and the qerr output is driven low, it stays latched low for the lpm duration plus two clock cycles or until reset is driven low. 7.2 functional information the SSTUB32868 is a 28-bit 1 : 2 configurable registered buffer designed for 1.7 v to 1.9 v v dd operation. all inputs are compatible with the jedec standard for sstl_18, except the chip-select gate-enable (csgen), control (c), and reset (reset ) inputs, which are lvcmos. all outputs are edge-controlled circuits optimized for unterminated dimm loads, and meet sstl_18 specifications, except the open-drain error (qerr ) output. the device supports low-power st andby operation. when reset is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (vref) inputs are allow ed. in addition, when reset is low, all registers are reset and all outputs are forced low except qerr . the lvcmos reset and c inputs always must be held at a valid logic high or low level. to ensure defined outputs from the regist er before a stable clock has been supplied, reset must be held in the low state during power-up. in the ddr2 rdi mm application, reset is specified to be completely asynchronous with respect to ck and ck . therefore, no timing relationship can be ensured between the two. when entering reset, the register will be clear ed and the data outp uts will be driven low quickly, relative to the time to disable the differential input receivers. however, when coming out of reset, the regist er will become active quickly, re lative to the time to enable the differential input receivers. as long as the data inputs are low, and the clock is stable table 5. parity and standby function table inputs output reset dcs0 [1] dcs1 [1] ck ck of inputs = h (d1 to d28) par_in [2] qerr [3] [4] hl x even l h hl x odd l l hl x even h l hl x odd h h hx l even l h hx l odd l l hx l even h l hx l odd h h hh h xxqerr 0 [5] h x x l or h l or h x x qerr 0 l x or floating x or floating x or floating x or floating x x or floating h
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 12 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity during the time from the lo w-to-high transition of reset until the input receivers are fully enabled, the design of the SSTUB32868 must ensure that the outpu ts will remain low, thus ensuring no glitches on the output. the SSTUB32868 includes a parity checking f unction. parity, which arrives one cycle after the data input to which it applies, is che cked on the par_in input of the device. the corresponding qerr output signal for the data inputs is generated two clock cycles after the data, to which the qerr signal applies, is registered. the SSTUB32868 accepts a parity bit from the memory controller on the parity bit (par_in) input, compares it with the data received on the dimm-independent d inputs (d1 to d5, d7, d9 to d12, d17 to d28 when c = 0; or d1 to d12, d17 to d20, d22, d24 to d28 when c = 1) and indicates whether a parity error has occurred on the open-drain qerr pin (active low). the convention is even pari ty, that is, valid parity is defined as an even number of ones across the dimm-independent data inputs combined with the parity input bit. to calculate parity, all dimm-indepen dent d inputs must be tied to a known logic state. if an error occurs and the qerr output is driven low, it stays latched low for a minimum of two clock cycles or until reset is driven low. if two or more consecutive parity errors occur, the qerr output is driven low and latched low for a clock duration equal to the pari ty error duration or until reset is driven low. if a parity error occurs on the clock cycle before the device enters the low-power mode (lpm) and the qerr output is driven low, then it stays latched low for the lpm duration plus two clock cycles or until reset is driven low. the dimm-dependent signals (dcke0, dcke1, dodt0, dodt1, dcs0 , dcs1 , dcs2 and dcs3 ) are not included in the parity check computation. the c input controls the pinout configuration from register a configuration (when low) to register b configuration (when high). the c input should not be switched during normal operation. it should be hard-wired to a valid low or high level to configure the register in the desired mode. the device also supports low-power active operation by monitoring both system chip select (dcs0 , dcs1 , dcs2 and dcs3 ) and csgen inputs and will gate the qn outputs from changing states when csgen, dcs0 and dcs1 inputs are high. if csgen or the dcsn inputs are low, the qn outputs will function normally. also, if all dcsn inputs are high, the device will gate the qerr output from changing states. if any of the dcsn are low, the qerr output will function normally. the reset input has priority over the dcsn control, and when driven low will fo rce the qn outputs low and the qerr output high. if the chip-select control functionality is not desired, then the csgen input can be hard-wired to ground (gnd), in which case the setup time requirement for dcsn would be the same as for the other d data inputs. to control the low-power mode with dcsn only, the csgen input should be pulled up to v dd through a pull-up resistor. the two vref pins (a5 and ab5) are connected together internally by approximately 150 . however, it is nece ssary to connect only one of the two vref pins to the external v ref power supply. an unused vref pin should be terminated with a v ref coupling capacitor. the SSTUB32868 is available in a tfgba176 package.
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 13 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 7.3 register timing (1) after reset is switched from low to high, all data and par_in i nput signals must be set and held low for a minimum time of t act(max) to avoid false error. (2) if the data is clocked on the m clock pulse, and par_in is clocked in at m + 1, the qerr output signal will be produced on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. fig 6. timing diagram during start-up (reset switches from low to high) ck dn, dodtn, dcken (1) qn, qodtn, qcken t su 002aab89 9 ck m m + 1 m + 2 m + 3 m + 4 dcsn reset t act t h t pdm , t pdmss ck to q par_in (1) t su t h t phl , t plh ck to qerr t phl ck to qerr qerr (2) high, low, or don't care high or low csgen data to qerr latency
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 14 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity (1) if the data is clocked in on the m clock pulse , and par_in is clocked in at m + 1, the qerr output signal will be generated on the m + 2 clock pulse and it will be valid on the m + 3 clock pulse. if an error occurs and the qerr output is driven low, it stays low for a minimum of two clock cycles or until reset is driven low. fig 7. timing diagram during norm al operation (reset = high) ck dn, dodtn, dcken qn, qodtn, qcken t su 002aab90 0 ck mm + 1m + 2m + 3m + 4 dcsn t h t pdm , t pdmss ck to q par_in t h t phl , t plh ck to qerr qerr (1) output signal is dependent on the prior unknown event high or low unknown input event t su csgen reset data to qerr latency
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 15 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity (1) after reset is switched from high to low, all data and clock input si gnals must be held at valid logic levels (not floating) for a minimum time of t inact(max) . fig 8. timing diagram during shutdown (reset switches from high to low) ck (1) csgen (1) reset t inact t phl reset to q par_in (1) t plh reset to qerr qerr high, low, or don't care high or low ck (1) dn, dodtn, dcken (1) qn, qodtn, qcken 002aac51 1 dcsn (1)
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 16 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 8. limiting values [1] the input and output negative-voltage ratings may be exc eeded if the input and output current ratings are observed. [2] this value is limited to 2.5 v maximum. 9. recommended operating conditions [1] the differential inputs must not be floating, unless reset is low. [2] the reset input of the device must be held at valid logic leve ls (not floating) to ensure proper device operation. table 6. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +2.5 v v i input voltage receiver [1] [2] ? 0.5 +2.5 v v o output voltage driver [1] [2] ? 0.5 v dd +0.5 v i ik input clamping current v i <0v or v i >v dd - 50 ma i ok output clamping current v o <0v or v o >v dd - 50 ma i o output current continuous; 0 v < v o < v dd - 50 ma i ccc continuous current through each v dd or gnd pin - 100 ma t stg storage temperature ? 65 +150 c v esd electrostatic discharge voltage human body model (hbm); 1.5 k ; 100 pf 2 - kv machine model (mm); 0 ; 200 pf 200 - v table 7. recommended operating conditions symbol parameter conditions min typ max unit v dd supply voltage 1.7 - 2.0 v v ref reference voltage 0.49 v dd 0.50 v dd 0.51 v dd v v t termination voltage v ref ? 0.040 v ref v ref + 0.040 v v i input voltage 0 - v dd v v ih(ac) ac high-level input voltage dn, csr and par_in inputs [1] v ref + 0.250 - - v v il(ac) ac low-level input voltage dn, csr and par_in inputs [1] --v ref ? 0.250 v v ih(dc) dc high-level input voltage dn, csr and par_in inputs [1] v ref + 0.125 - - v v il(dc) dc low-level input voltage dn, csr and par_in inputs [1] --v ref ? 0.125 v v ih high-level input voltage reset , csgen [2] 0.65 v dd --v v il low-level input voltage reset , csgen [2] - - 0.35 v dd v v icr common mode input voltage range ck, ck 0.675 - 1.125 v v id differential input voltage ck, ck 600 - - mv i oh high-level output current seldr either high or low - - ? 8ma i ol low-level output current seldr either high or low - - 8 ma t amb ambient temperature operating in free air SSTUB32868et/g 0 - 70 c SSTUB32868et/s 0 - 85 c
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 17 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 10. characteristics [1] instantaneous is defined as within < 2 ns following the output data transition edge. table 8. characteristics over recommended operating condi tions, unless otherwise noted. symbol parameter conditions min typ max unit v oh high-level output voltage i oh = ? 6ma; v dd = 1.7 v 1.2 - - v v ol low-level output voltage i ol =6ma; v dd =1.7v - - 0.5 v i i input current all inputs; v i =v dd or gnd; v dd =1.9v - - 5 a i dd supply current static standby; reset = gnd; v dd =1.9v; i o =0ma -- 2 ma static operating; reset =v dd ; v dd =1.9v; i o =0ma; v i =v ih(ac) or v il(ac) -- 80ma i ddd dynamic operating current per mhz clock only; reset =v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50 % duty cycle. i o =0ma; v dd =1.8v -16- a per each data input (1 : 1 mode); reset =v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; i o =0ma; v dd =1.8v -19- a per each data input (1 : 2 mode); reset =v dd ; v i =v ih(ac) or v il(ac) ; ck and ck switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; i o =0ma; v dd =1.8v -19- a c i input capacitance dn, csgen, par_in inputs; v i =v ref 250 mv; v dd =1.8v 2.5 - 4 pf dcsn ; v icr =0.9v; v id = 600 mv; v dd =1.8v 2.5 - 4 pf ck and ck ; v icr =0.9v; v id =600mv; v dd =1.8v 2- 3 pf reset ; v i =v dd or gnd; v dd =1.8v 3 - 5 pf z o output impedance normal drive; instantaneous [1] -15- normal drive; steady-state - 53 - high drive; instantaneous [1] -7- high drive; steady-state - 53 - input reset v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -2.5v i i input current v i =v dd ? 5- +5 a i l leakage current v i =v ss ? 100 ? 25 ? 10 a
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 18 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity [1] this parameter is not necessarily production tested. [2] vref must be held at a valid input voltage level, and data inputs must be held low for a minimum time of t act(max) after reset is taken high. [3] vref, data and clock inputs must be held at valid voltage levels (not floating) a minimum time of t inact(max) after reset is taken low. [1] includes 350 ps of test-load transmission line delay. table 9. timing requirements over recommended operating condi tions, unless otherwise noted. symbol parameter conditions min typ max unit f clk clock frequency - - 450 mhz t w pulse width ck, ck high or low 1 - - ns t act differential inputs active time [1] [2] --10ns t inact differential inputs inactive time [1] [3] --15ns t su set-up time dcsn before ck , ck , csr high; csr before ck , ck , dcsn high 0.6 - - ns dcsn before ck , ck , csr low 0.5 - - ns dodtn, dcken ad dn before ck , ck 0.5 - - ns par_in before ck , ck 0.5 - - ns t h hold time dcsn , dodtn, dcken and dn after ck , ck 0.4 - - ns par_in after ck , ck 0.4 - - ns table 10. switching characteristics over recommended operating condi tions, unless otherwise noted. symbol parameter conditions min typ max unit f clk(max) maximum clock frequency input 450 - - mhz t pdm peak propagation delay single bit switching; from ck and ck to qn [1] 1.1 - 1.5 ns t plh low to high propagation delay from ck and ck to qerr 1.2 - 3 ns from reset to qerr --3ns t phl high to low propagation delay from ck and ck to qerr 1- 2.4ns from reset to qn --3ns t pdmss simultaneous switching peak propagation delay from ck and ck to qn [1] --1.6ns table 11. output edge rates over recommended operating condi tions, unless otherwise noted. symbol parameter conditions min typ max unit dv/dt_r rising edge slew rate from 20 % to 80 % 1 - 4 v/ns dv/dt_f falling edge slew rate from 80 % to 20 % 1 - 4 v/ns dv/dt_ absolute difference between dv/dt_r and dv/dt_f (from 20 % to 80 %) or (from 80 % to 20 %) --1v/ns
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 19 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 11. test information 11.1 parameter measurement informati on for data output load circuit v dd =1.8v 0.1 v. all input pulses are supplied by generator s having the following characteristics: pulse repetition rate (prr) 10 mhz; z 0 =50 ; input slew rate = 1 v/ns 20 %, unless otherwise specified. the outputs are measured one at a ti me with one transition per measurement. (1) c l includes probe and jig capacitance. fig 9. load circuit, data output measurements (1) i dd tested with clock and data inputs held at v dd or gnd, and i o =0ma. fig 10. voltage and current waveforms; inputs active and inactive times v id = 600 mv. v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref ? 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 11. voltage waveforms; pulse duration r l = 100 r l = 1000 v dd 50 ck inputs ck ck out dut test point 002aab90 2 test point delay = 350 ps z o = 50 r l = 1000 c l = 30 pf (1) lvcmos reset 10 % i dd (1) t inact v dd 0.5v dd t act 90 % 0 v 002aaa37 2 0.5v dd v icr v icr v ih v il input t w v id 002aaa37 3
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 20 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity v id = 600 mv. v ref =0.5v dd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref ? 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 12. voltage waveforms; setup and hold times t plh and t phl are the same as t pd . fig 13. voltage waveforms; propagat ion delay times (clock to output) t plh and t phl are the same as t pd . v ih =v ref + 250 mv (ac voltage levels) for differential inputs. v ih =v dd for lvcmos inputs. v il =v ref ? 250 mv (ac voltage levels) for differential inputs. v il = gnd for lvcmos inputs. fig 14. voltage waveforms; propagat ion delay times (reset to output) t su v ih v il v id t h ck ck input v ref v ref v icr 002aaa374 v oh v ol output t plh 002aaa37 5 v t v icr v icr t phl ck ck v i(p-p) t phl 002aaa37 6 lvcmos reset output v t 0.5v dd v ih v il v oh v ol
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 21 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 11.2 data output slew rate measurement v dd =1.8v 0.1 v. all input pulses are supplied by generator s having the following characteristics: prr 10 mhz; z 0 =50 ; input slew rate = 1 v/ns 20 %, unless otherwise specified. (1) c l includes probe and jig capacitance. fig 15. load circuit, high -to-low slew measurement fig 16. voltage waveforms, high -to-low slew rate measurement (1) c l includes probe and jig capacitance. fig 17. load circuit, low- to-high slew measurement fig 18. voltage waveforms, low- to-high slew rate measurement c l = 10 pf (1) v dd out dut test point r l = 50 002aaa37 7 v oh v ol output 80 % 20 % dv_f dt_f 002aaa378 c l = 10 pf (1) out dut test point r l = 50 002aaa37 9 v oh v ol 80 % 20 % dv_r dt_r output 002aaa380
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 22 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 11.3 error output load circui t and voltage measurement v dd =1.8v 0.1 v. all input pulses are supplied by generator s having the following characteristics: prr 10 mhz; z 0 =50 ; input slew rate = 1 v/ns 20 %, unless otherwise specified. (1) c l includes probe and jig capacitance. fig 19. load circuit, error output measurements fig 20. voltage waveforms, open-drain output low-to-high transiti on time with respect to reset input fig 21. voltage waveforms, open-drain output high-to-low transiti on time with respect to clock inputs c l = 10 pf (1) v dd out dut test point r l = 1 k 002aaa50 0 0.5v dd t plh v dd 0 v 0.15 v v oh 0 v output waveform 2 reset 002aab903 lvcmos v icr t phl 0.5v dd v dd v ol timing inputs output waveform 1 v i(p-p) v icr 002aab904
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 23 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity fig 22. voltage waveforms, open-drain output low-to-high transiti on time with respect to clock inputs v icr t plh v oh 0 v timing inputs output waveform 2 v i(p-p) v icr 0.15 v 002aab907
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 24 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 12. package outline fig 23. package outline sot932-1 (tfbga176) references outline version european projection issue date iec jedec jeita sot932-1 - - - mo-246 - - - sot932- 1 06-01-11 06-01-16 unit a max mm 1.15 0.35 0.25 0.80 0.65 0.45 0.35 6.1 5.9 15.1 14.9 a 1 dimensions (mm are the original dimensions) t fbga176: plastic thin fine-pitch ball grid array package; 176 balls; body 6 x 15 x 0.7 mm 0 5 10 mm scale a 2 b d e e 2 13.65 e 0.65 e 1 4.55 w 0.08 v 0.15 y 0.1 y 1 0.1 c y c y 1 x ball a1 index area e 2 e 1/2 e b e 1 e 1/2 e a c b ? v m c ? w m a b c d e f h k g l j m n p r t u v w y aa ab 2468 1357 ball a1 index area b a d e detail x a a 2 a 1
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 25 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 26 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 24 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 2 and 13 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 24 . table 12. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 13. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 27 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations 15. revision history msl: moisture sensitivity level fig 24. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 14. abbreviations acronym description cmos complementary metal-oxide semiconductor ddr2 double data rate 2 dimm dual in-line memory module dram dynamic random access memory lvcmos low voltage complementary metal-oxide semiconductor rdimm registered dual in-line memory module sstl stub series terminated logic table 15. revision history document id release date data sheet status change notice supersedes SSTUB32868_4 20100422 product data sheet SSTUB32868_3 modifications: ? section 2 ? features and benefits ? : deleted (old) second bullet item ? table 8 ? characteristics ? : added sub-section ?input reset ? SSTUB32868_3 20070307 product data sheet - SSTUB32868_2 SSTUB32868_2 20060912 product data sheet - SSTUB32868_1 SSTUB32868_1 20060825 product data sheet - -
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 28 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 16.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer?s third party customer(s) (hereinafter both referred to as ?application?). it is customer?s sole responsibility to check whether the nxp semiconductors product is suitable and fit for the application planned. customer has to do all necessary testing for the application in order to avoid a default of the application and the product. nxp semiconducto rs does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicond uctors product is au tomotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive sp ecifications and standards, customer (a) shall use the product without nx p semiconductors? warranty of the document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
SSTUB32868_4 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 04 ? 22 april 2010 29 of 30 nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors SSTUB32868 1.8 v ddr2-800 configurable registered buffer with parity ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 22 april 2010 document identifier: SSTUB32868_4 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 functional description . . . . . . . . . . . . . . . . . . 10 7.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.2 functional information . . . . . . . . . . . . . . . . . . 11 7.3 register timing . . . . . . . . . . . . . . . . . . . . . . . . 13 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 9 recommended operating conditions. . . . . . . 16 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 19 11.1 parameter measurement information for data output load circuit . . . . . . . . . . . . . . . . . . 19 11.2 data output slew rate measurement. . . . . . . . 21 11.3 error output load circuit and voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . 22 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 13 soldering of smd packages . . . . . . . . . . . . . . 25 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 25 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 25 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 16 legal information. . . . . . . . . . . . . . . . . . . . . . . 28 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17 contact information. . . . . . . . . . . . . . . . . . . . . 29 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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