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cym9275 cym9276a cym9277b cym9278 64k x 36 sram module 128k x 36 sram module 256k x 36 sram module 512k x 36 sram module cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 april 2, 2001 1cym9277 features ? operates at 133 mhz uses 64k x 18 / 128k x 18 or 256k x 18 high-performance synchronous srams 144-position angled dimm from berg p/n 61178 3.3v inputs/data outputs functional description the cym9275, cym9276a, cym9277b, and the cym9278 are high-performance synchronous pipelined memory mod- ules organized as 64k, 128k, 256k, 512k by 36 bits. these modules are constructed using either 128k x 18 srams (9275, 9276a, 9277b) or 256k x 18 srams (9278) in plastic surface mount packages on an epoxy laminate board with pins. the modules are designed to be incorporated into large memory arrays. the modules are configured as single banks or multiple banks depending on the sram used to make the module. separate clock are provided for each of the banks. separate clocks are provided for each of the srams. multiple ground pins and on-board decoupling capacitors en- sure high performance with maximum noise immunity. all components on the cache modules are surface mounted on a multi-layer epoxy laminate (fr-4) substrate. the contact pins are plated with 150 micro-inches of nickel covered by 30 micro-inches of gold flash. logic block diagram - cym9275 d[0:31] dq[0:3] a[15:0] cs bw[0:3] pd 1 pd 0 gnd nc d[0:15] dq[0:1] clk oe we 64kx36 (2) 128k x 18 srams clk[0:1] weh wel adsc a 15:0 sgw oe cs clk[0:1] bwe bank 0 bank0 adsp cs oe
cym9275 cym9276a cym9277b cym9278 2 logic block diagram - cym9276a d[0:31] dq[0:3] a[16:0] cs[0:1] bw[0:3] pd 1 pd 0 nc gnd 9276a d[0:15] dq[0:1] clk adsc a 16:0 sgw oe cs d[0:15] dq[0:1] clk oe[0:1] we 128kx36 (2) 128k x 18 srams (2) 128k x 18 srams clk[0:1] clk[2:3] weh wel adsc a 16:0 sgw oe cs weh wel clk[0:3] bwe bwe bank0 bank1 bank0 adsp cs1 cs0 oe1 oe0
cym9275 cym9276a cym9277b cym9278 3 selection guide part number synchronous cache module cym9275 cym9276a cym9277b cym9278 133 100 133 100 133 100 133 100 module size 64 k x 72 128 k x 72 256 k x 72 512 k x 72 srams used 4 of 128k x 18 (high address bit tied off) 8 of 128k x 18 (high address bit tied off) 8 of 128k x 18 8 of 256k x 18 system clock (mhz) 133 100 133 100 133 100 133 100 data t co 4.5 ns 5.5 ns 4.5 ns 5.5 ns 4.5 ns 5.5 ns 4.5 ns 5.5 ns logic block diagram- cym9277b / cym9278 d[0:31] dq[0:3] a[17:0] cs[0:1] bw[0:3] pd 1 pd 0 9277b/9278 d[0:15] dq[0:1] clk oe[0:1] we (2) 256k x 18 srams clk[0:1] weh wel adsc a 17:0 sgw oe cs clk[0:3] bwe bank1 d[0:15] dq[0:1] clk (2) 256k x 18 srams weh wel adsc a 17:0 sgw oe cs bwe adsp bank0 clk[2:3] 512kx36 bank0 and 1 nc nc cs[0] cs[1] oe1 oe0 256kx36 gnd gnd bank0
cym9275 cym9276a cym9277b cym9278 4 pin configuration top view dual read-out simm (dimm) 10 9 56 7 8 4 1 2 gnd gnd v cc3 3 90 89 85 86 87 88 84 81 82 83 20 19 15 16 17 18 14 11 12 13 30 29 25 26 27 28 24 21 22 d 30 d 28 d 24 d 22 d 26 23 39 35 36 37 38 34 31 32 d 20 d 14 d 12 dq 1 d 18 33 40 41 42 52 51 47 48 49 50 46 43 44 d 8 d 6 d 4 d 0 a 3 d 2 45 57 58 59 60 56 53 54 a 5 gnd a 2 55 69 65 66 67 68 64 61 62 gnd 63 70 79 75 76 77 78 74 71 72 73 80 gnd d 21 100 99 95 96 97 98 94 91 92 93 d 29 d 23 d 27 d 25 110 109 105 106 107 108 104 101 102 103 d 19 d 17 d 15 d 13 120 119 115 116 117 118 114 111 112 113 d 11 121 122 d 9 d 7 d 5 d 3 d 1 127 128 129 130 126 123 124 125 gnd a 6 140 139 135 136 137 138 134 131 132 133 pd 0 a 4 144 141 142 143 a 9 a 16 a 12 a 13 d 16 gnd cs[0] a 8 a 10 a 14 a 15 pd 1 v cc3 v cc3 a 1 a 0 a 7 a 11 v cc3 gnd clk0 clk1 v cc3 d 10 clk3 clk2 v cc3 gnd gnd d 31 gnd gnd dq 0 dq 2 dq 3 gnd gnd a 17 nc nc gnd bw[2] cs[1] oe[1] adsp nc nc nc v cc3 v cc3 v cc3 bw[3] we gnd gnd gnd nc nc nc gnd gnd gnd gnd gnd v cc3 v cc3 v cc3 v cc3 oe[0] bw[0] gnd bw[1] gnd v cc3 nc nc nc nc nc nc nc nc nc nc nc nc gnd gnd v cc3 nc gnd nc nc nc nc v cc3 nc nc nc nc nc
cym9275 cym9276a cym9277b cym9278 5 pin definitions signal description v cc3 3v supply gnd ground a[17:0] addresses from processor adsp address strobe from the processor oe[1:0] output enables for each of the banks bw[0:3] byte writes we global write cs [1:0] chip select for the two banks pd 0 ?pd 1 presence detect output pins d[31:0] data lines from processor dq[3:0] data parity lines from processor clk[0:3] clock lines to the module nc signal not connected on module rsvd reserved presence detect pins pd 1 pd 0 cym9275 ? 64k x 36 gnd nc cym9276a ? 128k x 36 nc gnd cym9277b ? 256k x 36 gnd gnd cym9278 ? 512k x 36 nc nc
cym9275 cym9276a cym9277b cym9278 6 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?55c to +125c ambient temperature with power applied......................................... ?0c to +70c 3.3v supply voltage to ground potential...... ?0.5v to +4.5v dc voltage applied to outputs in high z state .............................................. ?0.5v to +4.6v dc input voltage ........................................... ?0.5v to +4.6v output current into outputs (low)............................. 20 ma operating range range ambient temperature v cc commercial 0c to +70c 3.3v 5% electrical characteristics over the operating range parameter description test condition min. max. unit v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage ?0.3 0.8 v v oh output high voltage v cc = min. i oh = ? 4 ma 2.4 v v ol output low voltage v cc = min. i ol = 8 ma 0.4 v i cc (9275) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 350 ma i cc (9276a) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 500 ma i cc (9277b) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 1000 ma i cc (9278) v cc operating supply current v cc = max., i out = 0 ma, f = f max = 1/t rc 1200 ma capacitance [1] parameter description test conditions part no. max. unit c a address input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 9275 12 pf 9276a 7 9277b 14 9278 20 c i control input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 9275 12 9276a 8 9277b 16 9278 20 c o input / output capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 9275 9 9276a 5 9277b 10 9278 16 c clk clock capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 9275 6 9276a 3 9277b 3 9278 5 note: 1. tested initially and after any design or process changes that may affect these parameters.
cym9275 cym9276a cym9277b cym9278 7 ac test loads and waveforms [3] 3.3v gnd 90% 10% 90% 10% 3ns 3 ns output r1 r2 5pf including jigand scope (a) (b) all input pulses output r l = 50 ? v l = 1.5v v ccq [2] switching characteristics over the operating range parameter description cym9275/76a/77b/78 133 mhz 100 mhz min. max. min. max. unit t cyc clock cycle time 7.5 10 ns t ch clock high 1.9 3.5 ns t cl clock low 1.9 3.5 ns t as address set-up before clk rise 2 2 ns t ah address hold after clk rise 0.5 0.5 ns t co data output valid after clk rise 4.5 5.5 ns t doh data output hold after clk rise 3 3 ns t ads adsp , adsc set-up before clk rise 2 3.1 ns t adsh adsp , adsc hold after clk rise 0. 5 0.5 ns t wes wh , wl set-up before clk rise 2 2 ns t weh wh , wl hold after clk rise 0.5 0.5 ns t ds data input set-up before clk rise 2 2 ns t dh data input hold after clk rise 0.5 0.5 ns t css chip select set-up 2 2 ns t csh chip select hold after clk rise 0.5 0.5 ns t eoz oe high to output high z [4] 77ns t eov oe low to output valid 4.5 5.5 ns notes: 2. resistor values for v ccq = 3.3v are r1 = 317 ? and r2 = 351 ? . 3. unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and load capacitance. shown in (a) and (b) of ac test loads. all measurements are made at room temperature. 4. t eoz is specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage.
cym9275 cym9276a cym9277b cym9278 8 switching waveforms write adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data- in t cyc t ch t cl t ads t adh t ads t adh t advs t advh wd1 wd2 wd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh 2b 3a 1a single write burst write unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don?t care = undefined pipelined write 2a 2c 2d t dh t ds high-z high-z unselected with ce 2 adv must be inactive for adsp write adsc initiated write
cym9275 cym9276a cym9277b cym9278 9 read [5, 6, 7] notes: 5. oe is low throughout this operation. 6. if adsp is asserted while cs is high, adsp will be ignored. 7. adsp has no effect on adv , wl , and wh if cs is high. switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 2a 2c 1a data out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 rd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t co t eov 2b 2c 2d 3a 1a t oehz t doh t clz t chz single read burst read unselected adsp ignored with ce 1 inactive suspend burst ce 1 masks adsp = don?t care = undefined pipelined read adsc initiated read unselected with ce 2
cym9275 cym9276a cym9277b cym9278 10 read / write switching waveforms (continued) adsp clk adsc adv add ce 1 oe gw we ce 2 ce 3 1a data in/out t cyc t ch t cl t ads t adh t ads t adh t advs t advh rd1 wd2 rd3 t ah t as t ws t wh t wh t ws t ces t ceh t ces t ceh t ces t ceh t eolz t co t eov 3a 3c 3d 1a t eohz t doh t chz single read burst read unselected adsp ignored with ce 1 inactive ce 1 masks adsp = don?t care = undefined pipelined read out 2a in 3b out out out out single write t ds t dh 2a out see note.
cym9275 cym9276a cym9277b cym9278 11 switching waveforms (continued) t as = don?t care = undefined t clz t chz t doh clk add we ce 1 data in/out adsc adsp adv ce oe d(c) t cyc t ch t cl t ads t adh t ceh t ces t weh t wes t co pipeline timing adsp ignored with ce 1 high rd1 rd2 rd3 rd4 wd1 wd2 wd3 wd4 1a out 2a out 3a out 4a out 1a in 2a in 3a in 4a in back to back reads adsp initiated reads adsc initiated reads
cym9275 cym9276a cym9277b cym9278 12 document #: 38-m-00083-*b ordering information speed (mhz) ordering code package name package type description operating range 100 cym9275pm-100c pm45 144-pin dual-readout simm (dimm) sync 64k x 72 commercial cym9276apm-100c pm45 144-pin dual-readout simm (simm) sync 128k x 72 cym9277bpm-100c pm46 144-pin dual-readout simm (dimm) sync 256k x 72 cym9278pm-100c pm46 144-pin dual-readout simm (dimm) sync 512k x 72 133 cym9275pm-133c pm45 144-pin dual-readout simm (dimm) sync 64k x 72 cym9276apm-133c pm45 144-pin dual-readout simm (simm) sync 128k x 72 cym9277bpm-133c pm46 144-pin dual-readout simm (dimm) sync 256k x 72 CYM9278PM-133C pm46 144-pin dual-readout simm (dimm) sync 512k x 72 package diagrams 144-pin single-sided dimm pm45
cym9275 cym9276a cym9277b cym9278 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagrams 144-pin dual-sided dimm pm46

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