View CLRC66301TRAYB_1155459.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. introduction remark: the information contained in this data sheet is to provide a preview of the contactless reader ic and must be regarded as a provisional advance specification. the complete overview will soon be available in a new revision. this document describes the functionality and electrical specificati ons of the contactless reader/writer ic clrc663. 2. general description the clrc663 is a highly integrated transceiver ic for contactless communication at 13.56 mhz. this transceiver ic utilizes an outstanding modulati on and demodulation concept completely integrated for different kinds of contactless communication methods and protocols at 13.56 mhz. the clrc663 transceiver ics support the following operating modes ? read/write mode supporting iso/iec 14443a/mifare ? read/write mode supporting iso/iec 14443b ? read/write mode supporting jis x 6319-4 (comparable with felica 1 (see section 30.5 ) scheme) ? passive initiator mode ac cording to iso/iec 18092 ? read/write mode supporting iso/iec 15693 ? read/write mode supporting icode epc uid/ epc otp ? read/write mode supporting iso/iec 18000-3 mode 3 the clrc663?s internal transmitter is able to drive a reader/writer antenna designed to communicate with iso/iec 14443a/mifare cards and transponders without additional active circuitry. the receiver module provid es a robust and efficient implementation for demodulating and decoding signals from iso 14443a/mifare compatible cards and transponders. the digital module manages the complete iso 14443a framing and error detection functionality (parity and crc). the clrc663 supports mifare 1k, mi fare 4k, mifare ultralight, mifare ultralight c, mifare plus and mifare desfire products. the clrc663 supports contactless communication and uses the mifare higher transfer speeds of up to 848 kbit/s in both directions. clrc663 contactless reader ic rev. 2.0 ? 15 june 2011 171120 preliminary data sheet public 1. in the following the word felica is used for jis x 6319-4
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 2 of 125 nxp semiconductors clrc663 contactless reader ic the clrc663 supports all layers of the iso/iec 14443b reader/writer communication scheme provided that: ? additional components, such as oscillators, power supplies and coils etc. are correctly implemented ? standard protocols are used, such as is o/iec 14443-4 and/or iso/iec 14443b anticollision the use of this nxp ic according to is o/iec 14443b could infringe upon third party patent rights. consequently, a purchaser mu st ensure that the appropriate third party patent licenses are obtained. when the clrc663 transceiver ic is enabled in the read/write mode for felica, it supports the felica communicati on scheme. the receiver part provides the demodulation and decoding circuitry for felica coded sign als. the digital part handles the felica framing and erro r detection such as crc. the clrc663 supports contactless communication using felica higher transfer speeds of up to 424 kbit/s in both directions. the clrc663 accommodates future development by supporting the p2p passive initiator mode in accordance with iso/iec 18092. the clrc663 supports vicinity protocol according iso/iec15693, epc uid and iso/iec 18000-3 mode 3. the complete vicini ty product family of nxp is supported and enable a readability for mid- ranger reader applications the following host interfaces are provided: ? serial peripheral interface (spi) ? serial uart (similar to rs232 with voltage levels dependent on pin voltage supply) ? i 2 c-bus interface (two version are implemented: i2c and i2cl) 3. features and benefits ? highly integrated analog circuitry to demodulate and decode responses ? buffered output drivers for connecting an antenna with the minimum number of external components ? supports iso/iec 14443 a/mifare, iso/ iec 14443 b and felica, p2p passive initiator mode in accordance with iso/iec 18092 ? supports iso/iec15693, icode epc uid and iso/iec 18000-3 mode 3 ? typical operating distance in read/write mode for communication to a iso/iec 14443a/mifare up to 12 cm depending on the antenna size and tuning ? supports mifare classic encryp tion in read/write mode ? supports higher transfer speed communication up to 848 kbit/s ? supported host interfaces ? spi up to 10 mbit/s ? two i 2 c-bus interfaces up to 400 kbd in fast mode, up to 1000 kbd in fast mode plus ? rs232 serial uart up to 1228.8 kbd, with voltage levels dependent on pin voltage supply ? fifo buffer handles 512 byte send and receive
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 3 of 125 nxp semiconductors clrc663 contactless reader ic ? flexible inte rrupt modes ? hard power down ? standby mode ? programmable and cascadable timers ? oscillator circuit for connection to 27.12 mhz quartz crystal ? 3.3 v to 5 v power supply with integrated voltage regulators for 1.8 v analog and digital core supplies ? free programmable i/o pins (gpio0/sigin; sigout) ? integern pll providing clock for standard microcontroller used frequencies ? low power card detection ? boundary scan interface ? integrated free -running low power oscillator ? true random number generator 4. quick reference data [1] v dd(pvdd) must always be the same or lower voltage than v dd . [2] i pd are the total currents over all supplies. [3] i dd(tvdd) depends on v dd(tvdd) and the external circuitry connected to tx1 and tx2. [4] during typical circuit operation, the overall current is below 100 ma. [5] typical value using a complementary driv er configuration and an antenna matched to 40 ? between pins tx1 and tx2 at 13.56 mhz. 5. ordering information [1] delivered in one tray. [2] delivered in five trays. table 1. quick reference data symbol parameter conditions min typ max unit v dd supply voltage 3 5 5.5 v v dd(tvdd) tvdd supply voltage [1] 355.5v v dd(pvdd) pvdd supply voltage 3 5 5.5 v i pd power-down current pdown pin pulled high [2] 840na i vdd supply current 17 20 ma i dd(tvdd) tvdd supply current [3] [4] [5] 100 200 ma t amb ambient temperature ? 25 +85 ? c table 2. ordering information type number package name description version clrc66301hn1/trayb [1] hvqfn33 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5 ? 5 ? 0.85 mm sot617-1 clrc66301hn1/traybm [2]
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 4 of 125 nxp semiconductors clrc663 contactless reader ic 6. block diagram the analog interface handles the modulation an d demodulation of the antenna signals for the contactless interface. the contactless uart manages the protocol dependency of the contactless interface settings managed by the host. the fifo buffe r ensures fast and convenient data transfer to and from the host and the contactless uart and vice versa. various host interfaces are implemented to meet different customer requirements. fig 1. simplified block diagram of the clrc663 001aaj627 host antenna fifo buffer analog interface contactless uart serial uart spi i 2 c-bus register bank
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 5 of 125 nxp semiconductors clrc663 contactless reader ic fig 2. detailed block diagram of the clrc663 001aam005 i 2 c, logical ram (fifo) 512 bytes registers statemachines eeprom 8 kbyte spi sam interface voltage regulator 3/5 v => 1.8 v dvdd por adc pll lpo rx osc tx voltage regulator 3/5 v => 1.8 v avdd rng analogue front-end boundary scan if0 ifsel0 ifsel1 if1 if2 if3 tck tdi tms tdo reset logic pdown/ reset i 2 c rs232 spi host interfaces interrupt controller irq gpio1/sigin timer1 crc gpio timer2/ woc sigpro tx codec rx decod cl- copro sigin/ sigout control sigout vmid rxn rxp tx1 tx2 xtal1 xtal2 sda2 scl2 vdd vss pvdd tvdd tvss aux1 aux2 avdd dvdd clkout clrc663
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 6 of 125 nxp semiconductors clrc663 contactless reader ic 7. pinning information 7.1 pin description fig 3. pinning configuration hvqfn33 (sot617-1) v ss on heatsink 001aam004 clrc663 33 vss transparent top view tx1 dvdd vdd tvdd sigout xtal1 gpio0 xtal2 tck pdown tms clkout tdi scl2 tdo sda2 avdd aux1 aux2 rxp rxn vmid tx2 tvss irq if3 - sda if2 if1 if0 ifsel1 ifsel0 pvdd 8 17 7 18 6 19 5 20 4 21 3 22 2 23 1 24 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 terminal 1 index area table 3. pin description pin symbol type description 1 tdo o test data output for boundary scan interface 2 tdi i test data input boundary scan interface 3 tms i/o test mode select boundary scan interface 4 tck i test clock boundary scan interface 5 gpio0/sigin i/o general purpose i/o 6 sigout o analog signal output 7 dvdd o digital power supply buffer 8 vdd pwr power supply 9 avdd o analog power supply buffer 10 aux1 o auxiliary outputs: pin is used for analog test signal 11 aux2 o auxiliary outputs: pin is used for analog test signal 12 rxp i receiver input pin for the received rf signal. 13 rxn i receiver input pin for the received rf signal. 14 vmid i/o internal receiv er reference voltage 15 tx2 o transmitter 1: delivers the modulated 13.56 mhz carrier 16 tvss pwr transmitter ground 17 tx1 o transmitter 2: delivers the modulated 13.56 mhz carrier 18 tvdd pwr transmitter voltage supply 19 xtal1 i oscillator input 20 xtal2 i oscillator input
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 7 of 125 nxp semiconductors clrc663 contactless reader ic [1] the pin functionality for the interfaces is explained in section 10 ? digital interfaces ? . 21 pdown/reset i reset and power-d own: when high, internal vo ltage regulator is switched off, the oscillator is stopped, and t he input pads are disconnected from the outside world. with a positive edge on this pin the internal reset phase starts. refer to table 1 ? quick reference data ? 22 clkout o clock output. 23 scl2 o serial clock line [1] 24 sda2 i serial data line [1] 25 pvdd i/o pad power supply 26 ifsel0 i/o interface selection 0 27 ifsel1 i/o interface selection 1 28 if0 i/o interface pin [1] 29 if1 i/o interface pin [1] 30 if2 i/o interface pin [1] 31 if3 - sda i/o interface pin [1] 32 irq o interrupt request: output to signal an interrupt event 33 vss pwr ground and heatsink connection table 3. pin description ?continued pin symbol type description
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 8 of 125 nxp semiconductors clrc663 contactless reader ic 8. functional description the clrc663 has the following read/write operating modes that support: ? iso/iec14443a/mifare ? iso/iec14443b ? felica ? iso/iec15693/icode ? icode epc uid ? iso/iec18000-3 mode 3 in the read/write mode the clrc663 enables the communication to a contactless iso 14443 a/mifare, iso 14443b or felica card . when using this n xp ic according to iso/iec 14443b no additional license fees will come up. 8.1 iso/iec14443a/mifare re ad/write functionality the physical level communication is shown in figure 5 . the physical parameters are described in ta b l e 4 . fig 4. read/write mode 001aal996 battery/power supply reader/writer contactless card microcontroller clrc663 iso/iec 14443 a card (1) reader to card 100 % ask, miller coded, transfer speed 106 kbit/s to 848 kbit/s (2) card to reader, subcarrier load modulat ion manchester coded or bpsk, transfer speed 106 kbit/s to 848 kbit/s fig 5. iso/iec 14443 a/mifare read/w rite mode communication diagram (1) (2) 001aam268 clrc663 iso/iec 14443 a card iso/iec 14443 a reader
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 9 of 125 nxp semiconductors clrc663 contactless reader ic the clrc663?s contactless uart and dedicated external host must manage the complete iso/iec 14443 a/mifare protocol. figure 6 shows the data coding and framing according to is o/iec 14443a /mifare. the internal crc coprocessor calculates the crc value based on iso/iec 14443 a part 3 and handles parity generation internally according to the transfer speed. automatic parity generation can be switched off using the txbitmode register -txparityen bit. 8.2 iso/iec14443b read /write functionality the physical level communication is shown in figure 7 . table 4. communication overview for is o/iec 14443 a/mifare reader/writer communication direction signal type transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s reader to card (send data from the clrc663 to a card) fc = 13.56 mhz reader side modulation 100 % ask ask ask ask bit encoding modified miller encoding modified miller encoding modified miller encoding modified miller encoding bit rate [kbit/s] fc/128 fc/64 fc/32 fc/16 card to reader (clrc663 receives data from a card) card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation baseband load modulation subcarrier frequency fc/16fc/16fc /16fc/16 bit encoding manchester encoding bpsk bpsk bpsk fig 6. data coding and framing according to iso/iec 14443 a 001aak585 iso/iec 14443 a framing at 106 kbd 8-bit data 8-bit data 8-bit data odd parity odd parity start odd parity start bit is 1 iso/iec 14443 a framing at 212 kbd, 424 kbd and 848 kbd 8-bit data 8-bit data 8-bit data odd parity odd parity start even parity start bit is 0 burst of 32 subcarrier clocks even parity at the end of the frame
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 10 of 125 nxp semiconductors clrc663 contactless reader ic the physical parameters are described in ta b l e 5 . the contactless uart of clrc663 and a dedicated external host are required to handle the complete iso/iec 14443b protocol. the following figure 8 ? data coding and framing according to iso/iec 14443 b ? shows the data coding and framing according to iso/iec 14443b sof and eof. (1) reader to card nrz, miller coded, transfer speed 106 kbit/s to 848 kbit/s (2) card to reader, subcarrier load modulation manchester coded or bpsk, transfer speed 106 kbit/s to 848 kbit/s fig 7. iso/iec 14443 a/mifare read/w rite mode communication diagram (1) (2) 001aal997 clrc663 iso/iec 14443 b card iso/iec 14443 b reader table 5. communication overview fo r iso/iec 14443 b reader/writer communication direction signal type transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s reader to card (send data from the clrc663 to a card) fc = 13.56 mhz reader side modulation 10 % ask 10 % ask 10 % ask 10 % ask bit encoding nrz nrz nrz nrz bit rate [kbit/s] 128 / fc 64 / fc 32 / fc 16 / fc card to reader (clrc663 receives data from a card) card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency fc/16fc/16fc /16fc/16 bit encoding bpsk bpsk bpsk bpsk fig 8. data coding and framing according to iso/iec 14443 b 001aam270 unmodulated (sub) carrier start of frame (sof) sequence 9.44 s ''0'' ''0'' 0 - 9.44 s ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''1'' ''1'' data last character unmodulated (sub) carrier end of frame (eof) sequence 9.44 s ''0'' ''0'' 0 - 9.44 s ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 11 of 125 nxp semiconductors clrc663 contactless reader ic 8.3 felica read/write functionality the felica mode is the general reader/writer to ca rd communication scheme according to the felica specification. the communication on a physical level is shown in figure 9 . the physical parameters are described in ta b l e 6 . the contactless uart of clrc663 and a dedicated external host controller are required to handle the comple te felica protocol. 8.3.1 felica framing and coding to enable the felica communication a 6 byte preamble (00h , 00h, 00h, 0 0h, 00h, 00h) and 2 bytes sync bytes (b2h, 4dh) are sent to synchronize the receiver. the following len byte indicates the length of t he sent data bytes plus the len byte itself. the crc calculation is done according to th e felica definitions with the msb first. to transmit data on the rf interface, the host controller has to send the len- and data- bytes to the clrc663's fifo-buffer. the preamble and the sync bytes are generated by the clrc663 automatically and must not be writ ten to the fifo by the host controller. the clrc663 performs internally th e crc calculation and adds the result to the data frame. example for felica crc calculation: fig 9. felica read/write communication diagram table 6. communication overview for felica reader/writer communication direction signal type transfer speed felica felica higher transfer speeds 212 kbit/s 424 kbit/s reader to card (send data from the clrc663 to a card) fc = 13.56 mhz reader side modulation 8 to 30 % ask 8 to 30 % ask bit encoding manchester encoding manchester encoding bit rate fc/64 fc/31 card to reader (clrc663 receives data from a card) card side load modulation 30/h^1.2 (h = field strength [a/m]) 30/h^1.2 (h = field strength [a/m]) bit encoding manchester encoding manchester encoding 001aam271 felica reader (pcd) clrc663 felica card (picc) 1. pcd to picc 8-30 % ask manchester coded, baudrate 212 to 424 kbaud 2. picc to pcd, > 12 % loadmodulation manchester coded, baudrate 212 to 424 kbaud table 7. felica framing and coding preamble sync len n-data crc 00h 00h 00h 00h 00h 00h b2h 4dh table 8. start value for the c rc polynomial: (00h), (00h) preamble sync len 2 data bytes crc 00h 00h 00h 00h 00h 00h b2h 4dh 03h abh cdh 90h 35h
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 12 of 125 nxp semiconductors clrc663 contactless reader ic 8.4 iso/iec15693 read/write functionality the physical parameters are described in ta b l e 9 . [1] fast inventory (page) read command only (icode proprietary command). table 9. communication overview for iso/ie c 15693 reader/writer reader to label communication direction signal type transfer speed fc/8192 kbit/s fc/512 kbit/s reader to label (send data from the clrc663 to a card) reader side modulation 10 to 30 % ask or 100 % ask 10 to 30 % ask 90 % to 100 % ask bit encoding 1/256 1/4 bit length 4.833 ms 302.08 ? s table 10. communication overview for iso/ie c 15693 reader/writer label to reader communication direction signal type transfer speed 6.62 (6.67) kbit/s 13.24 kbit/s [1] 26.48 (26.69) kbit/s 52.96 kbit/s label to reader (clrc663 receives data from a card) fc = 13.56 mhz card side modulation single (dual) subcarrier load modulation ask single subcarrier load modulation ask single (dual) subcarrier load modulation ask single subcarrier load modulation ask bit length ? s 151.06 (149.84) 75.52 37.76 (3.746) 18.88 bit encoding manchester coding manchester coding manchester coding manchester coding subcarrier frequency [mhz] fc/32 (fc/28) fc/32 (fc/28) fc/ 32 (fc/28) fc/32 (fc/28) fig 10. data coding and framing according to iso/iec 15693. standard mode reader to label 001aam272 pulse modulated carrier ~9.44 s 0 1 2 3 4 ~18.88 s . 2 . . . . . . . . . . . . . . . . . 2 2 . . . . . 2 2 25 555 5 ~4,833 ms 3 245
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 13 of 125 nxp semiconductors clrc663 contactless reader ic 8.5 epc-uid/uid-otp re ad/write functionality the physical parameters are described in ta b l e 11 . data coding and framing according epc global 13.56 mhz ism band class 1 radio frequency identification tag interface specification (candidate recommendation, version 1.0.0). 8.6 iso/iec18000-3 mode 3 read/write functionality this section intent ionally left blank. 8.7 iso/iec 18092 mode the iso/iec 18092 communication for passive communication mode. ? passive communication mode means that the target answers to an initiator command in a load modulation scheme. th e initiator is active in terms of generating the rf field. ? initiator: generates rf field at 13.56 mhz and starts the iso/iec 18092 communication. ? target: responds to initiator command either in a load modulation scheme in passive communication mode or using a self generat ed and self modulated rf field for active communication mode. the clrc663 supports passive initiator communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the iso/iec 18092 standard. table 11. communication overview for epc/uid communication direction signal type transfer speed 26.48 kbit/s 52.96 kbit/s reader to card (send data from the clrc663 to a card) reader side modulation 10 % to 30 % ask bit encoding rtz bit length 37.76 ? s card to reader (clrc663 receives data from a card) card side modulation single subcarrier load modulation bit length 18.88 ? s bit encoding manchester coding
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 14 of 125 nxp semiconductors clrc663 contactless reader ic 8.7.1 passive communication mode passive communication mode means that the targ et answers to an initiator command in a load modulation scheme. the initiator is active meaning generating the rf field. the contactless uart of clrc663 and a dedica ted host controller are required to handle the iso/iec 18092 passive initiator protocol. note: transfer speeds above 424 kbit/s are not defined in the iso/iec 18092 standard. the clrc663 supports these transfer speeds only with dedicated external circuits. fig 11. passive communication mode table 12. communication overview for passive communication mode communication direction 106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s 1.69 mbit/s, 3.39 mbit/s initiator ? target according to iso/iec 14443a 100 % ask, modified miller coded according to felica, 8 % to 30 % ask manchester coded digital capability to handle this communication ta r g e t ? initiator according to iso/iec 14443a subcarrier load modulation, manchester coded according to felica, > 12 % ask manchester coded host nfc initiator powered to generate rf field 1. initiator starts communication at selected transfer speed 2. targets answers using load modulated data at the same transfer speed host nfc target powered for digital processing 001aan217
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 15 of 125 nxp semiconductors clrc663 contactless reader ic 8.7.2 iso/iec 18092 framing and coding the iso/iec 18092 framing and coding in pass ive communication mode is defined in the iso/iec 18092 standard. 8.7.3 iso/iec 18092 protocol support the iso/iec 18092 protocol is not completely described in this document. for a detailed explanation of the protocol, refer to the is o/iec 18092 standard. however the data link layer is in accordance with the following policy: ? speed shall not be changed while continuum data exchange in a transaction. ? transaction includes initializ ation and anti-collision met hods and data exchange (in continuous way, meaning no interruption by another transaction). table 13. framing and coding overview transfer speed framing and coding 106 kbit/s according to the iso/iec 14443a/mifare scheme 212 kbit/s according to the felica scheme 424 kbit/s according to the felica scheme
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 16 of 125 nxp semiconductors clrc663 contactless reader ic 9. clrc663 registers 9.1 register bit behavior depending on the functionality of a register, the access conditions to the register can vary. in principle, bits with same behavior are grouped in common registers. the access conditions are described in ta b l e 1 4 . table 14. behavior of register bits and their designation abbreviation behavior description r/w read and write these bits can be writte n and read via the host interface. since they are used only for contro l purposes, the content is not influenced by the state machines but can be read by internal state machines. dy dynamic these bits can be written and re ad via the host interface. they can also be written automatically by internal state machines, for example command_reg register changes its value automatically after the execution of the command. r read only these register bits indicates hold values which are determined by internal states only. w write only reading these register bits always returns zero. rfu - these registers are reserved for future use and must not be changed. in case of a write access, it is recommended to write the value ?0?. table 15. clrc663 registers overview address register name function 00h command_reg starts and stops command execution 01h hostctrl_reg host control register 02h fifocontrol_reg control register of the fifo 03h waterlevel_reg defines the level of the fifo underflow and overflow warning 04h fifolength_reg defines the length of the fifo 05h fifodata_reg data in/out exchange register of fifo buffer 06h irq0_reg interrupt register 0 07h irq1_reg interrupt register 1 08h irq0en_reg interrupt enable register 0 09h irq1en_reg interrupt enable register 1 0ah error_reg error bits showing the error status of the last command execution 0bh status_reg contains status of the communication 0ch rxbitctrl_reg control register for anticollis ion adjustments for bit oriented protocols 0dh rxcoll_reg collision position register 0eh tcontrol_reg control of timer the timer section 0fh t0control_reg control of timer0 10h t0reloadhi_reg high byte of the reload value of timer0 11h t0reloadlo_reg low byte of the reload value of timer0 12h t0countervalhi_reg counter value high byte of timer0 13h t0countervallo_reg counter value low byte of timer0
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 17 of 125 nxp semiconductors clrc663 contactless reader ic 14h t1control_reg control of timer1 15h t1reloadhi_reg high byte of the reload value of timer1 16h t1reloadlo_reg low byte of the reload value of timer1 17h t1countervalhi_reg counter value high byte of timer1 18h t1countervallo_reg counter value low byte of timer1 19h t2control_reg control of timer2 1ah t2reloadhi_reg high byte of the reload value of timer2 1bh t2reloadlo_reg low byte of the reload value of timer2 1ch t2countervalhi_reg counter value high byte of timer2 1dh t2countervallo_reg counter value low byte of timer2 1eh t3control_reg control of timer3 1fh t3reloadhi_reg high byte of the reload value of timer3 20h t3reloadlo_reg low byte of the reload value of timer3 21h t3countervalhi_reg counter value high byte of timer3 22h t3countervallo_reg counter value low byte of timer3 23h t4control_reg control of timer4 24h t4reloadhi_reg high byte of the reload value of timer4 25h t4reloadlo_reg low byte of the reload value of timer4 26h t4countervalhi_reg counter value high byte of timer4 27h t4countervallo_reg counter value low byte of timer4 28h drvmod_reg driver mode register 29h txamp_reg transmitter amplifier register 2ah drvcon_reg driver configuration register 2bh txl_reg transmitter register 2ch txcrccon_reg transmitter crc control register 2dh rxcrccon_reg receiver crc control register 2eh txdatanum_reg transmitter data number register 2fh txmodwidth_reg transmitter modulation width register 30h txsym10burstlen_reg transmitter symbol 1 + symbol 0 burst length register 31h txwaitctrl_reg transmitter wait control 32h txwaitlo_reg transmitter wait low 33h framecon_reg transmitter frame control 34h rxsofd_reg receiver start of frame detection 35h rxctrl_reg receiver control 36h rxwait_reg receiver wait register 37h rxthreshold_reg receiver threshold 38h rcv_reg receiver register 39h rxana_reg receiver analog register 3ah rfu - 3bh serialspeed_reg serial speed register table 15. clrc663 registers overview ?continued address register name function
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 18 of 125 nxp semiconductors clrc663 contactless reader ic 3ch lpo_trimm_reg low power oscillator trimming register for low power card detection register 3dh pll_ctrl_reg integern pll control register, for uc clock output adjustment 3eh pll_divout_reg integern pll control register, for uc clock output adjustment 3fh lpcd_qmin_reg low power card detection q channel minimum threshold 40h lpcd_qmax_reg low power card detection q channel maximum threshold 41h lpcd_imin_reg low power card detection i channel minimum threshold 42h lpcd_i_result_reg low power card detection i channel result register 43h lpcd_q_result_reg low power card detection q channel result register 44h paden_reg gpio0 pin enable register 45h padout_reg gpio0 pin out register 46h padin_reg gpio0 pin in register 47h sigout_reg enables and controls the sigout pin 48h txbitmod_reg transmitter bit modus register 49h rfu - 4ah txdatacon_reg transmitter data configuration register 4bh txdatamod_reg transmitter data modulation register 4ch txsymfreq_reg transmitter symbol frequency 4dh txsym0h_reg transmitter symbol 0 high register 4eh txsym0l_reg transmitter symbol 0 low register 4fh txsym1h_reg transmitter symbol 1 high register 50h txsym1l_reg transmitter symbol 1 low register 51h txsym2_reg transmitter symbol 2 register 52h txsym3_reg transmitter symbol 3 register 53h txsym10len_reg transmitter symbol 1 + symbol 0 length register 54h txsym32len_reg transmitter symbol 3 + symbol 2 length register 55h txsym10burstctrl_reg transmitter sym bol 1 + symbol 0 burst control register 56h txsym10mod_reg transmitter symbol 1 + symbol 0 modulation register 57h txsym32mod_reg transmitter symbol 3 + symbol 2 modulation register 58h rxbitmod_reg receiver bit modulation register 59h rxeofsym_reg receiver e nd of frame symbol register 5ah rxsyncvalh_reg receiver synchronisation value high register 5bh rxsyncvall_reg receiver synch ronisation value low register 5ch rxsyncmod_reg receiver synchronisation mode register 5dh rxmod_reg receiver modulation register 5eh rxcorr_reg receiver correlation register 5fh fabcal_reg fab calibration register of the receiver 7fh version_reg version and subversion register table 15. clrc663 registers overview ?continued address register name function
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 19 of 125 nxp semiconductors clrc663 contactless reader ic 9.2 description/co mmand register 9.2.1 command_reg starts and stops command execution. table 16: command_reg register (address 00h); reset value: 40h bit 7 6 5 4 3 2 1 0 symbol standby mode off - command access rights dy r/w rfu dy table 17: description of command_reg bits bit symbol description 7 standby set to 1, the ic is entering power-down mode. 6 modemoff set to logic 1, the receiver and the transmitter circuit is powering down. 50 rfu 4 to 0 command defines the actual command for the clrc663. table 18: command overview command nr. nr. short description idle 0.0000 00h no action, cancels current command execution lpcd 0.0001 01h low power card detection and/or auto trimming loadkey 0.0010 02h reads a key from fifo buffer and puts it into key buffer mfauthent 0.0011 03h performs the mifare standard authentication in mifare read/write mode only ackreq 0.0100 04h performs a query, a ack and a req-rn for iso/iec 18000-3 mode 3 receive 0.0101 05h enables data receive transmit 0.0110 06h transmits data from the fifo buffer transceive 0.0111 07h transmits data from the fifo buffer and automatically activates the receiver after transmission finished writee2 0.1000 08h gets one byte from fifo buffer and writes it to the internal eeprom writee2pages 0.1001 09h gets up to 64 bytes from fifo buffer and writes it to the internal eeprom reade2 0.1010 0ah reads data from the eeprom and puts it into the fifo buffer loadreg 0.1100 0bh reads data from the internal eeprom an d initializes the clrc663 registers loadprotocol 0.1101 0ch reads data from the internal eeprom and initializes the clrc663 registers needed for a protocol change loadkeye2 0.1110 0eh copies a mifare ke y of the eeprom into the key buffer storekeye2 0.1111 0fh stores a mifare key into the eeprom soft reset 1.1111 1fh resets the clrc663 to eeprom configuration
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 20 of 125 nxp semiconductors clrc663 contactless reader ic 9.3 register description/sam register 9.3.1 hostctrl_reg via the hostctrl_register the interface access right can be controlled 9.4 register description/fifo register 9.4.1 fifocontrol_reg fifocontrol_reg register controls the behavior of the fifo table 19. hostctrl_reg register (address 01h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol regen bus host bussam - sam interface sam interface -- access rights r/w r/w r/w rfu r/w r/w rfu rfu table 20: description of hostctrl_reg bits bit symbol description 7 regen if this bit is set to logic 1, the register can be changed at the next register access. the next write acce ss clears this bit automatically. 6 bushost set to logic 1, the buscontrol enables the host interface. this bit can not be set together with bussam. this bit can only be set if the bit regen was previously set. 5 bussam set to logic 1, the buscontrol enables the sam interface. this bit can not be set together with bushost. this bit can only be set if the bit regen is previously set. 4- rfu 3 to 2 sam interface 00:off (default) 01:spi 10:i2cl 11:i2c standard i/o pad 1 to 0 - rfu table 21. fifocontrol_reg register (address 02h); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol fifo size hialert loalert fifo flash - water level fifo length access rights r/w r r w rfu r/w r
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 21 of 125 nxp semiconductors clrc663 contactless reader ic 9.4.2 waterlevel_reg defines the level for fifo under- and overflow warning. table 22: description of fifocontrol_reg bits bit symbol description 7 fifosize set to logic 1, fifo size 255 bytes; set to logic 0, fifo size is 512 bytes. the size can only be changed, when at the same write command a fifo flash is executed 6 hialert set to logic 1, when the number of bytes stored in the fifo buffer fulfils the following equation: hialert = (fifosize - fifolength) <= waterlevel 5 loalert set to logic 1, when the number of bytes stored in the fifo buffer fulfils the following conditions: loalert =1 if fifolength <= waterlevel 4 fifoflash set to logic 1 empties the fifo buffer. reading this bit will always return 0 3- rfu 2 waterlevel defines the higher bit for the waterlevel. this bit is only needed in the 512 bit fifo mode 1 to 0 fifolength defines the two higher bit for the fifo length. these two bits are only needed in the 512 bit fifo mode table 23: waterlevel_reg register (address 03h); reset value: 05h bit 7 6 5 4 3 2 1 0 symbol waterlevel access rights r/w table 24: description of waterlevel_reg bits bit symbol description 7 to 0 waterlevel this register defines a warning level to indicate a fifo-buffer overflow or underflow: the bit hialert bit in fifo control is set to logic 1, if the remaining number of bytes in the fifo-buffer space is equal or less than the defined number of waterlevel bytes. the bit loalert bit in fifo control is set to logic 1, if equal or less than waterlevel bytes are in the fifo. note: for the calculation of hialert and loalert see register description of these bits. note: in the 512 byte mode also the higher bit of fifolength in the fifocontrol register have to be taken into account
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 22 of 125 nxp semiconductors clrc663 contactless reader ic 9.4.3 fifolength_reg number of bytes in the fifo buffer. 9.4.4 fifodata_reg in- and output of fifo buffer. 9.5 register description/interrupt register 9.5.1 irq0_reg register interrupt register 0. table 25: fifolength_reg register (address 04h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol fifolength access rights r/w table 26: description of fifolength_reg bits bit symbol description 7 to 0 fifolength indicates the number of by tes in the fifo buffer. writing to the fifodata_reg register increments, reading decrements the fifo level. note: in the 512 byte mode also the higher bits of fifolength bit in the fifocontrol_reg register have to be taken into account. table 27: fifodata_reg register (address 09h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol fifodata access rights dy table 28: description of fifodata_reg bits bit symbol description 7 to 0 fifodata data input and output port for the internal fifo buffer. refer to section 13 ? fifo buffer ? table 29: irq0_reg register (address 06h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol set hi alertirq lo alertirq idleirq txirq rxirq errirq rxsof irq access rights w r/w/dy r/w/dy r/w/dy r/w /dy r/w/dy r/w/dy r/w/dy
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 23 of 125 nxp semiconductors clrc663 contactless reader ic 9.5.2 irq1_reg register interrupt register 1. table 30: description of irq0_reg bits bit symbol description 7 set set to logic 1, set defined bits in irq0_reg set to logic 0, clears marked bits in the irq0_reg. 6 hialerirq set to logic 1, when bit hialert in register status1reg is set. in opposition to hialert, hialertirq stores this event and can only be reset as indicated by bit set. 5 loalertirq set to logic 1, when bit loalert in register status1_reg is set. in opposition to loalert, loalertirq stores this event and can only be reset as indicated by bit set1 4 idleiirq set to logic 1, when a comma nd terminates by itself e.g. when the command_reg changes its value from any command to the idle command. if an unknown command is started, the command_reg changes its content to the idle state and the bit idleirq is set. starting the idle command by the controller does not set bit idleirq. 3 txirq set to 1, when data transmission is completed, which is immediately after the last bit is send. 2 rxirq set to 1, when the receiver detects the end of a data stream. note: this flag is no indication that the received data stream is correct. the error flags have to be evaluated to get the status of the reception. 1 errirq set to 1, when the one of the following errors is set: fifowrerr, fifoovl, proterr, nodataerr, integerr 0 rxsoflrq set to 1 when a sof or a subcarrier is detected table 31: irq1_reg register (address 07h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol set global irq lpcd_ irq timer4 irq timer3 irq timer2 irq timer1 irq timer0 irq access rights w r/w/dy r/w/dy r/w/dy r/w /dy r/w/dy r/w/dy r/w/dy table 32: description of irq1_reg bits bit symbol description 7 set set to logic 1, set defined bits in irq1_reg set to logic 0, clears marked bits in the irq1_reg. 6 globalirq set, if an enabled irq occurs. 5 lpcd_irq set if a card is detected in low power card detection sequence. 4 timer4irq set to logic 1 when timer4 has an underflow. 3 timer3irq set to logic 1 when timer3 has an underflow. 2 timer2irq set to logic 1 when timer2 has an underflow. 1 timer1irq set to logic 1 when timer1 has an underflow. 0 timer0irq set to logic 1 when timer0 has an underflow.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 24 of 125 nxp semiconductors clrc663 contactless reader ic 9.5.3 irq0en_reg register interrupt enable register for irq0_reg. 9.5.4 irq1en_reg register interrupt enable register for irq1_reg. table 33: irq0en_reg register (address 08h); reset value: 10h bit 7 6 5 4 3 2 1 0 symbol irq_inv hi alertirq en lo alertirq en idleirq en txirqen rxirqen errirqen rxsof irq en access rights r/w r/w r/w r/w r/w r/w r/w r/w table 34: description of irq0en_reg bits bit symbol description 7 irq_inv set to one the signal of the irq pin is inverted 6hi alerirqen set to logic 1, it allows the transmitter interrupt request (indicated by the bit hialertirq) to be propagated to the globalirq 5lo alertirqen set to logic 1, it allows the transmitter interrupt request (indicated by the bit loalertirq) to be propagated to the globalirq 4 idleiirqen set to logic 1, it allows the tr ansmitter interrupt request (indicated by the bit idleirq) to be propagated to the globalirq 3 txirqen set to logic 1, it allows the transmitter interrupt request (indicated by the bit txtirq) to be propagated to the globalirq 2 rxirqen set to logic 1, it allows the rece iver interrupt request (indicated by the bit rxirq) to be propagated to the globalirq 1 errirqen set to logic 1, it allows the e rror interrupt request (indicated by the bit errorirq) to be propagated to the globalirq 0rxsof irqen set to logic 1, it allows the rxsof interrupt request (indicated by the bit rxsofirq) to be propagated to the globalirq table 35: irq1en_reg register (address 09h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol irq pushpull irqpin en lpcd_ irqen timer4 irqen timer3 irqen timer2 irqen timer1 irqen timer0 irqen access rights r/w r/w r/w r/w r/w r/w r/w r/w table 36: description of irq1en_reg bits bit symbol description 7 irqpushpull set to 1 the irq-pin acts as pushpull pin, otherwise it acts as opendrain pin 6 irqpinen set to logic 1, it allows the glo bal interrupt request (indicated by the bit globalirq) to be propagated to the interrupt pin 5 lpcd_irqen set to logic 1, it allows the lpcdinterrupt request (indicated by the bit lpcdirq) to be propagated to the globalirq 4 timer4irqen set to logic 1, it allows the ti mer4 interrupt request (indicated by the bit timer4irq) to be propagated to the globalirq
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 25 of 125 nxp semiconductors clrc663 contactless reader ic 9.6 register description/cl register 9.6.1 error_reg register error register. 3 timer3irqen set to logic 1, it allows the ti mer3 interrupt request (indicated by the bit timer3tirq) to be propagated to the globalirq 2 timer2irqen set to logic 1, it allows the ti mer2 interrupt request (indicated by the bit timer2irq) to be propagated to the globalirq 1 timer1irqen set to logic 1, it allows the ti mer1 interrupt request (indicated by the bit timer1irq) to be propagated to the globalirq 0 timer0irqen set to logic 1, it allows the ti mer0 interrupt request (indicated by the bit timer0irq) to be propagated to the globalirq table 36: description of irq1en_reg bits ?continued bit symbol description table 37: error_reg register (address 0ah); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol ee_err fifo wrerr fifoovl minfra meerr nodata err colldet proterr integerr access rights d/w/r d/w/r d/w/r d/w/r d/w/r d/w/r d/w/r d/w/r table 38: description of error_reg bits bit symbol description 7 ee_err if this flag is set, an error appe ared during the last eeprom command. for details see the descriptions of the eeprom commands 6 fifowrerr if this flag is set, data was written into the fifo, during a transmission of a possible crc, during "rxwait", "wait for data" or "receiving" state, or during an authentication command. the flag is cleared when a new cl command is started. if rxmultiple is active, the flag is cleared after the error flags have been written to the fifo. 5 fifoovl this flag is set to 1 if data is writ ten into the fifo when it is already full. the data that is already in the fifo will remain untouched. all data that is written to the fifo after this flag is set to 1 will be ignored. 4min frameerr this flag is set to 1, if a valid sof was received, but afterwards less then 4 bits of data were received. note: frames with less than 4 bits of da ta are automatically discarded and the rxdecoder stays enabled. furthermore no rxirq is set. the same is valid for less than 3 bytes if the emd suppression is activated note: minframeerr is automatically cl eared at the start of a receive or transceive command. in case of a transceive command, it is cleared at the start of the receiving phase ("wait for data" state) 3 nodataerr this flag is set if data should be sent, but no data is in fifo
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 26 of 125 nxp semiconductors clrc663 contactless reader ic 9.6.2 status_reg status register. 2 colldet this flag is set to 1, if a collision has occurred. the position of the first collision is shown in the register rxcoll_reg. note: colldet is automatically cleared at the start of a receive or transceive command. in case of a transceive command , it is cleared at the start of the receiving phase (?wait for data? state). note: if a collision is part of the defi ned eof symbol, colldet is not set to 1. 1 proterr this flag is set to 1, if a protocol error has occurred. a protocol error can be a wrong stop bit, a missing or wrong is o/iec14443b eof or sof or a wrong number of received data bytes. when a protocol error is detected, data reception is stopped. note: proterr is automatically cleared at start of a receive or transceive command. in case of a transceive command , it is cleared at the start of the receiving phase (?wait for data? state). note: when a protocol error occurs the last received data byte is not written into the fifo. 0 integerr this flag is set to 1, if a data in tegrity error has been detected. possible cause can be a wrong parity or a wrong crc. in case of a data integrity error the reception is continued. note: integerr is automatically cleared at start of a receive or transceive command. in case of a transceive command, it is cleared at the start of the receiving phase (?wait for data? state). note: if a reversed parity bit is a stop criteria, integerr is not set to 1. note: if the nocoll bit is set, also a collision is setting the integerr. table 38: description of error_reg bits bit symbol description table 39: status_reg register (address 0bh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - crypto1 on -- comstate access rights rfu rfu r/w rfu rfu r table 40: description of status_reg bits bit symbol description 7, 6 - rfu 5 crypto1on indicates if the mifare crypto is on. clearing this bit is switching the mifare crypto off. the bit can only be set by the mfauthent command. 4to3 - rfu 2 to 0 comstate comstate shows the status of the transmitter and receiver state machine 000...idle 001...txwait 011...transmitting 101...rxwait 110...wait for data 111...receiving 100...not used
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 27 of 125 nxp semiconductors clrc663 contactless reader ic 9.6.3 rxbitctrl_reg receiver control register. table 41: rxbitctrl_reg register (address 0ch); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol values after coll rxalign nocoll rxlastbits access rights r/w r/w r/w r/w table 42: description of rxbitctrl_reg bits bit symbol description 7values after coll if cleared, every received bit after a collision is replaced by a zero. this function is needed for type a anticollision 6 to 4 rxalign used for reception of bit oriented frames: rxalign defines the bit position length for the first bit received to be stored. further received bits are stored at the following bit positions. example: rxalign = 0h - the lsb of the received bit is stored at bit 0, the second received bit is stored at bit position 1. rxalign = 1h - the lsb of the received bit is stored at bit 1, the second received bit is stored at bit position 2. rxalign = 7h - the lsb of the received bit is stored at bit 7, the second received bit is stored in t he following byte at position 0. note: if rxalign = 0, data is received byte-oriented, otherwise bit-oriented. the hardware does not cross-check this settings in any way 3 nocoll if this bit is set, a collision will result in an integerr 2 to 0 rxlastbits defines the number of valid bits of the last data byte received in bit-oriented communications. if zero the whole byte is valid. note: these bits are set by the rxdecoder in a bit-oriented communication at the end of the communication. they are reset at start of reception.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 28 of 125 nxp semiconductors clrc663 contactless reader ic 9.6.4 rxcoll_reg receiver collision register. table 43: rxcoll_reg register (address 0dh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol collpos valid collpos access rights r/w/dy r/w/dy table 44: description of rxcoll_reg bits bit symbol description 7 collpos valid if set to 1, the value for position of the collision is valid. otherwise no collision is detected or the position of t he collision is out of the range of bits collpos. this bit shall only be interpreted in passive communication mode at 106 kbit/s or iso14443a/mifare reader/writer mode. 6 to 0 collpos these bits show the bit position of the first detected collision in a received frame (only data bits are interpreted). collpos can only be displayed for the first 8 bytes of a data stream. example: 00h indicates a bit collision in the 1st bit 01h indicates a bit collision in the 2nd bit 08h indicates a bit collision in the 9th bit (1st bit of 2nd byte) 3fh indicates a bit collision in the 64th bit (8th bit of the 8th byte) these bits shall only be interpreted in passive communication mode at 106 kbit/s or iso/iec 14443a/mifare rea der /writer or is o/iec 15693/i-code sli read/write mode if bit collposvalid is set to 1. note: if rxbitctrl . rxalign is set to a value different to 0, this value is included in the collpos . example: rxalign = 4h, a collision occurs in the 4th received bit (which is the last bit of that uid byte). the collpos = 7h in this case. .
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 29 of 125 nxp semiconductors clrc663 contactless reader ic 9.7 register description/timer register 9.7.1 tcontrol_reg control register of the timer section. 9.8 t0control_reg control register of the timer0. table 45: tcontrol_reg register (address 0eh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t3 running t2 running t1 running t0 running t3start stopnow t2start stopnow t1start stopnow t0start stopnow access rights dy/r/w dy/r/w dy/r/w dy/r/w r/w r/w r/w r/w table 46: description of tcontrol_reg bits bit symbol description 7t 3 running shows if the timer n is running. if the t3startstopnow is set, this bit and the timer can be controlled 6t 2 running shows if the timer n is running. if the t2startstopnow is set, this bit and the timer can be controlled 5t 1 running shows if the timer n is running. if the t1startstopnow is set, this bit and the timer can be controlled 4t 0 running shows if the timer n is running. if the t0startstopnow is set, this bit and the timer can be controlled 3t 3 startstop now set to logic 1 the bit t3running can be set. 2t 2 startstop now set to logic 1 the bit t2running can be set. 1t 1 startstop now set to logic 1 the bit t1running can be set. 0t 0 startstop now set to logic 1 the bit t0running can be set. table 47: t0control_reg register (address 0fh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t0stop rx -t0startt0auto restarted - t0clk access rights r/w rfu r/w r/w rfu r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 30 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.1 t0reloadhi_reg high byte reload value of the timer 0. 9.8.2 t0reloadlo_reg low byte reload value of the timer 0. table 48: description of t0control_reg bits bit symbol description 7 t0stoprx if set to one, the timer stops immediately after receiving the first data. set to logic 0, indicates that the timer is not stopped automatically. note: if lfo trimming is selected by t0start, this bit has no effect 6- rfu 5 to 4 t0start 00b: the timer is not started automatically 01b: the timer starts automatically at the end of the transmission 10b: timer is used for lfo trimming without underflow (start/stop on posedge) 11b: timer is used for lfo trimming with underflow (start/stop on posedge) 3 t0autorestart set to logic 1, the timer automatically restarts its count-down from t0reloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer1irq is set to logic 1 when the timer reaches zero. 2- rfu 1 to 0 t0clk 00b: the timer input clock is 13.56 mhz. 01b: the timer input clock is 212 khz. 10b: the timer input clock is an underflow of timer 2. 11b: the timer input clock is an underflow of timer 1. table 49: t0reloadhi_reg register (address 10h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t0reload hi access rights r/w table 50: description of t0reloadhi_ reg bits bit symbol description 7 to 0 t0reloadhi defines the high byte of the reload value of the timer. with the start event the timer loads the value of the t0reloadval. changing this register affects the timer on ly at the next start event. table 51: t0reloadlo_reg register (address 11h); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol t0reloadlo access rights r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 31 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.3 t0countervalhi_reg high byte of the counter value of timer0. 9.8.4 t0countervallo_reg low byte of the counter value of timer0. 9.8.5 t1control_reg control register of the timer1. table 52: description of t0reloadlo_ reg bits bit symbol description 7..0 t0reloadlo defines the low byte of the reload value of the timer. with the start event the timer loads the value of the t0reloadval. changing this register affects the timer on ly at the next start event. table 53: t0countervalhi_reg register (address 12h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t0counterhi access rights r/w table 54: description of t0countervalhi_reg bits bit symbol description 7..0 t0counter valhi current high byte value of the counter 0. this value shall not be read out during reception. table 55: t0countervallo_reg register (address 13h); reset value:00h bit 7 6 5 4 3 2 1 0 symbol t0countervallo access rights r/w table 56: description of t0countervallo_reg bits bit symbol description 7 to 0 t0countervallo current value of the counter n. this value shall not be read out during reception. table 57: t1control_reg register (address 14h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t1stop rx -t1startt1auto restart - t1clk access rights r/w rfu r/w r/w rfu r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 32 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.6 t1reloadhi_reg high byte reload value of the timer1. 9.8.7 t1reloadlo_reg low byte reload value of the timer 1. table 58: description of t1control_reg bits bit symbol description 7 t1stoprx if set to one, the timer stops immediately after receiving the first data. set to logic 0, indicates that the timer is not stopped automatically. note: if lfo trimming is selected by t1start, this bit has no effect 6- rfu 5 to 4 t1start 00b: the timer is not started automatically 01b: the timer starts automatically at the end of the transmission 10b: timer is used for lfo trimming without underflow (start/stop on posedge) 11b: timer is used for lfo trimming with underflow (start/stop on posedge) 3 t1autorestart set to logic 1, the timer automatically restarts its countdown from tnreloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer1irq is set to logic 1 when the timer reaches zero 2- rfu 1 to 0 t1clk 00b: the timer input clock is 13.56 mhz 01b: the timer input clock is 212 khz. 10b: the timer input clock is an underflow of timer 0 11b: the timer input clock is an underflow of timer 2 table 59: t0reloadhi_reg register (address 15h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t1reloadhi access rights r/w table 60: description of t1reloadhi_ reg bits bit symbol description 7 to 0 t1reloadhi defines the high byte reload value of the timer1. with the start event the timer loads the value of the t1reloadvalhi_reg and t1reloadvallo_reg. changing this register affects the timer only at the next start event. table 61: t1reloadlo_reg register (address 16h); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol t1reloadlo access rights r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 33 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.8 t1countervalhi_reg high byte of the counter value of byte timer1. 9.8.9 t1countervallo_reg low byte of the counter value of byte timer1. 9.8.10 t2control_reg control register of the timer2. table 62: description of t1reloadvallo_ reg bits bit symbol description 7 to 0 t1reloadlo defines the low byte of the reload value of the timer1.with the start event the timer load the value of the t1reloadvalhi_reg and t1reloadvallo_reg. changing this register affects the timer only at the next start event. table 63: t1countervalhi_reg register (address 17h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t1countervalhi access rights r/w table 64: description of tncountervalhi_reg bits bit symbol description 7 to 0 t1counter valhi high byte of the curren t value of the timer1. this value shall not be read out during receive. table 65: t1countervallo_reg register (address 18h); reset value:00h bit 7 6 5 4 3 2 1 0 symbol t1countervallo access rights r/w table 66: description of t1countervallo_reg bits bit symbol description 7 to 0 t1counter vallo low byte of the current value of the counter 1. this value shall not be read out during receive. table 67: t2control_reg register (address 19h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t2stop rx -t2startt2auto restart - t2clk access rights r/w rfu r/w r/w rfu r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 34 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.11 t2reloadhi_reg high byte of the reload value of timer2. 9.8.12 t2reloadlo_reg low byte of the reload value of timer2. table 68: description of t2control_reg bits bit symbol description 7 t2stoprx if set to 1 the timer stops immediately after receiving the first data. set to logic 0, indicates, that the timer is not stopped automatically. note: if lfo trimming is selected by t2start, this bit has no effect 6- rfu 5 to 4 t2start 00b: the timer is not started automatically. 01b: the timer starts automatically at the end of the transmission. 10b: timer is used for lfo trimming without underflow (start/stop on posedge). 11b: timer is used for lfo trimming with underflow (start/stop on posedge). 3 t2autorestart set to logic 1, the timer automatically restarts its countdown from tnreloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer2irq is set to logic 1 when the timer reaches zero 2- rfu 1 to 0 t2clk 00b: the timer input clock is 13.56 mhz. 01b: the timer input clock is 212 khz. 10b: the timer input clock is an underflow of timer 0 11b: the timer input clock is an underflow of timer 1 table 69: t2reloadhi_reg register (address 1ah); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t2reloadhi access rights r/w table 70: description of tnreload_ reg bits bit symbol description 7 to 0 t2reloadhi defines the high byte of the reload value of the timer 2. with the start event the timer load the value of the t2reloadvalhi_reg and t2reloadvallo_reg. changing this register affects the timer only at the next start event. table 71: t2reloadlo_reg register (address 1bh); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol t2reloadlo access rights r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 35 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.13 t2countervalhi_reg high byte of the counter register of timer 2. 9.8.14 t2countervalloreg low byte of the current value of timer 2. 9.8.15 t3control_reg control register of the timer 3. table 72: description of t2reloadlo_reg bits bit symbol description 7 to 0 t2reloadlo defines the low byte of the reload value of the timer 2. with the start event the timer load the value of the t2reloadvalhi_reg and t2relaodvalo_reg. changing this register affects the timer only at the next start event. table 73: t2countervalhi_reg register (address 1ch); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t2counterhi access rights r/w table 74: description of t2countervalhi_reg bits bit symbol description 7 to 0 t2counter valhi high byte current counte r value of timer 2. this value shall not be read out during receive. table 75: t2countervallo_reg register (address 1dh); reset value:00h bit 7 6 5 4 3 2 1 0 symbol t2countervallo access rights r/w table 76: description of t2countervallo_reg bits bit symbol description 7..0 t2counter vallo low byte of the current counter value of timer 2. this value shall not be read out during receive. table 77: t3control_reg register (address 1eh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t3stop rx -t3startt3auto restart - t3clk access rights r/w rfu r/w r/w rfu r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 36 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.16 t3reloadhi_reg high byte of the reload value of timer3. 9.8.17 t3reloadlo_reg low byte of the reload value of timer 3. table 78: description of t3control_reg bits bit symbol description 7 t3stoprx if set to one, the timer stops immediately after receiving the first data. set to logic 0, indicates that the timer is not stopped automatically. note: if lfo trimming is selected by t3start, this bit has no effect 6- rfu 5 to 4 t3start 00b - timer is not started automatically 01b - timer starts automatically at the end of the transmission 10b - timer is used for lfo trimmi ng without underflow (start/stop on posedge) 11b - timer is used for lfo trimming with underflow (start/stop on posedge) 3 t3autorestart set to logic 1, the timer automatically restarts its countdown from tnreloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer1irq is set to logic 1 when the timer reaches zero 2- rfu 1 to 0 t3clk 00b - the timer input clock is 13.56 mhz. 01b - the timer input clock is 212 khz. 10b - the timer input clock is an underflow of timer 0 11b - the timer input clock is an underflow of timer 1 table 79: t3reloadhi_reg register (address 1fh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t3reloadhi access rights r/w table 80: description of t3reloadhi_ reg bits bit symbol description 7 to 0 t3reloadhi defines the high byte of the reload value of the timer 3. with the start event the timer load the value of the t3reloadvalhi_reg and t3reloadvallo_reg. changing this register affects the timer only at the next start event. table 81: t3reloadlo_reg register (address 20h); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol t3reloadlo access rights r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 37 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.18 t3countervalhi_reg high byte of the current coun ter value the 16 bit timer 3. 9.8.19 t3countervallo_reg low byte of the current counter value the 16 bit timer3. 9.8.20 t4control_reg the wake-up timer t4 activates the system af ter a given time. it can start a low power card detection table 82: description of t3reloadlo_reg bits bit symbol description 7 to 0 t3reloadlo defines the low byte of the reload value of timer 3. with the start event the timer load the value of the t3reloadvalhi_reg and t3relaodvallo_reg. changing this register affects the timer only at the next start event. table 83: t3countervalhi_reg register (address 21h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t3counterhi access rights r/w table 84: description of t3countervalhi_reg bits bit symbol description 7 to 0 t3counter valhi high byte of the current counter value of timer 3. this value shall not be read out during receive. table 85: t3countervallo_reg register (address 22h); reset value:00h bit 7 6 5 4 3 2 1 0 symbol t3countervallo access rights r/w table 86: description of t3countervallo_reg bits bit symbol description 7 to 0 t3counter vallo low byte current counter value of timer 3. this value shall not be read out during receive. table 87. t4control_reg register (address 23h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t4 running t4start stopnow t4auto trimm t4auto lpcd t4auto restart t4auto wakeup t4clk access rights r/w r/w r/w r/w r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 38 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.21 t4reloadhi_reg high byte of the reload value of the 16 bit timer 4. 9.8.22 t4reloadlo_reg low byte of the reload value of the 16 bit timer 4. table 88: description of t4control_reg bits bit symbol description 7 t4running shows if the timer 4 is running. if the bit t4startstopnow is set, this bit and the timer can be controlled. 6t4start stopnow set to logic 1, the bit t4running can be written 5 t4autotrimm if set to one, the timer ac tivates an lpo trimming procedure when it underflows. for the t4autotrimm function, at least one timer (t0?t3) has to be configured properly for trimming (t3 is not allowed if t4autolpcd is set in parallel). 4 t4autolpcd if set to one, the timer activa tes a low power card detection sequence. if a card is detected an irq is ra ised and the system remains active if enabled. if no card is detected the clrc663 enters the power down state if enabled. the timer is autom atically restarted (no gap). timer 3 is used to specify the time where t he rf field is enabled to check if a card is present. therefor you may not use timer 3 for t4autotrimm in parallel. 3 t4autorestart set to logic 1, the timer automatically restarts its countdown from t4reloadvalue, after the counter value has reached the value zero. set to logic 0 the timer decrements to zero and stops. the bit timer4irq is set to logic 1 when the timer reaches zero 2 t4auto wakeup if set, the clrc663 wakes up automatically, when the timer t4 has an underflow. this bit has to be set if the ic should enter the power down state after t4autotrimm and/or t4autolpcd is finished and no card has been detected. if the ic should stay active after one of these procedure this bit has to be set to 0. 1 to 0 t4clk 00b - the timer input clock is the lfo clock 01b - the timer input clock is the lfo clock/8 10b - the timer input clock is the lfo clock/16 11b - the timer input clock is the lfo clock/32 table 89: t4reloadhi_reg register (address 24h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t4reloadhi access rights r/w table 90: description of t4reloadhi _reg bits bit symbol description 7 to 0 t4reloadhi defines high byte of the for the reload value of timer 4. with the start event the timer 4 loads the t4reloadva l. changing this register affects the timer only at the next start event
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 39 of 125 nxp semiconductors clrc663 contactless reader ic 9.8.23 t4countervalhi_reg high byte of the counter value of the 16 bit timer 4. 9.8.24 t4countervallo_reg low byte of the counter value of the 16 bit timer 4. table 91: t4reloadlo_reg register (address 25h); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol t4reloadlo access rights r/w table 92: description of t4reloadlo_reg bits bit symbol description 7 to 0 t4reloadlo defines the low byte of the reload value of the timer 4. with the start event the timer loads the value of the tnreloadval. changing this register affects the timer on ly at the next start event. table 93: t4countervalhi_reg register (address 26h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol t4reloadhi access rights r/w table 94: description of t4countervalhi_reg bits bit symbol description 7 to 0 t4counter valhi high byte of the current counter value of timer 4. table 95: t4countervallo_reg register (address 27h); reset value:00h bit 7 6 5 4 3 2 1 0 symbol t4countervallo access rights r/w table 96: description of t4countervallo_reg bits bit symbol description 7 to 0 t4counter vallo low byte of the current counter value of the timer 4.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 40 of 125 nxp semiconductors clrc663 contactless reader ic 9.9 description/transmitter register 9.9.1 txmode_reg 9.9.2 txamp_reg 9.9.3 txcon_reg table 97. drvmode_reg register (address 28h); reset value: 86h bit 7 6 5 4 3 2 1 0 symbol tx2inv tx1inv - - txen txclk mode access rights r/w r/w rfu rfu r/w r/w table 98: description of drvmode_reg bits bit symbol description 7 tx2inv inverts transmitter tx2 at tx2 pin 6 tx1inv inverts transmitter tx1 at tx1 pin 5- rfu 4- rfu 3 txen if set to 1 both transmitter pins are enabled 2 to 0 txclkmode transmitter clock settings: refer to table 220 ? settings for tx1/2 ? table 99. txamp_ reg register (address 29h); reset value: 15h bit 7 6 5 4 3 2 1 0 symbol set_cw_amplitude - set_residual_carrier access rights r/w rfu r/w table 100. description of txamp_reg bits bit symbol description 7 to 6 set_cw_amplitude 0: tvdd - 100 mv 1: tvdd - 250 mv 2: tvdd - 500 mv 3: tvdd - 1 v note: if cwmax is set to 1, set_cw_amplitude has no influence onto the continuous amplitude 5- rfu 4 to 0 set_residual_ carrier set the residual carrier percentage. refer to section 11.2 table 101. txcon_reg register (address 2ah); reset value: 11h bit 7 6 5 4 3 2 1 0 symbol overshoott2 cw max tx inv txsel access rights r/w r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 41 of 125 nxp semiconductors clrc663 contactless reader ic 9.9.4 txl_reg 9.10 descripti on/crc register 9.10.1 txcrccon_reg table 102: description of drvcon_ reg bits bit symbol description 7 to 4 overshoott2 specifies the length (number of carrier clocks) of the additional modulation for overshoot prevention. refer to section 11.2.1 ? overshoot protection ? 3 cwmax set amplitude of continuous wave carrier to the maximum. if set to1, set_cw_amplitude has no influence on the continuous amplitude. 2 txinv if set to 1, the resulting modulation signal (which is defined by txsel is inverted 1 to 0 txsel defines which signal is used as source for modulation 00b...low 01b...txenvelope 10b...sigin 11b...rfu table 103. txl_reg register (address 2bh); reset value: 06h bit 7 6 5 4 3 2 1 0 symbol overshoott1 tx_set_iiload access rights r/w r/w table 104: description of txl reg bits bit symbol description 7 to 4 overshoott1 overshoot value for timer 1. refer to section 11.2.1 ? overshoot protection ? 3 to 0 tx_set_iload settings for set_iload and corresponding assumed tx-load current. default setting: ah remark: 0h is not allowed; table 105. txcrcon_reg register (address 2ch); reset value: 18h bit 7 6 5 4 3 2 1 0 symbol - txpresetval txcrctype txcrc invert txcrc en access rights rfu r/w r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 42 of 125 nxp semiconductors clrc663 contactless reader ic 9.10.2 rxcrccon_reg table 106: description of tccrcon _reg bits bit symbol description 7- rfu 6 to 4 txpresetval specifies the crc preset value (hex) for transmission. | crc16 crc8 crc5 ---------------------------------------------------------------- 000b | 0000????..00????...00 001b | 6363????..12????...12 010b | a671????..bf????..rfu 011b | fffe????.fd????..rfu 100b | rfu????.. rfu???...rfu 101b | rfu???? rfu???...rfu 110b | user def. ??.user def. ?.user def. 111b | ffff????. ff????...1f 3 to 2 txcrctype defines which type of crc (crc8/crc16/crc5) is calculated: 00b:?????????? crc5 is calculated 01b:?????????? crc8 is calculated 10b:??????????. crc16 is calculated 11b:??????????. rfu 1 txcrcinvert if set to 1, the resulting crc is inverted and attached to the data frame (iso/iec 3309) 0 txcrcen if set to 1, a crc is appended to the data stream table 107. rxcrccon_reg register (address 2dh); reset value: 18h bit 7 6 5 4 3 2 1 0 symbol rxforce crcwrite rxpresetval rxpresetval rxcrcinvert rxcrcen access rights r/w r/w r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 43 of 125 nxp semiconductors clrc663 contactless reader ic 9.11 description/transmitter register 9.11.1 txdatanum_reg table 108: description of rxcrccon_reg bits bit symbol description 7 rxforcecrc write set to 1, the received crc byte(s) are written to fifo. (if this bit is set to 0) crc bytes are only checked, but not written to fifo. this bit has to be always set in case of a not byte aligned crc (e.g. iso/iec 18000-3 mode3) 6 to 4 rxpresetval specifies the crc preset value (hex) for transmission. | crc16 crc8 crc5 ---------------------------------------------------------------- 000b | 0000????..00????...00 001b | 6363????..12????...12 010b | a671????..bf????..rfu 011b | fffe????.fd????..rfu 100b | rfu????.. rfu???...rfu 101b | rfu???? rfu???...rfu 110b | user def. ??.user def. ?.user def. 111b | ffff????. ff????...1f 3 to 2 rxcrctype defines which type of crc (crc8/crc16/crc5) is calculated: 00b:?????????? crc5 is calculated 01b:?????????? crc8 is calculated 10b:??????????. crc16 is calculated 11b:??????????. rfu 1 rxcrcinvert if set to 1, the crc check is done for the inverted crc. 0 rxcrcen if set to 1, the crc is checke d and in case of a wrong crc an error flag is set. otherwise the crc is calculated but the error flag is not modified. table 109: txdatanum_reg register (address 2eh); reset value: 0fh bit 7 6 5 4 3 2 1 0 symbol - - - keepbit grid dataen txlastbits access rights rfu rfu rfu r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 44 of 125 nxp semiconductors clrc663 contactless reader ic 9.11.2 txdatamodwidth_reg transmitter mode width register table 110: description of txdatanum_reg bits bit symbol description 7-5 rfu - 4 keepbitgrid if set, the time between consecutive transmissions starts is a multiple of the etu. depending on the dcodetype settings one etu is defined as follows: 4h - 7h - 37.76 ? s (26 khz)(epc/uid) 8h - 37.76 ? s (26 khz)(1 out of 4) 9h - bh - 604.16 ? s (1.6 khz)(1 out of 256) ch (dbfreq = 10 6khz) - 18.88 ? s (53 khz)(epcv2) ch (dbfreq = 212 khz) - 9.44 ? s (106 khz)(epcv2) others - 1/dbfreq 3 dataen if set to 0 - it is possi ble to send only a symbol pattern if set to 1 - also data is sent (be aware - that it is not possible to send only two symbols) 2 to 0 txlastbits defines how many bits of the la st data byte to be sent. if set to 000b all bits of the last data byte are sent. note - bits are skipped at the end of the byte. example - data byte b2h (sent lsb first). txlastbits = 011b (0x3) => 010b (lsb first) is sent txlastbits = 110b (0x6) => 010011b (lsb first) is sent table 111: txdatamodwidth_reg register (address 2fh); reset value: 27h bit 7 6 5 4 3 2 1 0 symbol dmodwidth access rights r/w table 112: description of txdatamodwidth_reg bits bit symbol description 7 to 0 dmodwidth specifies the length of a pulse for sending data with enabled pulse modulation. the length is given by the number of carrier clocks + 1. a pulse can never be longer than from the start of the pulse to the end of the bit. the starting position of a pulse is given by the setting of txdatamod.dpulsetype. note: this register is only used if miller modulation (iso/iec 14443a pcd) is used. the settings are also used for the modwidth of start and/or stop symbols.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 45 of 125 nxp semiconductors clrc663 contactless reader ic 9.11.3 txsym10burstlen_reg 9.11.4 txwaitctrl_reg table 113. txsym10burstlen_reg register (address 30h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - sym1burst len - sym0burst len access rights rfu r/w rfu r/w table 114: description of txsym10burstlen _reg bits bit symbol description 6 to 4 sym1burst len specifies the number of bits issu ed for symbol 1 burst. the 3 bits encodes a range from 8 to 256 bit 2 to 0 sym0burst len specifies the number of valid bits of the symbol definition of symbol0. the range is from 1 bit (value 0000b) to 16 bit (value 1111b) table 115. txwaitctrl_reg register (address 31h); reset value: c0h bit 7 6 5 4 3 2 1 0 symbol txwait start txwait etu txwait high.10 txwait high.9 txwait high.8 txstopbitlength access rights r/w r/w r/w r/w r/w r/w table 116: description of txwaitctrl_reg bits bit symbol description 7 txwait start if set to 0, the txwait time is star ting at the end of the send data (tx) if set to 1, the txwait time is star ting at the end of the received data (rx) 6 txwaitetu if set to 0, the txwait time is txwait ? 16/13.56 mhz if set to 1, the txwait time is txwait ? (0.5/dbfreq) 5 to 3 txwait high higher 3 bits of txwait. 2 to 0 txstopbit length defines number of stop-bits (= stop-bit + egt) to be send 000b: no stop-bit, no egt 001b: stop-bit, no egt 010b: stop-bit + 1 egt 011b: stop-bit + 2 egt 100b: stop-bit + 3 egt 101b:stop-bit + 4 egt 110b: stop-bit + 5 egt 111b: stop-bit + 6 egt note: this is only valid for iso/iec14443 type b
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 46 of 125 nxp semiconductors clrc663 contactless reader ic 9.11.5 txwaitlo_reg 9.11.6 framecon_reg table 117. txwaitlo_reg register (address 32h); reset value: 12h bit 7 6 5 4 3 2 1 0 symbol txwaitlo access rights r/w table 118: description of txwaitlo_reg bits bit symbol description 7 to 0 txwaitlo defines the minimum time between receive and send or between two send data streams note: txwait is a 11bit register (additional 3 bits are in the txwaitctrl register)! see also txwaitetu and txwaitstart. table 119. framecon_reg register (address 33h); reset value: cfh bit 7 6 5 4 3 2 1 0 symbol txparity en rxparit yen - - stopsym startsym access rights r/w r/w rfu rfu r/w r/w table 120: description of framecon_ reg bits bit symbol description 7 txparityen if high, a parity bit is calculated and appended to each byte transmitted 6 rxparityen defines which type of parity-bit is calculated. 0b: even parity 1b: odd parity 5 to 4 - - 3 to 2 stopsym defines which symb ol should be sent as stop-symbol 00b: no symbol is sent 01b: symbol1 is sent 10b: symbol2 is sent 11b: symbol3 is sent 1 to 0 startsym defines which symbol should be sent as start-symbol 00b: no symbol is sent 01b: symbol0 is sent 10b: symbol1 is sent 11b: symbol2 is sent
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 47 of 125 nxp semiconductors clrc663 contactless reader ic 9.12 description/ receiver register 9.12.1 rxsofd_reg 9.12.2 rxctrl_reg table 121. rxsofd_reg register (address 34h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - sof_en sof detected -subc_ en subc_ detected subc_ present access rights rfu rfu r/w r/w rfu r/w r/w r/w table 122: description of rxsofd_reg bits bit symbol description 7 to 6 - rfu 5 sof_en if set and a sof is det ected an rxsofirq is raised 4 sof_detected shows that a sof is or was detected. can be cleared by sw 3- rfu 2 subc_en if set and a subcarrier is detected an rxsofirq is raised. 1 subc_detected shows that a subcarrier is or was detected. can be cleared by sw 0 subc_present shows that a subcarrier is currently detected. table 123. rxctrl_reg register (address 35h); reset value: 04h bit 7 6 5 4 3 2 1 0 symbol rxallow bits rx multiple rxeof type egt_ check emd_ sup baud rate access rights r/w r/w r/w r/w r/w r/w table 124: description of rxctrl_ reg bits bit symbol description 7 rxallowbits if set to 1, data is written into fifo even if crc is enabled, and no complete byte has been received. this causes a data integrity error, because the crc is not correct 6 rxmultiple if set to 1, rxmultiple is ac tivated and the receiver will not terminate automatically (refer section 18.3.1.6 ? receive co mmand ? ) 5 rxeoftype if set to 0, an eof as def ined in the rxeofsymbolreg is expected. if set to 1, an iso/iec14443b eof is expected. note: setting this bit to 0 and additionally setting the 2 lsb in the rxeofsymbolreg to 0, disables the eof check
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 48 of 125 nxp semiconductors clrc663 contactless reader ic 9.12.3 rxwait_reg selects internal re ceiver settings. 9.12.4 rxthreshold_reg selects minimum threshold level for the bit decoder. 4 egt_check if set to 1, the egt is checked and if it is too long a protocol error is set. (this is only valid for iso/iec14443 type b) 3 emd_sup enables the emd suppression a ccording iso/iec14443. if an error occurs within the first three bytes, this frame is seen as emd and ignored. if rxforcecrcwrite is set, the fifo should not be read out before three bytes are written into. the fifo is cleared automatically in case of an emd error. a collision is treated as error. 2 to 0 baudrate defines the baud rate of the receiving signal. 000b: rfu 001b: rfu 010b: 26 kbd 011b: 52 kbd 100b: 106 kbd 101b: 212 kbd 110b: 424 kbd 111b: 847 kbd table 124: description of rxctrl_ reg bits bit symbol description table 125. rxwait_reg register (address 36h); reset value: 90h bit 7 6 5 4 3 2 1 0 symbol rxwaite tu rxwait access rights r/w r/w table 126: description of rxwait_reg bits bit symbol description 7 rxwaitetu if set to 0, the rxwait time is rxwait ? 16/13.56 mhz if set to 1, the rxwait time is rxwait ? (0.5/dbfreq) 6 to 0 rxwait defines the time after sending, where every input is ignored. table 127: rxthreshold_reg register (address 37h); reset value: 3fh bit 7 6 5 4 3 2 1 0 symbol minlevel minlevelp access rights r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 49 of 125 nxp semiconductors clrc663 contactless reader ic 9.12.5 rcv_reg 9.12.6 rxana_reg table 128: description of rxthreshold_reg bits bit symbol description 7 to 4 minlevel defines the minlevel of the reception. note: the minlevel should be higher than the noise level in the system 3 to 0 minlevelp defines the minlevel of the phase shift detector unit table 129. rcv_reg register (address 38h); reset value: 12h bit 7 6 5 4 3 2 1 0 symbol rcv_rx _single - sigpro_in_sel - colllevel access rights r/w rfu r/w rfu r/w table 130: description of rcv_reg bits bit symbol description 7 rcv_rx_ single single rx input pin mode; 0 -> fully differential; 1 -> quasi-differential 6- rfu 5 to 4 sigpro_in_sel defines input for the signal processing unit 00b - idle 01b - internal analogue block (rx) 10b - signal in over envelope 11b - signal in over s3c-generic 3 to 2 - rfu 1 to 0 colllevel defines how strong a signal must be to be interpreted as a collision. 00b - collision has at least 1/8 of signal strength 01b - collision has at least 1/4 of signal strength 10b - collision has at least 1/2 of signal strength 11b - collision detection is switched off. table 131. rxana_reg register (address 39h); reset value: 0ah bit 7 6 5 4 3 2 1 0 symbol vmid_r_sel - - rcv_hpcf rcv_gain access rights r/w rfu rfu r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 50 of 125 nxp semiconductors clrc663 contactless reader ic 9.13 description/ clock register 9.13.1 serialspeed_reg 9.13.2 lpo_trimm_reg 9.13.3 pll_ctrl_reg register control register for the integern pll. table 132: description of rxana_ reg bits bit symbol description 7, 6 vmid_r_setl selectio n of resistance between vdd and vss: 00h->1.4 k ? (recommended); 01h->2.8 k ? ; 10h->5.7 k ? ; 11h->11 k ? 5, 4 - rfu 3, 2 rcv_hpcf the rcv_hpcf [1:0] signals allow 4 different settings of the base band amplifier lower cut-off frequen cy from ~40 khz to ~300 khz. 1 to 0 rcv_gain with rcv_gain[1:0] four differ ent gain settings from 30 db and 60 db can be configured (differential output voltage/differential input voltage) table 133. serialspeed_reg register (address3bh); reset value: 7ah bit 7 6 5 4 3 2 1 0 symbol br_t0 br_t1 access rights r/w r/w table 134: serialspeed _reg bits bit symbol description 7 to 5 br_t0 if br_t0 = 0: transfer speed = 27.12 mhz / (br_t1 + 1) if br_t0 > 0: transfer speed = 27.12 mhz / (br_t1 + 33) / 2^(br_t0 ? 1) refer to section 10.3.1 4 to 0 br_t1 if br_t0 > 0: transfer speed = 27.12 mhz / (br_t1 + 33) / 2^(br_t0 ?? 1) refer to digital interfaces uard refer to section 10.3.1 table 135. lpo_trim_reg register (address 3ch); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol lpo_trimm access rights r/w table 136: lpo_trim_ reg bits bit symbol description 7 to 0 lpo_trimm trimm value. refer to section 16.3 ? low power oscillator (lpo) ? note: if the trimm value is increased , the frequency of the oscillator decreases
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 51 of 125 nxp semiconductors clrc663 contactless reader ic 9.13.4 pll_div_out_reg 9.14 description/lpcd register 9.14.1 lpcd_qmin_reg table 137. pll_ctrl_reg register (address3dh); reset value: 04h bit 7 6 5 4 3 2 1 0 symbol clkoutsel clkout_ en pll_pd pll_divfb access rights r/w r/w r/w r/w table 138: description of pll_ctrl_reg register bits bit symbol description 7 to 4 clkout 0000h.0001h... the pin cl kout is not used as clock output. it is used as io 0010b - pin clkout is hold on 0 0011b - pin clkout is hold on 1 0011b - pin clkout shows the output of the analog pll 0100b - pin clkout shows 27.12 mhz from the crystal 0101b - pin clkout shows 13.56 mhz derived from the crystal 0110b - pin clkout shows 6.78 mhz derived from the crystal 0111b - pin clkout shows 3.39 mhz derived from the crystal 1000b - pin clkout is toggled by the timer 0 overflow 1001b - pin clkout is toggled by the timer 1 overflow 1010b - pin clkout is toggled by the timer 2 overflow 1011b - pin clkout is toggled by the timer 3 overflow 1100b- 1111b rfu 3 clkout_en enables the clock at pin clkout 2 pll_pd pll power down 1-0 pll_divfd pll feedback divider table 139. pll_div_out_reg register (address 3eh); reset value: 20h bit 7 6 5 4 3 2 1 0 symbol plldiv_out access rights r/w table 140: plldiv_out_reg bits bit symbol description 7-0 plldiv_out pll output divider factor; refer to section 16.2 table 141. lpcd_qmin_reg register (address 3fh); reset value: 48h bit 7 6 5 4 3 2 1 0 symbol lpcd_i max.5 lpcd_i max.4 lpcd_qmin access rights dy/r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 52 of 125 nxp semiconductors clrc663 contactless reader ic 9.14.2 lpcd_qmax_reg 9.14.3 lpcd_imin_reg 9.14.4 lpcd_i_result_reg table 142: lpcd_qmin_reg bits bit symbol description 7, 6 lpcd_imax defines the highest two bits of the higher border for the lpcd. if the measurement value of the i channe l is higher than lpcd imax, a lpcd irq is raised 5 to 0 lpcd_qmin defines the lower border for the lpcd. if the measurement value of the q channel is higher than lpcd qmin, a lpcd irq is raised table 143. lpcd_qmax_reg register (address 40h); reset value: 12h bit 7 6 5 4 3 2 1 0 symbol lpcd_i max.3 lpcd_ imax.2 lpcd_qmax access rights dy/r/w r/w r/w table 144: lpcd_qmax_reg bits bit symbol description 7 to 6 lpcd_imax.3 -.2 defines the mid two bits of the higher border for the lpcd. if the measurement value of the i channe l is higher than lpcd imax, a lpcd irq is raised 5 to 0 lpcd_qmax defines the higher border fo r the lpcd. if the measurement value of the q channel is higher than lpcd qmax, a lpcd irq is raised table 145. lpcd_imin_reg register (address 41h); reset value: 88h bit 7 6 5 4 3 2 1 0 symbol lpcd_i max.1 lpcd_ imax.0 lpcd_imin access rights dy/r/w r/w r/w table 146: lpcd_imin_reg bits bit symbol description 7 to 6 lpcd_imax defines lowest two bits of the higher border for the lpcd. if the measurement value of the i channe l is higher than lpcd imax, a lpcd irq is raised. 5 to 0 lpcd_imin defines the lower border for the lpcd. if the measurement value of the i channel is lower than lpcd imin, a lpcd irq is raised. table 147. lpcd_i_result_reg register (address 42h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - - lpcd_i_result access rights rfu rfu r
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 53 of 125 nxp semiconductors clrc663 contactless reader ic 9.14.5 lpcd_result_q_reg 9.15 description/pad register 9.15.1 paden_reg table 148: lpcd_i_result_reg bits bit symbol description 7 to 6 - rfu 5 to 0 lpcd_i_ result shows the result of the last lpcd (i-channel) table 149. lpcd_result_q_reg register (address 43h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - lpcd_ irq_clr lpcd_reslult_q access rights rfu dy/r/w r table 150: lpcd_q_result_reg bits bit symbol description 7- rfu 6 lpcd_irq_clr if set no lpcd irq is raised any more until the next lpcd procedure. can be used by software to clear the interrupt source 5 to 0 lpcd_q_ result shows the result of the last lpcd (q-channel) table 151. paden_reg register (address 44h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol gpio0_ en clkout_ en ifsel1_ en ifsel0_ en tck_en tdi_en tdo_ en tms_ en access rights r/w r/w r/w r/w r/w r/w r/w r/w table 152: paden_reg bits bit symbol description 7 gpio0_en enables the output fu nctionality of the gpio0 pin 6 clkout_en enables the output functionality of the clkout pin 5 ifsel1_en enables the output functionality of the ifsel1 pin 4 ifsel0_en enables the output functionality of the ifsel0 pin 3 tck_en enables the output functional ity of the tck of the boundary scan interface 2 tmi_en enables the output functionalit y of the tmi of the boundary scan interface 1 tdo_en enables the output functionality of the tdo of the boundary scan interface 0 tms_en enables the output functionality of the tms of the boundary scan interface
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 54 of 125 nxp semiconductors clrc663 contactless reader ic 9.15.2 padout_reg 9.15.3 padin_reg table 153. padout_reg register (address 45h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol gpio0 _out clkout_ out ifsel1_ out ifsel0 _out tck_ out tmi_ out tdo_ out tms_ out access rights r/w r/w r/w r/w r/w r/w r/w r/w table 154: padout _reg bits bit symbol description 7 gpio0_out output buffer of the gpio0/sigin pin 6 clkout_out output buffer of the clkout pin 5 ifsel1_out output buffer of the ifsel1 pin 4 ifsel0_out output buffer of the ifsel0 pin 3 tck_out output buffer of the tck pin 2 tdi_out output buffer of the tdi pin 1 tdo_out output buffer of the tdo pin 0 tms_out output buffer of the tms pin table 155. padin_reg register (address 46h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol gpio0_ in clkout _in ifsel1_ in ifsel0_ in tck_in tdi_in tdo_in tms_in access rights rrrrrrrr table 156: padin_ reg bits bit symbol description 7 gpio0_in input buffer of the gpio0/sigin pin 6 clkout_in input buffer of the clkout pin 5 ifsel1_in input buffer of the ifsel1 pin 4 ifsel0_in input buffer of the ifsel0 pin 3 tck_in input buffer of the tck pin 2 tdi_in input buffer of the tdi pin 1 tdo_in input buffer of the tdo pin 0 tms_in input buffer of the tms pin
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 55 of 125 nxp semiconductors clrc663 contactless reader ic 9.15.4 sigout_reg 9.16 description/transm itter symbol register 9.16.1 txbitmod_reg table 157. sigout_reg register (address 47h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol pad speed -- - sigoutsel access rights r/w rfu rfu rfu r/w table 158: sigout _reg bits bit symbol description 7 padspeed if set, the pads are operating fa ster. the edges are faster, but it can be a problem if a lot of pads are switching at the same time. 6 to 4 - rfu 3 to 0 sigoutsel 0000b, 0001b the pin sigout is tristate 0010b the pin sigout is 0 0011b the pin sigout is 1 0100b the pin sigout shows the tx-envelope 0101b the pin sigout shows the tx-active signal 0110b the pin sigout shows the s3c (generic) signal 0111b the pin sigout shows the rx-envelope (only valid for iso/iec 14443a, 106 kbd) 1000b the pin sigout shows the rx-active signal 1001b the pin sigout shows the rx-bit signal table 159. txbitmod_reg register (address 48h); reset value: 20h bit 7 6 5 4 3 2 1 0 symbol txmsb first - txparity type - txstopbit type -txstart bittype txstart biten access rights r/w rfu r/w rfu r/w rfu r/w r/w table 160: description of txbitmod_reg bits bit symbol description 7 txmsbfirst if set to 1, data bytes are interpreted msb first for data transmission, which means data is converted. if this bit is set to 0, data is interpreted lsb first. 6- rfu 5 txparitytype defines the type of the parity bit. if set to 1, odd parity is calculated, otherwise even parity is calculated 4- rfu 3 txstopbittype defines the type of the st op-bit (0b: logic zero / 1b: logic one)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 56 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.2 txdatacon_reg 2- rfu 1 txstartbittype defines the type of the st art-bit (0b: logic zero / 1b: logic one) 0 txstartbiten if set to 1, a start-bit will be sent table 160: description of txbitmod_reg bits ?continued bit symbol description table 161. txdatacon_reg (address 4ah); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol dcodetype dscfreq dscfreq access rights r/w r/w r/w table 162: description of txdatacon_reg bits bit symbol description 7 to 4 dcodetype specifies the type of encoding of data to be used 0000b - no special coding 0001b - collider datastream is decoded 0010b - rfu 0011b - rfu 0100b - return to zero code - pulse at first position 0101b - return to zero code - pulse at 2nd position 0110b - return to zero code - pulse at 3rd position 0111b - return to zero code - pulse at 4th position 1000b - 1 out of 4 coding 1001b - 1 out of 256 code (range 0 - 255) [i-code sli] 1010b - 1 out of 256 code (range 0 - 255; 0x00 is encoded with no modulation, value 256 not used) [i-code 1] 1011b - 1 out of 256 code (range 0 - 255; 0x00 is encoded with a pulse on last position) [i code quite value] 1100b - pulse internal encoded (pie) [iso(iec18000-3 mode 3] 1101b - rfu 1110b - rfu 1111b - rfu 3 dscfreq specifies the subcarrier frequency of the used envelope. 0b 424 khz 1b 848 khz note: this setting is only relevant if an envelope is used which involves a subcarrier, e.g. manchester with subcarrier coding. 2 to 0 dbfreq specifies the frequency of the bit stream 000b - rfu 001b - rfu 010b - 26 khz 011b - 53 khz 100b - 106 khz 101b - 212 khz 110b - 424 khz 111b - 848 khz
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 57 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.3 txdatamod_reg 9.16.4 txsymfreq_reg table 163. txdatamod_reg register (address 4bh); reset value:04h bit 7 6 5 4 3 2 1 0 symbol frame step dmilleren dpulsetype dinvert denvtype access rights r/w r/w r/w r/w r/w table 164: description of txdatamod_reg bits bit symbol description 7 framestep if set to 1, at every start of tr ansmission, each byte of data is sent in a separate frame. sof and eof is appended to the data byte according to the framing settings. after one by te is transmitted, the txencoder waits for a new start trigger to cont inue with the next byte (trigger is generated automatically). if set to 0, transmission is done in the used way, where after a start trigger all data bytes are sent and the framing is done for the complete data stream only once. 6 dmilleren if set to 1, pulse modulati on is applied according to modified miller code. note: this bit shall only be set if dpulsetype is set to 01(bin) 5 to 4 dpulsetype specifies which type of pulse modulation is selected. 00b: no pulse modulation 01b: pulse starts at beginning of bit 10b: pulse starts at beginning of second bit half 11b: pulse starts at beginning of third bit quarter note: if dmilleren is set to 1, dpulsetype must be set to 01b 3 dinvert if set to 1, the output envelope is inverted. 2 to 0 denvtype specifies the type of envelope used for transmission of data packets. the selected envelope type is applied to the pseudo bit stream. 000b: direct output 001b: manchester code 010b: manchester code with subcarrier 011b: bpsk 100b: rz (pulse of half bit length at beginning of second half of bit) 101b: rz (pulse of half bit length at beginning of bit) 110b: rfu 111b: rfu table 165. txsymfreq_reg (address 4ch); reset value: 50h bit 7 6 5 4 3 2 1 0 symbol s32sc freq s32bfreq s10sc freq s10b freq access rights r/w r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 58 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.5 txsym0h_reg 9.16.6 txsym0l_reg table 166: description of txsymfreq_reg bits bit symbol description 7 s32scfreq specifies the frequency of the subcarrier of symbol2 and symbol3 0b...424 khz 1b...848 khz 6 to 4 s32bfreq specifies the frequency of the bit stream of symbol2 and symbole3 000b...rfu 001b...rfu 010b...26 khz 011b...53 khz 100b...106 khz 101b...212 khz 110b...424 khz 111b...848 khz 3 s10scfreq specifies the frequency of the subcarrier of symbol0 and symbol1 0b...424 khz 1b...848 khz 2 to 0 s10bfreq specifies the frequency of the bit stream of symbol0 and symbol1 000b...rfu 001b...rfu 010b...26 khz 011b...53 khz 100b...106 khz 101b...212 khz 110b...424 khz 111b...848 khz table 167. txsym0h_reg (address 4dh); reset value: 40h bit 7 6 5 4 3 2 1 0 symbol symbol0_h access rights r/w table 168: description of txsym0h_reg bits bit symbol description 7 to 0 symbol0h higher 8 bits of symbol definition for symbol0 table 169. txsym0l_reg (address 4eh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol symbol0_l access rights r/w table 170: description of txsym0l_ reg bits bit symbol description 7 to 0 symbol0 lower 8 bits of symbol definition for symbol0
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 59 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.7 txsym1h_reg 9.16.8 txsym1l_reg 9.16.9 txsym2_reg 9.16.10 txsym3_reg table 171. txsym1h_reg (address 4fh); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol symbol1_h access rights r/w table 172: description of txsym1h_reg bits bit symbol description 7 to 0 symbol1_h higher 8 bits of symbol definition for symbol1 table 173. txsym1l_reg (address 50h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol symbol1_l access rights r/w table 174: description of txsym1l_reg bits bit symbol description 7 to 0 symbol1_l lower 8 bits of symbol definition for symbol1 table 175. txsym2_reg (address 51h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol symbol2 access rights r/w table 176: description of txsym2_reg bits bit symbol description 7 to 0 symbol2 symbol definition for symbol2 table 177. txsym3_reg (address 52h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol symbol3 access rights r/w table 178: description of txsym3_reg bits bit symbol description 7 to 0 symbol3 symbol definition for symbol3
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 60 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.11 txsym10len_reg 9.16.12 txsym32len_reg 9.16.13 txsym10burstctrl_reg table 179. txsym10len_reg (address 53h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol sym1len sym0len access rights r/w r/w table 180: description of txsym10len_reg bits bit symbol description 7 to 4 sym1len specifies the number of valid bits of the symbol definition of symbol1. the range is from 1 bit (value 0000b) to 16 bits (value 1111b) 3 to 0 sym0len specifies the number of valid bits of the symbol definition of symbol0. the range is from 1 bit (value 0000b) to 16 bits (value 1111b) table 181. txsym32len_reg (address 54h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - sym3len - sym2len access rights rfu r/w r/w r/w rfu r/w r/w r/w table 182: description of txsym32len_reg bits bit symbol description 7- rfu 6 to 4 sym3len specifies the number of valid bits of the symbol definition of symbol3. the range is from 1bit (000b) to 8 bits (111b) 3- rfu 2 to 0 sym2len specifies the number of valid bits of the symbol definition of symbol2. the range is from 1bit (000b) to 8 bits (111b) table 183. txsym10burstctrl_reg register (address 55h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - sym1 burst type sym1burst len only sym1 bursten - sym0 burst type sym0b urst only sym0bu rsten access rights rfu r/w r/w r/w rfu r/w r/w r/w table 184: description of txsym10burstctrl_reg bits bit symbol description 7- rfu 6 sym1burst type specifies t he type of the burst of symbol1 (logical zero / logical one) 5 sym1burst only if set to 1 symbol1 consists only of a burst and no symbol pattern
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 61 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.14 txsym10mod reg 4 sym1bursten enables the burst of sy mbol 1 of the length defined in txsym10burstlen_reg 3- rfu 2 sym0burst type specifies t he type of the burst of symbol 0 (logical zero / logical one) 1 sym0burst only if set to 1, symbol 0 consists only of a burst and no symbol pattern 0 sym0bursten enables the burst of sy mbol 0 of the length defined in txsym10burstlen_reg table 184: description of txsym10burstctrl_reg bits ?continued bit symbol description table 185. txsym10mod_reg register (address 56h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol - s10 milleren s10pulsetype s10invert s10envtype access rights rfu r/w r/w r/w r/w table 186: description of txsym10mod_reg bits bit symbol description 7- rfu 6 s10milleren if set to 1, pulse modulati on is applied according to modified miller code. note: this bit shall be set only if s10pulsetype is set to 01 5 to 4 s10pulsetype specifies which type of pulse modulation is selected. 00b: no pulse modulation 01b: pulse starts at beginning of bit 10b: pulse starts at beginning of second bit half 11b: pulse starts at beginning of third bit quarter 3 s10inv if set to 1, the output envelope is inverted. 2 to 0 s10envtype specifies the type of envelope used for transmission of symbol 0 and symbol 1. the pseudo bit stream is logically combined with the selected envelope type. 000b: direct output 001b: manchester code 010b: manchester code with subcarrier 011b: bpsk 100b: rz (pulse of half bit length at beginning of second half of bit) 101b: rz (pulse of half bit length at beginning of bit) 110b - 111b: rfu
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 62 of 125 nxp semiconductors clrc663 contactless reader ic 9.16.15 txsym32mod_reg 9.17 description/recei ver symbol register 9.17.1 rxbitmod_reg table 187. txsym32mod_reg register (address 57h); reset value: 50h bit 7 6 5 4 3 2 1 0 symbol - s32 milleren s32pulsetype s32invert s32envtype access rights rfu r/w r/w r/w r/w table 188: description of txsym32mod_reg bits bit symbol description 7- rfu 6 s32milleren if set to 1, pulse modulati on is applied according to modified miller code. note: this bit shall be set only if s32pulsetype is set to 01 5 to 4 s32pulsetype specifies which type of pulse modulation is selected. 00b: no pulse modulation 01b: pulse starts at beginning of bit 10b: pulse starts at beginning of second bit half 11b: pulse starts at beginning of third bit quarter 3 s32inv if set to 1, the output envelope is inverted 2 to 0 s32envtype specifies the type of envelope used for transmission of symbol 0 and symbol 1. the pseudo bit stream is logically combined with the selected envelope type. 000b: direct output 001b: manchester code 010b: manchester code with subcarrier 011b: bpsk 100b: rz (pulse of half bit length at beginning of second half of bit) 101b: rz pulse of half bit length at beginning of bit) 110b - 111b: rfu table 189: rxbitmod_reg (address 58h); reset value: 02h bit 7 6 5 4 3 2 1 0 symbol - - rxstop oninvpar rxstop onlength rxmsb first rxstop biten rxparity type - access rights rfu rfu r/w r/w r/w r/w r/w rfu
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 63 of 125 nxp semiconductors clrc663 contactless reader ic 9.17.2 rxeofsym_reg table 190: description of rxbitmod_reg bits bit symbol description 7 to 6 - rfu 5 rxstopon invpar if set to 1, inverse parity bit is a stop condition 4 rxstop onlength if set to 1, data reception stops when the number of received bytes reach the defined frame length. the value for the frame length is taken from the first data-byte received. 3 rxmsbfirst if set to 1, data bytes are in terpreted msb first fo r data reception, which means data is converted at the clcopro interface. if this bit is set to 0, data is interpreted lsb first 2 rxstopbiten set to 1, a stop- bit is expected and will be checked and extracted from data stream. additionally on detection of a stop-bit a reset signal for the demodulator is generator to enable a re-synchronization of the demodulator. if the expected stop-bit is incorrect, a frame error flag is set and the reception is aborted. note: a stop bit is always considered to be a logic 1 1 rxparitytype defines which type of the parity-bit is calculated. 0b:?????..even parity 1b:?????..odd parity 0- rfu table 191. rxeofsym_reg (address 59h); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol rxeofsymbol access rights r/w table 192: description of rxeofsym_reg bits bit symbol description 7 to 0 rxeof symbol this value defines the pattern of the eof symbol with a maximum length of 4 bit. every tuple of 2 bits of the rxeofsymbol encodes one bit of the eof symbol. a 00 tuple closes the symbol. in this way symbols with less than 4 bits can be defined, starting with the bit0 and bit1. the leftmost active symbol pa ttern is processed first, which means the pattern is expected first. if the bit0 and bit1 are both zero, the eof symbol is disabled. the following mapping is defined: 00b - no symbol bit 01b - zero value 10b - one value 11b - collision example: 00011101b (1dh): zero-collision-zero 11101000b (e8h): no symbol because two lsbits are 0
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 64 of 125 nxp semiconductors clrc663 contactless reader ic 9.17.3 rxsyncvalh_reg 9.17.4 rxsyncvall_reg 9.17.5 rxsyncmod_reg table 193. rxsyncvalh_reg register (address5ah); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol rxsyncvalh access rights r/w table 194: description of rxsyncvalh_reg bits bit symbol description 15 to 0 rxsyncvalh defines the high byte of the sync pattern, which must be in front of the receiving data. table 195. rxsyncvall_reg register (address 5bh); reset value: 01h bit 7 6 5 4 3 2 1 0 symbol rxsyncvall access rights r/w table 196: description of rxsyncvall_reg bits bit symbol description 7 to 0 rxsyncvall defines the low byte of the sync pattern, which must be in front of the receiving data. table 197. rxsyncmode register (address 5ch); reset value: 00h bit 7 6 5 4 3 2 1 0 symbol synclen syncnegedge lastsynchalf synctype access rights r/w r/w r/w r/w table 198: description of rxsyncmod_reg bits bit symbol description 7 to 4 synclen defines how many bits of synclen are valid. 3 syncnegedge is used for sof with no correlation peak. the first negative edge of the correlation is used for defining the bid grid 2 lastsynchalf the last bit of the sync mode has only half of the length compared to all other bits. (iso/iec18000-3 mode 3) 1 to 0 synctype set to 0 all 16 bits of syncval are interpreted as burst. set to 1 a nibble of bits is interpreted as one bit in following way: {data, coll} data = zero or one; coll = 1 means a collision on this bit. note: if coll = 1 the value of data is ignored. set to 2 the synchronisation is done at every start bit of each byte (type b)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 65 of 125 nxp semiconductors clrc663 contactless reader ic 9.17.6 rxmod_reg 9.17.7 rxcorr_reg table 199: rxmod_reg register (address 5dh); reset value: 08h bit 7 6 5 4 3 2 1 0 symbol - - prefilter rectfilter sync high corr inv fsk bpsk access rights rfu rfu r/w r/w r/w r/w r/w r/w table 200: description of rxmod_reg bits bit symbol description 7 to 6 - rfu 5 prefilter if set to one 4 samples are combined to one data. (average) 4 rectfilter if set to one, the adc-values are changed to a more rectangular wave shape 3 synchigh defines if the bit grid is fixe d at maximum (1) or at minimum (0) value of the correlation. 2 corrinv defines a logical one: 0: subcarrier / no subcarrier 1 fsk if set to 1, the demodulation scheme is set to fsk 0 bpsk if set to 1, the modulation scheme is bpsk table 201: rxcorr_reg register (address 5eh); reset value: 80h bit 7 6 5 4 3 2 1 0 symbol corrfreq corrspeed corrlen - - - access rights r/w r/w r/w r/w r/w rfu rfu rfu table 202: description of rxcorr_reg bits bit symbol description 7, 6 corrfreq 00b: 212 khz 01b: 424 khz 10b: 848 khz 11b: 848 khz 5, 4 corrspeed defines the number of clocks used for one correlation. 00b: iso/iec 14443 01b: icode 53 kbd, felica 424 kbd 10b: icode 26 kbd, felica212 kbd 11b: rfu 3 corrlen defines the length of the correlation data. (64 or 32 values) set to one the lengths is 32 valu es. (iso/iec18000-3 mode3, 2 pulse manchester 848 khz subcarrier) 2 to 0 - rfu
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 66 of 125 nxp semiconductors clrc663 contactless reader ic 9.17.8 fabcali_reg 9.18 description/version register 9.18.1 version_reg 10. digital interfaces 10.1 microcontroller interface type the clrc663 supports direct interfacing of various hosts as the spi, i 2 c, i 2 cl and serial uart interface type. the clrc663 resets its interface and checks the current host interface type automatically having performed a power-on or hard reset. the clrc663 identifies the host interface by the means of th e logic levels on the control pins after the reset phase. this is done by a combinati on of fixed pin connections.the following table shows the different configurations: table 203: fabcali _reg register (address 5fh); reset value: b2h bit 7 6 5 4 3 2 1 0 symbol fabcali access rights r/w table 204: description of fabcali_reg bits bit symbol description 7 to 0 fabcali fab calibration of the receiver note: do not change boot value table 205. version_reg register (address 7fh); reset value: 10h bit 7 6 5 4 3 2 1 0 symbol version subversion access rights rr table 206: version_reg bits bit symbol description 7 to 4 version includes the version of the clrc663 3 to 0 subversion includes the subversion of the clrc663 table 207: connection scheme for detecting the different interface types uart spi i 2 c i 2 c-l if0 i/o rx mosi adr1 adr1 if1(scl) i/o - sck scl scl if2 i/o tx miso adr2 sda if3(sda) i/o trigger nss sda adr2 if1sel0 i 0 0 1 1 if1sel1 i 0 1 0 1
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 67 of 125 nxp semiconductors clrc663 contactless reader ic 10.2 spi compatible interface a serial peripheral interface (spi compatible) is supported to enable high speed communication to the host. the spi interface c an handle data speed of up to 10 mbit/s. in the communication with a host clrc663 acts as a slave receiving data from the external host for register settings and to send and receive data relevant for the communication on the rf interface. 10.2.1 general an interface compatible to an spi interface enables a high-speed serial communication between the clrc663 and a ? -controller for the communication. the implemented spi compatible interface is according to a standard spi interface. for timing specification refer to table 242 ? spi timing characteristics ? . the clrc663 acts as a slave during the spi communication. the spi clock sck has to be generated by the master. data communication from the master to the slave uses the line mosi. line miso is used to send data back from the clrc663 to the master. on both lines (mosi, miso) each data byte is sent by msb first. data on mosi line should be stable on rising edge of the clock line and c an change on falling edge. the same is valid for the miso line. data is pr ovided by the clrc663 on falling edge and is stable during rising edge. remark: clock polarity: idle low 10.2.2 read data to read out data using the spi compatible interface the following byte order has to be used. it is possible to read out up to n-data bytes. the first sent byte defines both, the mode itself and the address byte. remark: the most significant bit (m sb) has to be send first. fig 12. connection to host with spi 001aal998 clrc663 sck sck mosi mosi miso miso nss nss table 208: byte order for mosi and miso byte 0 byte 1 byte 2 to byte n byte n + 1 mosi address 0 address 1 address 2 ??.. address n 00 miso x data 0 data 1 ??.. data n ? 1 data n
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 68 of 125 nxp semiconductors clrc663 contactless reader ic 10.2.3 write data to write data to the clrc663 using the spi interface the following byte order has to be used. it is possible to write out up to n-data bytes by only sending one?s address byte. the first send byte defines both, the mode itself and the address byte. remark: the most significant bit (m sb) has to be send first. 10.2.4 address byte the address byte has to fulfil the following format: the lsb bit of the first byte defines the used mode. to read data from the clrc663 the lsb bit is set to logic 1. to write data to the clrc663 the msb bit has to be set to logic 0. the bits 6 to 0 define the address byte. note: when writing the sequence [address byte ][data1][data2][data3]..., [data1] is written to address [address byte], [data2] is written to addr ess [address byte + 1] and [data3] is written to [address byte + 2]. exception: this auto increment of the address byte is not valid for writing data to the fifo 10.2.5 timing specification spi the timing conditions for spi interface is as follow: table 209: byte order for mosi and miso byte 0 byte 1 byte 2 to byte n byte n + 1 mosi address 0 data 0 data 1 ??.. data n ?? 1 data n miso x x x ??.. x x table 210. address byte 0 register; address mosi 7 6 5 4 3 2 1 0 address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read) 0 (write) msb lsb table 211. timing conditions spi symbol parameter conditions min typ max unit t sckl sck low time v dd(pvdd) ? v dda = v ddd = v dd(tvdd) ; v ssa =v ssd =v ss(pvss) =v ss(tvss) =0v 50--ns t sckh sck high time v dd(pvdd) ? v dda = v ddd = v dd(tvdd) ; v ssa =v ssd =v ss(pvss) =v ss(tvss) =0v 50 ns t h(sckh-d) sck high to data input hold time sck to changing mosi; v dd(pvdd) ? v dda =v ddd = v dd(tvdd) ; v ssa =v ssd =v ss(pvss) =v ss(tvss) =0v 25 ns t su(d-sckh) data input to sck high set-up time changing mosi to sck; v dd(pvdd) ? v dda =v ddd =v dd(tvdd) ; v ssa =v ssd =v ss(pvss) =v ss(tvss) =0v 25 ns t h(sckl-q) sck low to data output hold time sck to changing miso; v ssa =v ssd =v ss(pvss) =v ss(tvss) =0v -25ns t (sckl-nssh) sck low to nss high time 0 ns t nssh nss high time before communication 50 - - ns
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 69 of 125 nxp semiconductors clrc663 contactless reader ic remark: to send more bytes in one data stream the nss signal must be low during the send process. to send more than one data stream the nss signal must be high between each data stream. 10.3 uart interface 10.3.1 selection of the transfer speeds the internal uart interf ace is compatible to a rs232 serial interface. table 213 ? selectable transfer speeds ? describes examples for different transfer speeds and relevant register settings. the resulting transfer speed error is less than 1.5 % for all described transfer speeds. the defau lt transfer speed is 115.2 kbit/s. to change the transfer speed, the host contro ller has to write a value for the new transfer speed to the register serialspeedreg . the bits br_t0 and br_t1 define factors to set the transfer speed in the serialspeedreg . table 212 ? settings of br_t0 and br_t1 ? describes the settings of br_t0 and br_t1 . fig 13. connection to host with spi 001aaj641 t sckl t sckh t sckl t dqxch t dshqx t dqxch t h(sckl-q) t clsh sck mosi miso msb msb lsb lsb nss table 212. settings of br_t0 and br_t1 br_t0 01234567 factor br_t011248163264 range br_t1 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 table 213: selectable transfer speeds transfer speed (kbit/s) serial speedreg transfer speed accuracy (%) decimal hexadecimal 7.2 250 fah ? 0.25 9.6 235 ebh 0.32 14.4 218 dah ? 0.25 19.2 203 cbh 0.32
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 70 of 125 nxp semiconductors clrc663 contactless reader ic the selectable transfer speeds as shown in table 213 ? selectable transfer speeds ? are calculated according to the following formulas: if br_t0 = 0: transfer speed = 27.12 mhz/( br_t1 +1) if br_t0 > 0: transfer speed = 27.12 mhz/( br_t1 +33)/2 (br_t0 ? 1) remark: transfer speeds above 1228.8 k are not supported. 10.3.2 framing remark: for data and address bytes the lsb bit has to be sent first. no parity bit is used during transmission. read data: to read out data using the uart interface the flow described below has to be used. the first send byte defines both the mode itself and the address. remark: note: the trigger on if3 pin has to be set, otherwise no ?read data? is possible 38.4 k 171 abh 0.32 57.6 k 154 9ah ? 0.25 115.2 k 122 7ah ? 0.25 128 k 116 74h ? 0.06 230.4 k 90 5ah ? 0.25 460.8 k 58 3ah ? 0.25 921.6 k 28 1ch 1.45 1228.8 k 21 15h 0.32 table 213: selectable transfer speeds transfer speed (kbit/s) serial speedreg transfer speed accuracy (%) decimal hexadecimal table 214: uart framing length value start bit 1 bit 0 data bits 8 bit data stop bit 1 bit 1 table 215: byte order to read data byte 0 byte 1 rx address tx data 0
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 71 of 125 nxp semiconductors clrc663 contactless reader ic write data: to write data to the clrc663 using the uart interface the following structure has to be used. remark: note: the trigger on if3 pin has to be set, otherwise no ?write data? is possible the first send byte defines both, the mode itself and the address. 10.4 i 2 c-bus interface an inter ic (i 2 c) bus interface is supported to enable a low cost, low pin count serial bus interface to the host. the implemented i 2 c interface is implemented according the nxp semiconductors i 2 c interface specification, rev. 3.0, june 2007. the implemented fig 14. schematic diagram to read data 001aam298 a0 a1 sa a2 a3 tx rx a4 a5 a6 rd/ nwr so d0 data address d1 sa d2 d3 d4 d5 d6 d7 so table 216: byte order to write data byte 0 byte 1 rx address 0 data 0 tx address 0 fig 15. schematic diagram to write data 001aam299 a0 a1 sa a2 a3 tx rx a4 a5 a6 rd/ nwr so a0 address address a1 sa a2 a3 a4 a5 a6 rd/ nwr so d0 data d1 sa d2 d3 d4 d5 d6 d7 so
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 72 of 125 nxp semiconductors clrc663 contactless reader ic interface can only act in slave mode. th erefore no clock generation and access arbitration is implemented in the clrc663. high speed mode is not supported by the clrc663 10.4.1 general the implemented interface is compatible to the ?i 2 c-bus specification version 3.0, june 2007?. the clrc663 can act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode plus. sda is a bidirectional line, connected to a po sitive supply voltage via a pull-up resistor. both lines sda and scl are set to high level if no data is transmitted. the clrc663 has a tri-state output stage to perform the wired-and function. data on the i 2 c-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 mbit/s in the fast mode plus. if the i 2 c interface is selected, a spike suppression acco rding to the i 2 c interface specification on scl and sda is activated. for timing requirements refer to table 243 ? i 2 c-bus timing in fast mode and fast mode plus ? 10.4.2 data validity data on the sda line shall be stable during the high period of the clock. the high or low state of the data line shall only chan ge when the clock signal on scl is low. 10.4.3 start and stop conditions to handle the data transfer on the i 2 c-bus, unique start (s) and stop (p) conditions are defined. a start condition is defined with a high-to- low transition on the sda line while scl is high. fig 16. i 2 c-bus interface 001aam000 clrc663 sda scl pull-up network pull-up network microcontroller fig 17. bit transfer on the i 2 c-bus. 001aam300 data line stable; data valid change of data allowed sda scl
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 73 of 125 nxp semiconductors clrc663 contactless reader ic a stop condition is defined with a low-to-high transition on the sda line while scl is high. the master always generates the start and st op conditions. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus stays busy if a repeated start (sr) is generated instead of a stop condition. in this respect, the start (s) and repeated start (sr) conditions are functionally identical. therefore, the s symbol will be us ed as a generic term to re present both the start and repeated start (sr) conditions. 10.4.4 byte format each byte has to be followed by an ackno wledge bit. data is transferred with the msb first, see figure 21 ? first byte following the start procedure ? . the number of transmitted bytes during one data tr ansfer is unrestricted but shall fulfil the read/write cycle format. 10.4.5 acknowledge an acknowledge at the end of one data byte is mandatory. the acknowledge-related clock pulse is generated by the master. the transmitte r of data, either master or slave, releases the sda line (high) during the acknowledge clock pulse. the receiver shall pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. the master can then generate either a stop (p) condition to stop the transfer, or a repeated start (sr) condition to start a new transfer. a master-receiver shall indicate the end of data to the slave- transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. the slave-transmitter shall release the data line to allow the master to generate a stop (p) or repeated start (sr) condition. fig 18. start and stop conditions 001aam301 start condition s scl sda scl sda stop condition p
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 74 of 125 nxp semiconductors clrc663 contactless reader ic 10.4.6 7-bit addressing during the i 2 c-bus addressing procedure, the first by te after the start condition is used to determine which slave will be selected by the master. as an exception several address numbers are reserved. during device configuration, the designer has to ensure, that no collision with these reserved addresses is possible. check the corresponding i 2 c specification for a complete list of reserved addresses. for all clrc663 devices the upper 5 bits of the device bus address are reserved by nxp and set to 01010(bin). the remaining 2 bits (adr_2, adr_1) of the slave address can freely configured by the customer in order to prev ent collisions with other i 2 c devices by using the interface pins (refer to table 207 ) or the value of the i 2 c address eeprom register. (refer to table 227 ). fig 19. acknowledge on the i 2 c- bus fig 20. data transfer on the i 2 c- bus 001aam302 clock pulse for acknowledgement 1 scl from master data output by receiverer data output by transmitter 289 acknowledge start condition s not acknowledge 001aam303 msb acknowledgement signal from slave acknowledgement signal from receiver clock line held low while interrupts are serviced byte complete, interrupt within slave 1 2789 12 9 ack ack 3 - 8 sr or p p sr s or sr fig 21. first byte following the start procedure 001aam304 bit 6 bit 5 bit 4 slave address bit 3 bit 2 bit 1 bit 0 r/w msb lsb
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 75 of 125 nxp semiconductors clrc663 contactless reader ic 10.4.7 register write access to write data from the host controller via i 2 c to a specific register of the clrc663 the following frame format shall be used. the first byte of a frame indicates th e device address according to the i 2 c rules. the second byte indicates the register address followed by up to n-data bytes. in one frame all n-data bytes are written to the same register address. this enables for example a fast fifo access. the read/write bit shall be set to logic 0. 10.4.8 register read access to read out data from a specific register ad dress of the clrc663 the host controller shall use the procedure: first a write access to the specific register address has to be performed as indicated in the following frame. the first byte of a frame indicates th e device address according to the i 2 c rules. the second byte indicates the register address. no data bytes are added. the read/write bit shall be logic 0. having performed this write access, the read access can start. the host has to send the device address of the clrc663. as an answ er to this the clrc663 responds with the content of this register. in one frame all n-data bytes could be read from the same register address. this enables for example a fast fifo access or register polling. note: when writing the sequence [address byte ][data1][data2][data3]..., [data1] is written to address [address byte], [data2] is written to addr ess [address byte + 1] and [data3] is written to [address byte + 2]. exception: this auto increment of the address byte is not valid for writing data to the fifo the read/write bit shall be set to logic 1.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 76 of 125 nxp semiconductors clrc663 contactless reader ic 10.4.9 i 2 cl bus interface the clrc663 provides an additional interface according of a logical handling of an i 2 c interface. this logical interf ace fulfills in general the i 2 c specification, but all timing related factor will not be according t he standard. standard i/o pad are used for communication and the communication speed is limited to 5 mbau d. the protocol itself is equivalent to the fast mode protocol of i 2 c. the interphase address is 01010xxb, where the last two bit of the address can be defined by the application. to define this two bit there are basically two possibilities. defining it with a pin, where the hi gher bit is fixed to 0 or the configuration is fixed via eeprom. refer to th e eeprom configuration in section 12 . the output of this interface port is an asynch ronous parallel port with two control lines, read (rd) and write (wr). the write access is synchronized in the host interface module. fig 22. register read and write access 001aam305 ack 0 (w) ack 0 sa i2c slave address a7-a0 clrc663 register address a6-a0 ack data [7..0] so so [0..n] ack 0 (w) ack optional, if the previous access was on the same register address read cycle write cycle 0 sa i2c slave address a7-a0 clrc663 register address a6-a0 1 (r) ack sa sent by master sent by slave i2c slave address a7-a0 ack data [7..0] so [0..n] 0..n nack data [7..0] table 217. timing parameter i 2 cl parameter min max unit f scl 05mhz t hd;sta 80 - ns t low 100 - ns t high 100 - ns t su;sda 80 - ns t hd;dat 050ns t su;dat 020ns t su;sto 80 - ns t buf 200 - ns
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 77 of 125 nxp semiconductors clrc663 contactless reader ic 10.4.10 i 2 clsam bus interface the clrc663 provides an additional i2c interfac e. this logical interf ace fulfills in general the i 2 c specification, but all timi ng related factors will not be according the standard. refer to i 2 cl. to use this interface the configuration has to be defined via eeprom. (refer to section 12 ) one major difference between i 2 c and i 2 cl is the missing pull-up resistor. the driver of the pad must push the line to the desired logic voltage. to avoid that two drivers are pushing the line at the same time fo llowing regulations must be fulfilled: scl: as there is no clock stretching allo wed the scl is always under control of the master. a buskeeper structure is not required. sda: the sda line is shared between master and slave. therefore the master and the slave must have the control over the own driver enable line of the sda pad. following rules must be followed: ? in the idle phase the sda line is driven high by the master ? in the time between start and stop cond ition the sda line is driven by master or slave when scl is low. if scl is high the sda line is not driven by any device ? to keep the value on the sda line a buskeeper structure is needed for the line 10.5 boundary scan the clrc663 provides a boundary scan interface according the ieee 1149.1. this interface provides a possibilities to test interconnections withou t using physical test probes. this is done by ?test cells?, con nected to each pin, which overrides the functionality of this pin. to be able to program the ?test cells? the following commands are supported: the standard ieee 1149.1 describe s the four basic blocks necessa ry to use this interface: test access port (tap); tap controller; - instruction register, - data register; table 218. boundary scan command value command parameter in parameter out 0h bypass - - 7h 1h preload data (pin) - 1h sample - data (pin) 2h id code (default) - data (32) 3h user code - data (32) 4h clamp - - 5h high z - - 7h extest data (pin) data (pin) 8h interface on/off interface (8) - 9h register access read address (7) data ah register access write address (7) - data (8) -
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 78 of 125 nxp semiconductors clrc663 contactless reader ic 10.5.1 test access port (tap) the access port is the interface between the chip and the environment. there are three inputs: test clock (tck); test mode select (t ms); test data input (tdi) and one output: test data output.tck and tms are broadcast signals, tdi to tdo generate a serial line called scan path. advantage of this technique is that indepen dent of the numbers of boundary scan devices the complete path can be han dled with four signal lines. the signals tck, tms are directly connected with the tap controller. because these signals are responsible for the mode of the chip, all boundary scan devises in one scan path will be in the same tap mode. 10.5.2 test clock (tck) the tck pin is the clock for the jtag module. th is clock is provided so the test logic can operate independently of any ot her system clocks. in addition , it ensures that multiple jtag tap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50 % duty cycle. when necessary, tck can be stopped at 0 or 1 for extended periods of time. while tc k is stopped at 0 or 1, the state of the tap controller does not change and data in the jtag instruction and data registers is not lost. by default, the internal pull-up resistor on th e tck pin is enabled after reset. this assures that no clocking occurs if the pin is not driv en from an external source. the internal pull-up and pull-down resistors can be turned off to save internal power as long as the tck pin is constantly being driven by an external source. 10.5.3 test mode select (tms) the tms pin selects the next state of the jt ag tap controller. tms is sampled on the rising edge of tck. depending on the curren t tap state and the sampled value of tms, the next state is entered. because the tms pin is sampled on the rising edge of tck, the ieee standard 1149.1 expect s the value on tms to change on the falling edge of tck. holding tms high for five consecutive tck cycl es drives the tap controller state machine to the test-logic-reset state. when the tap controller enters the test-logic-reset state, the jtag instruction register (ir) resets to the default instruction, idcode. therefore, this sequence can be used as a reset me chanism, similar to asserting trst. by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms; otherwise jtag communication could be lost an path. 10.5.4 test data input (tdi) the tdi pin provides a stream of serial info rmation to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current tap state and the current instruction, presents this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck, the i eee standard 1149.1 expects the value on tdi to change on t he falling edge of tck. by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi; otherwise jtag communication could be lost
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 79 of 125 nxp semiconductors clrc663 contactless reader ic 10.5.5 test data output (tdo) the tdo pin provides an output stream of seri al information from the ir chain or the dr chains. the value of tdo depends on the curr ent tap state, the current instruction, and the data in the chain being accessed. in order to save power when the jtag port is not being used, the tdo pin is placed in an inacti ve drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1149.1 ex pects the value on tdo to change on the falling edge of tck. by default, the internal pull-up resistor on th e tdo pin is enabled after reset. this assures that the pin remains at a constant logic leve l when the jtag port is not being used. the internal pull-up and pull-down resistors can be turned off to save internal power if a high-z output value is acceptable during certain tap controller states 10.5.6 instruction register the instruction register handles the worki ng mode of the boundary scan cell. basically there are three modes. by pass, sample/preload and extest. according to the standard also the definition of further commands are allowed. the clrc663 boundary scan interface has clamp and highz as additional instructions. 10.5.7 data register according to the ieee1149.1 standard there ar e two types of data register defined: bypass, boundary scan the bypass register enable the possibility to by pass a devise when part of the scan path. the boundary scan register is the chain of th e boundary cells. the size of this register can differ per device, in the clrc663 it has the size of 8 bits. 10.5.8 boundary scan cell the boundary scan cell opens th e possibility to control a hard ware pin independent of its normal usecase. basically the cell can only do one of the following: control, output and input. 10.5.9 boundary scan path this chapter shows the boundary scan path of the clrc663. fig 23. boundary scan cell path structure 001aam306 ta p logic logic ta p ic1 ic2 tck tms tck tms tdo tdo boundary scan cell tdi tdi
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 80 of 125 nxp semiconductors clrc663 contactless reader ic refer to the clrc663 bsdl file. 10.5.10 boundary scan description language (bsdl) all of the boundary scan devices have a unique boundary structure where it is necessary to know this for working with the device . important parts of this language are: ? available test bus signal ? compliance pins ? command register ? data register ? boundary scan structure (number and types of the cells, their function and the connection to the pins.) the clrc663 is using the cell bc_8 for the io-lines. the i 2 c pin is using a bc_4 cell. for all pad enable lines the cell bc5 is used. the manufacturer's iden tification is 02bh. ? attribute idcode_register of clrc663: entity is "0001" and -- version table 219. boundary scan path of the clrc663 number cell port function 23 bc_1 - control 22 bc_8 clkout bidir 21 bc_1 - control 20 bc_8 scl2 bidir 19 bc_1 control 18 bc_8 sda2 bidir 17 bc_1 control 16 bc_8 ifsel0 bidir 15 bc_1 control 14 bc_8 ifsel1 bidir 13 bc_1 control 12 bc_8 if0 bidir 11 bc_1 - control 10 bc_8 if1 bidir 9 bc_1 - control 8bc_8if2bidir 7 bc_1 if2 output2 6bc_4if3bidir 5 bc_1 - control 4 bc_8 irq bidir 3 bc_1 - control 2 bc_8 sigin bidir 1 bc_1 - control 0 bc_8 sigout bidir
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 81 of 125 nxp semiconductors clrc663 contactless reader ic ? "0011110010000010b" and -- part number (3c82h) ? "00000010101b" and -- manufacturer (02bh) ? "1b"; -- mandatory ? instruction_capture = 1001b the user code data is coded as followed: ? product id (2 bytes) ? feature lock ? version these four bytes are stored as th e first four bytes in the eeprom. 10.5.11 non ieee1149.1 commands 10.5.11.1 interface on/off with this command the host/sam interface can be deactivated and the read and write command of the boundary scan interface is activated. (data = 1). with update-dr the value is taken over. 10.5.11.2 register access read at capture-dr the actual address is read and stored in the dr. shifting the dr is shifting in a new address. with update-dr this address is taken over into the actual address. 10.5.11.3 register access writer with this command the host/sam interface can be deactivated and the read and write command of the boundary scan interface is activated. (data = 1). with update-dr the value is taken over.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 82 of 125 nxp semiconductors clrc663 contactless reader ic 11. analog interface and contactless uart 11.1 general the integrated contactless uart supports the external host online with framing and error checking of the protocol requirements up to 848 kbit/s. an external circuit can be connected to the communication interface pins gpio0/sigin and sigout to modulate and demodulate the data. the contactless uart handles the protocol requirements for the communication schemes in co-operation with the host. the protocol handling itself generates bit- and byte-oriented framing and handles error detection like pa rity and crc according to the different contactless communication schemes. remark: the size and the tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance. 11.2 tx transmitter the signal delivered on pin tx1 and pin tx2 is the 13.56 mhz carrier modulated by an envelope signal for energy and data transmission. it can be used to drive an antenna directly, using a few passive componen ts for matching and filtering, see section 23 ? application information ? . the signal on tx1 and tx2 can be configured by the register drvmode , see section 9.9.1 ? txmode_reg ? . the modulation index can be set by the txamp_reg. following figure shows the general relations during modulation note: when changing the continuous wave, the residual carrier also changes, while the modulation index remains the same. fig 24. general dependences of modulation 001aan355 time influenced by set_clk_mode envelope tx ask100 1: defined by set_cw_amplitude. 2: defined by set_residual_carrier. tx ask10 (1) (2)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 83 of 125 nxp semiconductors clrc663 contactless reader ic the registers section 9.9 and section 9.11 control the data rate, the framing during transmission and the setting of the antenna driver to support the requirements at the different specified modes and transfer speeds. the following abbreviations are used: ? rf: 13.56 mhz clock derived from 27.12 mhz quartz divided by 2 ? rf_n: inverted 13.56 mhz clock ? rf_hs: rf high side push ? rf_hs_n: rf high side push negative ? rf_ls: rf low side pull ? rf_ls_n: rf low side pull negative ? z: high impedance to adjust the modulation index follo wing parameter has to be considered: table 220: settings for tx1/2 envelope set_clk_mode invtx1/2 tx1/2 remarks 1 x 0 rf rf clock depending on invtx 1 x 1 rf_n rf clock depending on invtx 0 0b000 x z high impedance 0 0b001 x 0 output pulled to 0 in any case 0 0b010 x 1 output pulled to 1 in any case 0 0b110 0 rf_hs open drain, only high side (push) mos supplied with clock, clock parity defined by invtx; low side mos is off 0 0b110 1 rf_hs_n open drain, only high side (push) mos supplied with clock, clock polarity defined by invtx; low side mos is off 0 0b101 0 rf_ls open drain, only low side (pull) mos supplied with clock, clock parity defined by invtx; high side mos is off 0 0b101 1 rf_ls_n open drain, only low side (pull) mos supplied with clock, clock parity defined by invtx; high side mos is off 0 0b111 0 rf push/pull operation, clock polarity defined by invtx; setting for 10 % modulation 0 0b111 1 rf_n push/pull operation, clock polarity defined by invtx; setting for 10 % modulation table 221. settings for set_residual_carri er and corresponding residual carrier set_residual_carrier residual carrier [%] modulation index [%] 0990.5 1981.0 2962.0 3943.1 4914.7 5895.8
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 84 of 125 nxp semiconductors clrc663 contactless reader ic note: when vdd(tvdd) < 5 v it is not recommended to use a residual carrier < 50 % 11.2.1 overshoot protection the clrc663 provides an overshoot protec tion to avoid overshoots during a pcd communication. therefore two timer overs hoot_t1 and overshoot_t2 can be used. during the timer overshoot_t1 runs an amp litude defined by set_cw_amplitude bits is provided to the output driver. followed by an amplitude denoted by set_residual_carrier bits with the duration of overshoot_t2. 6877.0 7867.5 8858.1 9848.7 10 83 9.3 11 82 9.9 12 81 10.5 13 80 11.1 14 79 11.7 15 78 12.4 16 77 13.0 17 76 13.6 18 75 14.3 19 74 14.9 20 72 16.3 21 70 17.6 22 68 19.0 23 65 21.2 24 60 25.0 25 55 29.0 26 50 33.3 27 45 37.9 28 40 42.9 29 35 48.1 30 30 53.8 31 25 60.0 table 221. settings for set_residual_carri er and corresponding residual carrier ?continued set_residual_carrier residual carrier [%] modulation index [%]
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 85 of 125 nxp semiconductors clrc663 contactless reader ic 11.3 receiver circuitry 11.3.1 general the clrc663 features a versatile quadrature rece iver architecture with fully differential signal input at rxp and rxn. it can be co nfigured to achieve optimum performance for reception of various 13.56 mhz based protocols. for all processing units various adjustments can be made to obtain optimum performance. fig 25. example 1: overshoot_t1 = 2d; overhoot_t2 = 5d. fig 26. example 2: overshoot_t1 = 0d; overhoot_t2 = 5d 001aan356 2.5000000 3.0333333 3.5666667 4.1000000 time ( s) : /tx2 : /tx1 7.0 5.0 (v) 3.0 1.0 ? 1.0 001aan357 0 ? 1.0 12345 time ( s) 1.0 3.0 : vt("/tx2") : vt("/tx1") 5.0 (v) 7.0
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 86 of 125 nxp semiconductors clrc663 contactless reader ic 11.3.2 block diagram figure 27 shows the block diagram of the receiver circuitry. the receiving process includes several steps. first the quadratu re demodulation of the carrier signal of 13.56 mhz is done. several tuning steps in this circuit are possible. the receiver can also be used as single ended solution. in this case only one side has to be assembled and the rcv_rx_single has to be set. in the single ended use case two receiver pins have to be connected. remark: when using the receiver single ended the reading distance will be influenced because of decreased sensitivity as well as the noise immunity. the quadrature-demodulator uses two different clocks, q-clock and i-clock, with a phase shift of 90 ? between them. both resulting baseband signals are amplified, filtered and forwarded to a correlation circuitry. 11.4 s3c interface / (gpio0)sigin-sigout two main blocks are implemented in the cl rc663. a digital circuitry, comprising state machines, coder and decoder logic and an analog circuitry with the modulator and antenna drivers, receiver and amplification ci rcuitry. for example, the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to the pins (gpio0)sigin and sigout. the most important use of this topology is the active fig 27. block diagram of receiver circuitry table 222. usage of single or differential receiver mode rcv_rx_single pins rx_p and rx_n fully differential 0 provide differential signal from differential antenna by separate rx-coupling branches quasi differential 1 connect rxp and rxn together and provide single ended signal from antenna by a single rx-coupling branch 001aan358 13.56 mhz i/o clock generation i-clks q-clks clk_27 mhz timing generation adc adc_data_ready clk_27 mhz mixer mix_out_i_p 2-stage bba mix_out_i_n out_i_p 6-bit 6.78ms data out_i_n rx_p rx_n rx_p rx_n mixer mix_out_q_p 2-stage bba mix_out_q_n out_q_p 6-bit 6.78ms data out_q_n rcv_gain<1:0> rcv_hpcf<1:0> fully/quasi-differential fully/quasi-differential rcv_gain<1:0> rcv_hpcf<1:0> rx_p rx_n
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 87 of 125 nxp semiconductors clrc663 contactless reader ic antenna concept where the digital and the anal og part are ideologically separated. this opens the possibility to connect e.g. an additional digital pa rt of another device with the one analog antenna front-end. the table 223 and table 224 shows the necessary register configuration for the use case active antenna concept. the interface between these two blocks can be configured in the way, that the interfacing signals may be routed to th e pins sigin and sigout (see figure 29 ? overview (gpio0)sigin/sigout signal routing ? ). the configuration is done by bits mfoutsel, txsel and uartsel of registers txselreg and rxselreg. this topology supports, that some parts of the analog part of the clrc663 may be connected to the digital part of another device. the switch mfoutsel in register txselreg can be used to measure mifare and iso/iec14443 related signals. this is especia lly important during the design in phase or for test purposes to check the transmitted and received data. however, the most important us e of mfin/mfout pins is the active antenna concept. an external active antenna circuit can be connec ted to the digital circuit of the clrc663. mfoutsel has to be configured in th at way that the signal of the internal miller coder is send to mfout pin ( mfoutsel = 4). uartsel has to be configured to receive manchester signal with sub-carrier from mfin pin ( uartsel = 1). it is possible, to connect a 'passive antenna' to pins tx1, tx2 and rx (via the appropriate filter and matching circuit) and at the same time an active antenna to the pins mfout and mfin. in this configuration, two rf-parts may be driven (one after another) by one host processor. fig 28. block diagram of the active antenna concept table 223. register configuration of clrc663 active antenna concept (digital) register value description sigout.sigoutsel 0100h txenvelope rcv.sigpro_in_sel 10 11 receive over sigin (iso/iec14443a) receive over sigin (generic code) drvcon.txsel 00 low (idle) table 224. register configuration of clrc663 active antenna concept (antenna) register value description sigout.sigoutsel 0110h 0111h generic code (manchester) manchester with subcarrier (iso/iec14443a) rcv.sigpro_in_sel 01 internal drvcon.txsel 10 external (sigin) rxctrl.rxmultiple 1 rxmultiple on 001aam307 sigin sigin sigout sigout clrc663 (digital) clrc663 (antenna)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 88 of 125 nxp semiconductors clrc663 contactless reader ic remark: the clrc663 has an extra supply pin (svdd and pvss as ground line) for the mfin and mfout pads. if mfin pin is not used it sh ould be connected to svdd or pvss. if svdd pin is not used it should be connected to dvdd or pvdd or any other voltage supply pin.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 89 of 125 nxp semiconductors clrc663 contactless reader ic fig 29. overview (gpio0)sigin/sigout signal routing 001aam001 coder sigoutsel[4:0] uart sel[1:0] sigout sigin tx bit stream digital module clrc663 analog module clrc663 rx bit stream 0, 1 2 3 4 5 6 7 9 3-state low high tx envelope tx active s3c signal rx envelope 8 rx active rx bit signal decoder subcarrier demodulator driver sel[1:0] 0 1 2 3 low tx envelope rfu sigin 0 1 2 3 3-state internal analog block sigin over envelope sigin over s3c modulator driver tx2 tx1 rxn rxp demodulator
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 90 of 125 nxp semiconductors clrc663 contactless reader ic 12. memory organization of the eeprom 12.1 overview the clrc663 has a memory of 8 kb and is or ganized in sections with pages of 64 bytes. the following figure show the structure of the eeprom 12.2 eeprom memory organization remark: the size of sections 3 and 4 can be configured. fig 30. sector arrangement of the eeprom 001aan359 production and config section 0: register reset section 1: free size mka size rsp section 2: mifare key area (mka) section 3: rsp-area for tx section 4_tx: rsp-area for rx section 4_rx: table 225. table of the eepr om memory organization section page byte addresses access rights memory content see also 0 0 00 to 63 r/w product information field (read only) and configuration (read and write) section 12.2.1 1 1 to 2 64 to 191 r/w register reset 2 3 to 95 192 to 6143 r/w free 3 96 to 111 6144 to 7167 w mifare key area (wo) section 12.2.3 4 112 to 128 7168 to 8191 r register set protocol (ro)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 91 of 125 nxp semiconductors clrc663 contactless reader ic 12.2.1 production area the first page includes production data as well as configuration information. the size of the mifare key area (mka), specifies the number of ee-pages for the mka. the size of the register set protocol (rsp) , specifies the number of ee-pages for the rsp area. the number of pages is equa lly divided for use between tx and rx. 12.2.2 configuration area the clrc663 eeprom has a page si ze of 64 byte and is r/w. the second page includes configuration data. only the interface by te as well as the i 2 c-address and i 2 csam-address are selectable. 12.2.2.1 interface this section describes the in terface byte configuration. table 226. production area page 0 1 2 3 4 5 6 7 0.0 product id feature lock version part id batch part id batch 0.1 part id batch wafer number x-pos. y-pos. date date trimm ee 1.0 trimm lfo - - - mka size rsp size - - 1.1 rfu rfu - - - - table 227. configuration area page 0 1 2 3 4 5 6 7 2.0 i2c-address interface i2csam-address defaul t prot rx default prot tx - tx crc present 2.1 rx - crc present - - - - - - 3.0 tx - sequence off-on 3.1 tx - sequence on-off table 228. interface byte bit 7 6 5 4 3 2 1 0 i2c hsp - - i2c-address boundary scan host access rights r/w rfu rfu r/w r/w r/w
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 92 of 125 nxp semiconductors clrc663 contactless reader ic 12.2.3 mifare key area this area is write only. the keys can be lo aded into the mifare crypto unit with the keyloadee command. the size of the mka can be configured between 0 and 24 (00h - 18h) using the size_mka byte in the ee sect ion 0 (production area + configuration area). 12.2.4 register set protocol area the size of this area can be configured between 1 and 31 (01h - 1fh) using the size_rsp byte in the ee section 0 (production area + configuration area). half of the rsp area contains settings for th e tx registers (16 bytes). the other half of the area contains the settings for the rx registers (8 bytes) e.g. size_rsp = 4 max. number of tx setti ngs = ((size_rsp / 2 pages) ? 64 byte / page) / 16 byte / tx_sets = 8 tx_settings max. number of rx settings = ((size_rsp / 2 pages) ? 64 byte / page) / 8 byte / rx_sets = 16 rx_settings table 229. description of txdatamodwidth bits bit symbol description 7 i2c hsp when set to 0, the high speed mode is used when set to 1, the high speed + mode is used (default) 6, 5 rfu - 4 i2c add when set to 0, the pins are used (default) when set to 1, the eeprom is used 3 boundary scan when set to 1, the boundary scan interface is on (default) when set to 2, the boundary scan is off 2 to 0 host 000b - rs232 001b - i2c 010b - spi 011b - i2cl 1xx b - pin selection table 230. tx and rx arrangements in the register set protocol area section section 4 tx tx0 tx1 tx2 tx3 section 4 tx tx4 tx5 tx6 tx7 section 4 rx rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 section 4 rx rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 93 of 125 nxp semiconductors clrc663 contactless reader ic 13. fifo buffer 13.1 overview an 512 ? 8-bit fifo buffer is implemented in the clrc663. it buffers t he input and output data stream between the host and the internal state machine of the clrc663. thus, it is possible to handle data streams with lengths of up to 512 bytes without taking timing constraints into account. the fifo can also be limited to a size of 255 byte 13.2 accessing the fifo buffer the fifo-buffer input and output data bus is connected to the register fifodata_reg. writing to this register stores one byte in the fifo-buffer and increments the internal fifo-buffer write-pointer. readin g from this register shows the fifo-buffer contents stored at the fifo-buffer read-pointer and decrements the fifo-buffer read-pointer. the distance between the write- and read-pointer can be obtained by reading the register fifolength_reg. if the fifo is used in 512 byte mode, also the higher bit of fifolength in the fifocontrol_reg register (bit 0 and bit 1) has to be taken into account. when the ? -controller starts a command, the clrc663 may, while the command is in progress, access the fifo-buffer accordin g to that command. physically only one fifo-buffer is implemented, which can be used in input and output direction. therefore the ? -controller has to take care, not to access the fifo buffer in an unintended way. 13.3 controlling the fifo buffer besides writing to and reading from the fifo buffer, the fifo-buffer pointers might be reset by setting the bit fifoflash in fifoco ntrol_reg to 1. consequently, the fifolevel bits are set to logic 0, the bit errirq in the register irq0_reg is cleared, the actually stored bytes are not accessible any more and the fifo buffer can be filled with another 512 bytes (or 255 bytes if the bit fifosize is set to 1) again. 13.4 status information about the fifo buffer the host may obtain the following data about the fifo-buffers status: ? number of bytes already stored in the fifo-buffer: fifolength in register fifolength_reg ? warning, that the fifo-b uffer is almost full: hialert in register fifocontrol_reg according to the value of the water level in register waterlevel_reg (register 0x02 bit [2], register 0x03 bit[7:0]) ? warning, that the fifo-buffer is almost empty: loalert in register fifocontrol_reg ? fifoovl bit indicates, that bytes were writte n to the fifo buffer although it was already full: errirq in register irq0_reg . errirq can be cleared only by setting bit fifoflash in the register fifocontrol_reg . the clrc663 can generate an interrupt signal if: ? loalertirqen in register i rq0en_reg is set to logic 1 it will activate pin irq when loalert in the register fifocontrol_reg changes to 1. ? hialertirqen in register irq0en_reg is set to logic 1 it will activate pin irq when hialert in the register fifocontrol_reg changes to 1.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 94 of 125 nxp semiconductors clrc663 contactless reader ic the bit hialert is set to logic 1 if maximum water level bytes (as set in register waterlevel_reg ) or less can be stored in the fifo-buffer. it is generated according to the following equation: (1) the bit loalert is set to logic 1 if water level bytes (as set in register waterlevel_reg ) or less are actually stored in the fifo-buffer. it is generated according to the following equation: (2) hialert fifosize fifolength ? ? ? waterlevel ? = loalert fifolength waterlevel ? =
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 95 of 125 nxp semiconductors clrc663 contactless reader ic 14. timer unit the external host may use this timer to mana ge timing relevant tasks. the timer unit may be used in one of the following configurations: ? time-out counter ? watch-dog counter ? stop watch ? programmable one-shot ? periodical trigger the timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. the timer can be triggered by events which will be explained in the following, but the timer itself does not influence any internal event (e.g. a time-out during data reception does not influence the reception process automatically). furthermore, several timer rela ted bits are set and these bits can be used to generate an interrupt. the clrc663 has 4 identical timers (timer 0 - timer 3). each timer has an input clock of 13.56 mhz (derived from the 27.12 mhz quartz) and has 16 bits. the reload value for the counter is defined in a range of 0d to 65535d in the register tnreload_reg. timer 4 also can be used as wake up timer. in this case the internal lpo (low power oscillator) can be used as input clock. the current value of the timer is indicated by the register tncounterval_reg . if the counter reaches 0 an inte rrupt will be generated automa tically by the next clock indicated by setting the timerirq bit in t he register commonirq_reg. if enabled, this event can be indicated on the irq line. the bit timerirq can be set and reset by the host controller. depending on the co nfiguration the timer will stop at 0h or restart with the value from register treload_reg. the status of the timer is indicated by bit tnrunning in register tcontrol_reg. the timer can be manually started by setting tnrunning and tnstartstopnow in register controlreg or manually stopped by setting tnstartstopnow and clearing tnrunning in register tncontrol_reg . furthermore the timer can be started automatically by setting the bit tnstart in the register tnmode_reg to fulfil dedicated protocol requirements automatically. 14.1 usage timer unit 14.1.1 time-out- and watch-dog-counter having started the timer by setting tnreloadvalue the timer unit decrements the tncountervalue register beginning with a certain start event. if a certain stop event occurs e.g. a bit is received from the card, the timer unit stops (no interrupt is generated). on the other hand, if no stop event occurs, e.g. the card does not answer in the expected time, the timer unit decrements down to zero and generates a timer interrupt request. this signals the ? -processor that the expected event has not occurred in the given time t timer .
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 96 of 125 nxp semiconductors clrc663 contactless reader ic 14.1.2 wake-up timer (timer4) the wake-up timer can activate the system afte r a given time. it can start a low power card detection. for the lpcd it is recommended to set t4autowakeup and t4autorestart , to start the timer and go to standby. the internal lpo is used as input clock for this timer. if a card is detected stop the timer and start the communication. if t4autowakeup is not set, the ic will not enter standby mode in case no card is detected. refer to section 16.3 14.1.3 stop watch the time t timer 2 between a certain start- and stop event may be measured by the ? -processor by means of t he clrc663 timer unit. setting treloadvalue the timer starts to decrement. if the defined stop event occurs the timers stops. the time between start and stop can be calculated by ? -processor (3) if the timer does not decrements down to zero. 14.1.4 programmable one-shot timer the ? -processor starts the timer unit and waits fo r the timer interrupt. after the specified time t timer the interrupt will occur. 14.1.5 periodical trigger if the ? -processor sets bit tautorestart , it will generate an interr upt request periodically after every t timer. 2. refer to section 27 ? abbreviations ? ?? timer value value t timer load t t * re '
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 97 of 125 nxp semiconductors clrc663 contactless reader ic 15. interrupt request system the clrc663 indicates certain events by setting bit irq in the register status1reg and additionally, if activated, by pin irq. the si gnal on pin irq may be used to in terrupt the host using its interrupt handlin g capabilities. this allows th e implementation of efficient host software. the following table shows the available interr upt bits, the corresponding source and the condition for its activation. the interrupt bit timernirq in register irq1_reg indicates an interrupt set by the timer unit. the setting is done when the timer decrements from 1 down to 0. the txirq bit in register irq0_reg indicates that the transmission is finished. if the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit sets the interr upt bit automatically. the bit rxirq in register irq0_reg indicates an interrupt when the end of the received data is detected. the bit idleirq in register irq0_reg is set if a command finishes and the content of the command register changes to idle. the bit hialertirq in register irq0_reg is set to logic 1 if the hialert bit is set to logic 1, that means the fifo buffer has reached the level indicated by the bit waterlevel . the bit loalertirq in register irq0_reg is set to logic 1 if the loalert bit is set to logic 1, that means the fifo buffer has reached the level indicated by the bit waterlevel . the bit errirq in register irq0_reg indicates an error detected by the contactless uart during sending or receiving. this is indicated by any bit set to logic 1 in register errorreg . the bit lpcdirq in register irq0_reg indicates a card detected. the bit rxsofirq in register irq0_reg indicates a detection of a sof or a subcarrier by the contactless uart during receiving. the bit globalirq in register irq1_reg indicates an interrupt occurring at any other interrupt source when enabled. table 231: interrupt sources interrupt bit interrupt source is set automatically, when timerirq timer unit the timer counts from 1 to 0 txirq transmitter a transmitted data stream ends rxirq receiver a received data stream ends idleirq command register a command execution finishes hialertirq fifo-buffer the fifo-buffer is getting full loalertirq fifo-buffer the fifo-buffer is getting empty errirq contactless uart an error is detected lpcdirq lpcd a card was detected when in low power card detection mode rxsofirq receiver detection of a sof or a subcarrier globalirq all interrupt sources will be set if an other irq source is set
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 98 of 125 nxp semiconductors clrc663 contactless reader ic 16. clock generation 16.1 crystal oscillator the clock applied to the clrc663 acts as time basis for generation of the carrier sent out at tx and for the quadrature mixer i and q cl ock generation as well as for the coder and decoder of the synchronous system. therefore stability of the clock frequency is an important factor for proper performance. to ob tain highest performance, clock jitter has to be as small as possible. this is best achiev ed by using the internal oscillator buffer with the recommended circuitry. 16.2 integern pll clock line the clrc663 is able to provide a clock with configurable frequency at clkout from 1 mhz to 24 mhz (pll_ctrl_reg and pll_di v_reg). there it can serve as a clock source to a microcontr oller which avoids the need of a second crystal oscillator in the reader system. clock source for the integern-pll is the 27.12 mhz crystal oscillator. inside the pll the input frequency is divided by 2: fin = 13.56 mhz. two dividers are determining the output frequency. first a feedback integer-n divider configures the vco frequency to be n ? fin/2 (control signal pll_ set_divfb). as supported feedback divider ratios are 23, 27 and 28 vco frequencies can be 23 ? fin / 2 (312 mhz), 27 ? fin / 2 (366 mhz) and 28 ? fin / 2 (380 mhz). 23 is the recommended value. fig 31. quartz connection table 232: crystal requirements recommendations symbol parameter conditions min typ max unit f xtal crystal frequency - 27.12 - mhz ? f xtal /f xtal relative crystal frequency variation ? 250 +250 ppm esr equivalent series resistance -50100 ? c l load capacitance - 10 - pf p xtal crystal power dissipation -50100 ? w 001aam308 27.12 mhz xtal1 xtal2 clrc663
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 99 of 125 nxp semiconductors clrc663 contactless reader ic the vco frequency is divided by a factor which is defined by the output divider (pll_set_divout). of course only a limited accuracy of the output frequencies can be achieved by this approach. table 233 and table 234 : shows the accuracy achieved for various frequencies (integer multiples of 1 mhz and some typical rs232 frequencies) and the divider ratios to be used. the register bit clkouten enables the clock at clkout pin. the following formula can be used to calculate the output frequency: f out = 13.56 mhz ? pll_set_divb /pll_set_divout remark: at the value 0 to 7 have special division values. the following ta b l e 2 3 5 shows the recommended divider values for typical clock frequencies. remark: the recommended value for pll_set_divb = 00 h (divider value = 23 ). in this case the internal current consumption of the integern pll is a minimum. table 233: setting of feedback divider pll_set_divb [1:0] bit 1 bit 0 division 00 23 01 27 10 28 11 23 table 234: setting for the output divider ration pll_set_divout [7:0] value division 08 19 210 311 412 513 614 715 88 99 10 10 ... ... 253 253 254 254 table 235. divider values for selected frequencies using the integern pll frequency [mhz] 4 6 8 10 12 13 19 20 24 1.8432 3.6864 pll_set_divb 23 27 23 28 23 23 28 28 23 28 28 pll_set_divout 78 61 39 38 26 24 20 19 16 206 103 accuracy [%] 0.04 0.03 0.04 0.08 0.04 0.03 0.08 0.08 0.04 0.01 0.01
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 100 of 125 nxp semiconductors clrc663 contactless reader ic 16.3 low power oscillator (lpo) the lpo is implemented as a ring oscillator struct ure. frequency can be controlled/trimmed by adapting the cco bias cu rrent with lpo_trimm. target is to achieve a trimming accuracy of 2.5 % with a maximum of 8 trimm-bits for all pvt conditions taking into account also the reference current variations. with linear trimming behavior following re lation is valid for the output frequency: f_lpo f ipo = f center + delta_f ? (80h ? lpo_trimm); with f center being the frequency for lpo_trimm in the middle of the range (lpo_t rimm = 80h) and delta_f being the trimming step size which must be < 0.05 ? f_target (for 2.5 % accuracy). trimming will be done by a digital state ma chine which compares lpo-clock to a reference clock. as reference the 13.56 mhz crystal clock is available. the lpo frequency must be chosen such that a period of 1 ms (=1/1 khz) can easily be generated with a 2n-counter. for trimming m periods of the reference clock need to be counted with m = round(13.56 m/f_lpo). a small systemat ic error due to rounding of m to an integer value is introduced. this error is with 0.06 % much smaller than the targeted trimming accuracy of 2.5 %. the lpo can be set to power do wn with input pin pdown/reset. table 236: setting of lpo_trimm [7:0] value lpo frequency no. of reference clocks 416 848 532 424 664 212 7128 106
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 101 of 125 nxp semiconductors clrc663 contactless reader ic 17. power management 17.1 supply concept the clrc663 is supplies of v dd ? supply voltage, pvdd ? pad supply and tvdd ? tx power supply. these three voltages are independent and can have different as well as same supply voltage values. e.g. to operat e with a 3.3 v supplied microcontroller, pvdd and v dd shall be 3.3 v, to guarantee maximum field strength tvdd shall be 5 v. note: none of this three volt ages is allowed to be zero. independent of the voltage it is recommended to buffer these supplies with blocking capacitances. v dd and pvdd min 100 nf; tvdd min 100 nf parallel to 1 ? f note: avdd and dvdd are no voltage inputs! buffer them with blocking capacitances of 470 nf each. 17.2 power reduction mode 17.2.1 power-down a hard power-down is enabled with high level on pin pdown. this turns off the internal 1.8 v voltage regulators for the analog and digital core supply as well as the oscillator. all digital input buffers are separated from the input pads and clamped internally (except pin pdown itself). the output pins are switched to high impedance. to leave the power-down mode the level at the pin pdown as to be set to low. this will start the internal start up sequence. the reader ic is in full mode again when the internal reset sequence is finished, the crystal reaches the point in the oscillation cycle where the oscillation gets stable and th e booting sequence is finished. 17.2.2 standby mode the standby mode is entered immediately after setting the bit powerdown in the register command_reg to 1. all internal current sinks are switched off (including the oscillator buffer). in opposition to the power-down mode, the digital input buffers are not separated by the input pads and keep their functionality. the digital output pins do not change their state. during standby mode, all registers values, the fifo?s content and the configuration itself will keep its current content. to leave the standby mode the bit powerdown in the register command_reg is set to 0. this will start the internal start up sequence. the reader ic is in full mode again when the internal start up sequence is fi nished, the crystal reaches the point in the oscillation cycle where the oscillation gets stable and the booting sequence is finished. 17.2.3 modem off mode when the modemoff bit in the register control_reg is set to 1 the antenna transmitter and the receiver are switched off. to leave the modem off mode set the modemoff bit in the register control_reg to 0.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 102 of 125 nxp semiconductors clrc663 contactless reader ic 17.3 low power card detection (lpcd) the low power card detection is a energy sa ving modus when the clrc663 is not used permanently. the lpcd works in two phases. the standby ph ase, controlled with the wake up timer 4, which defines the duration of the sta ndby of the clrc663. second phase is the detection-phase. there the values of the i and q channel are detected and stored in the register map. (lpcd_i_result_reg, lpcd _q_result_reg).this time period can be handled with timer3. the value is compared with the min/max values in the registers (lpcd_imin_reg, lpcd_imax_reg; lpcd _qmin_reg, lpcd_qmax_reg). if it exceeds the limits, a lpcdirq will be raised. after the command lpcd the standby of the clrc663 is activated, if selected. the wake-up timer 4 can activate the system after a given time. for the lpcd it is recommended to set t4autowakeup and t4autorestart , to start the timer and then go to standby. if a card is detected the timer st ops and the communication can be started. if t4autowakeup is not set, the ic will not enter standby mode in ca se no card is detected. 17.4 reset and startup time a 10 ? s constant high level at the reset pin starts the internal reset procedure. the following figure shows the internal voltage regulator: this internal procedure consists of two phases: ? power on reset ? startup time when the clrc663 has finished this two phases the reader ic is in full mode an is ready to be used. refer to section 22.1 ? timing characteristics ? fig 32. internal pdown to voltage regulator logic 001aan360 pvdd pdown v ss peak filter internal voltage regulator v dd v ss 1.8 v 1.8 v avdd dvdd
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 103 of 125 nxp semiconductors clrc663 contactless reader ic 18. clrc663 command set 18.1 general description the behavior is determined by a state machine capable to perform a certain set of commands. by writing the according command-code to register command_reg the command is executed. arguments and/or data necessary to process a command, are exchanged via the fifo buffer. 18.2 general behavior ? a data transmission of the txencoder can be started by a command. when started, the communication is executed as defined in the txframecon register. therefore a communication frame can consist of a star t-symbol, a data-stream, and followed by an end-symbol. ? each command that needs a certain number of arguments will start processing only when it has received the correct number of arguments via the fifo buffer. ? the fifo buffer is not cleared automatically at command start. therefore, it is also possible to write the command arguments and/or the data bytes into the fifo buffer and start the command afterwards. ? each command may be interrupted by the host by writing a new command code into register command_reg e.g.: the idle-command. 18.3 clrc663 commands overview table 237. command overview command no. no. parameter short description idle 0.0000 00h no no action, cancels current command execution lpcd 0.0001 01h no low power card detection loadkey 0.0010 02h mifare key (6 bytes) reads a key from fifo buffer ant puts it into key buffer mfauthent 0.0011 03h authentication command code (60h, 61h), block address performs the mifare stand ard authentication in mifare read/write mode only ackreq 0.0100 04h no performs a query, an ack and a req-rn for iso/iec18000-3 mode 3 receive 0.0101 05h no activates the receive circuit transmit 0.0110 06h no transmits data from the fifo buffer transceive 0.0111 07h no transmits data from the fifo buffer and automatically activates the receiver after transmission finished writee2 0.1000 08h address (2 bytes, 0000h - 1fffh), data (1 byte) gets one byte from fifo buffer and writes it to the internal e2prom writee2pages 0.1001 09h page address (1 byte, 00h - 7fh), data (up to 64 bytes) gets up to 64 bytes from fifo buffer and writes it to the internal e2prom reade2 0.1010 0ah address (2 bytes, 0000h - 1fffh), length [1 byte, 01h (= 1 byte) - 00h (= 256 byte)] reads data from the e2prom and puts it into the fifo buffer
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 104 of 125 nxp semiconductors clrc663 contactless reader ic 18.3.1 clrc663 command description 18.3.1.1 idle command this command indicates that the rc663 is in idle mode. this command is also used to terminate the actual command. 18.3.1.2 lpcd command this command performs a low power card detection and or an automatic trimming of the lpo. the values of the sampled i and q channel are stored in the register map. the value is compared with the min/max values in the register. if it exceeds the limits, an lpcd_irq will be raised. after the command the st andby is activated if selected. 18.3.1.3 load key command parameter: mifare key (6 bytes). loads a mifare key (6 bytes) for authenticat ion from the fifo in to the crypto1 unit. unused bytes rema in in the fifo. abort condition: less than 6 bytes in fifo. 18.3.1.4 mfauthent command this command handles the mifa re authentication to enable a secure communication to any mifare classic card. the following data shall be written to the fifo before the command can be activated: ? loadkeye2 ? authentication command code (60h, 61h) ? block address ? card serial number byte 0 ? card serial number byte 1 ? card serial number byte 2 ? card serial number byte 3 in total, 12 bytes are written to the fifo. remark: when the mfauthent command is active, any fifo access is blocked. if there is an access to the fifo, the bit wrer r in the errorreg register is set. loadreg 0.1100 0bh eeaddress (2 bytes, within sector2), regadr (1 byte, 0x00 - 0xff), number of register to be copied (1 byte, 0x01 - 0xff). reads data from the internal e2prom and initializes the clrc663 registers loadprotocol 0.1101 0ch protocol number rx (1 byte, 0x00 - 0xff), protocol number tx (1 byte, 0x00 - 0xff) reads data from the internal e2prom and initializes the clrc663 registers needed for a protocol change loadkeye2 0.1110 0eh keynr (1 byte, 0x00 - 0xff) copies a key of the e2oprom into the key buffer storekeye2 0.1111 0fh keynr (1 byte, 0x00 - 0xff), one or more mifare keys ( 6 byte) stores a mifare key into the eeprom soft reset 1.1111 1fh no resets the clrc663 table 237. command overview ?continued command no. no. parameter short description
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 105 of 125 nxp semiconductors clrc663 contactless reader ic this command terminates automatically when the mifare card is authenticated and the bit mfcrypto1on in the status_reg register is set to logic 1. this command does not terminate automatically when the card does not answer, therefore the timer should be initialized to aut omatic mode. in this case, beside the bit idleirq, the bit timerirq can be used as termination criteria. during authentication processing the bit rxirq and bit txirq are bloc ked. the crypto1on bit is only valid after termination of the authentication command (eit her after processing the protocol or after writing idle to the command register). in case there is an error during authentication, the bit protocolerr in the errorreg register is set to logic 1 and the bit crypto1on in register status2reg is set to logic 0. 18.3.1.5 ack reqcommand performs a query (full command must be wr itten into the fifo); a ack and a reqrn command. all answer of the comma nd will be written into the fi fo. the error flag is copied after the answer into the fifo. this command terminates automatically when finished and the active command is idle. 18.3.1.6 receive command the clrc663 activates the receiver path and waits for any data stream to be received. the correct settings have to be chosen before starting this command. this command terminates automatically when the received data stream ends. this is indicated either by the end of frame patter n or by the length byte depending on the selected framing and speed. remark: if the bit rxmultiple in the rxmodereg register is set to logic 1, the receive command does not terminate automatically. it has to be terminated by activating any other command in the commandreg register. 18.3.1.7 transceive command this command transmits data from the fifo and receives data from the rf field conce. the first action is transmitting and afte r a transmission the command is changed to receive a data stream. each transmission process starts by writing the command into register commandreg e.g. the command idle. remark: if the bit rxmultiple in register rx modereg is set to logic 1, this command will never leave the receiving stat e, because the receiving will not be cancelled automatically. 18.3.1.8 transmit command the content of the fifo is transmitted imme diately after starting the command. before transmitting the fifo content all relevant register have to be set to transmit data. this command terminates automatically when the fifo gets empty. it can be terminated by any other command written to the command register. 18.3.1.9 writee2 command parameter: address (2 byte), data (1 byte)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 106 of 125 nxp semiconductors clrc663 contactless reader ic this command writes one byte into the eeprom. if th e fifo contains no data, the command will wait until the data is available abort condition: insufficient parameter in fifo; address-parameter outside of range 18.3.1.10 writee2page command parameter: page address (1 by te), data (up to 64 byte) this command writes up to 64 bytes into the eeprom. the addresses are not allowed to wrap over a page border. if this is the case, this additional data be ignored and stays in the fifo. the programming starts after 64 bytes are read from the fifo or the fifo is empty. abort condition: insufficient parameters in fifo; page address parameter outside of range 18.3.1.11 reade2 command parameter: address (2 by te); length (1 byte). reads up to 256 bytes from the eeprom to the fifo. if a read operation exceeds the address 0x1fff, the read operation continues from address 0x0000. abort condition: insufficient parameter in fifo; address parameter outside of range. 18.3.1.12 loadreg command parameter: address (2 byte, within the free sect ors); register address (1 byte), number of register to be copied (1 byte) read a defined number of bytes from the eeprom and copies the valu e into the register set, beginning at the given regadr. abort condition: insufficient parameter in fifo; address parameter outside of range. 18.3.1.13 loadp rotocol command parameter: protocol number rx (1 byte), protocol number tx (1 byte). read out the eeprom and copies the value to the rx-protected ar ea and to the tx protected area. these are all important registers to a protocol selection. abort condition: insuffic ient parameter in fifo 18.3.1.14 loadkeye2 command parameter: key number (1 byte) load a mifare key for authentication fr om the eeprom into the crypto1 unit. abort condition: insufficient paramete r in fifo; keynr is outside the mka. 18.3.1.15 storekeye2 command parameter: key number (1 byte), one or more mifare keys (a 6 bytes). stores mifare keys into the eeprom. if an incomplete key (less than 6 bytes) is written into the fifo, this key will be i gnored and will rema in in the fifo. abort condition: insufficient paramete r in fifo; keynr is outside the mka;
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 107 of 125 nxp semiconductors clrc663 contactless reader ic 18.3.1.16 soft reset command parameter: no, this command is performing a soft rest. during this command the default values for the register set will be read from the eeprom and stored in the register set.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 108 of 125 nxp semiconductors clrc663 contactless reader ic 19. limiting values 20. recommended operating conditions [1] v dd(pvdd) must always be the same or lower voltage than v dd . 21. thermal characteristics 22. characteristics table 238. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage 3 5.5 v v dd(pvdd) pvdd supply voltage ? 0.5 +5.5 v v dd(tvdd) tvdd supply voltage ? 0.5 +5.5 v p tot total power dissipation per package; umax * imax - 1125 mw v esd electrostatic discharge voltage human body model (hbm); 1500 ? , 100 pf; jesd22-a114-b - 2000 v table 239. operating conditions symbol parameter conditions min typ max unit v dd supply voltage 3 5 5.5 v v dd(tvdd) tvdd supply voltage [1] 355.5v v dd(pvdd) pvdd supply voltage 3 5 5.5 v t amb ambient temperature ? 25 +85 ? c table 240. thermal characteristics symbol parameter conditions package typ unit r th(j-a) thermal resistance from junction to ambient in still air with exposed pin soldered on a 4 layer jedec pcb hvqfn32 40 k/w table 241. characteristics symbol parameter conditions min typ max unit input characteristics i/o pin characteristics if3-sda in i 2 c configuration i li input leakage current output disabled - 2 100 na v il low-level input voltage ? 0.5 - 0.3xv dd(pvdd) v v ih high-level input voltage 0.7xv dd(pvdd) -v dd(pvdd) + 0.5 v v ol low-level output voltage i ol = 3 ma - - 0.3 v i ol low-level output current v ol = 0.4 v; standard mode, fast mode 4-- ma v ol = 0.6 v; standard mode, fast mode 6-- ma
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 109 of 125 nxp semiconductors clrc663 contactless reader ic t f(o) output fall time standard mode, fast mode, c l < 400 pf --250ns fast mode +; c l < 550 pf - - 120 ns t sp pulse width of spikes that must be suppressed by the input filter 0-50ns c i input capacitance - 3.5 5 pf c l load capacitance standard mode - - 400 pf fast mode - - 550 pf core supply pin avdd/dvdd v dda analog supply voltage - 1.8 - v v ddd digital supply voltage - 1.8 - v c load load capacitance avdd 220 470 - nf c load load capacitance dvdd 220 470 - nf current consumption i pd power-down current pdown pin pulled high [1] -840na i stb standby current standby bit = 1 - 3 6 ? a i dd supply current - 17 20 ma modem off - 0.45 0.5 ma i dd(tvdd) tvdd supply current - 100 200 ma i/o pin characteristics sigin, sigout, clkout, ifsel0, ifsel1, tck, tms, tdi, tdo, irq, if0, if1, if2, scl2, sda2 i li input leakage current output disabled - 50 500 na v il low-level input voltage ? 0.5 - 0.3xv dd(pvdd) v v ih high-level input voltage 0.7xv dd(pvdd) -v dd(pvdd) + 0.5 v v ol low-level output voltage i ol = ma, v dd(pvdd) =5.0v --0.4v i ol = ma, v dd(pvdd) =3.3v --0.4v v oh high-level output voltage i ol = ma, v dd(pvdd) =5.0v 4.6 - - v i ol = ma, v dd(pvdd) =3.3v 2.9 - - v c i input capacitance - 2.5 4.5 pf pull-up resistance for tck, tms, tdi, if2 r pu pull-up resistance 50 72 120 k ? pin characteristics aux 1, aux 2 v o output voltage rage 0 - 1.8 v c l load capacitance - - 400 pf pin characteristics rxp, rxn v i input voltage 0 - 1.8 v c i input capacitance 2 3.5 5 pf v mod modulation voltage - 2.5 - v table 241. characteristics ?continued symbol parameter conditions min typ max unit
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 110 of 125 nxp semiconductors clrc663 contactless reader ic [1] i pd is the total current for all supplies. [2] i dd(pvdd) depends on the overall load at the digital pins. [3] i dd(tvdd) depends on v dd(tvdd) and the external circuit c onnected to pins tx1 and tx2. [4] during typical circuit operation, the overall current is below 100 ma. [5] typical value using a complementary driv er configuration and an antenna matched to 40 ? between pins tx1 and tx2 at 13.56 mhz. vpp max range of signal on rxp, rxn - - 1.65 v pins tx1 and tx2 v o output voltage v ss(tvss) -v dd(tvdd) v r o output resistance - 1.5 - ? current consumption i pd power-down current - 8 200 na standby current [1] -36 ? a i lpcd lpcd sleep current [1] -36 ? a i vdd supply current - 17 20 ma i vdd modem off supply current, transceiver off - 0.45 0.5 ma i dd(pvdd) pvdd supply current [2] ma i dd(tvdd) tvdd supply current [3] [4 ] [5] -100200ma clock frequency pin clkout f clk clock frequency - 27.12 - mhz ? clk clock duty cycle - 50 - % crystal oscillator v o(p-p) peak-to-peak output voltage pin xtal1 - 1 - v v i input voltage pin xtal1 0 - 1.8 v c i input capacitance pin xtal1 - 3 - pf pin xtal2 - 3 - pf typical input requirements f xtal crystal frequency - 27.12 - mhz esr equivalent series resistance - 50 100 ? c l load capacitance - 10 - pf p xtal crystal power dissipation - 50 100 ? w table 241. characteristics ?continued symbol parameter conditions min typ max unit
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 111 of 125 nxp semiconductors clrc663 contactless reader ic 22.1 timing characteristics fig 33. pin rx input voltage range 001aak012 vmid 0 v ? 1 v v dda + 1 v v mod v i(p-p)(max) v i(p-p)(min) 13.56 mhz carrier table 242. spi timing characteristics symbol parameter conditions min typ max unit t sckl sck low time 50 - - ns t sckh sck high time 50 - - ns t h(sckh-d) sck high to data input hold time sck to changing mosi 25 - - ns t su(d-sckh) data input to sck high set-up time changing mosi to sck 25 - - ns t h(sckl-q) sck low to data output hold time sck to changing miso - - 25 ns t (sckl-nssh) sck low to nss high time 0--ns t nssh nss high time before communication 50 - - ns table 243. i 2 c-bus timing in fast mode and fast mode plus symbol parameter conditions fast mode fast mode plus unit min max min max f scl scl clock frequency 0 400 0 1000 khz t hd;sta hold time (repeated) start condition after this period, the first clock pulse is generated 600 - 260 ns t su;sta set-up time for a repeated start condition 600 - 260 ns t su;sto set-up time for stop condition 600 - 260 ns t low low period of the scl clock 1300 - 500 ns t high high period of the scl clock 600 - 260 ns
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 112 of 125 nxp semiconductors clrc663 contactless reader ic remark: to send more bytes in one data stream the nss signal must be low during the send process. to send more than one data stream the nss signal must be high between each data stream. t hd;dat data hold time 0 900 450 ns t su;dat data set-up time 100 - ns t r rise time scl signal 20 300 120 ns t f fall time scl signal 20 300 120 ns t r rise time sda and scl signals 20 300 120 ns t f fall time sda and scl signals 20 300 120 ns t buf bus free time between a stop and start condition 1.3 - 0.5 ? s fig 34. timing diagram for spi fig 35. timing for fast and standard mode devices on the i 2 c-bus table 243. i 2 c-bus timing in fast mode and fast mode plus ?continued symbol parameter conditions fast mode fast mode plus unit min max min max 001aaj641 t sckl t sckh t sckl t dqxch t dshqx t dqxch t h(sckl-q) t clsh sck mosi miso msb msb lsb lsb nss 001aaj635 sda t f scl t low t f t sp t r t hd;sta t hd;dat t hd;sta t r t high t su;dat ssrps t su;sta t su;sto t buf
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 113 of 125 nxp semiconductors clrc663 contactless reader ic 23. application information a typical application diagram using a complementary antenna connection to the clrc663 is shown in figure 36 . the antenna tuning and rf part matching is described in the application note ref. 1 and ref. 2 . 23.1 circuit description the matching circuit consists of an emc low pass filter (l0 and c0), a matching circuitry (c1 and c2), and a receiving circuits (r1 = r3, r2 = r4, c3 = c5 and c4 = c6;), and the antenna itself. for more detailed information about designing and tuning an antenna please refer to the application notes ? micore reader ic family; directly matched antenna design, ref. 1 and ? mifare (14443a) 13.56 mhz rfid proximity antennas, ref. 2 . 23.1.1 emc low pass filter the mifare system operates at a frequency of 13.56 mhz. this frequency is generated by a quartz oscillator to clock the clrc663 an d is also the basis fo r driving the antenna with the 13.56 mhz energy carrier. this will not only cause emitted power at 13.56 mhz but will also emit power at higher harmonics. the international emc regulations define the amplitude of the emitted power in a broad fre quency range. thus, an appropriate filtering of the output signal is necessa ry to fulfil these regulations. fig 36. typical applicatio n antenna circuit diagram 001aam269 vdd pvdd micro- processor host interface tvdd xtal1 xtal2 rxn vmid tx1 tvss tx2 9 82518 19 vss 33 20 13 14 17 16 15 14 21 28-31 32 pdown irq 7 dvdd avdd 12 rxp clrc663 r1 l0 c1 ra ra c1 l0 r2 r4 c0 c0 c2 c2 c rxn c rxp c vmid r3 27.12 mhz antenna lant
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 114 of 125 nxp semiconductors clrc663 contactless reader ic a multi-layer board is recommended to implemen t a low pass filter as shown in the circuit above. the low pass filter consists of the components l0 and c0. the recommended values are given in the above mentioned application notes. remark: to achieve best performance all compone nts shall have at least the quality of the recommended ones. remark: the layout has a major influence on the overall performance of the filter. 23.1.2 antenna matching due to the impedance transformation of the given low pass filter, the antenna coil has to be matched to a certain impedance. the matching elements c1 and c2 can be estimated and have to be fine tuned dependi ng on the design of the antenna coil. the correct impedance matching is important to provide the optimum performance. the overall quality factor has to be considered to guarantee a proper iso/iec 14443 communication scheme. environmental influences have to considered as well as common emc design rules. for details refer to the above mentioned application notes. remark: do not exceed the current limits i tvdd , otherwise the chip might be destroyed. remark: the overall 13.56 mhz rfid proximity an tenna design with the clrc663 chip is straight forward and doesn?t require a special rf-know how. however, all relevant parameters have to be considered to guarante e an overall optimum performance together with international emc compliance. 23.1.3 receiving circuit the internal receiving concept of the clrc663 makes use both side-bands of the sub-carrier load modulation of the card response via a differential receiving concept (rxp,rxn). no external filtering is required. it is recommended to use the internally generated vmid potential as the input potential of pin rx. this dc voltage level of vmid has to be coupled to the rx-pins via r2 and r4. to provide a stable dc reference voltage capacitances c4, c6 has to be connected between vmid and ground. refer to figure 36 considering the (ac) voltage limits at the rx-pins the ac voltage divider of r1 + c3 and r2 as well as r3 + c5 and r4 has to be designed. depending on the antenna coil design and the impedance matching the voltage at the antenna coil varies from antenna design to antenna design. therefore the recommended way to design the receiving circuit is to use the given values for r1(= r3), r2 (= r4), and c3 (= c5) from the above mentioned application note, and adjust the voltage at the rx-pins by varying r1(= r3) within the given limits. remark: r2 and r4 are ac-wise connected to ground (via c4 and c6).
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 115 of 125 nxp semiconductors clrc663 contactless reader ic 23.1.4 antenna coil the precise calculation of the antenna coils ? inductance is not practicable but the inductance can be estimated using the following formula. we recommend designing an antenna either with a circular or rectangular shape. (4) ? i 1 - length in cm of one turn of the conductor loop ? d 1 - diameter of the wire or width of the pcb conductor respectively ? k - antenna shape factor (k = 1,07 for circular antennas and k = 1,47 for square antennas) ? l 1 - inductance in nh ? n 1 - number of turns ? ln: natural logarithm function the actual values of the antenna inductan ce, resistance, and capacitance at 13.56 mhz depend on various parameters such as: ? antenna construction (type of pcb) ? thickness of conductor ? distance between the windings ? shielding layer ? metal or ferrite in the near environment therefore a measurement of those parameters under real life conditions, or at least a rough measurement and a tuning procedure is highly recommended to guarantee a reasonable performance. for details refer to the above mentioned application notes. l 1 2 = i 1 i 1 d 1 ------ ?? ln k ? ?? ?? n 1 18 ? ??
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 116 of 125 nxp semiconductors clrc663 contactless reader ic 24. package outline fig 37. package outline sot617-1 (hvqfn32) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 5.1 4.9 d h 3.25 2.95 y 1 5.1 4.9 3.25 2.95 e 1 3.5 e 2 3.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot617-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot617-1 hvqfn32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 916 32 25 24 17 8 1 x d e c b a e 2 terminal 1 index area terminal 1 index area 01-08-08 02-10-18 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 117 of 125 nxp semiconductors clrc663 contactless reader ic detailed package information can be found at http://www.nxp.com/package/sot617-1.html . 25. handling information moisture sensitivity level (msl) evaluation has been performed according to snw-fq-225b rev.04/07/07 (jedec j-std-020c) . msl for this package is level 2 which means 260 ? c convection reflow temperature. dry pack is required. 1 year out-of-pack floor life at maximum ambient temperature 30 ? c/ 85 % rh. 26. packing information fig 38. packing information 1 tray 001aaj740 strap 46 mm from corner tray chamfer pin 1 chamfer pin 1 printed piano box esd warning preprinted barcode label (permanent) barcode label (peel-off) qa seal hyatt patent preprinted the straps around the package of stacked trays inside the piano-box have sufficient pre-tension to avoid loosening of the trays. in the traystack (2 trays) only one tray type* allowed *one supplier and one revision number.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 118 of 125 nxp semiconductors clrc663 contactless reader ic 27. abbreviations table 244. abbreviations acronym description adc analog-to-digital converter bpsk binary phase shift keying crc cyclic redundancy check cw continuous wave egt extra guard time emc electro magnetic coupling emd electro magnetic disturbance eof end of frame epc electronic product code etu elementary time unit gpio general purpose input/output hbm human body model i 2 c inter-integrated circuit jtag joint test action group lfo low frequency oscillator lpcd low power card detection lsb least significant bit miso master in slave out mosi master out slave in msb most significant bit nrz not return to zero nss not slave select otp one time programmable pcd proximity coupling device (reader) pll phase-locked loop rtz return to zero rx receiver sof start of frame spi serial peripheral interface sw software t timer timing of the clk period (1/clk period) tx transmitter uart universal asynchronous receiver transmitter uid unique identification vco voltage controlled oscillator
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 119 of 125 nxp semiconductors clrc663 contactless reader ic 28. references [1] application note ? mfrc52x reader ic family directly matched antenna design [2] application note ? mifare (iso/iec 14443 a) 13.56 mhz rfid proximity antennas [3] bsdl file ? boundary scan description language file of the clrc663
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 120 of 125 nxp semiconductors clrc663 contactless reader ic 29. revision history table 245. revision history document id release date data sheet status change notice supersedes clrc663 v.2.0 20110615 preliminary data sheet - clrc663 v.1.0 modifications: ? general update clrc663 v.1.0 20110308 objective data sheet - -
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 121 of 125 nxp semiconductors clrc663 contactless reader ic 30. legal information 30.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 30.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 30.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comp lete, exhaustive or legally binding. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 122 of 125 continued >> nxp semiconductors clrc663 contactless reader ic export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully in demnifies nxp semi conductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive appl ications beyond nxp semiconductors? standard warranty and nxp semicond uctors? product specifications. 30.4 licenses 30.5 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. mifare ? is a trademark of nxp b.v. mifare ultralight ? is a trademark of nxp b.v. desfire ? is a trademark of nxp b.v. mifare plus ? is a trademark of nxp b.v. icode and i-code ? are trademarks of nxp b.v. 31. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com purchase of nxp ics with iso/iec 14443 type b functionality this nxp semiconductors ic is iso/iec 14443 type b software enabled and is licensed under innovatron?s contactless card patents license for iso/iec 14443 b. the license includes the right to use the ic in systems and/or end-user equipment. ratp/innovatron technology purchase of nxp ics with nfc technology purchase of an nxp semiconductors ic that complies with one of the near field communication (nfc) standards iso/iec 18092 and iso/iec 21481 does not convey an implied license unde r any patent right infringed by implementation of any of those standards. a license for the patents portfolio of nxp b.v. for the nfc standards needs to be obtained at via licensing, the pool agent of the nfc patent pool, e-mail: info@vialicensing.com .
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 123 of 125 continued >> nxp semiconductors clrc663 contactless reader ic 32. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 general description . . . . . . . . . . . . . . . . . . . . . . 1 3 features and benefits . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 3 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 iso/iec14443a/mifare read/write functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 iso/iec14443b read/write functionality . . . . . . 9 8.3 felica read/write functionality . . . . . . . . . . . . . 11 8.3.1 felica framing and coding . . . . . . . . . . . . . . . 11 8.4 iso/iec15693 read/write f unctionality . . . . . . 12 8.5 epc-uid/uid-otp read/wri te functionality . . 13 8.6 iso/iec18000-3 mode 3 read/write functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.7 iso/iec 18092 mode . . . . . . . . . . . . . . . . . . . 13 8.7.1 passive communication mode . . . . . . . . . . . . 14 8.7.2 iso/iec 18092 framing and coding . . . . . . . . 15 8.7.3 iso/iec 18092 protocol support. . . . . . . . . . . 15 9 clrc663 registers. . . . . . . . . . . . . . . . . . . . . . 16 9.1 register bit behavior. . . . . . . . . . . . . . . . . . . . 16 9.2 description/command register . . . . . . . . . . . . 19 9.2.1 command_reg . . . . . . . . . . . . . . . . . . . . . . . 19 9.3 register description/sam register . . . . . . . . . 20 9.3.1 hostctrl_reg . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.4 register description/fifo register . . . . . . . . . 20 9.4.1 fifocontrol_reg . . . . . . . . . . . . . . . . . . . . . . 20 9.4.2 waterlevel_reg . . . . . . . . . . . . . . . . . . . . . . . 21 9.4.3 fifolength_reg . . . . . . . . . . . . . . . . . . . . . . . 22 9.4.4 fifodata_reg . . . . . . . . . . . . . . . . . . . . . . . . 22 9.5 register description/interrupt register . . . . . . 22 9.5.1 irq0_reg register . . . . . . . . . . . . . . . . . . . . . 22 9.5.2 irq1_reg register . . . . . . . . . . . . . . . . . . . . . 23 9.5.3 irq0en_reg register . . . . . . . . . . . . . . . . . . . 24 9.5.4 irq1en_reg register . . . . . . . . . . . . . . . . . . . 24 9.6 register description/cl register. . . . . . . . . . . 25 9.6.1 error_reg register . . . . . . . . . . . . . . . . . . . . . 25 9.6.2 status_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.6.3 rxbitctrl_reg . . . . . . . . . . . . . . . . . . . . . . . . 27 9.6.4 rxcoll_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.7 register description/timer register . . . . . . . . 29 9.7.1 tcontrol_reg . . . . . . . . . . . . . . . . . . . . . . . . 29 9.8 t0control_reg . . . . . . . . . . . . . . . . . . . . . . . . 29 9.8.1 t0reloadhi_reg . . . . . . . . . . . . . . . . . . . . . . 30 9.8.2 t0reloadlo_reg. . . . . . . . . . . . . . . . . . . . . . 30 9.8.3 t0countervalhi_reg . . . . . . . . . . . . . . . . . . . 31 9.8.4 t0countervallo_reg . . . . . . . . . . . . . . . . . . 31 9.8.5 t1control_reg. . . . . . . . . . . . . . . . . . . . . . . . 31 9.8.6 t1reloadhi_reg . . . . . . . . . . . . . . . . . . . . . . 32 9.8.7 t1reloadlo_reg. . . . . . . . . . . . . . . . . . . . . . 32 9.8.8 t1countervalhi_reg . . . . . . . . . . . . . . . . . . . 33 9.8.9 t1countervallo_reg . . . . . . . . . . . . . . . . . . 33 9.8.10 t2control_reg. . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.11 t2reloadhi_reg . . . . . . . . . . . . . . . . . . . . . . 34 9.8.12 t2reloadlo_reg. . . . . . . . . . . . . . . . . . . . . . 34 9.8.13 t2countervalhi_reg . . . . . . . . . . . . . . . . . . . 35 9.8.14 t2countervalloreg . . . . . . . . . . . . . . . . . . . 35 9.8.15 t3control_reg. . . . . . . . . . . . . . . . . . . . . . . . 35 9.8.16 t3reloadhi_reg . . . . . . . . . . . . . . . . . . . . . . 36 9.8.17 t3reloadlo_reg. . . . . . . . . . . . . . . . . . . . . . 36 9.8.18 t3countervalhi_reg . . . . . . . . . . . . . . . . . . . 37 9.8.19 t3countervallo_reg . . . . . . . . . . . . . . . . . . 37 9.8.20 t4control_reg. . . . . . . . . . . . . . . . . . . . . . . . 37 9.8.21 t4reloadhi_reg . . . . . . . . . . . . . . . . . . . . . 38 9.8.22 t4reloadlo_reg. . . . . . . . . . . . . . . . . . . . . . 38 9.8.23 t4countervalhi_reg . . . . . . . . . . . . . . . . . . . 39 9.8.24 t4countervallo_reg . . . . . . . . . . . . . . . . . . 39 9.9 description/transmitter register . . . . . . . . . . . 40 9.9.1 txmode_reg . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.9.2 txamp_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.9.3 txcon_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.9.4 txl_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.10 description/crc register . . . . . . . . . . . . . . . . 41 9.10.1 txcrccon_reg . . . . . . . . . . . . . . . . . . . . . . . 41 9.10.2 rxcrccon_reg . . . . . . . . . . . . . . . . . . . . . . . 42 9.11 description/transmitter register . . . . . . . . . . . 43 9.11.1 txdatanum_reg . . . . . . . . . . . . . . . . . . . . . . 43 9.11.2 txdatamodwidth_reg . . . . . . . . . . . . . . . . . 44 9.11.3 txsym10burstlen_reg. . . . . . . . . . . . . . . . . 45 9.11.4 txwaitctrl_reg . . . . . . . . . . . . . . . . . . . . . . . 45 9.11.5 txwaitlo_reg . . . . . . . . . . . . . . . . . . . . . . . . 46 9.11.6 framecon_reg . . . . . . . . . . . . . . . . . . . . . . . 46 9.12 description/receiver register. . . . . . . . . . . . . 47 9.12.1 rxsofd_reg . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.12.2 rxctrl_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.12.3 rxwait_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.12.4 rxthreshold_reg . . . . . . . . . . . . . . . . . . . . . 48 9.12.5 rcv_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.12.6 rxana_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.13 description/clock register . . . . . . . . . . . . . . . 50 9.13.1 serialspeed_reg . . . . . . . . . . . . . . . . . . . . . . 50
clrc663 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. preliminary data sheet public rev. 2.0 ? 15 june 2011 171120 124 of 125 continued >> nxp semiconductors clrc663 contactless reader ic 9.13.2 lpo_trimm_reg . . . . . . . . . . . . . . . . . . . . . . 50 9.13.3 pll_ctrl_reg register. . . . . . . . . . . . . . . . . . 50 9.13.4 pll_div_out_reg . . . . . . . . . . . . . . . . . . . . . 51 9.14 description/lpcd register . . . . . . . . . . . . . . . 51 9.14.1 lpcd_qmin_reg . . . . . . . . . . . . . . . . . . . . . . 51 9.14.2 lpcd_qmax_reg . . . . . . . . . . . . . . . . . . . . . 52 9.14.3 lpcd_imin_reg. . . . . . . . . . . . . . . . . . . . . . . 52 9.14.4 lpcd_i_result_reg . . . . . . . . . . . . . . . . . . . 52 9.14.5 lpcd_result_q_reg . . . . . . . . . . . . . . . . . . 53 9.15 description/pad register. . . . . . . . . . . . . . . . . 53 9.15.1 paden_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.15.2 padout_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.15.3 padin_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.15.4 sigout_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.16 description/transmitter symbol register . . . . . 55 9.16.1 txbitmod_reg . . . . . . . . . . . . . . . . . . . . . . . . 55 9.16.2 txdatacon_reg . . . . . . . . . . . . . . . . . . . . . . . 56 9.16.3 txdatamod_reg . . . . . . . . . . . . . . . . . . . . . . 57 9.16.4 txsymfreq_reg . . . . . . . . . . . . . . . . . . . . . . 57 9.16.5 txsym0h_reg . . . . . . . . . . . . . . . . . . . . . . . . 58 9.16.6 txsym0l_reg . . . . . . . . . . . . . . . . . . . . . . . . 58 9.16.7 txsym1h_reg . . . . . . . . . . . . . . . . . . . . . . . . 59 9.16.8 txsym1l_reg . . . . . . . . . . . . . . . . . . . . . . . . 59 9.16.9 txsym2_reg . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.16.10 txsym3_reg . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.16.11 txsym10len_reg . . . . . . . . . . . . . . . . . . . . . 60 9.16.12 txsym32len_reg . . . . . . . . . . . . . . . . . . . . . 60 9.16.13 txsym10burstctrl_reg . . . . . . . . . . . . . . . . . 60 9.16.14 txsym10mod reg . . . . . . . . . . . . . . . . . . . . . 61 9.16.15 txsym32mod_reg . . . . . . . . . . . . . . . . . . . . . 62 9.17 description/receiver symbol register . . . . . . . 62 9.17.1 rxbitmod_reg . . . . . . . . . . . . . . . . . . . . . . . . 62 9.17.2 rxeofsym_reg . . . . . . . . . . . . . . . . . . . . . . . 63 9.17.3 rxsyncvalh_reg . . . . . . . . . . . . . . . . . . . . . . 64 9.17.4 rxsyncvall_reg . . . . . . . . . . . . . . . . . . . . . . 64 9.17.5 rxsyncmod_reg . . . . . . . . . . . . . . . . . . . . . . 64 9.17.6 rxmod_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.17.7 rxcorr_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.17.8 fabcali_reg. . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.18 description/version register . . . . . . . . . . . . . . 66 9.18.1 version_reg . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10 digital interfaces. . . . . . . . . . . . . . . . . . . . . . 66 10.1 microcontroller interface type . . . . . . . . . . . . 66 10.2 spi compatible interface . . . . . . . . . . . . . . . . 67 10.2.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2.2 read data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.2.3 write data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.2.4 address byte. . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.2.5 timing specification spi . . . . . . . . . . . . . . . . . 68 10.3 uart interface . . . . . . . . . . . . . . . . . . . . . . . . 69 10.3.1 selection of the transfer speeds . . . . . . . . . . 69 10.3.2 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4 i 2 c-bus interface . . . . . . . . . . . . . . . . . . . . . . 71 10.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4.2 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4.3 start and stop conditions. . . . . . . . . . . . . 72 10.4.4 byte format. . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.6 7-bit addressing . . . . . . . . . . . . . . . . . . . 74 10.4.7 register write access . . . . . . . . . . . . . . . . . . 75 10.4.8 register read access . . . . . . . . . . . . . . . . . . 75 10.4.9 i 2 cl bus interface . . . . . . . . . . . . . . . . . . . . . 76 10.4.10 i 2 clsam bus interface . . . . . . . . . . . . . . . . . 77 10.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . 77 10.5.1 test access port (tap) . . . . . . . . . . . . . . . . . 78 10.5.2 test clock (tck) . . . . . . . . . . . . . . . . . . . . . . 78 10.5.3 test mode select (tms) . . . . . . . . . . . . . . . . 78 10.5.4 test data input (tdi) . . . . . . . . . . . . . . . . . . . 78 10.5.5 test data output (tdo) . . . . . . . . . . . . . . . . . 79 10.5.6 instruction register . . . . . . . . . . . . . . . . . . . . . 79 10.5.7 data register . . . . . . . . . . . . . . . . . . . . . . . . . 79 10.5.8 boundary scan cell. . . . . . . . . . . . . . . . . . . . . 79 10.5.9 boundary scan path . . . . . . . . . . . . . . . . . . . . 79 10.5.10 boundary scan description language (bsdl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 10.5.11 non ieee1149.1 commands. . . . . . . . . . . . . 81 10.5.11.1 interface on/off . . . . . . . . . . . . . . . . . . . . . . . . 81 10.5.11.2 register access read . . . . . . . . . . . . . . . . . . 81 10.5.11.3 register access writer. . . . . . . . . . . . . . . . . . 81 11 analog interface and contactless uart . . . 82 11.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 11.2 tx transmitter . . . . . . . . . . . . . . . . . . . . . . . 82 11.2.1 overshoot protection . . . . . . . . . . . . . . . . . . . 84 11.3 receiver circuitry . . . . . . . . . . . . . . . . . . . . . . 85 11.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 11.3.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . 86 11.4 s3c interface / (gpio0)s igin-sigout . . . . . . 86 12 memory organization of the eeprom. . . . . . 90 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.2 eeprom memory organization. . . . . . . . . . . 90 12.2.1 production area . . . . . . . . . . . . . . . . . . . . . . . 91 12.2.2 configuration area . . . . . . . . . . . . . . . . . . . . . 91 12.2.2.1 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.2.3 mifare key area. . . . . . . . . . . . . . . . . . . . . . 92 12.2.4 register set protocol area . . . . . . . . . . . . . . . 92 13 fifo buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 13.2 accessing the fifo buffer . . . . . . . . . . . . . . . 93 13.3 controlling the fifo buffer . . . . . . . . . . . . . . . 93 13.4 status information about the fifo buffer . . . . 93
nxp semiconductors clrc663 contactless reader ic ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 june 2011 171120 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 14 timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.1 usage timer unit . . . . . . . . . . . . . . . . . . . . . . . 95 14.1.1 time-out- and watch-dog-counter . . . . . . . . 95 14.1.2 wake-up timer (timer4) . . . . . . . . . . . . . . . . . 96 14.1.3 stop watch . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 14.1.4 programmable one-shot timer . . . . . . . . . . . . 96 14.1.5 periodical trigger. . . . . . . . . . . . . . . . . . . . . . . 96 15 interrupt request system. . . . . . . . . . . . . . . . . 97 16 clock generation . . . . . . . . . . . . . . . . . . . . . . . 98 16.1 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 98 16.2 integern pll clock line. . . . . . . . . . . . . . . . . . 98 16.3 low power oscillator (lpo) . . . . . . . . . . . . . 100 17 power management . . . . . . . . . . . . . . . . . . . . 101 17.1 supply concept . . . . . . . . . . . . . . . . . . . . . . . 101 17.2 power reduction mode . . . . . . . . . . . . . . . . . 101 17.2.1 power-down . . . . . . . . . . . . . . . . . . . . . . . . . 101 17.2.2 standby mode. . . . . . . . . . . . . . . . . . . . . . . . 101 17.2.3 modem off mode . . . . . . . . . . . . . . . . . . . . 101 17.3 low power card detection (lpcd) . . . . . . . 102 17.4 reset and startup time . . . . . . . . . . . . . . . . . 102 18 clrc663 command set . . . . . . . . . . . . . . . . 103 18.1 general description . . . . . . . . . . . . . . . . . . . 103 18.2 general behavior . . . . . . . . . . . . . . . . . . . . . 103 18.3 clrc663 commands overview . . . . . . . . . . 103 18.3.1 clrc663 command description . . . . . . . . . 104 18.3.1.1 idle command . . . . . . . . . . . . . . . . . . . . . . . . 104 18.3.1.2 lpcd command . . . . . . . . . . . . . . . . . . . . . . 104 18.3.1.3 load key command . . . . . . . . . . . . . . . . . . . 104 18.3.1.4 mfauthent command . . . . . . . . . . . . . . . . . . 104 18.3.1.5 ack reqcommand . . . . . . . . . . . . . . . . . . . . 105 18.3.1.6 receive command . . . . . . . . . . . . . . . . . . . . 105 18.3.1.7 transceive command . . . . . . . . . . . . . . . . . . 105 18.3.1.8 transmit command . . . . . . . . . . . . . . . . . . . . 105 18.3.1.9 writee2 command . . . . . . . . . . . . . . . . . . . . 105 18.3.1.10 writee2page command . . . . . . . . . . . . . . . 106 18.3.1.11 reade2 command . . . . . . . . . . . . . . . . . . . . 106 18.3.1.12 loadreg command . . . . . . . . . . . . . . . . . . . 106 18.3.1.13 loadprotocol command . . . . . . . . . . . . . . . . 106 18.3.1.14 loadkeye2 command . . . . . . . . . . . . . . . . . 106 18.3.1.15 storekeye2 command . . . . . . . . . . . . . . . . . 106 18.3.1.16 soft reset command . . . . . . . . . . . . . . . . . . 107 19 limiting values. . . . . . . . . . . . . . . . . . . . . . . . 108 20 recommended operating conditions. . . . . . 108 21 thermal characteristics . . . . . . . . . . . . . . . . 108 22 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 108 22.1 timing characteristics . . . . . . . . . . . . . . . . . . 111 23 application information. . . . . . . . . . . . . . . . . 113 23.1 circuit description . . . . . . . . . . . . . . . . . . . . . 113 23.1.1 emc low pass filter . . . . . . . . . . . . . . . . . . . . 113 23.1.2 antenna matching . . . . . . . . . . . . . . . . . . . . . 114 23.1.3 receiving circuit. . . . . . . . . . . . . . . . . . . . . . . 114 23.1.4 antenna coil . . . . . . . . . . . . . . . . . . . . . . . . . 115 24 package outline. . . . . . . . . . . . . . . . . . . . . . . . 116 25 handling information . . . . . . . . . . . . . . . . . . . 117 26 packing information . . . . . . . . . . . . . . . . . . . . 117 27 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 118 28 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 29 revision history . . . . . . . . . . . . . . . . . . . . . . 120 30 legal information . . . . . . . . . . . . . . . . . . . . . 121 30.1 data sheet status . . . . . . . . . . . . . . . . . . . . . 121 30.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 121 30.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 121 30.4 licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 30.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 122 31 contact information . . . . . . . . . . . . . . . . . . . 122 32 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

▲Up To Search▲

Price & Availability of CLRC66301TRAYB

	To Download CLRC66301TRAYB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .