hy51v64164,hy51v65164 4mx16, extended data out mode this family is a 64m bit dynamic ram organized 4,194,304 x 16-bit configuration with extended data out mode cmos drams . extended data out mode is a kind of page mode which is useful for the read operation. the circuit and process design allow this device to achieve high performance and low power dissipation. optional features are access time(60 or 70ns) and refresh cycle(8k ref. or 4k ref.) and power consumption (normal or low power with self refresh). hyundai ? s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. description features ? extended data out operation ? read-modify-write capability ? multi-bit parallel test capability ? lvttl(3.3v) compatible inputs and outputs ? /cas-before-/ras, /ras-only, hidden and self refresh capability ? max. active power dissipation speed 60 8 k refresh 504 mw 4 k refresh 648 mw ? fast access time and cycle time speed 60 70 trac 60 ns 70 ns tcac 15 ns 20 ns thpc 25 ns 30 ns ? refresh cycle part number hy51v64164 1) hy51v65164 2) refresh 8 k 4 k normal 64 ms l-part 128 ms 1) normal read / write, /ras only refresh : 8k cycles / 64ms /cas-before-/ras, hidden refresh : 4k cycles / 64ms 2) normal read / write, /ras only refresh : 4k cycles / 64ms /cas-before-/ras, hidden refresh : 4k cycles / 64ms this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licences are implied rev.00 / oct.97 ordering information part name hy51v64164tc refresh 8 k power package 50 pin tsop-ii hy51v64164ltc 8 k l-part 50 pin tsop-ii hy51v64164sltc 8 k * sl-part 50 pin tsop-ii hy51v65164tc 4 k 50 pin tsop-ii hy51v65164ltc 4 k l-part 50 pin tsop-ii hy51v65164sltc 4 k * sl-part 50 pin tsop-ii 70 432 mw 576 mw hyundai semiconductor ? jedec standard pinout 50-pin plastic tsop-ii (400mil) ? single power supply of 3.3 0.3v ? early write or output enable controlled write 1 * sl : self refresh with low power. 1 st generation
functional block diagram we lcas ucas oe data input buffer dq0~7 dq8~15 data output buffer dq0~7 dq8~15 cas clock generator cloumn predecoder refresh controller row predecoder (13/12)* column decoder sense amp i/o gate memory array 4,194,304x16 row decoder ras clock generator x32 parallel test substrate bias generator v cc v ss address buffer ras dq0 ~ dq15 *( a12) for 8k refresh part (8 k refresh / 4k refresh)* (9/10)* (13/12)* 8 8 8 8 8 8 8 8 a0 a1 a11 *( a12) a10 a2 2 4 mx16,edo dram rev.00 / oct.97 refresh counter a3 a4 a5 a6 a7 a8 a9 hy51v64164,hy51v65164
hy51v64164,hy51v65164 pin configuration (marking side) pin description / ras / cas row address strobe column address strobe / we write enable / oe output enable a0~a12 address input (8k refresh product) a0~a11 address input (4k refresh product) dq0~dq15 data in/out vcc power (3.3v) vss ground nc no connection pin name parameter 3 4 mx16,edo dram rev.00 / oct.97 a12(n.c)* : for 4k refresh product 50 pin plastic tsop- ii (400mil) v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 n.c v cc we ras n.c n.c n.c n.c a0 a1 a2 a3 a4 a5 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 ucas oe n.c n.c a12(n.c)* a11 a10 a9 a8 a7 a6 v ss dq13 dq12 v ss dq11 dq10 dq9 dq8 n.c v ss lcas
hy51v64164,hy51v65164 absolute maximum rating symbol t a parameter ambient temperature rating 0 to 70 unit c t stg storage temperature -55 to 150 c v in, v out voltage on any pin relative to v ss -0.5 to 6.0 v v cc voltage on v cc relative to v ss -0.5 to 4.6 v i os short circuit output current 50 ma p d power dissipation 1 w t solder soldering temperature ? time 260 ? 10 c ? sec symbol i li parameter input leakage current (any input) unit m a min -5 max 5 test condition v ss v in v cc + 0.3 all other pins not under test = v ss dc and operating characteristics i lo output leakage current (any input) m a -5 5 v ss v out v cc /ras&/cas at v ih v ol output low voltage v - 0.4 i ol = 2.0 ma v oh output high voltage v 2.4 - i ol = -2.0 ma 4 recommended dc operating conditions symbol v cc parameter power supply voltage unit v max 3.6 typ 3.3 min 3.0 v ih input high voltage v v cc+ 0.3 1) - 2.0 v il input low voltage v 0.8 - -0.3 2) note : all voltages are referenced to v ss . 1) 6.0v at pulse width 10ns which is measured at v cc . 2) -1.0v at pulse width 10ns which is measured at v ss . ( t a = 0 c to 70 c ) 4 mx16,edo dram rev.00 / oct.97 note : operation at or above absolute maximum ratings could adversely affect device reliability and cause permanent damage.
hy51v64164,hy51v65164 dc characteristics symbol i cc1 parameter operating current speed 60 70 unit ma ( t a = 0 c to 70 c , v cc = 3.3 0.3v , v ss = 0v, unless otherwise noted.) note 8 k refresh 140 120 4 k refresh 180 160 test condition / ras, /cas cycling t rc = t rc(min.) max. current i cc2 lvttl standby current ma 1 1 / ras, /cas 3 v ih other inputs 3 v ss i cc3 / ras-only refresh current 60 70 ma 140 120 180 160 / ras cycling,/cas = v ih t rc = t rc(min.) i cc4 edo mode current 60 70 ma 140 120 160 130 / cas cycling, /ras = v il t hpc = t hpc(min.) i cc5 cmos standby current l-part m a 500 300 500 300 / ras = /cas 3 v cc - 0.2v i cc6 / cas-before-/ras refresh current 60 70 ma 180 160 180 160 t rc = t rc(min.) i cc7 battery back-up current (l-part) m a 700 700 v ih = v cc - 0.2v, v il = 0.2v /cas = cbr cycling or 0.2v /oe&/we = v ih = v cc - 0.2v address = don ? t care, t rc = 31.25 us dq0~dq15 = open, t ras 300 ns i cc8 self refresh current (l-part) m a 700 700 / ras&/cas = 0.2v other pins are same as i cc7 1. i cc1 , i cc3 , i cc4 and i cc6 depend on output loading and cycle rates(t rc and t hpc ). 2. specified values are obtained with output unloaded. 3. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 , address can be changed only once while /ras=v il . in i cc4 , address can be changed maximum once while /cas=v ih withen one edo mode cycle time t hpc . 5 4 mx16,edo dram rev.00 / oct.97
t rc random read or write cycle time ns symbol parameter unit note ac characteristics ( t a = 0 c to 70 c , v cc = 3.3 0.3v , v ss = 0v, unless otherwise noted.) hy51v64164,hy51v65164 read-modify-write cycle time edo mode cycle time edo mode read-modify-write cycle time access time from /ras access time from /cas access time from column address access time from /cas precharge / cas to output low impedance output buffer turn-off delay from /cas transition time(rise and fall) / ras precharge time / ras pulse width / ras pulse width(edo mode) / ras hold time / cas hold time / cas pulse width / ras to /cas delay time / ras to column address delay time / cas to /ras precharge time / cas precharge time row address set-up time row address hold time column address set-up time column address hold time column address to /ras lead time read command set-up time read command hold time referenced to /cas t rwc t hpc t hprwc t rac t cac t aa t cpa t clz t cez t t t rp t ras t rasp t rsh t csh t cas t rcd t rad t crp t cp t asr t rah t asc t cah t ral t rcs t rch ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 4,5,10,11 4,5,10 4,5,11 4 3 4 10 11 15 14 14 7 / oe to output in low impedance t olz ns column address hold time from /ras t ar ns read command hold time referenced to /ras t rrh 130 min max 70 ns 170 30 75 - - - - 0 0 2 50 70 70 20 65 15 20 15 5 10 0 10 0 15 35 0 0 - - - - 70 20 35 40 - 15 50 - 10 k 100 k - - 10 k 50 35 - - - - - - - - - 3 - 55 - 0 - min max 60 ns 110 140 25 60 - - - - 0 0 2 40 60 60 15 55 10 20 15 5 10 0 10 0 10 30 0 0 - - - - 60 15 30 35 - 15 50 - 10 k 100 k - - 10 k 45 30 - - - - - - - - - 3 - 50 - 0 - ns 7 4 mx16,edo dram rev.00 / oct.97 1 # 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
t cwl write command to /cas lead time symbol parameter unit note ac characteristics continued hy51v64164,hy51v65164 data-in set-up time data-in hold time refresh period(4096 cycles) refresh period(8192 cycles) refresh period(l-part) ns write command set-up time / cas to /we delay time / ras to /we delay time column address to /we delay time / cas set-up time(cbr cycle) / cas hold time(cbr cycle) / ras to /cas precharge time / cas precharge time(cbr counter test) / ras hold time referenced to /oe / oe access time / oe to data delay output buffer turn-off delay time from /oe / oe command hold time / we delay time from /cas precharge / ras hold time from /cas precharge / we to /ras precharge time(cbr cycle) / we to /ras hold time(cbr cycle) write command set-up time(test mode in) write command hold time(test mode in) / ras pulse width(self refresh) t ds t dh t ref t wcs t cwd t rwd t awd t csr t chr t rpc t cpt t roh t oea t oed t oez t oeh t cpwd t rhcp t wrp t wrh t wts t wth t rass ns ns ms ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 17 8,20 8,20 12,13 12 12,13 9 9,16 9 9 18 19 6 6 write command hold time write command pulse width t wch t wp write command to /ras lead time t rwl ns ns ns write command hold time from /ras t wcr ns data-in hold time referenced to /ras t dhr min max 70 ns 15 0 10 - - - 0 45 95 60 5 10 5 35 0 - 20 0 20 64 40 10 10 10 10 100 k - - - 64 64 128 - - - - - - - - - 20 - 15 - - - - - - - - 10 10 20 - - - 50 - 50 - min max 60 ns 10 0 10 - - - 0 36 80 50 5 10 5 30 0 - 15 0 15 54 35 10 10 10 10 100 k - - - 64 64 128 - - - - - - - - - 15 - 15 - - - - - - - - 10 10 15 - - - 45 - 45 - ns 4 mx16,edo dram rev.00 / oct.97 32 # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
ac characteristics continued symbol parameter unit note hy51v64164,hy51v65164 t wpe / we pulse width(edo cycle) ns / oe to /cas hold time ns / cas hold time to /oe ns t och t cho t oep / oe precharge time ns 8 output data hold time output buffer turn-off delay from /ras output buffer turn-off delay from /we t doh t rez t wez / we to data delay time t wed ns ns ns ns 6 6 / ras precharge time(self refresh) / cas hold time(self refresh) t rps t chs 70 ns 5 5 5 min max 15 5 - - - - - 5 0 0 - 15 15 130 -50 - - 60 ns min max 5 5 5 15 5 - - - - - 5 0 0 - 15 15 110 -50 - - ns ns 4 mx16,edo dram rev.00 / oct.97 61 # 62 63 64 65 66 67 68 69 70
test mode symbol parameter unit note hy51v64164,hy51v65164 / cas to /we delay time / ras to /we delay time column address to /we delay time t cwd t rwd t awd / oe access time / oe to data delay t oea t oed / oe command hold time / we delay time from /cas precharge t oeh t cpwd min max 70 ns 50 100 65 - - - - 25 25 - 25 69 - - min max 60 ns 41 85 55 - - - - 20 20 - 20 59 - - ns ns ns ns ns ns ns 9 16 9 9 4 mx16,edo dram rev.00 / oct.97 # 42 43 44 50 51 53 54 t rc random read or write cycle time read-modify-write cycle time edo mode cycle time edo mode read-modify-write cycle time access time from /ras access time from /cas access time from column address access time from /cas precharge t rwc t hpc t hprwc t rac t cac t aa t cpa / ras pulse width / ras pulse width(edo mode) / ras hold time / cas hold time t ras t rasp t rsh t csh / cas pulse width t cas column address to /ras lead time t ral 135 175 35 80 - - - - - - - - 75 25 40 45 75 75 25 70 10 k 100 k - - 25 10 k 40 - 115 145 30 65 - - - - - - - - 65 20 35 40 65 65 20 60 10 k 100 k - - 20 10 k 35 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4,5,10,11 4,5,10 4,5,11 4 4 1 2 3 4 5 6 7 8 13 14 15 16 17 27
hy51v64164,hy51v65164 note 1. an initial pause of 200 m s is required after power-up followed by 8 /ras-only refresh cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 /cas- before-/ras initialization cycles instead of 8 /ras-only refresh cycles are required. the device should be carefully initialized to be prevented from being entered into multi bit parallel test mode during initialization. 2. if /ras=v ss during power-up, the hy51v64164, hy51v65164 could begin an active cycle. this condition results in higher current than necessary current which is demanded from the power supply during power-up. 3. it is recommended that /ras and /cas track with vcc during power-up or be held at a valid v ih in order to minimize the power-up current. 4. v ih(min.) and v il(max.) are reference levels for measuring timing of input signals. transition times are measured between v ih(min.) and v il(max.) , and are assumed to be 5ns for all inputs. 5. measured at v oh =2.0v and vol=0.8v with a load equivalent to 1ttl loads and 100pf. 6. t wez , t rez , t cez and t oez define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. either t rch or t rrh must be satisfied for a read cycle. 8. these parameters are referenced to /cas leading edge in early write cycles and to /we leading edge in read-modify- write cycles and late write cycle. 9. t wcs , t rwd , t cwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs(min.) , the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. if t rwd 3 t rwd(min.) , t cwd 3 t cwd(min.) , t awd 3 t awd(min) , and t cpwd 3 t cpwd(min.) , the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 10.operation within the t rcd(max.) limit ensures that t rac(max.) can be met. t rcd(max.) is specified as a reference point only. if t rcd is greater than the specified t rcd(max.) limit, then access time is controlled by t cac . 11.operation within the t rad(max.) limit ensures that t rac(max.) can be met. t rad(max.) is specified as a reference point only. if t rad is greater than the specified t rad(max.) limit, then access time is controlled by t aa . 12.t ref(max) =128ms is applied to l-parts and sl-parts. 13.a burst of 8192 /ras-only refresh cycles must be executed within 64ms (128ms for l-parts) after exiting self refresh. (cbr refresh & hidden refresh : 4k cycle/64ms) 14.t asc ,t cah are referenced to the earlier /cas falling edge. 15.t cp is specified from the last /cas rising edge in the previous to the first /cas falling edge in the next cycle. 16.t cwd is referenced to the later /cas falling edge at word read-modifiy-write cycle. 17.t cwl is specified from /we falling edge to the earlier /cas rising edge. 18.t csr is referenced to the earlier /cas falling before /ras transition low. 19.t chr is referenced to the later /cas rising high after /ras transition low. 20.t ds is specified for the earlier /cas falling edge and t dh is specified by the later /cas falling edge in early write cycle. 10 capacitance symbol c in1 parameter input capacitance (a0~a12) max 5 unit pf c in2 input capacitance (/ras, /cas, /we, /oe) 7 pf c dq data input / output capacitance (dq0~dq15) 7 pf ( t a = 0 c to 70 c , v cc = 3.3 0.3v, v ss = 0v, f = 1mhz, unless otherwise noted.) typ. - - - 4 mx16,edo dram rev.00 / oct.97
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