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high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 1 of 19 advanced information c9850 product features ? four differential host clocks ? two 3v mref single ended for drcg ? four 3v, 66 mhz clocks ? ten 3v, 33 mhz pci clocks ? two 48 mhz clocks ? two 14.318 mhz reference clocks ? select logic for differential swing control, test mode, hi-z, power-down, spread spectrum, and frequency selection ? external resistor for cpu current reference ? 56 pin ssop and tssop package product description this device is an advanced performance single package clock solution for high end pentium iii designs using rambus memory system architectures. it provides all of the system motherboard?s clocks needed to support the cpu, memory and peripheral devices. included in the frequency table are specific +5% margin test frequencies to assist designers in verification of adequate timing margins in designs. all cpu (host) clocks are deferential and comply with intel specified timing requirements. frequency selection table sel 100/133 sela selb cpu(1:4), cpu# (1:4) 3vmref/ 3vmref_b 3v66 (0:3) pci (0:9) 48 m (0:1) ref (1:2) 0 0 0 100 mhz 50 mhz 66.7 mhz 33.3 mhz 48 mhz 14.318 mhz 0 0 1 105 mhz 52.5 mhz 70.0 mhz 35.0 mhz 48 mhz 14.318 mhz 0 1 0 200 mhz 50 mhz 66.7 mhz 33.3 mhz 48 mhz 14.318 mhz 0 1 1 high z high z high z high z high z high z 1 0 0 133.3 mhz 66.7 mhz 66.7 mhz 33.3 mhz 48 mhz 14.318 mhz 1 0 1 126.7 mhz 63.3 mhz 63.3 mhz 31.7 mhz 48 mhz 14.318 mhz 1 1 0 200 mhz 66.7 mhz 66.7 mhz 33.3 mhz 48 mhz 14.318 mhz 1 1 1 xin/2 xin/4 xin/4 xin/8 xin/2 xin block diagram pin configuration vssr ref1/multsel0 ref2/multsel1 vddr xin xout vssp pci0 pci1 vddp pci2 pci3 vssp pci4 pci5 vddp pci6 pci7 vssp pci8 pci9 vddp sel100/133 vssu 48m0/sela 48m1/selb vddu pwrdwn# vddm 3vmref 3vmref_b vssm spread# cpu1 cpu1# vddc cpu2 cpu2# vssc cpu3 cpu3# vddc cpu4 cpu4# vssc i_ref vdd vss vdd 3v66_0 3v66_1 vss vssl 3v66_2 3v66_3 vddl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 osc vco1 vco2 i_ref vddr ref1/multsel0 ref2/multsel1 vssr sel1 sel2 3vmref 3vmref_b vddc cpu(1:4) cpu#(1:4) vssc vddl 3v66(0:3) vssl vddp pci (0:9) vssp vddu 48m(0:1)/sel(a:b) vssu sela/b 2 xout xin spread# sel100/133 pwrdwn#
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 2 of 19 advanced information c9850 pin description pin no. pin name i/o description 55 3vmref o 3v reference to memory clock driver. it is synchronous to the cpu clock. see table 1, pg 1 for spread selection. 54 3vmref_b o 3v reference to memory clock driver (180 out of phase with 3vmref). 52* spread# i invokes spread spectrum functionality on the differential host clocks. mref/mref_b clocks, 66 mhz clocks, and 33 mhz pci clocks. active low. 51 cpu1 50 cpu1# o cpu clock pair. these two clocks are 180 o out of phase with each other. see the table on page 1 of this data sheet for the frequency selections. 48 cpu2 47 cpu2# o cpu clock pair. these two differential clocks are 180 o out of phase with each other. see the table on page 1 of this data sheet for the frequency selections. 45 cpu3 44 cpu3# o cpu clock pair. these two differential clocks are 180 o out of phase with each other. see the table on page 1 of this data sheet for the frequency selections. 42 cpu4 41 cpu4# o cpu clock pair. these two differential clocks are 180 o out of phase with each other. see the table on page 1 of this data sheet for the frequency selections. 39 i_ref this pin is the reference current input for the cpu pairs. this pin takes a fixed precision resistor tied to ground in order to establish the appropriate current. see pg. 9. 35, 34, 31, 30 3v66 (0:3) o 66.67 mhz 3.3 volt outputs. these clocks are differential to the cpu clocks. 28* pwrdwn# i invokes power-down mode. active low. sets all clocks low. 25* 48 m0/sela 26* 48 m1/selb sela and selb inputs are sensed on power-up and then internally latched prior to the pin being used for output of 3v 48 mhz clocks. 23* sel100/133 i cpu frequency select pin. see the table on page 1 of this data sheet for the frequency selections. 21, 20, 18, 17, 15, 14, 12, 11, 9, 8 pci (0:9) o 3.3v 33 mhz pci output clocks. see the table on page 1 of this data sheet for the frequency selections. 6 xout o 14.318 mhz crystal output. 5 xin i 14.318 mhz crystal input. 2 ref1/multsel (0) i 3 ref2/multsel (1) multsel0 and multsel1 inputs are sensed on power-up and then internally latched prior to the pin being used for output of 3v 14.318 mhz clocks. they sel i_ref values, see pg. 9. 56 vddm p power pin recommended 3 vmref and 3vmref_b dedicated use. 53 vssm p ground pin recommended for 3vmref and 3vmref_b dedicated use. 49 vddc p power pin recommended for cpu/cpu# dedicated use. 46 vssc p ground pin recommended for cpu/cpu# dedicated use. 38, 36 vdd p power pin recommended for dedicated core use. 37, 33 vss p ground pin recommended for dedicated core use. 29 vddl p power pins recommended for 3v66 dedicated use. 32 vssl p ground pin recommended for 3v66 dedicated use.
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 3 of 19 advanced information c9850 pin description (cont.) pin no. pin name i/o description 27 vddu p power pin recommended for 48 mhz dedicated use. 24 vssu p ground pin recommended for 48 mhz dedicated use. 22, 16, 10 vddp p power pins recommended for pci dedicated use. 19, 13, 7 vssp p ground pins recommended for pci dedicated use. 4 vddr p power pin recommended for ref clock and xtal dedicated use. 1 vssr p ground pin recommended for ref clock and xtal dedicated use. note: all pin numbers that are followed with an astirik (*) contain internal pull-up resistors. these internal devices are sufficient enough to guarantee a logic 1 will be sensed internally of no external circuitry is connected. power on bi-directional pins power up condition: pins 2, 3, 25, and 26 are power up bi-directional pins and are used for different features in this device (see pin description, page 2). during power-up, these pins are in input mode (see fig 2, below), therefore, they are considered input select pins internal to the ic. after a settling time, the selection data is latch into internal control registers and these pins become toggling clock outputs. - hi-z inputs toggle outputs power supply ramp select data is latched into register then pin becomes clock output signal. vdd rail ref1/multsel0 ref2/multsel1 48m0/sela 48m1/selb fi g . 1
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 4 of 19 advanced information c9850 strapping resistor options for pins with internal pull-ups: the power up bidirectional pins have a large value pull- up each (250k ?) , therefore, a selection ?1? is the default. if the system uses a slow power supply (over 3ms settling time), then it is recommended to use an external pullup (rup) in order to insure a high selection. in this case, the designer may choose one of two configurations, see fig. 2a and fig. 2b. fig. 2a represents an additional pull up resistor 50k ? connected from the pin to the power line, which allows a faster pull to a high level. if a selection ?0? is desired, then a jumper is placed on jp1 to a 5k ? resistor as implemented as shown in fig.2a. please note the selection resistors (rup, and rdn ) are placed before the damping resistor (rd) close to the pin. fig. 2b represent a single resistor 10k ? connected to a 3 way jumper, jp2. when a ?1? selection is desired, a jumper is placed between leads1 and 3. when a ?0? selection is desired, a jumper is placed between leads 1 and 2. load load fig.2a fig.2b vdd vdd rup 50k rd imi c9850 bidirectional jp1 jumper jp2 3 way jumper rsel 10k rd imi c9850 bidirectional rdn 5k maximum ratings 1 maximum input voltage: vss - 0.5v maximum input voltage: vdd + 0.7v storage temperature: -65 c to + 150 c operating temperature: 0 c to +85 c maximum esd protection 2000v maximum power supply: 5.5v 1 note: 1. the voltage on any input or i/o cannot exceed the power pin during power-up. power supply sequencing is not required. this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, vin and vout should be constrained to the range: vss<(vin or vout) high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 5 of 19 advanced information c9850 dc parameters characteristic symbol min typ max units conditions supply voltage vdd3 3.135 3.465 v input high voltage vih3 2.0 vdd +0.3 v note 1 input low voltage vil3 vss ? 0.3 0.8 v note 1 input leakage current iil -5 +5 a 0 < v in < v dd tri-state leakage current ioz - - 10 a input low current (@vin = vss) iil -66 -5 a input high current (@vin = vdd) iih 5 a for pins with internal pull up resistors, note 3 dynamic supply current idd - - 250 ma 475 ? current reference at lout=*iref, cpu=133mhz, msel0 = 0, msel1 = 1 power down current (vdd) idd pd - - 60 ma pwrdwn# pin = low input pin capacitance cin 5 pf except xin and xout crystal pin capacitance cxtal 34 36 38 pf present between both pin 5 and 6 to ground. crystal dc bias voltage v bias 0.3vdd vdd/2 0.7vdd v crystal startup time txs - - 40 s from stable 3.3v power supply. ambient temperature ta 0 70 o cno airflow notes 1. all inputs are specified when using a 3.3v power supply. 2. although internal pull-up resistors have a typical value of 250k, this value may vary between 200k and 500k.
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 6 of 19 advanced information c9850 ac parameters 133 mhz cpu 100 mhz cpu characteristic symbol min max min max units notes cpu clk period - average tperiod 7.5 7.65 10.0 10.2 ns 11 absolute minimum cpu clk period abs/minperiod 7.35 n/a 9.85 n/a ns 11 output current (cpu) ioh 12.9 14.9 12.9 14.9 ma 11 (voltage at given load) (voh) (0.66) (0.76) (0.66) (0.75) (v) vol vss= 0.0 0.05 vss = 0.0 0.05 v 11 vcrossover vcrossover 45% voh 55% voh 45% voh 55% voh v11 host/cpu clk rise time trise 175 700 175 700 ps 11, 12 host/cpu clk fall time tfall 175 700 175 700 ps 11, 12 rise time and fall time matching rise/fall matching 20% 20% 11 overshoot voh + 0.2v voh + 0.2v 11 undershoot -0.2 -0.2 v 11 cycle to cycle jitter tjcc 200 ps 200 ps ps 13 cpu to cpu clock skew tskew 150 150 ps duty cycle tdc 45 55 45 55 % 11 mref, mref_b clk period tperiod 15.0 15.3 20. 20.4 ns 2, 9 mref, mref_b clk high time thigh 5.25 n/a 7.5 n/a ns 5, 10 mref, mref_b clk low time tlow 5.05 n/a 7.3 n/a ns 6, 10 mref, mref_b clk rise time trise 0.4 1.6 0.4 1.6 ns 8 mref, mref_b, clk fall time tfall 0.4 1.6 0.4 1.6 ns 8 mref and mref_b duty cycle tdc 45 55 45 55 % 11 mref & mref_b cycle to cycle jitter tjcc 250 ps 250 ps ps 12 ref clk rise time trise 2.0 2.0 ns 8 ref clk fall time tfall 2.0 2.0 ns 8 ref duty cycle tdc 45 55 45 55 % 11 ref cycle to cycle jitter tjcc 1.0 1.0 ns 12 48m clk rise time trise 2.0 2.0 ns 8 48m clk fall time tfall 2.0 2.0 ns 8 48m duty cycle tdc 45 55 45 55 % 11 48m cycle to cycle jitter tjcc 350 350 ps 12
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 7 of 19 advanced information c9850 ac parameters (cont.) 133 mhz cpu 100 mhz cpu characteristic symbol min max min max units notes 3v66 clk period tperiod 15.0 16.0 15.0 15.2 ns 3v66 clk high time thigh 5.25 n/a 5.25 n/a ns 2, 9 3v66 clk low time tlow 5.05 n/a 5.05 n/a ns 5, 10 3v66 clk rise time trise 0.5 2.0 0.5 2.0 ns 6, 10 3v66 clk fall time tfall 0.5 2.0 0.5 2.0 ns 8 3v66 duty cycle tdc 45 55 45 55 % 11 3v66 to 3v66 clock skew tskew 250 250 ps 3v66 cycle to cycle jitter tjcc 300 ps 300 ps ps 12 pci clk period tperiod 30.0 30.0 ns 8 pci clk high time thigh 12.0 12.0 ns 2, 9 pci clk low time tlow 12.0 12.0 ns 5, 10 pci clk rise time trise 0.5 2.0 0.5 2.0 ns 6, 10 pci clk fall time tfall 0.5 2.0 0.5 2.0 ns 8 pci duty cycle tdc 45 55 45 55 % 11 pci to pci clock skew tskew 500 500 ps pci cycle to cycle jitter tjcc 500 500 ps 12 output enable delay (all outputs) tpzl, tpzh 1.0 10.0 1.0 10.0 ns output disable delay (all outputs) tplz, tpzh 1.0 10.0 1.0 10.0 ns all clock stabilization from power-up tstable 3 3 ns 7 notes: 1. all output drivers have monotonic rise/fall times through the specified vol/voh levels. 2. period, jitter, offset and skew measured on rising edge @ 1.25v for 2.5v clocks and @1.5v for 3.3v clocks. 3. the pci clock is the host clock divided by four at host = 133 mhz. pci clock is the host clock divided by three at host = 100 mhz. 4. 3v66 is internal vco frequency divided by four for host = 133 mhz. 3v66 clock is internal vco frequency divided by three for host = 100 mhz. 5. thigh is measured at 2.0v for 2.5v outputs, 2.4v for 3.3v outputs. 6. tlow is measured at 0.4v for all outputs. 7. the time specified is measured from when vdd achieves its nominal operating level (typical condition vdd = 3.3v) till the frequency output is stable and operating within specification. 8. trise and tfall are measured as a transition through the threshold region vol = 0.4v and voh = 2.0v 9. the average period over any 1 us period of time is greater than the minimum specified period. 10. calculated at minimum edge-rate (1v/ns) to guarantee 45/55% duty-cycle. 11. cpu clock test load is rs=33.2 ohms, rp = 49.9. 12. 20% and 80% 13. measured at 1.25 volts 14. measured at 1.50 volts
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 8 of 19 advanced information c9850 group to group offset limits groups offset measurement loads (lumped) measure point 3v66 to pci 1.5-3.5 ns 3v66 leads 3v66@ 30 pf, pci @ 30 pf 3v66@ 1.5v, pci @ 1.5 v notes: 1. all offsets are to be measured at rising edges. lumped capacitive test loads for single ended outputs clock max load units pci clocks (pclk) 30 pf mref, mref_b 20 pf 3v66 30 pf 48 mhz clock 20 pf ref 20 pf cpu (1:4), (1:4)# rs = 33.2, rp = 49.9 ohm test and measurement setup for differential output signals the following shows lumped test load configurations for the differential host clock outputs. multsel(0:1) = (0, 1) figure 3. lumped test load configuration test nodes rp rs rs rp
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 9 of 19 advanced information c9850 for single ended output signals spectrum spread clocking description spread spectrum is a modulation technique for distributing clock period over a certain bandwidth (called spread bandwidth). this technique allows the distribution of the energy (emi) over a range of frequencies therefore reducing the radiation generated from clocks. as the spread is a percentage of the rested (non-spread) frequency, it is effective at the fundamental and all its harmonics. in this device spread spectrum is enabled through pin 52 (spread#). as the name suggests, spread spectrum is enabled when spread# is low. this pin has a 250k ? internal pull up, therefore, defaults to a high (spread spectrum disabled) unless externally forced to a low. when spread# is forced low, the device will be down spread (fig.5b) mode at ?0.5%, and the center frequency is shifted down from its rested (non-spread) value by -0.25%. (ex.: assuming the center frequency is 100mhz in non-spread mode; when down spread is enabled, the center frequency shifts to 99.75mhz.), see fig.4 below. - - 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc 0.4v 2.0v 1.25v 2.5v 0v 2.5v signals tdc tr tf probe output under test load cap - -
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 10 of 19 advanced information c9850 fig.4 spectrum spreading selection table unspread frequency in mhz down spreading desired f min (mhz) f center (mhz) f max (mhz) spread (%) 100.0 99.5 99.75 100.0 .5 133.3 132.2 132.6 133.3 .5 spread off spread on center frequency, center frequency,
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 11 of 19 advanced information c9850 host swing select functions multsel0 multsel1 board target trace/termz reference rr, iref = vdd/(3*rr) output current voh @z, iref = 2.32ma 0 0 60 ohms rf = 475 1%, iref = 2.32ma ioh = 5*iref 0.7v @ 60 0 0 50 ohms rr = 475 1%, iref = 2.32ma ioh = 5*iref 0.59v @ 50 0 1 60 ohms rr = 475 1%, iref = 2.32ma ioh = 6*iref 0.85v @ 60 0 1 50 ohms rr = 475 1%, iref = 2.32ma ioh = 6*iref 0.71v @ 50 1 0 60 ohms rr = 475 1%, iref = 2.32ma ioh = 4*iref 0.56v @ 60 1 0 50 ohms rr = 475 1%, iref = 2.32ma ioh = 4*iref 0.47v @ 50 1 1 60 ohms rr = 475 1%, iref = 2.32ma ioh = 7*iref 0.99v @ 60 1 1 50 ohms rr = 475 1%, iref = 2.32ma ioh = 7*iref 0.82v @ 50 0 0 30 (dc equiv) rr = 221 1% iref = 5ma ioh = 5*iref 0.75v @ 30 0 0 25 (dc equiv) rr = 221 1% iref = 5ma ioh = 5*iref 0.62v @ 20 0 1 30 (dc equiv) rr = 221 1% iref = 5ma ioh = 6*iref 0.90v @ 30 0 1 25 (dc equiv) rr = 221 1% iref = 5ma ioh = 6*iref 0.75v @ 20 1 0 30 (dc equiv) rr = 221 1% iref = 5ma ioh = 4*iref 0.60v @ 30 1 0 25 (dc equiv) rr = 221 1% iref = 5ma ioh = 4*iref 0.5v @ 20 1 1 30 (dc equiv) rr = 221 1% iref = 5ma ioh = 7*iref 1.05v @ 30 1 1 25 (dc equiv) rr = 221 1% iref = 5ma ioh = 7*iref 0.84v @ 20 note: the entries in boldface are the primary system configurations of interest. the outputs should be optimized for these configurations.
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 12 of 19 advanced information c9850 buffer characteristics current mode cpu clock buffer characteristics the current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. the following parameters are used to specify output buffer characteristics: 1. output impedance of the current mode buffer circuit - ro (see figure 5). 2. minimum and maximum required voltage operation range of the circuit ? vop (see figure 5). 3. series resistance in the buffer circuit ? ros (see figure 5). 4. current accuracy at given configuration into nominal test load for given configuration. figure 5 host clock (hcsl) buffer characteristics characteristic minimum maximum ro 3000 ohms (recommended) n/a ros vout n/a 1.2v iout is selectable depending on implementation. the parameters above apply to all configurations. vout is the voltage at the pin of the device. the various output current configurations are shown in the host swing select functions table. for all configurations, the deviation from the expected output current is +/- 7% as shown in the table current accuracy (page 13). 1.2v 0v iout iout ros ro vdd3 (3.3v +/- 5%) vout = 1.2v max vout
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 13 of 19 advanced information c9850 current accuracy conditions configuration load min max iout vdd = nominal (3.30v) all combinations of m0, m1 and rr shown in host swing select function table nominal test load for given configuration -7% inom + 7% inom iout vdd = 3.30 +/- 5% all combinations of m0, m1 and rr shown in host swing select function table nominal test load for given configuration -12% inom + 12% inom note: inom refers to the expected current based on the configuration of the device. buffer characteristics for 48 mhz and ref characteristic symbol min typ max units conditions pull-up current min ioh min -12 -53 ma voh=vddmin-0.5v (2.64v) pull-up current max ioh max -27 -92 ma voh=vddmin/2 (1.56v) pull-down current min iol min 927mavol=0.4v pull-down current max iol max 26 79 ma vol=vddmin/2 (1.56v) 3.3v output rise edge rate trh 0.5 - 2.0 v/ns 3.3v +/- 5% @ 0.4v ? 2.4 v 3.3v output fall edge rate tfh 0.5 - 2.0 v/ns 3.3v +/- 5% @ 2.4v ? 0.4 v output impedance zo 20 40 60 ? buffer characteristics for pci, 3v66, mref, mref_b characteristic symbol min typ max units conditions pull-up current min ioh min -11 -83 ma voh=vdd-0.5v (2.64v) pull-up current max ioh max -30 -184 ma v oh=vdd/2 (1.56v) pull-down current min iol min 938mavol=0.4v pull-down current max iol max 28 148 ma vol=vdd/2 (1.56v) 3.3v output rise edge rate trh 1/1 - 4/1 v/ns 3.3v +/- 5% @ 0.4v ? 2.4 v 3.3v output fall edge rate tfh 1/1 - 4/1 v/ns 3.3v +/- 5% @ 2.4v ? 0.4 v output impedance zo 12 30 55 ?
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 14 of 19 advanced information c9850 suggested oscillator crystal parameters characteristic symbol min typ max units conditions frequency f o 14.17 14.31818 14.46 mhz tolerance t c - - +/-100 ppm note 1 frequency stability t s - - +/- 100 ppm stability (t a -10 to +60c) note 1 operating mode - - - - parallel resonant, note 1 load capacitance c xtal - 20 - pf the crystal?s rated load. note 1 effective series resistance (esr) r esr - 40 - ohms note 2 note1: for best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifications note 2: larger values may cause this device to exhibit oscillator startup problems to obtain the maximum accuracy, the total circuit loading capacitance should be equal to c xtal . this loading capacitance is the effective capacitance across the crystal pins and includes the clock generating device pin capacitance (c ftg ), any circuit trace capacitance (c pcb ), and any onboard discrete load capacitance (c disc ). the following formula and schematic illustrates the application of the loading specification of a crystal (c xtal )for a design. c l = (c xinpcb + c xinftg + c xindisc ) x (c xoutpcb + c xoutftg + c xoutdisc ) (c xinpcb + c xinftg + c xindisc ) + (c xoutpcb + c xoutftg + c outdisc ) where: c xtal = the load rating of the crystal c xoutftg = the clock generators xin pin effective device internal capacitance to ground c xoutftg = the clock generators xout pin effective device internal capacitance to ground c xinpcb = the effective capacitance to ground of the crystal to device pcb trace c xoutpcb = the effective capacitance to ground of the crystal to device pcb trace c xindisc = any discrete capacitance that is placed between the xin pin and ground c xoutdisc = any discrete capacitance that is placed between the xout pin and ground c xinpcb c xoutpcb c xoutdisc c xindisc c xinftg c xoutftg xin xout clock generator as an example, and using this formula for this datasheet?s device, a design that has no discrete loading capacitors (c disc ) and each of the crystal to device pcb traces has a capacitance (c pcb ) to ground of 4pf (typical value) would calculate as: c l = (4pf + 36pf + 0pf) x (4pf + 36pf + 0pf) = 40 x 40 = 1600 = 20pf (4pf + 36pf + 0pf) + (4pf + 36pf + 0pf) 40 + 40 80 therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design examp le, you should specify a parallel cut crystal that is designed to work into a load of 20pf
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 15 of 19 advanced information c9850 package drawing and dimensions (56 pin tssop)
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 16 of 19 advanced information c9850 package drawing and dimensions (cont.) 56 pin tssop dimensions inches millimeters symbol min nom max min nom max a - - 0.2794 - - 1.10 a1 0.0013 0.0025 0.0038 0.05 0.10 0.15 a2 0.0216 0.0229 0.0241 0.85 0.90 0.95 000 0.00254 0.10 b 0.0043 - 0.0069 0.17 - 0.27 b1 0.0043 0.0051 0.0058 0.17 0.20 0.23 bbb 0.0020 0.08 c 0.0023 - 0.0051 0.09 - 0.20 c1 0.0023 0.0032 0.0041 0.09 0.127 0.16 0 - 8 0 - 8 e 0.0127 bsc 0.50 bsc h 0.0206 8.10 bsc d 0.3531 0.3556 0.3581 13.90 14.00 14.10 e 0.1524 0.1549 0.1575 6.00 6.10 6.20 l 0.0127 0.0152 0.0191 0.50 0.60 0.75 notes: 1. die thickness allowable is 0.279 +/- 0.0127 (0.0110 +/- .005 inches) 2. dimensions & tolerance per asme. y14, 5m-1994. 3. datum plane h located at mold parting line and coincident with lead. where lead exits plastic body at bottom of parting line. 4. datums a-b and d to be determined where centerline between leads exits plastic body at datum plane h. 5. ?d? and ?e? are reference datums and do not include mode flash or protrusions, and are measured at the bottom parting line. mold flash or protrusions shall not exceed 0.15mm on d and 0.25mm on e per side. 6. dimension is the length of terminal for soldering to a substrate. 7. terminal positions are shown for reference only. 8. formed leads shall be planar with respect to one another within 0.076mm at seating plane. 9. the lead width dimension does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm total in excess of the lead width dimension located on the lower radius or the foot. minimum space between protrusions and an adjacent lead to be 0.08mm for 0.50mm pitch. 10. section ?c-c? to be determined at 0.10 to 0.25mm from the lead tip. 11. this part is compliant with jedec specification mo-153, variations db, dc, de ed, ee, and fe.
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 17 of 19 advanced information c9850 package drawing and dimensions (56 pin ssop) 56 pin ssop outline dimensions inches millimeters symbol min nom max min nom max a 0.095 0.102 0.110 2.41 2.59 2.79 a 1 0.008 0.012 0.016 0.20 0.31 0.41 a2 0.088 0.090 0.092 2.24 2.29 2.34 b 0.008 0.010 0.0135 0.203 0.254 0.343 c 0.005 - 0.010 0.127 - 0.254 d .720 .725 .730 18.29 18.42 18.54 e 0.292 0.296 0.299 7.42 7.52 7.59 e 0.025 bsc 0.635 bsc h 0.400 0.406 0.410 10.16 10.31 10.41 a 0.10 0.013 0.016 0.25 0.33 0.41 l 0.024 0.032 0.040 0.61 0.81 1.02 a0o5o8o 0o5o8o x 0.085 0.093 0.100 2.16 2.36 2.54 ordering information part number package type production flow c9850ay 56 pin ssop commercial, 0oc to +70oc c9850at 56 pin tssop commercial, 0oc to +70oc marking: example: cypress c9850 date code, lot # c9850ay package y = ssop t = tssop revision device number a b e a a 1 a 2 d e h l c
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 18 of 19 advanced information c9850 notice cypress semiconductor corporation reserves the right to make changes to its products in order to improve design, performance or reliability. cypress semiconductor corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by cypress semiconductor corporation for the use of its products in the life supporting and medical applications
high performance pentium ? ? ? ? iii clock generator cypress semiconductor corporation http://www.cypress.com document#: 38-07067 rev. *a 12/22/2002 page 19 of 19 advanced information c9850 document title: c9850 high performance pentium? iii clock generator document number: 38-07067 rev. ecn no. issue date orig. of change description of change ** 107122 06/11/01 ika convert from imi to cypress *a 122752 12/22/02 rbi add power up requirements to maximum ratings information

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