View SI3056_922899.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.02 2/04 copyright ? 2004 by silicon laboratories SI3056-ds102 SI3056 si3018/19/10 g lobal s erial i nterface d irect a ccess a rrangement features complete daa includ es the following: applications description the SI3056 is an integrated direct access arrangement (daa) with a programmable line interface to meet global telephone line requirements. available in two 16-pin sm all outline packages, it eliminates the need for an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. the SI3056 dramatically reduces the number of discrete components and cost requir ed to achieve compliance with global regulatory requirements. the SI3056 interfaces directly to standard modem dsps. functional block diagram programmable line interface ac termination dc termination ring detect threshold ringer impedance 80 db dynamic range tx/rx paths integrated codec and 2- to 4-wire hybrid integrated ring detector type i and ii caller id support line voltage monitor loop current monitor polarity reversal detection programmable digital gain clock generation pulse dialing support overload detection low-profile 16-pin soic packages 3.3 v power supply direct interface to dsps serial interface control for up to eight devices >5000 v isolation proprietary isolation technology parallel handset detection +3.2 dbm tx/rx level mode (600 ? ) programmable digital hybrid for near- end echo reduction v.92 modems voice mail systems multi-function printers set-top boxes fax machines internet appliances personal digital assistants isolation interface hybrid and dc termination ring detect off-hook isolation interface digital interface control interface SI3056 si3018/19/10 qe2 qe qb rng2 rng1 dct3 dct2 vreg2 vreg dct sc ib rx mclk sclk fsync sdi sdo fc/rgdt rgdt/fsd/m1 ofhk m0 reset aout/int us patent # 5,870,046 us patent # 6,061,009 other patents pending ordering information see page 95. pin assignments SI3056 si3018/19/10 fc/rgdt 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 mclk fsync sclk v d sdo sdi reset ofhk rgdt/fsd/m1 m0 v a gnd aout/int c1a c2a 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 dct2 ignd dct3 qb qe2 sc vreg2 rng2 qe dct rx ib c1b c2b vreg rng1
SI3056 si3018/19/10 2 rev. 1.02
rev. 1.02 3 SI3056 si3018/19/10 t able of c ontents section page electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 typical application schema tic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 aout pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 upgrading from the si3034 /35/44 to SI3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 line-side device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 isolation barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 transmit/receive full scale level (si3019 line-side on ly) . . . . . . . . . . . . . . . . . . . . . . 24 parallel handset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 line voltage/loop current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 dc termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ac termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 transhybrid balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 ring detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 ring validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 ringer impedance and thre shold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 pulse dialing and spark quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 billing tone detection and receive overl oad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 billing tone filter (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 on-hook line monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 caller id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 multiple device support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 in-circuit testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 appendix?ul1950 3rd edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 pin descriptions: SI3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 pin descriptions: si3018/19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3
SI3056 si3018/19/10 4 rev. 1.02 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 evaluation board ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 product selection and identificat ion guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 part designators (partial list) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 soic package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 silicon laboratories ? SI3056 support document ation . . . . . . . . . . . . . . . . . . . . . . . . . . 101 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
SI3056 si3018/19/10 rev. 1.02 5 electrical specifications table 1. recommended operating conditions parameter 1 symbol test condition min 2 typ max 2 unit ambient temperature t a k-grade 0 25 70 c SI3056 supply voltage, digital 3 v d 3.0 3.3 3.6 v notes: 1. the SI3056 specifications are guarantee d when the typical application circuit (including component tolerance) and the SI3056 and any si3018 or si3019 are used. see figure 1 6 on page 17 for typical application schematic. 2. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated. 3. 3.3 v applies to both the digital and serial interface and the digital signals rgdt/fsd, ofhk, reset, m0, and m.
SI3056 si3018/19/10 6 rev. 1.02 table 2. loop characteristics (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, see figure 1) parameter symbol test condition min typ max unit dc termination voltage v tr i l =20ma, mini=11, ilim = 0, dcv = 00, dcr = 0 ??6.0 v dc termination voltage v tr i l = 120 ma, mini = 11, ilim = 0, dcv = 00, dcr = 0 9??v dc termination voltage v tr i l =20ma, mini=00, ilim = 0, dcv = 11, dcr = 0 ??7.5 v dc termination voltage v tr i l = 120 ma, mini = 00, ilim = 0, dcv = 11, dcr = 0 9??v dc termination voltage v tr i l =20ma, mini=00, ilim = 1, dcv = 11, dcr = 0 ??7.5 v dc termination voltage v tr i l =60ma, mini=00, ilim = 1, dcv = 11, dcr = 0 40 ? ? v dc termination voltage v tr i l =50ma, mini=00, ilim = 1, dcv = 11, dcr = 0 ??40 v on hook leakage current i lk v tr =?48v ? ? 3 a operating loop current i lp mini = 00, ilim = 0 10 ? 120 ma operating loop current i lp mini = 00, ilim = 1 10 ? 60 ma dc ring current dc current flowing through ring detection circuitry ?1.5 3 a ring detect voltage* v rd rt = 0 13.5 15 16.5 v rms ring detect voltage* v rd rt = 1 19.35 21.5 23.65 v rms ring frequency f r 13 ? 68 hz ringer equivalence number ren ? ? 0.2 *note: the ring signal is guaranteed to not be detected below the minimum. the ring signal is guaranteed to be detected above the maximum.
SI3056 si3018/19/10 rev. 1.02 7 figure 1. test circuit for loop characteristics table 3. dc characteristics, v d =3.3 v (v d = 3.0 to 3.6 v, t a = 0 to 70 c) parameter symbol test condition min typ max unit high level input voltage v ih 2.4 ? ? v low level input voltage v il ??0.8v high level output voltage v oh i o =?2 ma 2.4 ? ? v low level output voltage v ol i o = 2 ma ? ? 0.35 v input leakage current i l ?10 ? 10 a power supply cu rrent, digital 1 i d v d pin ? 15 ? ma total supply current, sleep mode 1 i d pdn = 1, pdl = 0 ? 9 ? ma total supply current, deep sleep 1,2 i d pdn = 1, pdl = 1 ? 1 ? ma notes: 1. all inputs at 0.4 or v d ? 0.4 (cmos levels). all inputs are held st atic except clock and all outputs unloaded (static i out = 0ma). 2. rgdt is not functional in this state. tip ring + ? v tr 600 ? 10 f i l si3018
SI3056 si3018/19/10 8 rev. 1.02 table 4. ac characteristics (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, see figure 16 on page 17) parameter symbol test condition min typ max unit sample rate 1 fs fs = f pll2 /5120 7.2 ? 16 khz pll output clock frequency 1 f pll1 f pll1 =(f mclk x m)/n ? 98.304 ? mhz transmit frequency response low ?3 dbfs corner ? 0 ? hz receive frequency response low ?3 dbfs corner, filt = 0 ?5?hz receive frequency response low ?3 dbfs corner, filt = 1 9 ?200?hz transmit full scale level 2 v fs full = 0 (0 dbm) ? 1.1 ? v peak full = 1 9 (3.2 dbm) 1.58 v peak receive full scale level 2,3 v fs full = 0 (0 dbm) 1.1 v peak full = 1 9 (3.2 dbm) ? 1.58 ? v peak dynamic range 4,5 dr ilim = 0, dcv = 11, dcr = 0, i l = 120 ma, mini = 00 ?80?db dynamic range 4,5 dr ilim = 0, dcv = 00, dcr = 0, i l =20ma, mini=11 ?80?db dynamic range 4,5 dr ilim = 1, dcv = 11, dcr = 0, i l =60ma, mini=00 ?80?db transmit total harmonic distortion 6,7 thd ilim = 0, dcv = 11, dcr = 0, i l = 120 ma, mini = 00 ??72?db transmit total harmonic distortion 6,7 thd ilim = 0, dcv = 00, dcr = 0, i l =20ma, mini=11 ??78?db receive total harmonic distortion 6,7 thd ilim = 0, dcv = 00, dcr = 0, i l =20ma, mini=11 ??78?db receive total harmonic distortion 6,7 thd ilim = 1, dcv = 11, dcr = 0, i l =60ma, mini=00 ??78?db notes: 1. see figure 25 on page 35. 2. measured at tip and ring with 600 ? termination at 1 khz, as shown in figure 1. 3. receive full scale level produces ?0.9 dbfs at sdo. 4. dr = 20 x log |v in | + 20 x log (rms signal/rms noise). measurement is 300 to 3400 hz. applies to both transmit and receive paths. v in = 1 khz, ?3 dbfs, fs = 10300 hz. 5. when using the si3010 line-side, the typical dr values will be approximately 10 db lower. 6. thd = 20 x log (rms distortion/rms signal). vin = 1 khz, ?3 dbfs, fs = 10300 hz. 7. when using the si3010 line-side, the typical thd values will be approximately 10 db higher. 8. dr cid = 20 x log (rms v cid /rms v in ) + 20 x log(rms v in /rms noise). v cid is the 6 v full scale level for the typical application circuit in figure 16. with the enhanced cid circuit, the v cid full scale level is 1.5 v peak, and dr cid increases to 62 db. 9. available on the si3019 line-side device only.
SI3056 si3018/19/10 rev. 1.02 9 dynamic range (caller id mode) 8,5 dr cid vin = 1 khz, ?13 dbfs ? 50 ? db caller id full scale level 8 v cid ?6?v peak aout low level current ? ? 10 ma aout high level current ? ? 10 ma table 4. ac characteristics (continued) (v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, see figure 16 on page 17) parameter symbol test condition min typ max unit notes: 1. see figure 25 on page 35. 2. measured at tip and ring with 600 ? termination at 1 khz, as shown in figure 1. 3. receive full scale level produces ?0.9 dbfs at sdo. 4. dr = 20 x log |v in | + 20 x log (rms signal/rms noise). measurement is 300 to 3400 hz. applies to both transmit and receive paths. v in = 1 khz, ?3 dbfs, fs = 10300 hz. 5. when using the si3010 line-side, the typical dr values will be approximately 10 db lower. 6. thd = 20 x log (rms distortion/rms signal). vin = 1 khz, ?3 dbfs, fs = 10300 hz. 7. when using the si3010 line-side, the typical thd values will be approximately 10 db higher. 8. dr cid = 20 x log (rms v cid /rms v in ) + 20 x log(rms v in /rms noise). v cid is the 6 v full scale level for the typical application circuit in figure 16. with the enhanced cid circuit, the v cid full scale level is 1.5 v peak, and dr cid increases to 62 db. 9. available on the si3019 line-side device only.
SI3056 si3018/19/10 10 rev. 1.02 figure 2. general inputs timing diagram table 5. absolute maximum ratings parameter symbol value unit dc supply voltage v d ?0.5 to 3.6 v input current, SI3056 digital input pins i in 10 ma digital input voltage v ind ?0.3 to (v d + 0.3) v operating temperature range t a ?40 to 100 c storage temperature range t stg ?65 to 150 c note: permanent device damage can occur if the above absolut e maximum ratings are exceeded. restrict functional operation to the conditions as specified in the operational se ctions of this data sheet. exposure to absolute maximum rating conditions for extended periods might affect device reliability. table 6. switching characteristics?general inputs (v d = 3.0 to 3.6 v, t a = 70 c for k-grade, c l = 20 pf) parameter 1 symbol min typ max unit cycle time, mclk t mc 16.67 ? 1000 ns mclk duty cycle t dty 40 50 60 % rise time, mclk t r ?? 5 ns fall time, mclk t f ?? 5 ns mclk before reset t mr 10 ? ? cycles reset pulse width 2 t rl 250 ? ? ns m0, m before reset 3 t mxr 20 ? ? ns notes: 1. all timing (except rise and fall time) is referenced to the 50% level of the waveform. input test levels are v ih = v d ? 0.4 v, v il = 0.4 v. rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. the minimum reset pulse width is the greater of 250 ns or 10 mclk cycle times. 3. m0 and m are typically connected to v d or gnd and should not be changed during normal operation. mclk m0, m1 t r reset t mc t mr t f t mxr v ih v il t rl
SI3056 si3018/19/10 rev. 1.02 11 figure 3. serial interface timing diagram (dce = 0) table 7. switching characteristics?serial interface (dce = 0) (v d = 3.0 to 3.6 v, t a = 70 c for k-grade, c l =20pf) parameter symbol min typ max unit cycle time, sclk t c 244 1/256 fs ? ns sclk duty cycle t dty ?50 ? % delay time, sclk to fsync t d1 ?? 20ns delay time, sclk to sdo valid t d2 ?? 20ns delay time, sclk to fsync t d3 ?? 20ns setup time, sdi before sclk t su 25 ? ? ns hold time, sdi after sclk t h 20 ? ? ns setup time, fc before sclk t sfc 40 ? ? ns hold time, fc after sclk t hfc 40 ? ? ns note: all timing is referenced to the 50% level of the waveform. input test levels are v ih =v d ? 0.4 v, v il =0.4v. d15 sclk t c t d1 v oh v ol fsync (mode 0) fsync (mode 1) t d3 t d3 16-bit sdo 16-bit sdi d14 d1 d0 d0 d1 d14 d15 t su t h t sfc t hfc fc t d2 d0
SI3056 si3018/19/10 12 rev. 1.02 figure 4. serial interface timing diagram (dce = 1, fsd = 0) table 8. switching characteristics?serial interface (dce = 1, fsd = 0) (v a = charge pump, v d = 3.0 to 3.6 v, t a = 0 to 70 c for k-grade, c l = 20 pf) parameter 1,2 symbol min typ max unit cycle time, sclk t c 244 1/256 fs ? ns sclk duty cycle t dty ?50 ?% delay time, sclk to fsync t d1 ?? 20ns delay time, sclk to fsync t d2 ?? 20ns delay time, sclk to sdo valid t d3 ?? 20ns delay time, sclk to sdo hi-z t d4 ?? 20ns delay time, sclk to fsd t d5 ?? 20ns delay time, sclk to fsd t d6 ?? 20ns setup time, sdo before sclk t su 25 ? ? ns hold time, sdo after sclk t h 20 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih =v d ? 0.4 v, v il =0.4v. 2. see "multiple device support" on page 37 for functional details. sclk fsync (mode 1) t c t d1 t d2 t d2 fsync (mode 0) t d2 t d6 t d2 sdo (master) fsd (mode 0) sdo (slave 1) t d3 d15 d14 d13 d0 t su t h t d4 t d3 d15 t d5 sdi d15 d0 d14 t h t su t d5 fsd (mode 1) 16 sclks 16 sclks d13
SI3056 si3018/19/10 rev. 1.02 13 figure 5. serial interface timing diagram (dce = 1, fsd = 1) table 9. switching characteristics?serial interface (dce = 1, fsd = 1) (v d = 3.0 to 3.6 v, t a = 70 c for k-grade, c l =20pf) parameter 1, 2 symbol min typ max unit cycle time, sclk t c 244 1/256 fs ? ns sclk duty cycle t dty ?50 ?% delay time, sclk to fsync t d1 ?? 20ns delay time, sclk to fsync t d2 ?? 20ns delay time, sclk to sdo valid t d3 ?? 20ns delay time, sclk to sdo hi-z t d4 ?? 20ns delay time, sclk to fsd t d5 ?? 20ns setup time, sdo before sclk t su 25 ? ? ns hold time, sdo after sclk t h 20 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform. input test levels are v ih =v d ? 0.4 v, v il =0.4v. 2. see "multiple device support" on page 37 for functional details. d15 d1 d0 sclk fsync (mode 1) sdo (master) fsd sdi t c sdo (slave 1) t d1 d14 t d2 t d3 d15 d14 d13 d0 t su t h t d4 t d3 d15 t d5 t h t su
SI3056 si3018/19/10 14 rev. 1.02 table 10. digital fir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, sample rate = 8 khz, t a = 70 c for k-grade) parameter symbol min typ max unit passband (0.1 db) f (0.1 db) 0?3.3khz passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.1 ? 0.1 db stopband ? 4.4 ? khz stopband attenuation ?74 ? ? db group delay t gd ? 12/fs ? s note: typical fir filter characteristics for fs = 8000 hz are shown in figures 6, 7, 8, and 9. table 11. digital iir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, sample rate = 8 khz, t a = 70 c for k-grade) parameter symbol min typ max unit passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.2 ? 0.2 db stopband ? 4.4 ? khz stopband attenuation ?40 ? ? db group delay t gd ? 1.6/fs ? s note: typical iir filter characteristics for fs = 8000 hz are shown in figures 10, 11, 12, and 13. figures 14 and 15 show group delay versus input frequency.
SI3056 si3018/19/10 rev. 1.02 15 figure 6. fir receive filter response figure 7. fir receive filter passband ripple figure 8. fir transmit filter response figure 9. fir transmit filter passband ripple for figures 6?9, all filter plots apply to a sample rate of fs = 8 khz.
SI3056 si3018/19/10 16 rev. 1.02 figure 10. iir receive filter response figure 11. iir receive filter passband ripple figure 12. iir transmit filter response figure 13. iir transmit filter passband ripple figure 14. iir receive group delay figure 15. iir transmit group delay
SI3056 si3018/19/10 rev. 1.02 17 typical application schematic vd vd rgdtb m0 ofhkb ring mclk fc sdi aout resetb fsyncb sclk sdo tip decoupling cap for u1 va no ground plane in daa section decoupling cap for u1 vd q3 r15 c1 d1 r11 rv1 r3 u2 si3018/19 qe 1 dct 2 rx 3 ib 4 c1b 5 c2b 6 vreg 7 rng1 8 dct2 16 ignd 15 dct3 14 qb 13 qe2 12 sc 11 vreg2 10 rng2 9 r13 fb1 c2 fb2 r52 c9 c51 + c4 q4 r9 r12 r6 q1 c6 d2 r5 c50 r16 r10 q5 q2 u1 SI3056 mclk 1 fsync 2 sclk 3 vd 4 sdo 5 sdi 6 fc/rgdt 7 reset 8 aout/int 11 c2a 9 c1a 10 gnd 12 va 13 m0 14 rgdt/fsd/m1 15 ofhk 16 z1 c7 r8 r2 r4 c3 r53 c10 c8 r7 r1 r51 c5 figure 16. typical application circuit for the SI3056 and si3018/19/10 (refer to an67 for recommended layout guidelines)
SI3056 si3018/19/10 18 rev. 1.02 bill of materials component(s) value supplier(s) c1, c2 33 pf, y2, x7r, 20% panasonic, murata, vishay c3 1 10 nf, 250 v, x7r, 20% venkel, smec c4 1.0 f, 50 v, elec/tant, 20% panasonic c5, c6, c50, c51 0.1 f, 16 v, x7r, 20% venkel, smec c7 2.7 nf, 50 v, x7r, 20% venkel, smec c8, c9 680 pf, y2, x7r, 10% panasonic, murata, vishay c10 0.01 f, 16 v, x7r, 20% venkel, smec c30, c31 3 not installed, 120 pf, 250 v, x7r, 10% venkel, smec d1, d2 2 dual diode, 225 ma, 300 v, (cmpd2004s) central semiconductor fb1, fb2 ferrite bead, blm21ag601sn1 murata q1, q3 npn, 300 v, mmbta42 onsemi, fairchild q2 pnp, 300 v, mmbta92 onsemi, fairchild q4, q5 npn, 80 v, 330 mw, mmbta06 onsemi, fairchild rv1 sidactor, 275 v, 100 a teccor, protek, st micro r1 1.07 k ? , 1/2 w, 1% venkel, smec, panasonic r2 150 ? , 1/16 w, 5% venkel, smec, panasonic r3 3.65 k ? , 1/2 w, 1% venkel, smec, panasonic r4 2.49 k ? , 1/2 w, 1% venkel, smec, panasonic r5, r6 100 k ? , 1/16 w, 5% venkel, smec, panasonic r7, r8 3 20 m ? , 1/16 w, 5% venkel, smec, panasonic r9 1 m ? , 1/16 w, 1% venkel, smec, panasonic r10 536 ? , 1/4 w, 1% venkel, smec, panasonic r11 73.2 ? , 1/2 w, 1% venkel, smec, panasonic r12, r13 4 0 ? , 1/16 w venkel, smec, panasonic r15, r16 5 0 ? , 1/16 w venkel, smec, panasonic r30, r32 3 not installed, 15 m ? , 1/8 w, 5% venkel, smec, panasonic r31, r33 3 not installed, 5.1 m ? , 1/8 w, 5% venkel, smec, panasonic r51, r52 4.7 k ? , 1/16 w, 5% venkel, smec, panasonic u1 SI3056 silicon labs u2 si3018/19/10 silicon labs z1 zener diode, 43 v, 1/2 w general semi, onsemi, diodes inc. notes: 1. value for c3 above is recommended for use with the si3018. in voice applications, a c3 value of 3.9 nf (250 v, x7r, 20%) is recommended to improve return loss performance. 2. several diode bridge configurations are acceptable. parts such as a single hd04, a single df-04s or four 1n4004 diodes may be used (suppliers include general semiconductor, diodes inc., etc.). 3. c30?31 and r30?r33 can be substituted for r7-8 to implement the enhanced caller id circuit. 4. 56 ? , 1/16 w, 1% resistors may be substituted for r12?r13 (0 ? ) to decrease emissions. 5. murata blm21ag601sn1 may be substituted for r15?r16 (0 ? ) to decrease emissions.
SI3056 si3018/19/10 rev. 1.02 19 aout pwm output figure 17 illustrates an optional circui t to support the pulse width modulati on (pwm) output capability of the SI3056 for call progress monitoring purposes. set the pwme bit (register 1, bit 3) to enable this mode. figure 17. aout pwm circuit for call progress registers 20 and 21 allow the receive and transmit paths to be attenuated linearly. when these registers are set to all 1s, the receive and transmit paths are muted. these registers affect the call progress output only and do not affect transmit and receive operations on the telephone line. the pwmm[1:0] bits (register 1, bits 5:4) select one of the three different pwm output modes for the aout signal, including a delta-sigma data stream, a conventional 32 kh z return to zero pwm output, and balanced 32 khz pwm output. +5 va ls1 speaker q6 mosfet n gsd r41 15 k ? c41 1000 pf aout table 12. component values?aout pwm component value supplier ls1 brt1209pf-06 intervox q6 fdv301n fairchild c41 1 nf, 16 v, x7r venkel, smec r41 15 k ?, 1/16 w, 5% venkel, smec, panasonic
SI3056 si3018/19/10 20 rev. 1.02 functional description the SI3056 is an integrated direct access arrangement (daa) that provides a programmable line interface to meet global telephone line interface requirements. the SI3056 implements s ilicon laboratories ? proprietary isolation technology and offers the highest level of integration by replacing an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid with two 16-pin packages (soic or tssop). the SI3056 daa is software programmable to meet global requirements and is compliant with fcc, tbr21, jate, and other country-spec ific ptt specifications as shown in table 15 on page 25. in addition, the SI3056 meets the most stringent worldwide requirements for out-of-band energy, emissions, immunity, high-voltage surges, and safety, including fcc part 15 and 68, en55022, en55024, and many other standards. upgrading from the si3034/35/44 to SI3056 the SI3056 offers silicon laboratories ? customers currently using si3034/35/44 standard serial interface daa chipsets with an upgrade path for use in new designs. the SI3056 digital interface is similar to the si3034/35/44 daas , thus the SI3056 retains the ability to connect to many widely available dsps. this also allows customers to leverage software developed for existing si3034/35/44 designs. more importantly, the SI3056 also offers a number of new features not provided in the si3034/35/44 daas. an overview of the feature differences between the si3044 and the SI3056 is presented in table 13. finally, the globally-compliant SI3056 can be implemented with roughly half the external components required in the already highly integrated si3034/35/44 daa application circuits. the following items have changed in the SI3056 as compared to the si3034/35/44 daas: the pinout, the app lication circuit, and the bill of materials. the SI3056 is not pin compatible with si3034/35/44 daa chipsets. new features have been added to the SI3056 including more ac terminations, a programmable hybrid, finer gain/attenuation step resolution, finer resolution loop current mon itoring capability, ring validation, more hw interrupts, a 200 hz low frequency filter pole. (see the appropriate functional descriptions.) the secondary communication data format (see "digital interface" on page 36). the low-power sleep mode, and system requirements to support wake-on-ring. (see "power management" on page 37.) line-side device support three different line-side devices can be used with the SI3056 system-side device: globally-compliant line-side device?targets global daa requirements. use the si3018 global line-side device for this configuration. this line-side device supports both fcc-compliant countries and non- fcc-compliant countries. globally-compliant, enhanced features line-side device?targets embedded and voice applications with global daa requirements. use the si3019 line- side device for this configuration. the si3019 contains all the features available on the si3018, plus the following additional features/enhancements: sixteen selectable ac terminations to increase return loss and trans-hybrid loss performance. higher transmit and receive level mode. selectable 200 hz low frequency pole. ? 16 to 13.5 db digital gain/attenuation adjustment in 0.1 db increments for the transmit and receive paths. programmable line current/voltage threshold interrupt. globally-compliant, low-speed only line-side device?targets embedded 2400 bps soft modem applications. use the si3010 line-side device for this configuration. the si3010 contains all the features available on the si3018, except the transmit and receive paths are optimized and tested only for modem connect rates up to 2400 bps.
SI3056 si3018/19/10 rev. 1.02 21 table 13. new SI3056 features chipset si3044 SI3056 system-side part # si3021 line-side part # si3015 si3010 si3018 si3019 global daa yesyesyesyes digital interface ssi ssi ssi ssi power supply 3.3v or 5v 3.3v 3.3v 3.3v max modem connect rate 56 kbps 2400 bps 56 kbps 56 kbps data bus width 16-bit 16-bit 16-bit 16-bit control register addressing 6-bit 8-bit 8-bit 8-bit max sampling frequency 11.025khz 16khz 16khz 16khz ac terminations 24416 programmable gain 3 db steps 3 db steps 3 db steps 0.1 db steps loop current monitoring 3 ma/bit 1.1 ma/bit 1.1 ma/bit 1.1 ma/bit line voltage monitoring 2.75 v per bit 1 v per bit 1 v per bit 1 v per bit polarity reversal detection yes (sw polling) yes (hw interrupt) yes (hw interrupt) yes (hw interrupt) line i/v threshold detection no no no yes ring qualification no yes yes yes wake-on-ring support yes yes (mclk active) yes (mclk active) yes (mclk active) hw interrupts ring detect only 7 hw interrupts 7 hw interrupts 8 hw interrupts integrated fixed analog hybrid yesyesyesyes programmable digital hybrid no yes yes yes max transmit/receive level into 600 ? load +3.2 dbm 0 dbm 0 dbm +3.2 dbm
SI3056 si3018/19/10 22 rev. 1.02 table 14. country specific register settings register 16 31 16 16 26 26 26 30 2 16 3 country ohs ohs2 rz rt ilim dcv[1:0] mini[1:0] acim[3:0] act act2 argentina 0 0 0 0 0 11 00 0000 0 0 australia 1 0 0 0 0 00 11 0011 0 1 austria 0 1 0 0 1 11 00 0011 0 1 bahrain 0 0 0 0 1 11 00 0010 0 1 belgium 0 1 0 0 1 11 00 0010 0 1 brazil 0 0 0 0 0 11 00 0000 0 0 bulgaria 0 0 0 0 1 11 00 0011 0 1 canada 0 0 0 0 0 11 00 0000 0 0 chile 0 0 0 0 0 11 00 0000 0 0 china 0 0 0 0 0 00 11 1111 1 0 colombia 0 0 0 0 0 11 00 0000 0 0 croatia 0 0 0 0 1 11 00 0010 0 1 cyprus 0 0 0 0 1 11 00 0010 0 1 czech republic 0 0 0 0 1 11 00 0010 0 1 denmark 0 1 0 0 1 11 00 0010 0 1 ecuador 0 0 0 0 0 11 00 0000 0 0 egypt 0 0 0 0 0 00 11 0000 0 0 el salvador 0 0 0 0 0 11 00 0000 0 0 finland 0 1 0 0 1 11 00 0010 0 1 france 0 1 0 0 1 11 00 0010 0 1 germany 0 1 0 0 1 11 00 0011 0 1 greece 0 1 0 0 1 11 00 0010 0 1 guam 0 0 0 0 0 11 00 0000 0 0 hong kong 0 0 0 0 0 11 00 0000 0 0 hungary 0 0 0 0 0 11 00 0000 0 0 iceland 0 1 0 0 1 11 00 0010 0 1 india 0 0 0 0 0 11 00 0100 0 1 indonesia 0 0 0 0 0 11 00 0000 0 0 ireland 0 1 0 0 1 11 00 0010 0 1 israel 0 0 0 0 1 11 00 0010 0 1 italy 0 1 0 0 1 11 00 0010 0 1 japan 0 0 0 0 0 00 11 0000 0 0 jordan 0 0 0 0 0 00 11 0000 0 0 kazakhstan 0 0 0 0 0 00 11 0000 0 0 kuwait 0 0 0 0 0 11 00 0000 0 0 latvia 0 0 0 0 1 11 00 0010 0 1 lebanon 0 0 0 0 1 11 00 0010 0 1 luxembourg 0 1 0 0 1 11 00 0010 0 1 note: 1. supported for loop current 20 ma. 2. available with si3019 line-side only. 3. available with si3018 line-side only.
SI3056 si3018/19/10 rev. 1.02 23 macao 0 0 0 0 0 11 00 0000 0 0 malaysia 1 0 0 0 0 0 00 11 0000 0 0 malta 0 0 0 0 1 11 00 0010 0 1 mexico 0 0 0 0 0 11 00 0000 0 0 morocco 0 0 0 0 1 11 00 0010 0 1 netherlands 0 1 0 0 1 11 00 0010 0 1 new zealand 0 0 0 0 0 11 00 0100 1 1 nigeria 0 0 0 0 1 11 00 0010 0 1 norway 0 1 0 0 1 11 00 0010 0 1 oman 0 0 0 0 0 00 11 0000 0 0 pakistan 0 0 0 0 0 00 11 0000 0 0 peru 0 0 0 0 0 11 00 0000 0 0 philippines 0 0 0 0 0 00 11 0000 0 0 poland 0 0 1 1 0 11 00 0000 0 0 portugal 0 1 0 0 1 11 00 0010 0 1 romania 0 0 0 0 0 11 00 0000 0 0 russia 0 0 0 0 0 00 11 0000 0 0 saudi arabia 0 0 0 0 0 11 00 0000 0 0 singapore 0 0 0 0 0 11 00 0000 0 0 slovakia 0 0 0 0 1 11 00 0010 0 1 slovenia 0 0 0 0 1 11 00 0010 0 1 south africa 1 0 1 0 0 11 00 0011 0 1 south korea 0 0 0 0 0 11 00 0000 0 0 spain 0 1 0 0 1 11 00 0010 0 1 sweden 0 1 0 0 1 11 00 0010 0 1 switzerland 0 1 0 0 1 11 00 0010 0 1 syria 0 0 0 0 0 00 11 0000 0 0 taiwan 0 0 0 0 0 00 11 0000 0 0 tbr21 0 0 0 0 1 11 00 0010 0 1 thailand 0 0 0 0 0 00 11 0000 0 0 uae 0 0 0 0 0 11 00 0000 0 0 united kingdom 0 1 0 0 1 11 00 0101 0 1 usa 0 0 0 0 0 11 00 0000 0 0 yemen 0 0 0 0 0 11 00 0000 0 0 table 14. country specific register settings (continued) register 16 31 16 16 26 26 26 30 2 16 3 country ohs ohs2 rz rt ilim dcv[1:0] mini[1:0] acim[3:0] act act2 note: 1. supported for loop current 20 ma. 2. available with si3019 line-side only. 3. available with si3018 line-side only.
SI3056 si3018/19/10 24 rev. 1.02 power supplies the SI3056 system-side device operates from a 3.0? 3.6 v power supply. the SI3056 input pins are 5 v tolerant. the SI3056 output pins only drive 3.3 v. the line-side device derives its power from two sources: the SI3056 and the telephone line. the SI3056 supplies power over the patented isolation link between the two devices, allowing the line-side device to communicate with the SI3056 while on-hook and perform other on- hook functions such as line voltage monitoring. when off-hook, the line-side device also derives power from the line current supplied from the telephone line. this feature is exclusive to daas from silicon laboratories ? and allows the most cost-effective implementation for a daa while still maintaining r obust performance over all line conditions. initialization when the SI3056 is power ed up, assert the reset pin. when the reset pin is deasserted, the registers have default values. this reset condition guarantees the line- side device is powered do wn without the possibility of loading the line (i.e., off-hook ). an example initialization procedure is outlined in the following list: 1. program the pll with registers 8 and 9 (n[7:0], m[7:0]) to the appropriate divider ratios for the supplied mclk frequency and the sample rate in register 7 (src), as defined in "clock generation" on page 34. 2. wait 1 ms until the pll is locked. 3. write a 00h into register 6 to power up the line-side device. 4. set the required line interface parameters (i.e., dcv[1:0], mini[1:0], ilim, dcr, act and act2 or acim[3:0], ohs, rt, rz, atx[2:0] or tga2 and txg2) as defined by ?country specific register settings? shown in table 14. when this procedure is complete, the SI3056 is ready for ring detection and off-hook. isolation barrier the SI3056 achieves an isolation barrier through low- cost, high-voltage capacitors in conjunction with silicon laboratories ? proprietary signal processing techniques. these techniques eliminat e signal degradation from capacitor mismatches, common mode interference, or noise coupling. as shown in figure 16 on page 17, the c1, c2, c8, and c9 capacitors isolate the SI3056 (system-side) from the line-side device. transmit, receive, control, ring detect, and caller id data are passed across this barrier. y2 class capacitors can be used to achieve surge performance of 5 kv or greater. the capacitive communications link is disabled by default. to enable it, the pdl bit (register 6, bit 4) must be cleared. no communication between the system- side and line-side can occur until this bit is cleared. the clock generator must be programmed to an acceptable sample rate before clearing the pdl bit. transmit/receive full scale level (si3019 line-side only) the SI3056 supports programmable maximum transmit and receive levels. to esta blish the full scale tx/rx level set the full bit (register 31, bit 7). with full = 1, the full scale signal level increases to support applications that require higher signal levels. with the full bit set, the daa can transmit and receive +3.2 dbm into a 600 ? load (or 1 dbv into all reference impedances). the default full scale value is 0 dbm (full = 0). parallel handset detection the SI3056 can detect a parallel handset going off- hook. when the SI3056 is off-hook, the loop current can be monitored with the lcs bits. a significant drop in loop current signals that a parallel handset is going off- hook. if a parallel handset causes the lcs bits to read all 0s, the drop-out detect (dod) bit can be checked to verify a valid line exists. the lvs bits can be read to determine the line voltage when on-hook and off-hook. significant drops in line voltage can signal a parallel handset. for the SI3056 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to support two off-hook daas on the same line. improved parallel handset operation can be achieved by changing the dc impedance from 50 to 800 ? and reducing the dct pin voltage with the dvc[1:0] bits. line voltage/loop current sensing the SI3056 can measure loop current and line voltage with the si3010, si3018, and the si3019 line-side devices. the 8-bit lcs2[7:0] and lcs[4:0] registers report loop current. the 8-bit lvs[7:0] register reports line voltage. these registers can help determine the following: when on-hook, detect if a line is connected. when on-hook, detect if a parallel phone is off-hook. when off-hook, detect if a parallel phone goes on or off-hook. detect if enough loop current is available to operate. when used in conjunction with the opd bit, detect if an overcurrent condition exists. (see "overload detection" on page 32.)
SI3056 si3018/19/10 rev. 1.02 25 line voltage measurement the SI3056 device reports line voltage with the lvs[7:0] bits (register 29) in both on- and off-hook states with a resolution of 1 v per bit. the accuracy of these bits is approximately 10%. bits 0 through 6 of this register indicate the value of the line voltage in 2?s compliment format. bit 7 of this register indicates the polarity of the tip/ring voltage. if the inte bit (register 2) and the polm bit (register 3) are set, a hardware interrupt is generated on the aout/int pin when bit 7 of the lvs register changes state. the edge-triggered interrupt is cleared by writing 0 to the poli bit (register 4). the poli bit is set each time bit 7 of the lvs register changes state and must be written to 0 to clear it. the default state of the lvs register forces the lvs bits to 0 when the line voltage is 3 v or less. the lvfd bit (register 31, bit 0) disables the force-to-zero function and allows the lvs register to display non-zero values of 3 v and below. this register might display unpredictable values at line voltages between 0 to 2 v. at 0 v, the lvs register displays all 0s. loop current measurement when the SI3056 is off-hook, the lcs2[7:0] and lcs[4:0] bits measure loop current in 1.1 ma/bit and 3.3 ma/bit resolution respectively. these bits enable detection of another phone going off-hook by monitoring the dc loop current. the lcs bits are decoded from lcs2; so, both are available at the same time. the line current sense transfer function is shown in figure 18 and detailed in table 15. off-hook the communication system generates an off-hook command by applying a logic 0 to the ofhk pin or by setting the oh bit (register 5, bit 0).the ofhk pin must be enabled by setting the ohe bit (register 5, bit 1). the polarity of the ofhk pin is selected by the opol bit (register 5, bit 4). with ofhk asserted, the system is in an off-hook state. the off-hook state seizes the line for incoming/outgoing calls and also can be used for pulse dialing. with ofhk deasserted, negligible dc current flows through the hookswitch. when the ofhk pin is asserted, the hookswitch transistor pair , q1 and q2, turn on. this applies a termination impedance across tip and ring and causes dc loop current to flow. the termination impedance has an ac and dc component. figure 18. typical loop current lcs transfer function table 15. loop current transfer function lcs[4:0] condition 00000 insufficient line current for normal operation. use the dod bit (register 19, bit 1) to determine if a line is connected. 00100 minimum line current for normal operation. 11111 loop current is greater than 127 ma. an overcurrent situation may exist. 0 3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 33 36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.1 62.7 66 69.3 72.6 75.9 79.2 127 82.5 85.8 89.1 92.4 95.7 99 102.3 loop current ( ma ) lcs bits 29.7 0 5 10 15 20 25 30 possible overload
SI3056 si3018/19/10 26 rev. 1.02 several events occur in the daa when the ofhk pin is asserted or the oh bit is set. there is a 250 s latency to allow the off-hook command to be communicated to the line-side device. once the line-side device goes off- hook, an off-hook counter forces a delay for line transients to settle before transmission or reception occurs. this off-hook counter time is controlled by the foh[1:0] bits (register 31, bits 6:5). the default setting for the off-hook counter time is 128 ms, but can be adjusted up to 512 ms or down to either 64 or 8 ms. after the off-hook counter has expired, a resistor calibration is performed for 17 ms. this allows circuitry internal to the daa to adjust to the exact conditions present at the time of going off-hook. this resistor calibration can be disabled by setting the rcald bit (register 25, bit 5). after the resistor calibration is performed, an adc calibration is performed fo r 256 ms. this calibration helps to remove offset in the a/d sampling the telephone line. this adc calibration can be disabled by setting the cald bit (register 17, bit 5). see ?calibration? on page 38. for more information on automatic and manual calibration. silicon laboratories ? recommends that the resistor and the adc calibrations not be disabled except when a fast response is needed after going off-hook, such as when responding to a type ii caller-id signal. see ?caller id? on page 31. to calculate the total time required to go off-hook and start transmission or reception, the digital filter delay (typically 1.5 ms with the fi r filter) should be included in the calculation. interrupts the aout/int pin can be used as a hardware interrupt pin by setting the inte bit (register 2, bit 7). when this bit is set, the call progress output function (aout) is not available. the default state of this interrupt output pin is active low, but active high operation can be enabled by setting the intp bit (register 2, bit 6). this pin is an open-drain output when the inte bit is set, and requires a 4.7 k ? pullup or pulldown for correct operation. if multiple int pins are connected to a single input, the combined pullup or pulldown resistance should equal 4.7 k ? . bits 7?2, and 0 in register 3 and bit 1 in register 44 can be set to enable hardware interrupt sources. when one or more of these bits are set, the aout/int pin becomes active and stays active until the interrupts are serviced. if more than one hardware interrupt is enabled in register 3, software polling determines the cause of the interrupts. register 4 and bit 3 of register 44 contain sticky interrupt flag bits. clear these bits after being set to service the interrupt. registers 43 and 44 contain the line current/voltage threshold interrupt. this interrupt will trigger when either the measured line voltage or current in the lvs or lcs2 registers, as selected by th e cvs bit (register 44, bit 2), crosses the threshold programmed into the cvt[7:0] bits. an interrupt can be programmed to occur when the measured value rises above or falls below the threshold. only the magnitude of the measured value is used to compare to the threshold programmed into the cvt[7:0] bits, and thus on ly positive numbers should be used as a threshold. this line current/voltage threshold interrupt is only available with the si3019 line-side device. dc termination the daa has programmable settings for dc impedance, minimum operational loop current, and tip/ring voltage. the dc impedance of the daa is normally represented with a 50 ? slope as shown in figure 19, but can be changed to an 800 ? slope by setting the dcr bit. this higher dc termination presents a higher resistance to the line as loop current increases. . figure 19. fcc mode i/v characteristics, dcv[1:0] = 11, mini[1:0] = 00, ilim = 0 for applications that require current limiting per the tbr21 standard, the ilim bit can be set to select this mode. in the current limiting mode, the dc i/v curve is changed to a 2000 ? slope above 40 ma, as shown in figure 20. the daa operates with a 50 v, 230 ? feed, which is the maximum line feed specified in the tbr21 standard. 12 11 10 9 8 7 6 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 loop current (a) fcc dct mode voltage across daa (v)
SI3056 si3018/19/10 rev. 1.02 27 figure 20. tbr21 mode i/v characteristics, dcv[1:0] = 11, mini[1:0] = 00, ilim = 1 the mini[1:0] bits select the minimum operational loop current for the daa, and the dcv[1:0] bits adjust the dct pin voltage, which affects the tip/ring voltage of the daa. these bits permit important trade-offs for the system designer. increasing the tip/ring voltage provides more signal headroom, while decreasing the tip/ring voltage allows compliance to ptt standards in low-voltage coun tries such as japan. increasing the minimum operational loop current above 10 ma also increases signal headroom and prevents degradation of the signal level in lo w-voltage countries. ac termination the SI3056 has four ac termination impedances with the si3019 and si3018 line-side devices, and sixteen ac termination impedances with the si3019 line-side device. the act and act2 bits select the ac impedance on the si3018 line-side device. the acim[3:0] bits select the ac impedance on the si3019. the available ac termination settings are listed for the line-side devices in tables 16 and 17. the most widely used ac terminations are available as register options to satisfy various global ptt requirements. the real 600 ? impedance satisfies the requirements of fcc part 68, jate, and many other countries. the 270 ? + (750 ? || 150 nf) satisfies the requirements of tbr21 (act = 0, act = 1, or acim [3:0] = 0010). 45 40 35 30 25 20 15 10 5 .015 .02 .025 .03 .035 .04 .045 .05 .055 .06 loop current (a) tbr21 dct mode voltage across daa (v) table 16. ac termination settings for the si3010 and si3018 line-side devices act act2 ac termination 0 0 real, nominal 600 ? termination that sat- isfies the impedance requirements of fcc part 68, jate, and other countries. 1 0 complex impedance that satisfies global impedance requirements. 0 1 complex impedance that satisfies global impedance requirements except new zealand. achieves higher return loss for countries requiring complex ac termina- tion. [220 ? + (820 ? || 120 nf) and 220 ? + (820 ? || 115 nf)] 1 1 complex impedance for use in new zealand. [370 ? + (620 ? || 310 nf)] table 17. ac termination settings for the si3019 line-side device acim[3:0] ac termination 0000 600 ? 0001 900 ? 0010 270 ? + (750 ? || 150 nf) and 275 ? + (780 ? || 150 nf) 0011 220 ? + (820 ? || 120 nf) and 220 ? + (820 ? || 115 nf) 0100 370 ? + (620 ? || 310 nf) 0101 320 ? + (1050 ? || 230 nf) 0110 370 ? + (820 ? || 110 nf) 0111 275 ? + (780 ? || 115 nf) 1000 120 ? + (820 ? || 110 nf) 1001 350 ? + (1000 ? || 210 nf) 1010 0 ? + (900 ? || 30 nf) 1011 600 ? + 2.16 f 1100 900 ? + 1 f 1101 900 ? + 2.16 f 1110 600 ? + 1 f 1111 global complex impedance
SI3056 si3018/19/10 28 rev. 1.02 there are two selections that are useful for satisfying non-standard ac termination requirements. the 350 ? + (1000 ? || 210 nf) impedance selection is the ansi/ eia/tia 464 compromise impedance network for trunks. the last ac termination se lection, acim[3:0] = 1111, is designed to satisfy minimum return loss requirements for every country in the world that requires a complex termination. for any of the ac termination settings, the programmable hybrid can be used to further reduce near-end echo. see the following ?transhybrid balance? section for more details. transhybrid balance the SI3056 contains an on-c hip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. this hybrid circuit is adjusted for each ac termination setting selected. the SI3056 also offers a digital filter stage for additional near-end echo cancellation. for each ac termination setting selected, the eight programmable hybrid registers (registers 45-52) can be programmed with coefficients to provide increased cancellation of real- world line anomalies. this digital filter can produce 10 db or greater of near-end echo cancellation in addition to the echo cancella tion provided by the analog hybrid circuitry. ring detection the ring signal is resistively coupled from tip and ring to the rng1 and rng2 pins. the SI3056 supports either full- or half-wave ring detection. with full-wave ring detection, the designer can detect a polarity reversal of the ring signal. see ?caller id? on page 31. the ring detection threshold is programmable with the rt bit (register 16, bit 0) and rt2 bit (register 17, bit 4). the ring detector output can be monitored in three ways. the first method uses the rgdt pin. the second method uses the register bits, rdtp, rdtn, and rdt (register 5). the final method uses the dtx output. the ring detector mode is controlled by the rfwe bit (register 18, bit 1). when the rfwe bit is 0 (default mode), the ring detector oper ates in half-wave rectifier mode. in this mode, only positive ring signals are detected. a positive ring signal is defined as a voltage greater than the ring threshold across rng1-rng2. conversely, a negative ring signal is defined as a voltage less than the negative ring threshold across rng1-rng2. when the rfwe bit is 1, the ring detector operates in full-wave rectifier mode. in this mode, both positive and negative ring signals are detected. the first method to monitor ring detection output uses the rgdt pin. when the rgdt pin is used, it defaults to active low, but can be changed to active high by setting the rpol bit (register 14, bit 1). this pin is an open-drain output, and requires a 4.7 k ? pullup or pulldown for correct operation. if multiple rgdt pins are connected to a single input, the combined pullup or pulldown resistance should equal 4.7 k ?. when the rfwe bit is 0, the rgdt pin is asserted when the ring signal is positive, which results in an output signal frequency equal to the actual ring frequency. when the rfwe bit is 1, the rgdt pin is asserted when the ring signal is positive or negative. the output then appears to be twice the frequency of the ring waveform. the second method to monitor ring detection uses the ring detect bits (rdtp, rdtn, and rdt). the rdtp and rdtn behavior is based on the rng1-rng2 voltage. when the signal on rng1-rng2 is above the positive ring threshold, the rdtp bit is set. when the signal on rng1-rng2 is below the negative ring threshold, the rdtn bit is set. when the signal on rng1-rng2 is between these thresholds, neither bit is set. the rdt behavior is also based on the rng1-rng2 voltage. when the rfwe bit is 0, a positive ring signal sets the rdt bit for a period of time. when the rfwe bit is 1, a positive or ne gative ring signal sets the rdt bit. the rdt bit acts like a one shot. when a new ring signal is detected, the one shot is reset. if no new ring signals are detected prior to the one shot counter reaching 0, then the rdt bit clears. the length of this count is approximately 5 seconds. the rdt bit is reset to 0 by an off-hook event. if the rdtm bit (register 3, bit 7) is set, a hardware interrupt occurs on the aout/int pin when rdt is triggered. this interrupt can be cleared by writing to the rdti bit (register 4, bit 7). when the rdi bit (register 2, bit 2) is set, an interrupt occurs on both the beginning and end of the ring pulse as defined by the rto bits (register 23, bits 6:3). ring validation should be enabled when using the rdi bit. the third method to monitor detection uses the dtx data samples to transmit ring data. if the communications link is active (pdl = 0) and the device is not off-hook or in on-hook line monitor mode, the ring data is presented on dtx. the waveform on dtx depends on the state of the rfwe bit. when rfwe is 0, dtx is ?32768 (0x8000) while the rng1-rng2 voltage is between the thresholds. when a ring is detected, dtx transitions to +32767 when the ring signal is positive, then goes back to ?32768 when the ring is near 0 and negative. thus a near square
SI3056 si3018/19/10 rev. 1.02 29 wave is presented on dtx that swings from ?32768 to +32767 in cadence with the ring signal. when rfwe is 1, dtx sits at approximately +1228 while the rng1-rng2 voltage is between the thresholds. when the ring becomes positive, dtx transitions to +32767. when the ring signal goes near 0, dtx remains near 1228. as the ring becomes negative, the dtx transitions to ?32768. this repeats in cadence with the ring signal. to observe the ring signal on dtx, watch the msb of the data. the msb toggles at the same frequency as the ring signal independent of the ring detector mode. this method is adequate for determining the ring frequency. ring validation this feature prevents false triggering of a ring detection by validating the ring frequency. invalid signals, such as a line voltage change when a parallel handset goes off- hook, pulse dialing, or a high-voltage line test are ignored. ring validation can be enabled during normal operation and in low power sleep mode. the external mclk signal is required in low power sleep mode for ring validation. the ring validation circuit operates by calculating the time between alternating crossings of positive and negative ring thresholds to validate that the ring frequency is within tolerance. high and low frequency tolerances are programmable in the ras[5:0] and rmx[5:0] fields. the rcc[2:0] bits define how long the ring signal must be within tolerance. once the duration of the ring frequency is validated by the rcc bits, the circuitry stops checking for frequency tolerance and begins checking for the end of the ring signal, which is defined by a lack of additional threshold crossings for a period of time configured by the rto[3:0] bits. when the ring frequency is first validated, a timer defined by the rdly[2:0] bits is started. if the rdly[2:0] timer expires before the ring timeout, then the ring is validated and a valid ring is indicated. if the ring timeout expires before the rdly[2:0] timer, a valid ring is not indicated. ring validation requires five parameters: timeout parameter to place a lower limit on the frequency of the ring signal on the ras[5:0] bits (register 24). this is measured by calculating the time between crossings of positive and negative ring thresholds. minimum count to place an upper limit on the frequency on the rmx[5:0] bits (register 22). time interval over which the ring signal must be the correct frequency on the rcc[2:0] bits (register 23). timeout period that defines when the ring pulse has ended based on the most recent ring threshold crossing. delay period between when the ring signal is validated and when a valid ring signal is indicated to help accommodate distinctive ringing. the rngv bit (register 24, bit 7) enables or disables the ring validation feature in normal operating mode and low-power sleep mode. ring validation affects the behavior of the rdt status bit, the rdti interrupt, the int pin, and the rgdt pin. 1. when ring validation is enabled, the status bit seen in the rdt read-only bit (r5.2), represents the detected envelope of the ring. the ring validation parameters are configurable so that this envelope may remain high throughout a distinctive-ring sequence. 2. the rdti interrupt fires when a validated ring occurs. if rdi is zero (default), the interrupt occurs on the rising edge of rdt. if rdi is set, the interrupt occurs on both rising and falling edges of rdt. 3. the int pin follows the rdti bit with configurable polarity. the rgdt pin can be configured to follow the ringing signal envelope detected by the ring validation circuit by setting rfwe to 0. if rfwe is set to 1, the rgdt pin follows an unqualified ring detect one-shot signal initiated by a ring- threshold crossing and terminated by a fixed counter timeout of approximately 5 seconds. (this information is shown in register 18). ringer impedance and threshold the ring detector in many daas is ac coupled to the line with a large 1 f, 250 v decoupling capacitor. the ring detector on the SI3056 is resistively coupled to the line. this produces a high ringer impedance to the line of approximately 20 m ? to meet the majority of country ptt specifications, including fcc and tbr21. several countries including poland, and south africa, may require a maximum ringer impedance that can be met with an internally synthe sized impedance by setting the rz bit (register 16, bit 1). some countries also specify ringer thresholds differently. the rt bit (register 16, bit 0) selects between two different ringer thresholds: 15 v 10% and 21.5 v 10%. these two settings satisfy ringer threshold requirements worldwide. the thresholds are set so that a ring signal is guaranteed to not be detected below the minimum, and a ring signal is guaranteed to be detected above the maximum. pulse dialing and spark quenching pulse dialing results from going off- and on-hook to generate make and break pulses. the nominal rate is 10 pulses per second. some countries have strict
SI3056 si3018/19/10 30 rev. 1.02 specifications for pulse fidelity that include make and break times, make resistance, and rise and fall times. in a traditional solid-state dc holding circuit, there are many problems in meeting these requirements. the SI3056 dc holding circuit actively controls the on- hook and off-hook transients to maintain pulse dialing fidelity. spark quenching requirements in countries such as italy, the netherlands, south africa, and australia deal with the on-hook transition during pulse dialing. these tests provide an inductive dc feed resulting in a large voltage spike. this spike is caused by the line inductance and the sudden decrease in current through the loop when going on-hook. the traditional solution to the problem is to put a para llel resistive capacitor (rc) shunt across the hookswitch relay. however, the capacitor required is large (~1 f, 250 v) and relatively expensive. in the SI3056, loop current can be controlled to achieve three distinct on-hook speeds to pass spark quenching tests without additional bom components. through settings of four bits in three registers, ohs (register 16), ohs2 (reg ister 31), sq1 and sq0 (register 59), a slow ramp down of loop current can be achieved which induces a delay between the time oh bit is cleared and the time the daa actually goes on- hook. to ensure proper operation of the daa during pulse dialing, disable the automatic resistor calibration that is performed each time the daa enters the off-hook state by setting the rcald bit (register 25, bit 5). billing tone det ection and receive overload ?billing tones? or ?metering pulses? generated by the central office can cause modem connection difficulties. the billing tone is typically either a 12 or 16 khz signal and is sometimes used in germany, switzerland, and south africa. depending on line conditions, the billing tone might be large enough to cause major errors in the line data. the SI3056 chipset can provide feedback indicating the beginning and end of a billing tone. billing tone detection is enabled with the bte bit (register 17, bit 2). billing tones less than 1.1 v pk on the line are filtered out by the low pass digital filter on the SI3056. the rov bit is set when a line signal is greater than 1.1 v pk , indicating a receive overload condition. the btd bit is set when a billing tone is large enough to excessively reduce the line-derived power supply of the line-side device. the ovl bit (register 19) can be polled following a billing tone detection. the ov l bit indicates that the billing tone has passed when it returns to 0. the btd and rov bits are sticky, and must be written to 0 to be reset. after the billing tone passes, the daa initiates an auto-calibration sequence that must complete before data can be transmitted or received. certain line events, such as an off-hook event on a parallel phone or a polarity reversal, can trigger the rov or the btd bits. look for multiple events before qualifying if billing tones are present. after the billing tone passes, the daa initia tes an auto-calibration sequence that must complete before data can be transmitted or received. although the daa remains of f-hook during a billing tone event, the received data from the line is corrupted when a large billing tone occurs. if the user wishes to receive data through a billing tone, an ex ternal lc filter must be added. a manufacturer can provide this filter to users in the form of a dongle that connects on the phone line before the daa. this pr events the manufacturer from having to include a costly lc filter to support multiple countries and customers. alternatively, when a billing t one is detected, the system software notifies the user that a billing tone has occurred. notification prompt s the user to contact the telephone company to disa ble billing tones or to purchase an external lc filter. billing tone filter (optional) to operate withou t degradation duri ng billing tones in germany, switzerland, and south africa, requires an external lc notch filter. the SI3056 can remain off-hook during a billing tone event, bu t line data is lost in the presence of large billing tone signals. the notch filter design requires two notches, one at 12 khz and one at 16 khz. because these components are expensive and few countries utilize billing tone s, this filter is typically placed in an external dongle or added as a population option for these countries. figure 21 shows an example billing tone filter.
SI3056 si3018/19/10 rev. 1.02 31 figure 21. billing tone filter l1 must carry the entire loop current. the series resistance of the inductors is important to achieve a narrow and deep notch. this design has more than 25 db of attenuation at both 12 khz and 16 khz. the billing tone filter affect s the ac termination and return loss. the global complex ac termination (acim = 1111) passes global return loss specifications with and without the billing to ne filter by at least 3 db. on-hook line monitor the SI3056 can receive line activity when in an on-hook state. a low-power adc located on the line-side device digitizes the signal passed across the rng1/2 pins and then sends the signal digitally across the isolation link to the host. this mode is typically used to detect caller id data and is enabled by setting the onhm bit (register 5, bit 3). caller id the SI3056 can pass caller id data from the phone line to a caller id decoder connected to the serial port. type i caller id type i caller id sends the cid data while the phone is on-hook. in systems where the caller id data is passed on the phone line between the first an d second rings, utilize the following method to capture the caller id data: 1. after identifying a ring signal using one of the methods described in "ring detection" on page 28, determine when the first ring is complete. 2. assert the onhm bit (register 5, bit 3) to enable caller id data detection. the caller id data passed across the rng 1/2 pins is presented to the host via the sdo pin. 3. clear the onhm bit after the caller id data is received. in systems where the caller id data is preceded by a line polarity (battery) reversal, use the following method to capture the caller id data: 1. enable full wave rectified ring detection (rfwe, register 18, bit 1). 2. monitor the rdtp and rdtn register bits (or the poli bit) to identify whether a polarity reversal or ring signal has occurred. a polarity reversal trips either the rdtp or rdtn ring detection bits, and thus the full-wave ring detector must be used to distinguish a polarity reversal from a ring. the lowest specified ring frequency is 15 hz; therefore, if a battery reversal occurs, the dsp should wait a minimum of 40 ms to verify that the event observed is a battery reversal and not a ring signal. this time is greater than half the period of the longest ring signal. if another edge is detected during this 40 ms pause, this event is characterized as a ring signal and not a battery reversal. 3. assert the onhm bit (register 5, bit 3) to enable the caller id data detection. the caller id data passed across the rng 1/2 pins is presented to the host via the sdo pin. 4. clear the onhm bit after the caller id data is received. type ii caller id type ii caller id sends the cid data while the phone is off-hook and is often referred to as caller id/call waiting (cid/cw). to receive the cid data while off-hook, use the following procedure (see figure 22): 1. the caller alert signal (cas) tone is sent from the central office (co) and is digitized along with the line data. the host processor must detect the presence of this tone. 2. the daa must then check for another parallel device on the same line. this is accomplished by briefly going on- hook, measuring the line voltage, and then returning to an off-hook state. a. set the cald bit (register 17, bit 5) to disable the calibration that automatically occurs when going off- hook. b. set the rcald bit (register 25, bit 5) to disable the resistor calibration from occurring when going off- hook. c. set the foh[1:0] bits (register 31, bits 6:5) to 11 to table 18. component values?optional billing tone filters symbol value c1,c2 0.027 f, 50 v, 10% c3 0.01 f, 250 v, 10% l1 3.3 mh, >120 ma, <10 ? , 10% l2 10 mh, >40 ma, <10 ? , 10% l2 c3 ring tip from line to daa c1 c2 l1
SI3056 si3018/19/10 32 rev. 1.02 reduce the off-hook counter time to 8 ms. d. clear the oh bit (or drive the ofhk pin to the inactive state) to put the daa in an on-hook state. the rxm bit (register 19, bit 3) may also be set to mute the receive path. e. read the lvs bits to determine the state of the line. if the lvs bits read the typical on-hook line voltage, then no parallel devices are active on the line and cid data reception can be continued. if the lvs bits read well below the typical on-hook line voltage, then one or more devices are present and active on the same line that are not compliant with type ii cid. do not continue cid data reception. f. set the oh bit to 1 (or drive the ofhk pin to the active state) to return to an off-hook state. after returning to an off-hook state and waiting 8 ms for the off-hook counter, normal data transmission and reception can proceed. if a non-compliant parallel device is present, then a reply tone is not sent by the host tone generator and the co does not proceed with sending the cid data. if all devices on the line are type ii cid compliant, then the host must mute its upstream data output to avoid propagation of its reply tone and the subsequent cid data. after muting its upstream data output, the host processor should then return an acknowledgement (ack) tone to the co to request the transmission of the cid data. 3. the co then responds with the cid data and the host processor unmutes the upstream data output and continues with normal operation. 4. the muting of the upstream data path by the host processor mutes the handset in a telephone application so the user cannot hear the acknowledgement tone and cid data being sent. 5. the cald and rcald bits can be cleared to re-enable the automatic calibration when going off-hook. the foh[1:0] bits also can be programmed to 01 to restore the default off-hook counter time. because of the nature of the low-power adc, the data presented on sdo could have up to a 10% dc offset. the caller id decoder must either use a high pass or a band pass filter to accurately retrieve the caller id data. figure 22. implementing type ii caller id on the SI3056 overload detection the SI3056 can be programmed to detect an overload condition that exceeds the normal operating power range of the daa circuit. to use the overload detection feature, the following steps should be followed: 1. set the oh bit (register 5, bit 0) to go off-hook, and wait 25 ms to allow line transients to settle. 2. enable overload detection by then setting the ope bit high (register 17, bit 3). if the daa then senses an overload situation, it automatically presents an 800 ? impedance to the line notes: 1. the off-hook counter and calibrations prevent transmission or reception of data for 402.75 ms (default) for the line voltage to settle. 2. the caller alert signal (cas) tone transmits from the co to signal an incoming call. 3. the device is taken on-hook to read the line voltage in the lv s bits to detect parallel handsets. in this mode, no data is transmitted on the sdo pin. 4. when the device returns off-hook, the normal off-hook counter is reduced to 8 ms. if the cald and rcald bits are set, then the automatic calibrations are not performed. 5. after allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. if cid data reception is required, send the appropriate signal to the co at this time. 6. this example uses the oh bit to put the SI3056 into an off-hook state. the ofhk pin can also be used to accomplish this. to use the ofhk pin instead of the oh bit, simply enable the ohe bit (register 5, bit 1) and drive the ofhk pin low during the preceding sequence. this has the same effect as setting the oh bit. foh[1] bit rcald bit cald bit oh bit 6 foh[0] bit cas tone received on-hook off-hook counter (8 ms) off-hook ack line on-hook off-hook counter and calibration (402.75 ms nominally) off-hook 1 234
SI3056 si3018/19/10 rev. 1.02 33 to reduce the hookswitch current. at this time, the daa also sets the opd bit (register 19, bit 0) to indicate that an overload condition exists. the line current detector within the daa has a threshold that is dependant upon the ilim bit (register 26). when ilim = 0, the overload detection threshold equals 160 ma. when ilim = 1, the overload detection threshold equals 60 ma. the ope bit should always be cleared before going off-hook. gain control the SI3056 supports different gain and attenuation settings depending on the line-side device being used. for both devices, gains of 0, 3, 6, 9, and 12 db can be selected for the receive path with the arx[2:0] bits. the receive path can also be muted with the rxm bit. attenuations of 0, 3, 6, 9, and 12 db can also be selected for the transmit path with the atx[2:0] bits. the transmit path also can be muted with the txm bit (register 15). when using the si3019 line-side device, the SI3056 provides even more flexible gain and attenuation settings. the txg2 and rxg2 bits (registers 38?39) enable gain or attenuation in 1 db increments up to 15 db for the transmit and receive paths. the tga2 and rga2 bits select either gain or attenuation for these registers. the txg3 and rxg3 bits (registers 40?41) enable gain or attenuation in 0.1 db increments up to 1.5 db for the transmit and receive paths. the tga3 and rga3 bits select either gain or attenuation for these registers. these additional gain/attenuation registers are active only when the arx[2:0] and atx[2:0] bits are set to all 0s. figure 23. si3018/19/10 signal flow diagram figure 24. SI3056 signal flow diagram filter selection the SI3056 supports additional filter selections for the receive and transmit signals as defined in table 10 and table 11 on page 14. the iire bit (register 16, bit 4) selects between the iir and fir filters. the iir filter provides a shorter, but non-linear, group delay alternative to the default fir filter and only operates with an 8 khz sample rate. also, on the si3019 line-side device, the filt bit (register 31, bit 1) selects a ?3 db low frequency pole of 5 hz when cleared and 200 hz when set. the filt bit affects the receive path only. to SI3056 adc dac link analog hybrid act tx co digital hybrid iire digital filter tga2 txg2 to si3018/19/10 link tga3 txg3 rga2 rxg2 rga3 rxg3 iire digital filter sdi sdo
SI3056 si3018/19/10 34 rev. 1.02 clock generation the SI3056 has an on-chip clock generator. using a single mclk input frequency, the SI3056 generates all the desired standard modem sample rates. the clock generator consists of two phase-locked loops (pll1 and pll2) that achieve the desired sample frequencies. figure 25 illust rates the clock generator. the architecture of the dual pll scheme provides fast lock time on initial star t-up, fast lock time when changing modem sample rates, high noise immunity, and can change modem sample rates with a single register write. many mclk frequencies between 1 and 60 mhz are supported. mclk should be from a clean source, preferably directly from a crystal with a constant frequency and no dropped pulses. if the input clock frequency is dithered to achieve a required average frequency, the clock signal should not change more than +7 or ?8 clock pulses per audio frame. in serial mode 2 (refer to the ?digital interface? section), the SI3056 operates as a slave device. the clock generator is configured based on the src register to generate the required internal clock frequencies. in this mode, pll2 is powered-down. for further details of slave mode operation, see "multiple device support" on page 37. programming the clock generator as shown in figure 25, pll1 must output a clock equal to 98.304 mhz (f base ). the f base is determined by programming the following registers: register 8: pll1 n[7:0] divider. register 9: pll1 m[7:0] divider. the main design consideration is the generation of a base frequency, defined as follows: n (register 8) and m (register 9) are 8-bit unsigned values. f mclk is the frequency of the clock provided to the mclk pin. table 19 lists several standa rd crystal oscillator rates that can be supplied to mclk. this list represents a sample of mclk frequency choices. many others are possible. after pll1 is programmed, the src[3:0] bits can achieve the standard modem sampling rates with a single write to register 7. see "sample rate control" on page 56. when programming the registers of the clock generator, the order of register writes is important. for pll1 updates, n (register 8, bits 7:0) must be written first, then immediately followed by a write to m (register 9, bits 7:0). the values shown in table 19 satisfy the preceding equation. however, when programming the registers for n and m, the value placed in these registers must be one less than the value calculated from the equations. for example, with an mclk of 46.08 mhz, the values placed in the n and m registers are 0x0d and 0x4f, respectively. pll lock times the SI3056 changes sample rates quickly. however, lock time varies based on the programming of the clock generator. the following relationships describe the boundaries on pll locking time: pll1 lock time < 1 ms pll2 lock time 100 s to 1 ms for modem designs, silicon laboratories ? recommends that pll1 be programmed during initialization. no furthe r programming of pll1 is necessary. the src[3:0] register can be programmed for the required initial samp le rate, typically 7200 hz. rate changes are made by writing to src[3:0] (register 7, bits 3:0). the final design consideration for the clock generator is the update rate of pll1. the following criteria must be satisfied for the plls to remain stable: where f up1 is shown in figure 25. f base f mclk m n ---------------------------- - 98.304 mhz == f up1 f mclk n ------------------- = 144 khz
SI3056 si3018/19/10 rev. 1.02 35 figure 25. update rate of pll1 div 8-bit pll1 div n2 div 3 div 16 pll2 div 8- bit div m2 decoder decoder 1 0 01 01 sclk f up1 98.304 m hz 32.768 m hz n1 m1 slave srate mclk
SI3056 si3018/19/10 36 rev. 1.02 digital interface the SI3056 has two serial interface modes that support most standard modem dsps. the m0 and m1 mode pins select the interface mode. the key difference between these two serial modes is the operation of the fsync signal. table 20 summarizes the serial mode definitions. the digital interface consists of a single, synchronous serial link that communicates both telephony and control data. in serial mode 0 or 1, the SI3056 operates as a master, where the master clock (mclk) is an input, the serial data clock (sclk) is an output, and the frame sync signal (fsync ) is an output. the mclk frequency and the value of the sample rate control registers 7, 8, and 9 determine the sample rate (fs). the serial port clock, sclk, runs at 256 bits per frame, where the frame rate is equivalent to the sample rate. see "clock generation" on page 34 for details on programming sample rates. the SI3056 transfers 16- or 15-bit telephony data in the primary timeslot and 16-bit control data in the secondary timeslot. figures 26 and 27 show the relative timing of the serial frames. primary frames occur at the frame rate and are always present. to minimize overhead in the external dsp, secondary frames are present only when requested. two methods exist for requesting a secondary frame to transfer control information. the default powerup mode uses the lsb of the 16-bit transmit (tx) data word as a flag to request a secondary transfer. only 15-bit tx data is transferred, which results in a small loss of snr but provides software control of the secondary frames. as an alternative method, the fc pin can serve as a hardware flag for requesting a secondary frame. the external dsp can turn on the 16-bit tx mode by setting the sb bit (register 1, bit 0). in the 16-bit tx mode, the hardware fc pin must be used to request secondary transfers. figures 28 and 29 illustrate the secondary frame read cycle and write cycle, respectively. during a read cycle, the r/w bit is high and the 7-bit address field contains the address of the register to be read. the contents of the 8-bit control register are placed on the sdo signal. during a write cycle, the r/w bit is low and the 7-bit address field contains the address of the register to be written. the 8-bit data to be written immediately follows the address on sdi. only one register can be read or written during each secondary frame. see "control registers" on page 48 for the register addresses and functions. in serial mode 2, the si30 56 operates as a slave device, where mclk is an input, sclk is a no connect, and fsync is an input. in addition, the rgdt /fsd/m1 pin operates as a delayed frame sync (fsd) and the fc/ rgdt pin operates as ring detect (rgdt ). in this mode, fc operation is not supported. for details on operating the SI3056 as a slave device, see ?multiple device support? . table 19. mclk examples mclk (mhz) n m 1.8432 3 160 4.0960 1 24 6.1440 1 16 8.1920 1 12 9.2160 3 32 10.3680 27 256 11.0592 9 80 12.288 1 8 14.7456 3 20 18.4320 3 16 24.5760 1 4 25.8048 21 80 44.2368 9 20 46.0800 15 32 47.9232 39 80 56.0000 35 36 table 20. serial modes mode m1 m0 description 0 0 0 fsync frames data 1 0 1 fsync pulse starts data frame 21 0slave mode 3 1 1 reserved
SI3056 si3018/19/10 rev. 1.02 37 multiple device support the SI3056 supports the operation of up to seven additional devices on a single serial interface. figure 34 shows the typical connection of the SI3056 and one additional serial voice codec (si3000). the SI3056 must be the master in this configuration. configure the secondary codec as a slave device with the master?s sclk used as the mclk input to the codec, and the master?s frame sync delay signal (fsd) used as the codec?s fsync input. on powerup, the SI3056 master does not detect the additional codec on the serial bus. the fc/rgdt pin is an input, operating as the hardware control for secondary frames, and the rgdt/fsd/m1 pin is an output, operating as the active low ring detection signal. program the master device for master/slave mode before enabling the isolation link, because a ring signal causes a false transition to the slave device?s fsync. register 14 provides the necessary control bits to configure the SI3056 for master/slave operation. bit 0 (dce) sets the SI3056 in master/slave mode, also referred to as daisy-chain mode. when the dce bit is set, the fc/rgdt pin becomes the ring detect output and the rgdt /fsd/m1 pin becomes the frame sync delay output. when using multiple devices, secondary frame communication must be requested via software in the lsb of the transmit (tx) data word. bits 7:5 (nslv2:nslv0) set the number of slaves to be supported on the serial bus. for each slave, the SI3056 generates an fsync to the dsp. in daisy-chain mode, the polarity of the ring signal can be controlled by bit 1 (rpol). when rpol = 1, the ring detect signal (now an output on the fc/rgdt pin) is active high. the SI3056 supports a variety of codecs and additional SI3056s. the type of slave codec(s) used is set by the ssel[1:0] bits (register 14, bits 4:3) and determines the type of signalling used in the lsb of sdo. this assists the host in isolating which data stream is the master and which is the slave. if the lsb is used for signalling, the master de vice has a uni que setting relative to the slave devices. the dsp can use this information to determine which fsync marks the beginning of a sequence of data transfers. the delayed frame sync (fsd) of each device is supplied as the fsync of each subsequent slave device in the daisy chain. the master SI3056 generates an fsync signal for each device every 16 or 32 slck periods. the delay period is set by fsd (register 14, bit 2). figure 30 on page 43 and figure 33 on page 45 show the relative timing for daisy chaining operation. primary communication frames occur in sequence, followed by secondary communication frames, if requested. when writing/read ing the master device via a secondary frame, all secondary frames of the slave devices also must be writte n. when writing/reading a slave device via a second ary frame, the secondary frames of the master and all other slaves must be written also. ?no operation? writes/reads to secondary frames are accomplished by writing/reading a 0 value to address 0. if fsd is set for 16 sclk periods between fsync s, only serial mode 1 can be used. in addition, the slave devices must delay the tri-state to active transition of their sdo sufficiently from the rising edge of sclk to avoid bus contention. the SI3056 supports the operation of up to eight SI3056 devices on a single serial bus. the master SI3056 must be configured in serial mode 1. configure the slave(s) SI3056 in serial mode 2. figure 35 on page 47 shows a typical master/slave connection using three SI3056 devices. when in serial mode 2, fsync becomes an input, rgdt /fsd/m1 becomes the delay frame sync output, and fc/rgdt becomes the ring detection output. the serial interface runs at the mclk input frequency fed from a master device (such as a master SI3056's sclk output). to achieve the proper sampling frequency, the src[3:0] bits (register 7, bits 3:0) must be programmed with the proper sample rate value before the sampled line data is valid. the sclk pin of the slave is a no connect in this configuration. the delay between fsync input and delayed frame sync output (rgdt /fsd/m1) is 16 sclk periods. the rgdt /fsd/m1 output has a waveform identical to the fsync signal in serial mode 0. in addition, the lsb of sdo is set to 0 by default for all devices in serial mode 2. power management the SI3056 supports four basic power management operation modes. the modes are normal operation, reset operation, sleep mode, and full powerdown mode. pdn and pdl bits (register 6) control the power management modes. on powerup, or following a reset, the SI3056 is in reset operation. the pdl bit is set, and the pdn bit is cleared. the SI3056 is operational, except for the isolation link. no communication between the SI3056 and line-side device can occur during reset operation. bits associated with the line-side device are not valid in this mode. the most common mode of operation is the normal operation. in this mode, the pdl and pdn bits are cleared. the SI3056 is oper ational and the isolation link
SI3056 si3018/19/10 38 rev. 1.02 is passing information between the SI3056 and the line- side device. the SI3056 supports a low-power sleep mode to support ring validation and wake-on-ring features. the clock generator registers 7, 8, and 9 must be programmed with valid, non-zero values and the pdl bit must be clear before enabling sleep mode. the pdn bit must then be set. when the SI3056 is in sleep mode the mclk signal must rema in active. in low-power sleep mode with mclk ac tive, the SI3056 is non- functional except for the isolation link and the rgdt signal. to take the SI3056 out of sleep mode, pulse the reset pin (reset ) low. in summary, the powerdown/up sequence for sleep mode is as follows: 1. ensure that registers 7, 8, and 9 have valid non-zero values, and ensure the pdl bit (register 6, bit 4) is cleared. 2. set the pdn bit (register 6, bit 3). 3. mclk must stay active. 4. reset the SI3056 by pulsing the reset pin. 5. program registers to desired settings. the SI3056 also supports an additional powerdown mode. when both the pdn (register 6, bit 3) and pdl (register 6, bit 4) bits are set, the chipset enters a complete powerdown mode and draws negligible current (deep sleep mode). turn off the pll2 before entering deep sleep mode (i.e., set register 9 to 0 and then register 6 to 0x18). in this mode, the SI3056 is non-functional. normal operation is restored by the same process for taking the daa out of sleep mode. calibration the SI3056 initiates two auto-calibrations by default when the device goes off-hook or experiences a loss in line power. a 17 ms resistor calibration is performed to allow circuitry internal to the daa to adjust to the exact line conditions present at that time. this resistor calibration can be disabled by setting the rcald bit (register 25, bit 5). a 256 ms adc calibration is also performed to remove offsets that might be present in the on-chip a/d converter which could affect the a/d dynamic range. the adc auto-calibration is initiated after the daa dc terminatio n stabilizes, and the resistor calibration completes . because large variations in line conditions and line card behavior exist, it could be beneficial to use manual calibration instead of auto- calibration. execute manual adc calibration as close as possible to 256 ms before valid transmit/receive data is expected. take the following steps to implement manual adc calibration: 1. the cald (auto-calibration disable?register 17) bit must be set to 1. 2. the mcal (manual calibration) bit must be toggled to 1 and then 0 to begin and complete the calibration. 3. the calibration is completed in 256 ms. in-circuit testing with the SI3056?s advanced design the designer can determine system functionalit y during production line tests, and during support for end-user diagnostics. six loopback modes allow incr eased coverage of system components. four of the test modes require a line-side power source. although a standard phone line can be used, the test circuit in figure 1 on page 7 is adequate. in addition, an off-hook s equence must be performed to connect the power source to the line-side device. for the start-up loopback test mode, line-side power is not necessary and no off-hook sequence is required. the start-up test mode is enabled by default. when the pdl bit (register 6, bit 4) is set (the default case), the line-side is in a powerdown mode and the dsp-side is in a digital loop-back mode. data received on sdi passes through the internal filters and transmitted on sdo which introduces approximately 0.9 db of attenuation on the sdi signal received. the group delay of both transmit and receive filters exists between sdi and sdo. clearing the pdl bit disables this mode and the sdo data is switched to the receive data from the line-side. when the pdl bit is cleared, the fdt bit (register 12, bit 6) becomes active, indicating the successful communication between the line-side and dsp-side. this can be used to verify that the isolation link is operational. the digital data loop-back mode offers a way to input data on the sdi pin and have the identical data be output on the sdo pin by bypassing the transmit and receive filters. setting the ddl bit (register 10, bit 0) enables this mode. no line-side power or off-hook sequence is required for this mode, which provides an easy way to verify communication between the host processor/dsp and the daa. the remaining test modes require an off-hook sequence to operate. the following sequence defines the off-hook requirements: 1. powerup or reset. 2. program the clock generator to the chosen sample rate. 3. enable line-side by clearing the pdl bit. 4. issue an off-hook command. 5. delay 402.75 ms to allow calibration to occur. 6. set the test mode. in the communications link loopback mode, the host sends a digital input test pattern on sdi and receives
SI3056 si3018/19/10 rev. 1.02 39 that digital test pattern back on sdo. to enable this mode, set the idl bit (register 1, bit 1). in this mode, the isolation barrier is tested. the digital stream is delivered across the isolation capacitors, c1 and c2 of figure 15 on page 16, to the line-side device and returned across the same barrier. in this mode, the 0.9 db attenuation and filter group delays also exist. the analog loopback mode allows an external device to drive a signal on the telephone line into the line-side device and returns the signal on to the line. this mode allows testing of external components connecting the rj-11 jack (tip and ring) to the line-side device. to enable this mode, set the al bit (register 2, bit 3). the pcm analog loopback mode extends the signal path of the analog loopback mode. in this mode, an analog signal can be driven from the line into the si3019 line-side device. this analog signal is converted to digital data and then passed across the isolation barrier capacitors to the system-side device. the data passes through the receive filter, is routed back through the transmit filter, and is then passed back across the isolation barrier and sent back out onto the line as an analog signal. set the pcml bit (register 33, bit 7) to enable this mode. the final testing mode, internal analog loopback, allows the system to test the basic operation of the transmit and receive paths on the line-side device and the external components shown in figure 15 on page 16. in this test mode, the host provides a digital test waveform on sdi. this data passes ac ross the isolation barrier, is transmitted to and received from the line, passes back across the isolation barrier, and is presented to the host on sdo. to enable this mode, clear the hbe bit (register 2, bit 1). when the hbe bit is cleared, this causes a dc offset that affects the signal swing of the transmit signal. silicon laboratories ? recommends that the transmit signal be 12 db lower than normal tran smit levels. a lower level eliminates clipping from the dc offset that results from disabling the hybrid. it is assumed in this test that the line ac impedance is nominally 600 ?. note: all test modes are mutually exclusive. if more than one test mode is enabled concurrently, the results are unpredictable. exception handling the SI3056 provides several mechanisms to determine if an error occurs during operation. through the secondary frames of the serial link, the controlling systems can read several status bits. the bit of highest importance is the frame det ect bit (fdt, register 12, bit 6), which indicates that the system-side (SI3056) and line-side devices are communicating. during normal operation, the fdt bit can be checked before reading bits for information about the line-side. if fdt is not set, the following bits related to the line-side are invalid? rdt, rdtn, rdtp, lcs[4:0], lsid[1:0], revb[3:0], lcs2[7:0], lvs[7:0], rov, btd, dod, and ovl; the rgdt operation is also non-functional. following powerup and reset, the fdt bit is not set because the pdl bit (register 6 bit 4) defaults to 1. the communications link does not operate and no information about the line-side can be determined. the user must program the clock generator to a valid configuration for the system and clear the pdl bit to activate the communications link. as the system- and line-side devices are establishing communication, the system-side device does not generate fsync signals. establishing communication takes less than 10 ms. therefore, if the controlli ng dsp serial interface is interrupt driven based on the fsync signal, the controlling dsp does not requi re a special delay loop to wait for this event to complete. the fdt bit also can indicate if the line-side device executes an off-hook request successfully. if the line- side device is not connected to a phone line, the fdt bit remains cleared. the controlling dsp must provide sufficient time for the line-side to execute the off-hook request. the maximum time for fdt to be valid following an off-hook request is 10 ms. if the fdt bit is high, the lcs[4:0] bits indicate the amount of loop current flowing. if the fdt fa ils to be set following an off- hook request, the pdl bit (register 6) must be set high for at least 1 ms to reset the line-side.
SI3056 si3018/19/10 40 rev. 1.02 revision identification with the SI3056 the system designer can determine the revision of the SI3056 and/or the line-side device. the reva[3:0] bits (register 11, bits 3:0) identify the revision of the SI3056. the revb[3:0] bits (register 13, bits 3:0) identify the revision of the line-side dev ice. table 21 lists revision values fo r all devices and might contain future revisions not yet in existence. table 21. revision values revision SI3056 si3018 si3019 si3010 a 0001 0001 0001 0001 b 0010 0010 0010 0010 c 0011 0011 0011 0011 d 0100 0100 0100 0100 e 0101 0101 0101 0101 f 0110 0110 0110 0110
SI3056 si3018/19/10 rev. 1.02 41 figure 26. software fc/rgdt secondary request figure 27. hardware fc/rgdt secondary request communications frame 1 (cf1) (cf2) 16 sclks 128 sclks 256 sclks primary fsync fc 0 xmt data secondary data xmt data sdi rcv data secondary data rcv data sdo d15 ?d1 d0 = 1 (software fc bit) secondary primary d15 ?d1 d0 = 0 (software fc bit) communications frame 1 (cf1) (cf2) 16 sclks 128 sclks 256 sclks primary fsync fc 0 xmt data secondary data xmt data sdi rcv data secondary data rcv data sdo d15?d0 secondary primary
SI3056 si3018/19/10 42 rev. 1.02 figure 28. secondary communication data format?read cycle figure 29. secondary communication data format?write cycle fsync (mode 1) sdi d15 d14 d13 d12 d11 d10 d9 d8 d7 d0 1 a a a a a a a sdo d d7 d6 d5 d4 d3 d2 d1 d0 d d d d d d d fsync (mode 0) r/w fsync (mode 1) sdi d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 a a a a a a a sdo d d d d d d d d fsync (mode 0) r/w
SI3056 si3018/19/10 rev. 1.02 43 figure 30. daisy chaining of a single slave (pulse fsd) figure 31. daisy chaining of a single slave (frame fsd) 128 sclks 128 sclks 32 sclks 32 sclks primary frame (data) secondary frame (control) master slave 1 master fsync master fsd/ slave1 fsync sdi [0] sdi [15..1] sdo [0] sdo[15..1] comments serial mode 1 reg 14: nslv = 1, ssel = 2, fsd = 0, dce = 1 serial mode 2 reg 14 reset values: nslv = 1, ssel = 3, fsd = 1, dce = 1 1 master 1 slave1 master master slave1 slave1 slave1 slave1 master master 0 slave1 1 master primary frames with secondary frame requested via sdi[0] = 1 128 sclks 128 sclks 16 sclks primary frame (data) secondary frame (control) master slave 1 master fsync master fsd/ slave1 fsync sdi [0] sdi [15..1] sdo [0] sdo[15..1] comments serial mode 1 reg 14: nslv = 1, ssel = 2, fsd = 1, dce = 1 serial mode 2 reg 14 reset values: nslv = 1, ssel = 3, fsd = 1, dce = 1 1 master 1 slave1 master master slave1 slave1 slave1 slave1 master master 0 slave1 1 master primary frames with secondary frame requested via sdi[0] = 1 16 sclks 16 sclks 16 sclks
SI3056 si3018/19/10 44 rev. 1.02 master slave 1 master fsync master fsd/ slave1 fsyn c serial m ode 1 reg 14: nslv = 7, ssel = 2, fsd = 1, dce = 1 serial m ode 2 reg 14 reset values: nslv = 1, ssel = 3, fsd = 1, dce = 1 slave1 fsd / slave2 fsyn c slave2 fsd / slave3 fsyn c slave3 fsd / slave4 fsyn c slave4 fsd / slave5 fsyn c slave5 fsd / slave6 fsyn c slave6 fsd / slave7 fsyn c sdi [0] sd i [15..1] sdo [0] sd o[15..1] comments 128 sc lks secondary frame (control) 128 sc lks primary frame (d ata) 16 sc lks master master slave1 slave1 slave1 slave1 master master primary frames with secondary frame req uested via sd i[0] = 1 slave2 slave2 slave3 slave3 slave5 slave5 slave4 slave4 slave6 slave6 slave7 slave7 slave2 slave2 slave3 slave3 slave5 slave5 slave4 slave4 slave6 slave6 slave7 slave7 1 master 1 master 1 slave1 0 slave1 1 slave2 0 slave2 1 slave3 0 slave3 1 slave4 0 slave4 1 slave5 0 slave5 1 slave6 0 slave6 1 slave7 0 slave7 figure 32. daisy chaining of eight daas
SI3056 si3018/19/10 rev. 1.02 45 figure 33. daisy chaining with framed fsync and framed fsd primary frame (d ata) secondary frame (c ontrol) master slave 1 master fsd/ slave1 fsyn c sdi [0] sdi [15..1] sd0 [0] sd0 [15..1] c om m ents prim ary fram es w ith secondary fram e requested via sd i[0] = 1 128 sc lks 128 sc lks 16 sclks master fsync slave1 slave1 slave1 slave1 master master master master 1 slave1 0 slave1 1 master 1 master ser ial m ode 0 r eg 14: n slv = 1, ssel = 2, fsd = 0, d ce = 1 ser ial m ode 2 r eg 14 r eset values: n slv = 1, ssel = 3, fsd = 1, dc e = 1
SI3056 si3018/19/10 46 rev. 1.02 figure 34. typical connection for master/slave operation (e.g., data/fax/voice modem) sclk sdo sdi int0 fsync sclk sdo sdi fsync mclk fc/rgdt rgdt/fsd/m1 sclk sdo sdi fsync mclk mclk host SI3056 si3000 47 k ? 47 k ? 47 k ? +5 v m0 vcc voice codec 47 k ?
SI3056 si3018/19/10 rev. 1.02 47 figure 35. typical connection for multiple daas sclk sdo sdi into fsync sclk sdo sdi fsync mclk fc/rgdt rgdt/fsd/m1 m0 sclk sdo sdi fsync mclk m0 sclk sdo sdi fsync mclk rgdt/fsd/m1 m0 rgdt/fsd/m1 mclk host SI3056?master SI3056?slave 1 SI3056?slave 2 vcc 47 k ? 47 k ? nc nc 47 k ? vcc 47 k ? vcc 47 k ?
SI3056 si3018/19/10 48 rev. 1.02 control registers table 22. register summary register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 control 1 sr pwmm[1:0] pwme idl sb 2 control 2 inte intp wdten al rdi hbe rxe 3 interrupt mask rdtm rovm fdtm btdm dodm lcsom dlcsm polm 4 interrupt source rdti rovi fdti btdi dodi lcsoi dlcsi poli 5 daa control 1 rdtn rdtp opol onhm rdt ohe oh 6 daa control 2 pdl pdn 7 sample rate control src[3:0] 8 pll divide n n[7:0] 9 pll divide m m[7:0] 10 daa control 3 ddl 11 system-side and line-side revision lsid[3:0] reva[3:0] 12 line-side device status fdt lcs[4:0] 13 line-side device revision 0 revb[3:0] 14 interface control nslv[2:0] ssel[1:0] fsd rpol dce 15 tx/rx gain control 1 txm atx[2:0] rxm arx[2:0] 16 international control 1 act2 2 ohs act 2 iire rz rt 17 international control 2 calz mcal cald ope bte rov btd 18 international control 3 rfwe 19 international control 4 ovl dod opd 20 call progress rx attenuation arm[7:0] 21 call progress tx attenuation atm[7:0] 22 ring validation control 1 rdly[1:0] rmx[5:0] 23 ring validation control 2 rdly[2] rto[3:0] rcc[2:0] 24 ring validation control 3 rngv reserved ras[5:0] 25 resistor calibration rcals rcalm rcald reserved rcal[3:0] 26 dc termination control dcv[1:0] mini[1:0] reserved ilim dcr 27 reserved 28 loop current status lcs2[7:0] 29 line voltage status lvs[7:0] 30 ac termination control acim[3:0] 1 31 daa control 4 full 1 foh[1:0] reserved ohs2 reserved filt 1 lvfd 1 32?37 reserved 38 tx gain control 2 tga2 1 txg2[3:0] 1 39 rx gain control 2 rga2 1 rxg2[3:0] 1 40 tx gain control 3 tga3 1 txg3[3:0] 1 41 rx gain control 3 rga3 1 rxg3[3:0] 1 42 reserved 43 line current/voltage threshold interrupt cvt[7:0] 1 44 line current/voltage threshold interrupt control cvi 1 cvs 1 cvm 1 cvp 1 45?52 programmable hybrid register 1?8 hyb1?8[7:0] 53?58 reserved reserved 59 spark quenching control reserved sq1 reserved sq0 reserved notes: 1. bit is available for si 3019 line-side device only. 2. bit is available for si3010 and si3018 line-side device only.
SI3056 si3018/19/10 rev. 1.02 49 reset settings = 0000_0000 register 1. control 1 bitd7d6d5d4d3d2d1d0 name sr pwmm[1:0] pwme idl sb type r/w r/w r/w r/w r/w bit name function 7sr software reset. 0 = enables the daa for normal operation. 1 = sets all registers to their reset value. note: bit automatically clears after being set. 6 reserved read returns zero. 5:4 pwmm[1:0] pulse width modulation mode. used to select the type of signal output on the call progress aout pin. 00 = pwm output is clocked at 16.384 mhz as a delta-sigma data stream. a local density of 1s and 0s tracks the combined transmit and receive signals. 01 = balanced conventional pwm output signal has high and low portions of the modulated pulse that are centered on the 16 khz sample clock. 10 = conventional pwm output signal returns to logic 0 at regular 32 khz intervals and rises at a time in the 32 khz period proportional to its instantaneous amplitude. 11 = reserved. 3pwme pulse width modulation enable. sums the transmit and receive audio paths and pr esents it as a cmos digital-level output of pwm data. use the circuit in ?aout pwm circuit for call progress? . 0 = pulse width modulation signal for aout disabled. 1 = pulse width modulation signal for call progress analog output (aout) enabled. 2 reserved read returns zero. 1idl isolation digital loopback. 0 = digital loopback across the isolation barrier is disabled. 1 = enables digital loopback mode across the isolation barrier. the line-side device must be enabled and off hook before setting this mode. this data path includes the tx and rx filters. 0sb serial digital interface mode. 0 = operation is in 15-bit mode, and the lsb of the data field indicates that a secondary frame is required. 1 = the serial port is operating in 16-bit mode and requires a secondary frame sync signal, fc, to initiate control data reads/writes.
SI3056 si3018/19/10 50 rev. 1.02 reset settings = 0000_0011 register 2. control 2 bitd7d6d5d4d3d2d1d0 name inte intp wdten al rdi hbe rxe type r/w r/w r/w r/w r/w r/w r/w bit name function 7inte interrupt pin enable. 0=the aout/int pin functions as an analog output for call progress monitoring purposes. 1=the aout/int pin functions as a hardware interrupt pin. 6intp interrupt polarity select. 0=the aout/int pin, when used in hardware interrupt mode, is active low. 1=the aout/int pin, when used in hardware interrupt mode, is active high. 5 reserved returns to zero. 4wdten watchdog timer enable. when set, this bit can only be cleared by a hardware reset. the watchdog timer monitors register accesses. if no register accesses occu r within a 4 second window, the daa is put into an on-hook state. a write of a daa register restarts the watchdog timer counter. if the watchdog timer times out, the oh and ohe bits are cleared, placing the daa into an on-hook state. setting the oh bit or setting the ohe bit and asserting the ofhk pin places the daa back into an off-hook state. 0 = watchdog timer disabled. 1 = watchdog timer enabled. 3al analog loopback. 0 = analog loopback mode disabled. 1 = enables external analog loopback mode. 2rdi ring detect interrupt mode. this bit operates in conjunction with the rdtm and rdti bits. this bit is selected if one or two interrupts are generated for every ring burst. 0 = an interrupt is generated at the beginning of every ring burst. 1 = an interrupt is generated at the beginning an d end of every ring burst. the interrupt at the beginning of the ring burst must be serviced (by writing a 0 to the rdti bit) before the end of the ring burst for both interrupts to occur. 1hbe hybrid enable. 0 = disconnects hybrid in transmit path. 1 = connects hybrid in transmit path. 0rxe receive enable. 0 = receive path disabled. 1 = enables receive path.
SI3056 si3018/19/10 rev. 1.02 51 reset settings = 0000_0000 register 3. interrupt mask bitd7d6d5d4d3 d2 d1 d0 name rdtm rovm fdtm btdm dodm lcsom polm type r/w r/w r/w r/w r/w r/w r/w bit name function 7rdtm ring detect mask. 0 = a ring signal does not cause an interrupt on the aout/int pin. 1 = a ring signal causes an interrupt on the aout/int pin. 6rovm receive overload mask. 0 = a receive overload does not cause an interrupt on the aout/int pin. 1 = a receive overload causes an interrupt on the aout/int pin. 5fdtm frame detect mask. 0 = the communications link achieving frame lock does not cause an interrupt on the aout/ int pin. 1 = the communications link achi eving frame lock causes an interrupt on the aout/int pin. 4btdm billing tone detect mask. 0 = a detected billing tone does not cause an in terrupt on the aout/int pin. 1 = a detected billing tone causes an interrupt on the aout/int pin. 3dodm drop out detect mask. 0 = a line supply dropout does not cause an interrupt on the aout/int pin. 1 = a line supply dropout causes an interrupt on the aout/int pin. 2lcsom loop current sense overload mask. 0 = an interrupt does not occur when the lcs bits are all 1s. 1 = an interrupt occurs when the lcs bits are all 1s. 1dlcsm delta loop current sense mask. 0 = an interrupt does not occur when the lcs bits change. 1 = an interrupt does occur when the lcs bits change. 0polm polarity reversal detect mask. generated from bit 7 of the lvs register. when this bit transitions, it indicates that the polarity of tip and ring was switched. 0 = a polarity change on tip and ring does not cause an interrupt on the aout/int pin. 1 = a polarity change on tip and ring causes an interrupt on the aout/int pin.
SI3056 si3018/19/10 52 rev. 1.02 reset settings = 0000_0000 register 4. interrupt source bitd7d6d5d4d3d2d1d0 name rdti rovi fdti btdi dodi lcsoi poli type r/w r/w r/w r/w r/w r/w r/w bit name function 7rdti ring detect interrupt. 0 = a ring signal is not occurring. 1 = a ring signal is detected. if the rdtm (register 3) and inte (register 2) bits are set a hard- ware interrupt occurs on the aout/int pin. this bit must be written to a 0 to be cleared. the rdi bit (register 2) determines if this bit is set only at the beginning of a ring pulse, or at the end of a ring pulse as well. this bit should be cleared af ter clearing the pdl bit (register 6) because pow- ering up the line-side device may cause this interrupt to be triggered. 6rovi receive overload interrupt. 0 = an excessive input level on the receive pin is not occurring. 1 = an excessive input level on the receive pin is detected. if the rovm and inte bits are set a hardware interrupt occurs on the aout/int pin. this bit must be written to 0 to clear it. this bit is identical in function to the rov bit (register 17). clearing this bit also clears the rov bit. 5fdti frame detect interrupt . 0 = frame detect is established on the communications link. 1 = this bit is set when the communications link does not have frame lock. if the fdtm and inte bits are set, a hardware inte rrupt occurs on the aout/int pin. once set, this bit must be written to a 0 to be cleared. 4btdi billing tone detect interrupt. 0 = a billing tone has not occurred. 1 = a billing tone has been detected . if the btdm and inte bits are set, a hardwa re interrupt occurs on the aout/int pin. this bit must be written to 0 to clear it. 3dodi drop out detect interrupt . 0 = the line-side power supply has not collapsed. 1 = the line-side power supply has collapsed. if the dodm and inte bits are set, a hardware interrupt occurs on the aout/int pin. this bit must be written to 0 to be cleared. this bit should be cleared after clearing the pdl bit (register 6) because powering as the line-side device can cause this interrupt to be triggered. 2lcsoi loop current sense overload interrupt . 0 = the lcs bits have not reached max (all ones). 1 = the lcs bits have reached max value. if the lcsom bit (register 3) and the inte bit are set, a hardware interrupt occurs on the aout/int pin. this bit must be written to 0 to clear it. lcsoi does not necessarily imply that an overcu rrent situation has occurred. an overcurrent sit- uation in the daa is determined by the status of the opd bit (register 19). after the lcsoi inter- rupt fires, the opd bit should be checked to determine if an overcurrent situation exists.
SI3056 si3018/19/10 rev. 1.02 53 1 dlcsi delta loop current sense interrupt 0 = the lcs bits have not changed value. 1 = the lcs bits have changed value; a hardware interrupt occurs on the aout/int pin. this bit must be written to a 0 to be cleared. 0 poli polarity reversal detect interrupt. 0 = bit 7 of the lvs register does not change states. 1 = bit 7 of the lvs register changes from a 0 to a 1, or from a 1 to a 0, indicating the polarity of tip and ring is switched. if the polm and inte bits are set, a hardware interrupt occurs on the aout/int pin. to clear the interrupt, write this bit to 0. bit name function
SI3056 si3018/19/10 54 rev. 1.02 reset settings = 0000_0000 register 5. daa control 1 bitd7d6d5d4d3d2d1d0 name rdtn rdtp opol onhm rdt ohe oh type r r r/w r/w r r/w r/w bit name function 7 reserved read returns zero. 6 rdtn ring detect signal negative. 0 = no negative ring signal is occurring. 1 = a negative ring signal is occurring. 5rdtp ring detect signal positive. 0 = no positive ring signal is occurring. 1 = a positive ring signal is occurring. 4opol off-hook polarity. 0 = off-hook pin is active low. 1 = off-hook pin is active high. 3onhm on-hook line monitor. 0 = normal on-hook mode. 1 = enables low-power on-hook monitoring mode allowing the host to receive line activity without going off-hook. this mode is used for caller-id detection. 2 rdt ring detect. 0 = reset either 5 seconds after last positive ri ng is detected or when the system executes an off-hook. only a positive ring sets this bit when rfwe = 0. when rfwe = 1, either a positive or negative ring sets this bit. 1 = indicates a ring is occurring. 1ohe off-hook pin enable. 0 = off-hook pin is ignored. 1 = enables operation of the off-hook pin. 0oh off-hook. 0 = line-side device on-hook. 1 = causes the line-side device to go off-hook. th is bit operates independently of the ohe bit and is a logic or with the off-hook pin when enabled.
SI3056 si3018/19/10 rev. 1.02 55 reset settings = 0001_0000 register 6. daa control 2 bit d7d6d5d4d3d2d1d0 name pdl pdn type r/w r/w bit name function 7:5 reserved read returns zero. 4pdl powerdown line-side device. 0 = normal operation. program the clock generator before clearing this bit. 1 = places the line-side device in lower power mode. 3pdn powerdown system-side device. 0 = normal operation. 1 = powers down the system-s ide device. a pulse on reset is required to restore normal operation. 2:0 reserved read returns zero.
SI3056 si3018/19/10 56 rev. 1.02 reset settings = 0000_0000 register 7. sample rate control bit d7d6d5d4 d3 d2d1d0 name src[3:0] type r/w bit name function 7:4 reserved read returns zero. 3:0 src[3:0] sample rate control. sets the sample rate of the line-side device. 0000 = 7200 hz 0001 = 8000 hz 0010 = 8229 hz 0011 = 8400 hz 0100 = 9000 hz 0101 = 9600 hz 0110 = 10286 hz 0111 = 12000 hz 1000 = 13714 hz 1001 = 16000 hz 1010?1111 = reserved
SI3056 si3018/19/10 rev. 1.02 57 reset settings = 0000_0000 (serial mode 0, 1) reset settings = 0001_0011 (serial mode 2) reset settings = 0000_0000 reset settings = 0000_0000 register 8. pll divide n bit d7d6d5d4d3d2d1d0 name n[7:0] type r/w bit name function 7:0 n[7:0] pll n divider. contains the (value ?1) for determining the output frequency on pll1. register 9. pll divide m bit d7d6d5d4d3d2d1d0 name m[7:0] type r/w bit name function 7:0 m[7:0] pll m divider. contains the (value ?1) for determining the output frequency on pll1. register 10. daa control 3 bit d7d6d5d4 d3 d2 d1 d0 name ddl type r/w bit name function 7:1 reserved read returns zero. 0 ddl digital data loopback. 0 = normal operation. 1 = takes data received on drx and loops it back out to dtx before the tx and rx filters. outputted data is identi cal to inputted data.
SI3056 si3018/19/10 58 rev. 1.02 reset settings = xxxx_xxxx reset settings = 0000_0000 register 11. system- and line-side device revision bit d7d6d5d4d3d2d1d0 name lsid[3:0] reva[3:0] type r r bit name function 7:4 lsid[3:0] line-side id bits. these four bits will always re ad one of the following valu es depending on which line-side device is used. lsid[3:0] si3018 0001 si3019 0011 si3010 0101 3:0 reva[3:0] system-side revision. four-bit value indicating the re vision of the system-side device. register 12. line-side device status bit d7d6d5d4d3d2d1d0 name fdt lcs[4:0] type r r bit name function 7 reserved read returns zero. 6fdt frame detect. 0 = indicates communications link has not established frame lock. 1 = indicates communications link frame lock is established. 5 reserved read returns zero. 4:0 lcs[4:0] loop current sense. 5-bit value returning the loop current when the daa is in an off-hook state. 00000 = loop current is less than required for normal operation. 00100 = minimum loop current for normal operation. 11111 = loop current is >127 ma, and a current overload condition may exist.
SI3056 si3018/19/10 rev. 1.02 59 reset settings = xxxx_xxxx register 13. line-side device revision bit d7d6d5d4d3d2d1d0 name 0 revb[3:0] type r bit name function 7 reserved read returns zero. 6 0 this bit always reads a zero. 5:2 revb[3:0] line-side device revision. four-bit value indicating the revision of the line-side device. 1:0 reserved read returns zero.
SI3056 si3018/19/10 60 rev. 1.02 reset settings = 0000_0000 (serial mode 0,1) reset settings = 0011_1101 (serial mode 2) register 14. serial interface control bitd7d6d5d4d3d2d1d0 name nslv[2:0] ssel[1:0] fsd rpol dce type r/w r/w r/w r/w r/w bit name function 7:5 nslv[2:0] number of slaves devices. 000 = 0 slaves. redefines the fc/rgdt and rgdt /fsd pins. 001 = 1 slave device 010 = 2 slave devices 011 = 3 slave devices 100 = 4 slave devices (for four or more slave devices, the fsd bit must be set.) 101 = 5 slave devices 110 = 6 slave devices 111 = 7 slave devices 4:3 ssel[1:0] slave device select. 00 = 16-bit sdo receive data 01 = reserved 10 = 15-bit sdo receive data, lsb = 1 11 = 15-bit sdo receive data, lsb = 0 2fsd delayed frame sync control. 0 = sets the number of sclk periods between frame syncs to 32. 1 = sets the number of sclk periods between frame syncs to 16. this bit must be set when SI3056 devices are slaves. for th e master SI3056, only serial mode 1 is allowed when this bit is set. 1rpol ring detect polarity. 0=the fc/rgdt pin (operating as ring detect) is active low. 1=the fc/rgdt pin (operating as ring detect) is active high. 0dce daisy-chain enable. 0 = daisy-chaining disabled. 1 = enables the SI3056 to operate with slave dev ices on the same serial bus. the fc/rgdt signal (pin 7) becomes the ring detect output and the rdgt /fsd signal (pin 15) becomes the delayed frame sync signal. all other bits in this register are ignored if dce = 0.
SI3056 si3018/19/10 rev. 1.02 61 reset settings = 0000_0000 register 15. tx/rx mute bitd7d6 d5 d4d3d2d1d0 name txm atx[2:0] rxm arx[2:0] type r/w r/w r/w r/w bit name function 7txm transmit mute. 0 = transmit signal is not muted. 1 = mutes the transmit signal. 6:4 atx[2:0] analog transmit attenuation. 000 = 0 db attenuation 001 = 3 db attenuation 010 = 6 db attenuation 011 = 9 db attenuation 1xx = 12 db attenuation note: write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38?41 available only with the si3019 line-side device. 3rxm receive mute. 0 = receive signal is not muted. 1 = mutes the receive signal. 2:0 arx[2:0] analog receive gain. 000=0db gain 001=3db gain 010=6db gain 011=9db gain 1xx = 12 db gain note: write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38?41 available only with the si3019 line-side device.
SI3056 si3018/19/10 62 rev. 1.02 reset settings = 0000_0000 register 16. inte rnational control 1 bit d7 d6d5d4d3d2d1d0 name act2 ohs act iire rz rt type rw r/w r/w r/w r/w r/w bit name function 7 act2 ac termination select 2 (si3018 line-side device only). works with the act bit to select one of four ac terminations: act2 act ac termination 0 0 real, 600 ? 0 1 global complex impedance 1 0 global complex impedance, except new zealand 1 1 new zealand complex impedance the global complex impedance meets minimum return loss requirements in countries that require a complex ac termination. for improved return loss performance, the other complex impedances can be used. 6ohs on-hook speed. this bit, in combination with the ohs2 bit (regist er 31) and the sq[1:0] bits (register 59), sets the amount of time for the line-side device to go on-hook. the on-hook speeds specified are measured from the time the oh bit is cleared until loop current equals zero. ohs ohs2 sq[1:0] mean on-hook speed 0 0 00 less than 0.5 ms 0 1 00 3 ms 10% (meets etsi standard) 1 x 11 26 ms 10% (meets australia spark quenching spec) 5 act ac termination select. (si3018 line-side device only). when the act2 bit is cleared, t he act bit selects the following: 0 = selects the real ac impedance (600 ?) 1 = selects the global complex impedance. 4 iire iir filter enable. 0 = fir filter enabled for transmit and receiv e filters. see figures 6?9 on page 15. 1 = iir filter enabled for transmit and receive filters. see figures 10?15 on page 16. 3:2 reserved read returns zero. 1rz ringer impedance. 0 = maximum (high) ringer impedance. 1 = synthesized ringer impedance enabled. see "ringer impedance and threshold" on page 29. 0rt ringer threshold select. this bit is used to satisfy country requirements on ring detection. signals below the lower level do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. rt rt lower level rt upper level 013.5 v rms 16.5 v rms 1 19.35 v rms 23.65 v rms
SI3056 si3018/19/10 rev. 1.02 63 reset settings = 0000_0000 register 17. inte rnational control 2 bit d7 d6 d5 d4d3d2d1d0 name calz mcal cald ope bte rov btd type r/w r/w r/w r/w r/w r/w r bit name function 7calz clear adc calibration. 0 = normal operation. 1 = clears the existing calibration data. this bi t must be written back to 0 after being set. 6mcal manual adc calibration. 0 = no calibration. 1 = initiate manual adc calibration. 5cald adc auto-calibration disable. 0 = enable auto-calibration. 1 = disable auto-calibration. 4 reserved read returns zero. 3ope overload protect enable. 0=disabled. 1 = enabled. the ope bit should always be cleared before going off-hook. 2bte billing tone detect enable. when set, the daa can detect a billing tone signal on the line and maintain on off-hook state through the billing tone. if a billing tone is detect ed, the btd bit (register 17) is set to indicate the event. writing this bit to zero clears the btd bit. 0 = billing tone detection disabled . the bdt bit is not function. 1 = billing tone detecti on enabled. the bd t is functional. 1rov receive overload. this bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). writing a zero to this location clears this bit and the rovi bit (register 4, bit 6). 0 = normal receive input level. 1 = excessive receive input level. 0btd billing tone detected. this bit is set if a billing to ne is detected. writing a ze ro to bte clears this bit. 0 = no billing tone detected. 1 = billing tone detected.
SI3056 si3018/19/10 64 rev. 1.02 reset settings = 0000_0000 register 18. inte rnational control 3 bit d7d6d5d4 d3 d2 d1 d0 name rfwe type r/w bit name function 7:2 reserved 1rfwe ring detector full-wave rectifier enable. when rngv (register 24) is disabled, this bit controls the ring detector mode and the asser- tion of the rgdt pin. when rngv is enabled, this bit configures the rgdt pin to either follow the ringing signal detected by the ring validation ci rcuit, or to follow an unqualified ring detect one-shot signal initiated by a ring-threshold cr ossing and terminated by a fixed counter timeout of approximately 5 seconds. rngv rfwe rgdt 00 half-wave 0 1 full-wave 1 0 validated ring envelope 1 1 ring threshold crossing one-shot 0 reserved
SI3056 si3018/19/10 rev. 1.02 65 reset settings = 0000_0000 register 19. inte rnational control 4 bit d7d6d5d4d3d2d1 d0 name ovl dod opd type r r r bit name function 7:3 reserved read returns zero. 2ovl receive overload detect. this bit has the same function as rov in regist er 17, but clears itself after the overload is removed. see ?billing tone dete ction and receive overload? on page 30. this bit is only masked by the off-hook counter and is not affected by the bte bit. 0 = normal receive input level. 1 = excessive receive input level. 1dod recal/dropout detect. when the line-side device is off-hook, it is po wered from the line itself . this bit will read 1 when loop current is not flowing. for example, if the line-derived power supply collapses, such as when the line is disconnected, this bit is set to 1. additionally, when on-hook and the line- side device is enabled, this bit is set to 1. 0 = normal operation. 1 = line supply dropout detected when off-hook. 0opd overload protection detect. this bit is used to indicate that the daa has de tected a loop current overload. the detector fir- ing threshold depends on the setting of the ilim bit (register 26). opd ilim overcurrent threshold overcurrent status 0 0 160 ma no overcurrent condition exists 0 1 60 ma no overcurrent condition exists 1 0 160 ma an overcurrent condition has been detected 1 1 60 ma an overcurrent condition has been detected
SI3056 si3018/19/10 66 rev. 1.02 reset settings = 0000_0000 reset settings = 0000_0000 register 20. call progr ess rx attenuation bit d7 d6 d5 d4 d3 d2 d1 d0 name arm[7:0] type r/w bit name function 7:0 arm[7:0] aout receive path attenuation. when decremented from the default setting, these bits linearly attenuate the aout receive path signal used for call progress monitoring. setting the bits to all 0s mutes the aout receive path. attenuation = 20 log(arm[7:0]/64) 1111_1111 = +12 db (gain) 0111_1111 = +6 db (gain) 0100_0000 = 0 db 0010_0000 = ?6 db (attenuation) 0001_0000 = ?12 db . . . 0000_0000 = mute register 21. call progress transmit attenuation bit d7 d6 d5 d4 d3 d2 d1 d0 name atm[7:0] type r/w bit name function 7:0 atm[7:0] aout transmit path attenuation. when decremented from the default settings, these bits linearly attenuate the aout trans- mit path signal used for call progress monitori ng. setting the bits to all 0s mutes the aout transmit path. attenuation = 20 log(atm[7:0]/64) 1111_1111 = +12 db (gain) 0111_1111 = +6 db (gain) 0100_0000 = 0 db 0010_0000 = ?6 db (attenuation) 0001_0000 = ?12 db . . . 0000_0000 = mute
SI3056 si3018/19/10 rev. 1.02 67 reset settings = 1001_0110 register 22. ring validation control 1 bit d7d6d5 d4 d3d2 d1 d0 name rdly[1:0] rmx[5:0] type r/w r/w bit name function 7:6 rdly[1:0] ring delay bits 1 and 0. these bits, in combination with the rdly[2] bit (register 23), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. rdly[2] rdly[1:0] delay 0000 m s 001 256 m s 010 512 m s . . . 1 11 1792 m s 5:0 rmx[5:0] ring assertion maximum count. these bits set the maximum ring frequency for a valid ring signal within a 10% margin of error. during ring qualification, a timer is loaded with the ras[5:0] field upon a tip/ring event and decrements at a regular rate. when a subsequent tip/ring event occurs, the timer value is compared to the rmx[5:0] field and if it exceeds the value in rmx[5:0] then the frequency of the ring is too high and th e ring is invalidated. the difference between ras[5:0] and rmx[5:0] identifies the minimum duration between tip/ring events to qual- ify as a ring, in binary-coded increments of 2.0 ms (nominal). a tip/ring event typically occurs twice per ring tone period. at 20 hz, tip/ring events would occur every 1/ (2 x 20 hz) = 25 ms. to calculate the correct rm x[5:0] value for a frequency range [f_min, f_max], the following equation should be used: to compensate for error margin and ensure a sufficient ring detection window, it is recom- mended that the calculated value of rmx[5:0] be incremented by 1. rmx 5:0 [] ras 5:0 [] 1 2 f_max 2 ms -------------------------------------------- - rmx ras , ?
SI3056 si3018/19/10 68 rev. 1.02 reset settings = 0010_1101 register 23. ring validation control 2 bitd7d6d5d4d3d2d1d0 name rdly[2] rto[3:0] rcc[2:0] type r/w r/w r/w bit name function 7 rdly[2] ring delay bit 2. this bit, in combination with the rdly[1:0] bits (register 22), set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. rdly[2] rdly[1:0] delay 000 0 m s 001 256 m s 010 512 m s . . . 1 11 1792 m s 6:3 rto[3:0] ring timeout. these bits set when a ring signal is determined to be over after the most recent ring thresh- old crossing. rto[3:0] ring timeout 0000 80 m s 0001 128 m s 0010 256 m s . . . 1111 1920 m s 2:0 rcc[2:0] ring confirmation count. these bits set the amount of time that the ring frequency must be with in the tolerances set by the ras[5:0] bits and the rmx[5:0] bits to be classified as a valid ring signal. rcc[2:0] ring confir mation count time 000 100 m s 001 150 m s 010 200 m s 011 256 m s 100 384 m s 101 512 m s 110 640 m s 111 1024 m s
SI3056 si3018/19/10 rev. 1.02 69 reset settings = 0001_1001 register 24. ring validation control 3 bit d7 d6 d5 d4 d3 d2 d1 d0 name rngv reserved ras[5:0] type r/w r r/w bit name function 7rngv ring validation enable. 0 = ring validation feature is disabled. 1 = ring validation feature is enabled in both normal operating mode and low-power mode. 6 reserved reserved and may read either a 1 or 0. 5:0 ras[5:0] ring assertion time. these bits set the minimum ring frequency for a valid ring signal within a 10% margin of error. during ring qualification, a timer is loaded with the ras[5:0] field upon a tip/ring event and decrements at a regular rate. when a subsequent tip/ring event occurs, the timer value is compared to the rmx[5:0] field and if it exceeds the value in rmx[5:0] then the frequency of the ring is too high and the ring is invalidated. the difference between ras[5:0] and rmx[5:0] identifies the minimum duration between tip/ring events to qual- ify as a ring, in binary-coded increments of 2.0 ms (nominal). a tip/ring event typically occurs twice per ring tone period. at 20 hz, tip/ring events would occur every 1/ (2 x 20 hz) = 25 ms. to calculate the correct rm x[5:0] value for a frequency range [f_min, f_max], the following equation should be used: to compensate for error margin and ensure a sufficient ring detection window, it is recom- mended that the calculated value of rmx[5:0] be incremented by 1. rmx 5:0 [] ras 5:0 [] 1 2f_min 2 ms ------------------------------------------- rmx ras , ?
SI3056 si3018/19/10 70 rev. 1.02 reset settings = xx0x_xxxx register 25. resistor calibration bitd7d6d5 d4 d3d2d1d0 name rcals rcalm rcald reserved rcal[3:0] type r r/w r/w r r/w bit name function 7rcals resistor auto calibration. 0 = resistor calibration is not in progress. 1 = resistor calibration is in progress. 6rcalm manual resistor calibration. 0 = no calibration. 1 = initiate manual resistor calibration. (after a manual calibration has been initiated, this bit must be cleared within 1 ms.) 5 rcald resistor calibration disable. 0 = internal resistor calibration enabled. 1 = internal resistor calibration disabled. 4 reserved do not write to this register bit. this bit always reads a zero. 3:0 rcal[3:0] always write back the value read.
SI3056 si3018/19/10 rev. 1.02 71 reset settings = 0000_0000 register 26. dc termination control bitd7d6d5d4d3d2d1d0 name dcv[1:0] mini[1:0] ilim dcr type r/w r/w r/w r/w bit name function 7:6 dcv[1:0] tip/ring voltage adjust. adjust the voltage on the dct pin of the line-si de device, which affects the tip/ring voltage on the line. low voltage countries should us e a lower tip/ring voltage. raising the tip/ ring voltage improves signal headroom. dcv[1:0] dct pin voltage 00 3.1 v 01 3.2 v 10 3.35 v 11 3.5 v 5:4 mini[1:0] minimum operational loop current. adjusts the minimum loop current so the daa can operate. increasing the minimum opera- tional loop current improves signal he adroom at a lower tip/ring voltage. mini[1:0] min loop current 00 10 ma 01 12 ma 10 14 ma 11 16 ma 3:2 reserved do not write to these register bits. 1 ilim current limiting enable. 0 = current limiting mode disabled. 1 = current limiting mode enabled. limits loop current to a maximum of 60 ma per the tbr21 standard. 0 dcr dc impedance selection. 0=50 ? dc termination is selected. use this mode for all standard applications. 1 = 800 ? dc termination is selected.
SI3056 si3018/19/10 72 rev. 1.02 reset settings = xxxx_xxxx reset settings = 0000_0000 reset settings = 0000_0000 register 27. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not read or write. register 28. loop current status bitd7d6d5d4d3d2d1d0 name lcs2[7:0] type r bit name function 7:0 lcs2[7:0] loop current status. eight-bit value returning the loop current. each bit represents 1.1 ma of loop current. 0000_0000 = loop current is less than required for normal operation. register 29. line voltage status bitd7d6d5d4d3d2d1d0 name lvs[7:0] type r bit name function 7:0 lvs[7:0] line voltage status. eight-bit value returning the loop voltage. each bit represents 1 v of loop voltage. this regis- ter operates in on-hook and off-hook modes. bit se ven of this register indicates the polarity of the tip/ring voltage. when this bit changes stat e, it indicates that a polarity reversal has occurred. the value returned is represented in 2?s compliment. 0000_0000 = no line is connected.
SI3056 si3018/19/10 rev. 1.02 73 reset settings = 0000_0000 register 30. ac termination control (si3019 line-side device only) bitd7d6d5d4d3d2 d1d0 name acim[3:0] type r/w bit name function 7:5 reserved read returns zero. 4:0 acim ac impedance selection (si3019 line-side device only). the off-hook ac termination is selected from the following: 0000 = 600 ? 0001 = 900 ? 0010 = 270 ? + (750 ? || 150 nf) (tbr21) and 275 ? + (780 ? || 150 nf) 0011 = 220 ? + (820 ? || 120 nf) (australia/new zealand) and 220 ? + (820 ? || 115 nf) (slovakia/slovenia/south afri ca/germany/austria/bulgaria) 0100 = 370 ? + (620 ? || 310 nf) (new zealand #2/india) 0101 = 320 ? + (1050 ? || 230 nf) (england) 0110 = 370 ? + (820 ? || 110 nf) 0111 = 275 ? + (780 ? || 115 nf) 1000 = 120 ? + (820 ? || 110 nf) 1001 = 350 ? + (1000 ? || 210 nf) 1010 = 0 ? + (900 ? || 30 nf) 1011 = 600 ? + 2.16 f 1100 = 900 ? + 1 f 1101 = 900 ? + 2.16 f 1110 = 600 ? + 1 f 1111 = global impedance
SI3056 si3018/19/10 74 rev. 1.02 reset settings = 0010_0000 register 31. daa control 3 bitd7d6d5d4d3d2d1d0 name full foh[1:0] ohs2 filt lvfd type r/w r/w r/w r/w r/w bit name function 7full full scale transmit and receive m ode (si3019 line-side device only). 0=default. 1 = transmit/receive full scale. this bit changes the full scale of the adc and dac from 0 min to +3.2 dbm into a 600 ? load (or 1 dbv into all reference impedances). when this bit is set, the dcv[1:0] bits (register 26) should be set to all 1s to avoid distortion at low loop currents. 6:5 foh[1:0] fast off-hook selection. these bits determine the length of the off- hook counter. the default setting is 128 ms. 00 = 512 ms. 01 = 128 ms. 10 = 64 ms. 11 = 8 ms. 3ohs2 on-hook speed 2. this bit, in combination with the ohs bit (register 16) and the sq[1:0] bits on-hook speeds specified are measured from the time the oh bit is cleared until loop current equals zero. ohs ohs2 sq[1:0] mean on-hook speed 0 0 00 less than 0.5 ms 0 1 00 3 ms 10% (meets etsi standard) 1 x 11 26 ms 10% (meets australia spark quenching spec) 4,2 reserved read returns zero. 1filt filter pole selection (si3019 line-side device only). 0 = the receive path has a low ?3 dbfs corner at 5 hz. 1 = the receive path has a low ?3 dbfs corner at 200 hz. 0lvfd line voltage force disable (s i3019 line-side device only). 0 = normal operation. 1 = the circuitry that forces the lvs register (register 29) to all 0s at 3 v or less is disabled. the lvs register may display unpredictable values at voltages between 0 to 2 v. all 0s are displayed if the line voltage is 0 v.
SI3056 si3018/19/10 rev. 1.02 75 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 32. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 33. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 34. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero.
SI3056 si3018/19/10 76 rev. 1.02 reset settings = 0000_0000 reset settings = 0000_0000 reset settings = 0000_0000 register 35. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 36. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 37. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero.
SI3056 si3018/19/10 rev. 1.02 77 reset settings = 0000_0000 register 38. tx gain control 2 (si3019 line-side device only) bitd7d6d5d4d3d2d1d0 name tga2 txg2[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4tga2 transmit gain or attenuation 2. 0 = incrementing the txg2[3:0] bits results in gaining up the transmit path. 1 = incrementing the txg2[3:0] bits results in attenuating the transmit path. 3:0 txg2[3:0] transmit gain 2. each bit increment represents 1 db of gain or attenuation, up to a maximum of +12 db and ? 15 db respectively. for example: tga2 txg2[3:0] result x 0000 0 db gain or attenuation is applied to the transmit path. 0 0001 1 db gain is applied to the transmit path. 0 : 0 11xx 12 db gain is applied to the transmit path. 1 0001 1 db attenuation is ap plied to the transmit path. 1 : 1 1111 15 db attenuation is applied to the transmit path.
SI3056 si3018/19/10 78 rev. 1.02 reset settings = 0000_0000 register 39. rx gain control 2 (si3019 line-side device only) bitd7d6d5d4d3d2d1d0 name rga2 rxg2[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4rga2 receive gain or attenuation 2. 0 = incrementing the rxg2[3:0] bits results in gaining up the receive path. 1 = incrementing the rxg2[3:0] bits results in attenuating the receive path. 3:0 rxg2[3:0] receive gain 2. each bit increment represents 1 db of gain or attenuation, up to a maximum of +12 db and ? 15 db respectively. for example: rga2 rxg2[3:0] result x 0000 0 db gain or attenuation is applied to the receive path. 0 0001 1 db gain is applied to the receive path. 0 : 0 11xx 12 db gain is applied to the receive path. 1 0001 1 db attenuation is applied to the receive path. 1 : 1 1111 15 db attenuation is applied to the receive path.
SI3056 si3018/19/10 rev. 1.02 79 reset settings = 0000_0000 register 40. tx gain control 3 (si3019 line-side device only) bitd7d6d5d4d3d2d1d0 name tga3 txg3[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4tga3 transmit gain or attenuation 3. 0 = incrementing the txg3[3:0] bits results in gaining up the transmit path. 1 = incrementing the txg3[3:0] bits results in attenuating the transmit path. 3:0 txg3[3:0] transmit gain 3. each bit increment represents 0.1 db of gain or attenuation, up to a maximum of 1.5 db. for example: tga3 txg3[3:0] result x 0000 0 db gain or attenuation is applied to the transmit path. 0 0001 0.1 db gain is appli ed to the transmit path. 0 : 0 1111 1.5 db gain is appli ed to the transmit path. 1 0001 0.1 db attenuation is applied to the transmit path. 1 : 1 1111 1.5 db attenuation is applied to the transmit path.
SI3056 si3018/19/10 80 rev. 1.02 reset settings = 0000_0000 register 41. rx gain control 3 (si3019 line-side device only) bitd7d6d5d4d3d2d1d0 name rga3 rxg3[3:0] type r/w r/w bit name function 7:5 reserved read returns zero. 4rga3 receive gain or attenuation 2. 0 = incrementing the rxg3[3:0] bits results in gaining up the receive path. 1 = incrementing the rxg3[3:0] bits results in attenuating the receive path. 3:0 rxg3[3:0] receive gain 3. each bit increment represents 0.1 db of gain or attenuation, up to a maximum of 1.5 db. for example: rga3 rxg3[3:0] result x 0000 0 db gain or attenuation is applied to the receive path. 0 0001 0.1 db gain is applied to the receive path. 0 : 0 1111 1.5 db gain is applied to the receive path. 1 0001 0.1 db attenuation is applied to the receive path. 1 : 1 1111 1.5 db attenuation is applied to the receive path.
SI3056 si3018/19/10 rev. 1.02 81 reset settings = 0000_0000 reset settings = 0000_0000 register 42. reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. register 43. line current / voltage interrupt threshold (si3019 line-side device only) bit d7 d6 d5 d4 d3 d2 d1 d0 name cvt[7:0] type r/w bit name function 7:0 cvt[7:0] current/voltage threshold. determines the threshold at which an interrupt is generated from either the lcs or lvs regis- ter. generate this interrupt to occur when the line current or line voltage rises above or drops below the value in the cvt[7:0] register.
SI3056 si3018/19/10 82 rev. 1.02 reset settings = 0000_0000 register 44. line current/voltage interrupt control (si3019 line-side device only) bit d7 d6 d5 d4 d3 d2 d1 d0 name cvi cvs cvm cvp type r/w r/w r/w r/w bit name function 7:4 reserved read returns zero. 3cvi current/voltage interrupt. 0 = the current / voltage threshold has not been crossed. 1 = the current / voltage threshold is crossed. if the cvm and inte bits are set, a hardware interrupt occurs on the aout/int pin. once set, this bit must be written to 0 to be cleared. 2cvs current/voltage select. 0 = the line current shown in the lcs2 register generates an interrupt. 1 = the line voltage shown in the lvs register generates an interrupt. 1cvm current/voltage interrupt mask. 0 = the current / voltage threshold being triggered does not cause a hardware interrupt on the aout/int pin. 1 = the current / voltage threshold being triggered causes a hardware interrupt on the aout/ int pin. 0cvp current/voltage interrupt polarity. 0 = the current / voltage threshold is triggered by the absolute value of the number in either the lcs2 or lvs register falling belo w the value in the cvt[7:0] register. 1 = the current / voltage threshold is triggered by the absolute value of the number in the either the lcs2 or lvs register rising above the value in the cvt[7:0] register.
SI3056 si3018/19/10 rev. 1.02 83 reset settings = 0000_0000 reset settings = 0000_0000 register 45. programmable hybrid register 1 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb1[7:0] type r/w bit name function 7:0 hyb1[7:0] programmable hybrid register 1. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on th e hybrid response. see "transhybrid balance" on page 28 for more information on selecting coefficients for the programmable hybrid. register 46. programmable hybrid register 2 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb2[7:0] type r/w bit name function 7:0 hyb2[7:0] programmable hybrid register 2. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the second tap in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. see "transhybrid bal- ance" on page 28 for more information on selecting coefficients for the programmable hybrid.
SI3056 si3018/19/10 84 rev. 1.02 reset settings = 0000_0000 reset settings = 0000_0000 register 47. programmable hybrid register 3 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb3[7:0] type r/w bit name function 7:0 hyb3[7:0] programmable hybrid register 3. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the third t ap in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. see "transhybrid bal- ance" on page 28 for more information on selecting coefficients for the programmable hybrid. register 48. programmable hybrid register 4 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb4[7:0] type r/w bit name function 7:0 hyb4[7:0] programmable hybrid register 4. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the fourth tap in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. see "transhybrid bal- ance" on page 28 for more information on selecting coefficients for the programmable hybrid.
SI3056 si3018/19/10 rev. 1.02 85 reset settings = 0000_0000 reset settings = 0000_0000 register 49. programmable hybrid register 5 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb5[7:0] type r/w bit name function 7:0 hyb5[7:0] programmable hybrid register 5. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the fifth ta p in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on th e hybrid response. see "transhybrid balance" on page 28 for more information on selecting coefficients for the programmable hybrid. register 50. programmable hybrid register 6 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb6[7:0] type r/w bit name function 7:0 hyb6[7:0] programmable hybrid register 6. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the sixth ta p in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. see"transhybrid balance" on page 28 for more information on selecting coefficients for the programmable hybrid.
SI3056 si3018/19/10 86 rev. 1.02 reset settings = 0000_0000 reset settings = 0000_0000 register 51. programmable hybrid register 7 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb7[7:0] type r/w bit name function 7:0 hyb7[7:0] programmable hybrid register 7. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the seventh tap in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. see "transhybrid bal- ance" on page 28 for more information on selecting coefficients for the programmable hybrid. register 52. programmable hybrid register 8 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb8[7:0] type r/w bit name function 7:0 hyb8[7:0] programmable hybrid register 8. these bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the eighth tap in the 8-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. see"transhybrid balance" on page 28 for more information on selecting coefficients for the programmable hybrid.
SI3056 si3018/19/10 rev. 1.02 87 reset settings = xxxx_xxxx reset settings = xxxx_xxxx reset settings = xxxx_xxxx register 53. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits. register 54. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits. register 55. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits.
SI3056 si3018/19/10 88 rev. 1.02 reset settings = xxxx_xxxx reset settings = xxxx_xxxx reset settings = xxxx_xxxx register 56. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits. register 57. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits. register 58. reserved bit d7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved do not write to these register bits.
rev. 1.02 89 SI3056 si3018/19/10 reset settings = xxxx_xxxx register 59. spark quenching control bitd7d6d5d4d3d2d1d0 name sq1 sq0 type r/w r/w register 59. spark quenching control bit name function 7 reserved always write this bit to zero. 6, 4 sq[1:0] spark quenching. these bits, in combination with the ohs bit (register 16), and the ohs2 bit (register 31), set the amount of time for the line-side device to go on-hook. the on-hook speeds specified are measured from the time the oh bit is cleared until loop current equals zero. ohs ohs2 sq[1:0] mean on-hook speed 0 0 00 less than 0.5 ms 0 1 00 3 ms10% (meets etsi standard) 1 x 11 26 ms 10% (meets australia spark quenching spec) 5 reserved always write this bit to zero. 3:0 reserved always write these bits to zero.
90 rev. 1.02 SI3056 si3018/19/10 a ppendix ?ul1950 3 rd e dition although designs using the SI3056 comply with ul1950 3rd edition and pass all overcurrent and overvoltage tests, there are still seve ral issues to consider. figure 36 shows two designs that can pass the ul1950 overvoltage tests, and electromagnetic emissions. the top schematic of figure 36 shows the configuration in which the ferrite beads (fb1, fb2) are on the unprotected side of the sidactor (rv1). for this configuration, the current rating of the ferrite beads needs to be 6 a. however, the higher current ferrite beads are less effective in reducing electromagnetic emissions. the bottom schematic of figure 36 shows the configuration in which the ferrite beads (fb1, fb2) are on the protected side of the sidactor (rv1). for this design, the ferrite beads can be rated at 200 ma. in a cost optimized design, compliance to ul1950 does not always require overvoltage tests. plan ahead to know which overvoltage tests apply to the system. system-level elements in th e construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. consult with a professional testing agency during the design of the product to determine the tests that apply to the system. figure 36. circuits that pass all ul1950 overvoltage tests rv1 rv1 c8 fb1 fb2 tip ring tip ring fb1 fb2 75 ? @ 100 mhz, 6 a 75 ? @ 100 mhz, 6 a 600 ? at 100 mhz, 200 ma 600 ? at 100 mhz, 200 ma c9 1.25 a 1.25 a c8 c9
SI3056 si3018/19/10 rev. 1.02 91 pin descriptions: SI3056 table 23. SI3056 pin descriptions pin # pin name description 1mclk master clock input. high speed master clock in put. generally supplied by the system crystal clock or modem/dsp. 2fsync frame sync output. data framing signal that indicates the start and stop of a communication/data frame. 3sclk serial port bit clock output. controls the serial data on sdo and latches the data on sdi. 4v d digital supply voltage. provides the 3.3 v digital supply voltage to the SI3056. 5sdo serial port data out. serial communication data that is provided by the SI3056 to the modem/dsp. 6sdi serial port data in. serial communication and control data that is generated by the modem/dsp and pre- sented as an input to the SI3056. 7 fc/rgdt secondary transfer request input/ring detect. an optional signal to instruct the SI3056 that control data is being requested in a sec- ondary frame. when daisy chain is enabled, this pin becomes the ring detect output. produces an active low rectified version of the ring signal. 8 reset reset input. an active low input that resets all control r egisters to a defined, initialized state. also used to bring the SI3056 out of sleep mode. 9c2a isolation capacitor 2a. connects to one side of the isolation capa citor c2. used to communicate with the line- side device. 10 c1a isolation capacitor 1a. connects to one side of the isolation capa citor c1. used to communicate with the line- side device. fc/rgdt 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 mclk fsync sclk v d sdo sdi reset ofhk rgdt/fsd/m1 m0 v a gnd aout/int c1a c2a
SI3056 si3018/19/10 92 rev. 1.02 11 aout/int analog speaker out/mode select 1. provides an analog output signal for driv ing a call progress speaker or a hardware interrupt for multiple sources of interrupts. 12 gnd ground. connects to the system digital ground. 13 v a analog supply voltage. provides the analog supply voltage for the SI3056. 14 m0 mode select 0. the first of two mode select pins that selects the operation of the serial port/dsp inter- face. 15 rgdt /fsd/m1 ring detect/delayed frame sync/mode select 1. output signal that indicates the status of a ri ng signal. produces an active low rectified version of the ring signal. when daisy chain is enabled, this signal becomes a delayed frame sync to drive a slave device. it is al so the second of two mode select pins that selects the operation of the serial port/dsp interface when reset is deasserted. 16 ofhk off-hook/interrupt. an active low input control signal that provides a termination across tip and ring for line seizing and pulse dialing, table 23. SI3056 pin descriptions (continued) pin # pin name description
SI3056 si3018/19/10 rev. 1.02 93 pin descriptions: si3018/19 table 24. si3018/19 pin descriptions pin # pin name description 1qe transistor emitter. connects to the emitter of q3. 2 dct dc termination. provides dc termination to the telephone network. 3rx receive input. serves as the receive side input from the telephone network. 4ib isolation capacitor 1b. connects to one side of isolation capacitor c1. used to communicate with the system- side device. 5c1b internal bias. provides internal bias. 6c2b isolation capacitor 2b. connects to one side of the isolation capacitor c2. used to communicate with the system-side device. 7vreg voltage regulator. connects to an external capacitor to provide bypassing for an internal power supply. 8rng1 ring 1. connects through a resistor to the ring lead of the telephone line. provides the ring and caller id signals to the system-side device. 9rng2 ring 2. connects through a resistor to the tip lead of the telephone line. provides the ring and caller id signals to the system-side device. 10 vreg2 voltage regulator 2. connects to an external capacitor to provide bypassing for an internal power supply. 11 sc circuit enable. enables transistor network. should be tied through a 0 ? resistor to i gnd . 12 qe2 transistor emitter 2. connects to the emitter of transistor q4. 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 qe dct rx ib c1b c2b vreg rng1 dct2 ignd dct3 qb qe2 sc vreg2 rng2
SI3056 si3018/19/10 94 rev. 1.02 13 qb transistor base. connects to the base of transistor q4. 14 dct3 dc termination 3. provides dc termination to the telephone network. 15 ignd isolated ground. connects to ground on the line-side interface. 16 dct2 dc termination 2. provides dc termination to the telephone network. table 24. si3018/19 pin descriptions (continued) pin # pin name description
SI3056 si3018/19/10 rev. 1.02 95 ordering guide chipset region interface digital (soic) line (soic) digital (tssop) line (tssop) temperature si3034 global dsp serial i/f si3021-ks si3014-ks si3021-kt si3014-kt 0 to 70 c si3035 fcc/japan dsp serial i/f si3021-ks si3012-ks si3021-kt si3012-kt 0 to 70 c si3044 enhanced global dsp serial i/f si3021-ks si3015-ks 0 to 70 c si3044 enhanced global dsp serial i/f si3021-bs si3015-bs ?40 to 85 c si3050/19 enhanced global pcm/spi or gci si3019-ks si3050-kt si3019-kt 0 to 70 c si3050/18 global pcm/spi or gci si3018-ks si3050-kt si3018-kt 0 to 70 c SI3056/18 global dsp serial i/f SI3056-ks si3018-ks si3018-kt 0 to 70 c SI3056/19 enhanced global dsp serial i/f SI3056-ks si3019-ks si3019-kt 0 to 70 c SI3056/10 low-speed global dsp serial i/f SI3056-ks si3010-ks 0 to 70 c note: many of the above devices are available in lead-free packages. for lead-free parts, the ?k? in the part number suffix is replaced with an ?f?.
SI3056 si3018/19/10 96 rev. 1.02 evaluation board ordering guide part number line-side device platform intended use includes platform board? includes daa daughter card? SI3056ppt-evb si3018 parallel port direct connection to a pc to use with included windows ? - based sw program. yes (ppt) yes SI3056ppt1-evb si3019 parallel port SI3056ppt2-evb si3010 parallel port SI3056ssi-evb si3018 serial interface with buffer direct connection to processor or dsp (in customer application or to another evb). yes (ssi) yes SI3056ssi1-evb si3019 serial interface with buffer SI3056ssi2-evb si3010 serial interface with buffer SI3056dc-evb si3018 daughtercard only direct connection to processor or dsp (in customer applica- tion). no yes SI3056dc1-evb si3019 daughtercard only SI3056dc2-evb si3010 daughtercard only
SI3056 si3018/19/10 rev. 1.02 97 product selection and identification guide product identification the product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number. example: part designators (partial list) ks?standard temperature range fs?standard temperature range, lead-free bs?extended temperature range r?tape and reel packing xs?customer-specific part evb?evaluation board device finished goods part number description marking SI3056 SI3056-ks commercial part fg part # SI3056 SI3056-fs commercial part, lead-free version fg part # SI3056 SI3056-xs4 customer-specific bond option custom SI3056 SI3056-zs4 customer-specific bond option, lead-free version custom SI3056 SI3056-xs5 customer-specific bond option custom SI3056 SI3056-zs5 customer-specific bond option, lead-free version custom SI3056 SI3056-xs8 customer-specific bond option custom SI3056 SI3056-zs4 customer-specific bond option, lead-free version custom si3018-ks part designator: temperat ure, packing, product, etc. part number identifier product family silicon laboratories inc.
SI3056 si3018/19/10 98 rev. 1.02 soic package outline figure 37 illustrates the package details for the daa. table 25 lists the valu es for the dimensions shown in the illustration. figure 37. 16-pin small outline integrated circuit (soic) package table 25. package diagram dimensions symbol millimeters min max a1.351.75 a1 .10 .25 b.33.51 c.19.25 d 9.80 10.00 e3.804.00 e 1.27 bsc ? h5.806.20 h.25.50 l .40 1.27 ?0.10 0o 8o e h a1 b c h l e see detail f detail f a 16 9 8 1 d seating plane
SI3056 si3018/19/10 rev. 1.02 99 document change list revision 0.2 to revision 0.71 updated list of applications on cover page, including ability to suppor t v.92 modems. updated transmit full scale level test condition and note in table 4 (ac characteristics) for description of vcid and drcid. updated specifications in table 7, table 8, and table 9 (switching characteristics) and figure 3, figure 4, and figure 5. updated ?bill of materials? with revised values for c3, (10% to 20% tolerance relaxation on same value cap) q4-5 (voltage rating was misstated at 60 v, changed to correct 80 v value), r51-52 power rating relaxed from 1/10 w to 1/16 w, and updated recommended ferrite bead part numbers. fixed several grammatical errors in functional descriptions, and globally replaced all instances of ctr21 with tbr21. added new functional description ?upgrading from the si3034/35/44 to SI3056? to describe new features and changes to consider when migrating to the SI3056. updated ?power supplies? functional description to reflect 5 v tolerance on SI3056 input pins. updated ?transmit/receive full scale level (si3019 line-side only)? functional description. updated?line voltage/loop current sensing? functional description. updated ?ring validation? functional description. updated ?type ii caller id? functional description. updated ?gain control? functional description. updated ?digital interface? functional description and figure 28. updated ?power management? functional description to qualify description to qualify wake-on-ring support in low-power sleep mode. updated ?in-circuit testing? functional description. updated ?transmit/receive full scale level (si3019 line-side only)? functional description. updated ?line voltage measurement? functional description. updated ?interrupts? functional description. updated ?dc termination? functional description. updated ?control registers? to reflect lvfd bit available exclusively with the si3019 line-side. updated the following bit descriptions: r4.7 r12.4?0 r14.2 r17.4 r20-21 r28 r29 r31.0,3,7 r38?41 updated ?ordering guide.? added list of support documentation. revision 0.71 to revision 1.0 added si3010 to data sheet title, and to line-side device support functional description, and application circuit. updated tables 2, 3, & 4 based on production test results. updated table 4 with footnotes to explain expected dr and thd when using the SI3056 with the si3010 low-speed line-side device. updated bom. updated country specific register settings. updated the following functional descriptions: line voltage/loop current sensing interrupts dc termination ring detection ring validation ringer impedance and threshold caller id overload detection gain control (added diagram) power management revision identification updated register summary updated the following register descriptions register 1 bit 1 register 3 bit 1 (added bit description) register 4 bit 1 (added bit description) register 5 bit 2 register 12 bits 4:0 register 13 bit 6 register 16 bit 0 register 18 bit 1 register 19 bit 1 register 24 bits 5:0 register 31 bit 7 updated ordering guide added evaluation board ordering guide
SI3056 si3018/19/10 100 rev. 1.02 revision 1.0 to revision 1.01 removed ?confidential? watermark. revision 1.01 to revision 1.02 updated table 2, ?loop characteristics,? on page 6. updated table 4, ?ac characteristics,? on page 8 updated "bill of materials" on page 18 added optional caller id circuit components in footnotes. removed r14. updated line voltage/loop current sensing functional description. updated "ordering guide" on page 95. updated "soic package outline" on page 98. updated table 25, ?package diagram dimensions,? on page 98.
SI3056 si3018/19/10 rev. 1.02 101 silicon laboratories ? SI3056 support documentation application note 13: silicon daa software guidelines application note 16: multiple device support application note 17: designing for international safety compliance application note 67: layout guidelines application note 72: ring detection/validation with the si305x daas application note 84: digital hybrid with the si305x daas si30xxppt-evb data sheet si30xxssi-evb data sheet note: refer to www.silabs.com for a current list of support documents for this chipset.
SI3056 si3018/19/10 102 rev. 1.02 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, are trademarks of silicon laboratories inc. other products or brand names mentioned herein are trademark s or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon labor atories assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and specifically di sclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of SI3056

	To Download SI3056 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .