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  3/97 block diagram complementary outputs practical operation switching frequencies to 1mhz 50ns propagation delay to output high current dual totem pole outputs (1.5a peak) wide bandwidth error amplifier fully latched logic with double pulse suppression pulse-by-pulse current limiting soft start / max. duty cycle control under-voltage lockout with hysteresis low start up current (1.1 ma) trimmed bandgap reference (5.1v 1%) the uc1824 family of pwm control ics is optimized for high fre- quency switched mode power supply applications. particular care was given to minimizing propagation delays through the comparators and logic circuitry while maximizing bandwidth and slew rate of the error amplifier. this controller is designed for use in either current- mode or voltage mode systems with the capability for input voltage feed-forward. protection circuitry includes a current limit comparator with a 1v threshold, a ttl compatible shutdown port, and a soft start pin which will double as a maximum duty cycle clamp. the logic is fully latched to provide jitter free operation and prohibit multiple pulses at an out- put. an under-voltage lockout section with 800mv of hysteresis as- sures low start up current. during under-voltage lockout, the outputs are high impedance. these devices feature totem pole outputs designed to source and sink high peak currents from capacitive loads, such as the gate of a power mosfet. the on state is designed as a high level. uc1824 uc2824 uc3824 high speed pwm controller features description udg-92034-1
connection diagrams dil-16 (top view) j or n package soic-16 (top view) dw package uc1824 uc2824 uc3824 electrical characteristics: unless otherwise stated,these specifications apply for , r t = 3.65k, c t = 1nf, v cc = 15v, -55 c uc1824 uc3824 parameters test conditions uc2824 min typ max min typ max units oscillator section (cont.) clock out high 3.9 4.5 3.9 4.5 v clock out low 2.3 2.9 2.3 2.9 v ramp peak * 2.6 2.8 3.0 2.6 2.8 3.0 v ramp valley * 0.7 1.0 1.25 0.7 1.0 1.25 v ramp valley to peak * 1.6 1.8 2.0 1.6 1.8 2.0 v error amplifier section input offset voltage 10 15 mv input bias current 0.6 3 0.6 3 m a input offset current 0.1 1 0.1 1 m a open loop gain 1v < v o < 4v 60 95 60 95 db cmrr 1.5v < v cm < 5.5v 75 95 75 95 db psrr 10v < v cc < 30v 85 110 85 110 db output sink current v pin 3 = 1v 12.5 12.5 ma output source current v pin 3 = 4v -0.5 -1.3 -0.5 -1.3 ma output high voltage i pin 3 = -0.5ma 4.0 4.7 5.0 4.0 4.7 5.0 v output low voltage i pin 3 = 1ma 0 0 .5 1.0 0 0.5 1.0 v unity gain bandwidth * 35.5 35.5 mhz slew rate * 612 612 v/ m s pwm comparator section pin 7 bias current v pin 7 = 0v -1 -5 -1 -5 m a duty cycle range 0 80 0 85 % pin 3 zero dc threshold v pin 7 = 0v 1.1 1.25 1.1 1.25 v delay to output * 50 80 50 80 ns soft-start section charge current v pin 8 = 0.5v 3 9 20 3 9 20 m a discharge current v pin 8 = 1v 1 1 ma current limit / shutdown section pin 9 bias current 0 < v pin 9 < 4v 15 10 m a current limit threshold 0.9 1.0 1.1 0.9 1.0 1.1 v shutdown threshold 1.25 1.40 1.55 1.25 1.40 1.55 v delay to output 50 80 50 80 ns output section output low level i out = 20ma 0.25 0.40 0.25 0.40 v i out = 200ma 1.2 2.2 1.2 2.2 v output high level i out = -20ma 13.0 13.5 13.0 13.5 v i out = -200ma 12.0 13.0 12.0 13.0 v collector leakage v c = 30v 100 500 10 500 m a rise/fall time * cl = 1nf 3060 3060ns under-voltage lockout section start threshold 8.8 9.2 9.6 8.8 9.2 9.6 v uvlo hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 v supply current section start up current v cc = 8v 1.1 2.5 1.1 2.5 ma icc v pin 1 , v pin 7 , v pin 9 = 0v; v pin 2 = 1v 22 33 22 33 ma unless otherwise stated,these specifications apply for , r t = 3.65k, c t = 1nf, v cc = 15v, -55 c high speed circuits demand careful attention to layout and component placement. to assure proper performance of the uc1824 follow these rules: 1) use a ground plane. 2) damp or clamp parasitic inductive kick energy from the gate of driven mosfets. do not allow the output pins to ring below ground. a series gate resistor or a shunt 1 amp schottky diode at the output pin will serve this purpose. 3) bypass v cc , v c , and v ref . use 0.1 m f monolithic ceramic capacitors with low equivalent series inductance. allow less than 1 cm of total lead length for each capacitor be- tween the bypassed pin and the ground plane. 4) treat the timing capacitor, c t , like a bypass capacitor. uc1824 uc2824 uc3824 open loop frequency response unity gain slew rate simplified schematic error amplifier circuit synchronized operation uc1824 printed circuit board layout considerations two units in close proximity generalized synchronization 4
oscillator circuit uc1824 uc2824 uc3824 m primary output deadtime vs c t (3k r t 100k) timing resistance vs frequency 80 100 120 140 160 10k 100k 470pf 1.0nf 1m freq (hz) t (ns) d primary output deadtime vs frequency tc () t (ns) no 0 10 20 30 40 50 60 70 80 -75 -50 -25 0 25 50 75 100 125 typical non-overlap time (t no ) over temperature non-overlap time (t no ) 5
uc1824 uc2824 uc3824 forward technique for off-line voltage mode application constant volt-second clamp circuit the circuit shown here will achieve a constant volt-sec- ond product clamp over varying input voltages. the ramp generator components, r t and c r are chosen so that the ramp at pin 9 crosses the 1v threshold at the same time the desired maximum volt-second product is reached. the delay through the functional nor block must be such that the ramp capacitor can be com- pletely discharged during the minimum deadtime. output section simplified schematic rise/fall time (c l =1nf) rise/fall time (c l =10nf) saturation curves 6
uc1824 uc2824 uc3824 open loop laboratory test fixture udg-92036-2 this test fixture is useful for exercising many of the uc1824s functions and measuring their specifications. as with any wideband circuit, careful grounding and by- pass procedures should be followed. the use of a ground plane is highly recommended. unitrode corporation 7 continental blvd. merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 7
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated


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