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intel ? e7500 chipset datasheet intel ? e7500 memory controller hub (mch) february 2002 document number: 290730-001
2 datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? e7500 chipset mch component may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. iintel, intel netburst and the intel logo are trademarks or registered trademarks of intel corporation or its subsidiaries in t he united states and other countries. *other names and brands may be claimed as the property of others. copyright? 2002, intel corporation
datasheet 3 contents 1 introduction ................................................................................................................11 1.1 glossary of terms ...............................................................................................11 1.2 reference documents.........................................................................................12 1.3 intel ? e7500 chipset system architecture..........................................................12 1.3.1 intel ? 82801ca i/o controller hub 3-s (ich3-s)...................................13 1.3.2 intel ? 82870p2 pci/pci-x 64-bit hub 2 (p64h2)...................................14 1.4 intel ? e7500 mch overview...............................................................................14 1.4.1 processor system interface ...................................................................15 1.4.2 main memory interface...........................................................................15 1.4.3 hub interface_a (hi_a) ..........................................................................15 1.4.4 hub interface_b?d (hi_b?d).................................................................16 1.4.5 mch clocking ........................................................................................16 1.4.6 smbus interface.....................................................................................16 2 signal description ...................................................................................................17 2.1 system bus interface signals .............................................................................19 2.2 ddr channel a signals ......................................................................................22 2.3 ddr channel b signals ......................................................................................23 2.4 hub interface_a signals......................................................................................24 2.5 hub interface_b signals......................................................................................25 2.6 hub interface_c signals .....................................................................................26 2.7 hub interface_d signals .....................................................................................27 2.8 clocks, reset, power, and miscellaneous signals .............................................28 2.9 pin states during and after reset ......................................................................28 3 register description ...............................................................................................31 3.1 register terminology ..........................................................................................31 3.2 platform configuration.........................................................................................32 3.3 general routing configuration accesses ...........................................................33 3.3.1 standard pci configuration mechanism ................................................33 3.3.2 logical pci bus 0 configuration mechanism .........................................34 3.3.3 primary pci downstream configuration mechanism .............................34 3.3.4 hi_b, hi_c, hi_d bus configuration mechanism ..................................34 3.4 sticky registers...................................................................................................35 3.5 i/o mapped registers .........................................................................................35 3.5.1 conf_addr?configuration address register ...................................35 3.5.2 conf_data?configuration data register..........................................36 3.6 dram controller registers (device 0, function 0).............................................37 3.6.1 vid?vendor identification register (d0:f0) .........................................38 3.6.2 did?device identification register (d0:f0) ..........................................38 3.6.3 pcicmd?pci command register (d0:f0) ..........................................39 3.6.4 pcists?pci status register (d0:f0) ..................................................40 3.6.5 rid?revision identification register (d0:f0) .......................................41 3.6.6 subc?sub-class code register (d0:f0) ............................................41 3.6.7 bcc?base class code register (d0:f0).............................................41 3.6.8 mlt?master latency timer register (d0:f0) ......................................42
4 datasheet 3.6.9 hdr?header type register (d0:f0).................................................... 42 3.6.10 svid?subsystem vendor identification register (d0:f0) .................... 42 3.6.11 sid?subsystem identification register (d0:f0) ................................... 43 3.6.12 mchcfg?mch configuration register (d0:f0).................................. 43 3.6.13 mchcfgns?mch memory scrub and initialization configuration register (d0:f0)..................................................................................... 45 3.6.14 fdhc?fixed dram hole control register (d0:f0)............................. 46 3.6.15 pam[0:6]?programmable attribute map registers (d0:f0).................. 47 3.6.16 drb?dram row boundary register (d0:f0) ..................................... 49 3.6.17 dra?dram row attribute register (d0:f0) ....................................... 50 3.6.18 drt?dram timing register (d0:f0) .................................................. 51 3.6.19 drc?dram controller mode register (d0:f0) ................................... 52 3.6.20 clock_dis?ck/ck# disable register (d0:f0).................................. 53 3.6.21 smram?system management ram control register (d0:f0) ........... 54 3.6.22 esmramc?extended system management ram control register (d0:f0) ................................................................................................... 55 3.6.23 tolm?top of low memory register (d0:f0) ...................................... 56 3.6.24 remapbase?remap base address register (d0:f0)....................... 56 3.6.25 remaplimit?remap limit address register (d0:f0)........................ 57 3.6.26 skpd?scratchpad data register (d0:f0)............................................ 57 3.6.27 dvnp?device not present register (d0:f0) ....................................... 58 3.7 dram controller error reporting registers (device 0, function 1) ................... 59 3.7.1 vid?vendor identification register (d0:f1) ......................................... 60 3.7.2 did?device identification register (d0:f1).......................................... 60 3.7.3 pcicmd?pci command register (d0:f1) .......................................... 61 3.7.4 pcists?pci status register (d0:f1) .................................................. 61 3.7.5 rid?revision identification register (d0:f1) ....................................... 62 3.7.6 subc?sub-class code register (d0:f1) ............................................ 62 3.7.7 bcc?base class code register (d0:f1)............................................. 63 3.7.8 mlt?master latency timer register (d0:f1) ...................................... 63 3.7.9 hdr?header type (d0:f1) .................................................................. 64 3.7.10 svid?subsystem vendor identification register (d0:f1) .................... 65 3.7.11 sid?subsystem identification register (d0:f1) ................................... 65 3.7.12 ferr_global?global error register (d0:f1)................................... 66 3.7.13 nerr_global?global error register (d0:f1) .................................. 67 3.7.14 hia_ferr?hub interface_a first error register (d0:f1) ................... 68 3.7.15 hia_nerr?hub interface_a next error register (d0:f1)................... 69 3.7.16 scicmd_hia?sci command register (d0:f1) .................................. 70 3.7.17 smicmd_hia?smi command register (d0:f1).................................. 71 3.7.18 serrcmd_hia?serr command register (d0:f1) .......................... 72 3.7.19 sysbus_ferr?system bus first error register (d0:f1).................. 73 3.7.20 sysbus_nerr?system bus next error register (d0:f1)................. 74 3.7.21 scicmd_sysbus?sci command register (d0:f1).......................... 75 3.7.22 smicmd_sysbus?smi command register (d0:f1) ......................... 76 3.7.23 serrcmd_sysbus?serr command register (d0:f1).................. 77 3.7.24 dram_ferr?dram first error register (d0:f1) .............................. 78 3.7.25 dram_nerr?dram next error register (d0:f1) ............................. 78 3.7.26 scicmd_dram?sci command register (d0:f1).............................. 79 3.7.27 smicmd_dram?smi command register (d0:f1) ............................. 79 3.7.28 serrcmd_dram?serr command register (d0:f1)...................... 80
datasheet 5 3.7.29 dram_celog_add?dram first correctable memory error address register (d0:f1).......................................................................80 3.7.30 dram_uelog_add?dram first uncorrectable memory error address register (d0:f1).......................................................................81 3.7.31 dram_celog_syndrome?dram first correctable memory error register (d0:f1) ............................................................................81 3.8 hi_b virtual pci-to-pci bridge registers (device 2, function 0) .......................82 3.8.1 vid2?vendor identification register (d2:f0) .......................................83 3.8.2 did2?device identification register (d2:f0) ........................................83 3.8.3 pcicmd2?pci command register (d2:f0) ........................................84 3.8.4 pcists2?pci status register (d2:f0) ................................................85 3.8.5 rid2?revision identification register (d2:f0) .....................................86 3.8.6 subc2?sub-class code register (d2:f0) ..........................................86 3.8.7 bcc2?base class code register (d2:f0) ...........................................87 3.8.8 mlt2?master latency timer register (d2:f0) ....................................87 3.8.9 hdr2?header type register (d2:f0)..................................................88 3.8.10 pbusn2?primary bus number register (d2:f0) ................................88 3.8.11 busn2?secondary bus number register (d2:f0) ..............................89 3.8.12 subusn2?subordinate bus number register (d2:f0) .......................89 3.8.13 smlt2?secondary bus master latency timer register (d2:f0) ........90 3.8.14 iobase2?i/o base address register (d2:f0).....................................91 3.8.15 iolimit2?i/o limit address register (d2:f0)......................................91 3.8.16 sec_sts2?secondary status register (d2:f0) .................................92 3.8.17 mbase2?memory base address register (d2:f0) .............................93 3.8.18 mlimit2?memory limit address register (d2:f0) ..............................94 3.8.19 pmbase2?prefetchable memory base address register (d2:f0)......95 3.8.20 pmlimit2?prefetchable memory limit address register (d2:f0).......95 3.8.21 bctrl2?bridge control register (d2:f0) ...........................................96 3.9 hi_b virtual pci-to-pci bridge registers (device 2, function 1) .......................97 3.9.1 vid?vendor identification register (d2:f1) .........................................98 3.9.2 did?device identification register (d2:f1) ..........................................98 3.9.3 pcicmd?pci command register (d2:f1) ..........................................99 3.9.4 pcists?pci status register (d2:f1) ..................................................99 3.9.5 rid?revision identification register (d2:f1) .....................................100 3.9.6 subc?sub-class code register (d2:f1) ..........................................100 3.9.7 bcc?base class code register (d2:f1)...........................................101 3.9.8 hdr?header type register (d2:f1)..................................................101 3.9.9 svid?subsystem vendor identification register (d2:f1) ..................102 3.9.10 sid?subsystem identification register (d2:f1) .................................102 3.9.11 hib_ferr?hub interface_b first error register (d2:f1) .................103 3.9.12 hib_nerr?hub interface_b next error register (d2:f1).................104 3.9.13 serrcmd2?serr command register (d2:f1) ..............................105 3.9.14 smicmd2?smi command register (d2:f1)......................................106 3.9.15 scicmd2?sci command register (d2:f1) ......................................107 3.10 hi_c virtual pci-to-pci bridge registers (device 3, function 0,1)..................108 3.10.1 did?device identification register (d3:f0) ........................................108 3.10.2 did?device identification register (d3:f1) ........................................108 3.11 hi_d virtual pci-to-pci bridge registers (device 4, function 0,1)..................109 3.11.1 did?device identification register (d4:f0) ........................................109 3.11.2 did?device identification register (d4:f1) ........................................109
6 datasheet 4 system address map ............................................................................................ 111 4.1 system memory spaces ................................................................................... 111 4.1.1 vga and mda memory spaces........................................................... 113 4.1.2 pam memory spaces .......................................................................... 114 4.1.3 isa hole memory space ...................................................................... 115 4.1.4 i/o apic memory space ...................................................................... 115 4.1.5 system bus interrupt memory space................................................... 115 4.1.6 device 2 memory and prefetchable memory ....................................... 115 4.1.7 device 3 memory and prefetchable memory ....................................... 116 4.1.8 device 4 memory and prefetchable memory ....................................... 116 4.1.9 hi_a subtractive decode ..................................................................... 116 4.1.10 main memory addresses...................................................................... 116 4.2 i/o address space ............................................................................................ 117 4.3 smm space....................................................................................................... 117 4.3.1 system management mode (smm) memory range ............................ 117 4.3.2 tseg smm memory space................................................................. 118 4.3.3 high smm memory space ................................................................... 118 4.3.4 smm space restrictions ...................................................................... 118 4.3.5 smm space definition.......................................................................... 119 4.4 memory reclaim background ........................................................................... 120 4.4.1 memory re-mapping............................................................................ 120 5 reliability, availability, serviceability, usability, and manageability (rasum) ....................................................................................... 121 5.1 dram ecc ....................................................................................................... 121 5.2 dram scrubbing .............................................................................................. 121 5.3 dram auto-initialization ................................................................................... 121 5.4 smbus access .................................................................................................. 121 6 electrical characteristics .................................................................................... 123 6.1 absolute maximum ratings .............................................................................. 123 6.2 thermal characteristics .................................................................................... 123 6.3 power characteristics ....................................................................................... 124 6.4 i/o interface signal groupings.......................................................................... 125 6.5 dc characteristics ............................................................................................ 127 7 ballout and package specifications ............................................................... 131 7.1 ballout ............................................................................................................... 131 7.2 package specifications ..................................................................................... 141 7.3 chipset interface trace length compensation................................................. 143 7.3.1 mch system bus signal package trace length data ........................ 144 7.3.1.1 mch ddr channel a signal package trace length data..... 145 7.3.1.2 mch ddr channel b signal package trace length data..... 148 7.3.1.3 mch hub interface_a signal package trace length data......................................................................................... 151 7.3.1.4 mch hub interface_b signal package trace length data......................................................................................... 151 7.3.1.5 mch hub interface_c signal package trace length data......................................................................................... 152 7.3.1.6 mch hub interface_d signal package trace length data......................................................................................... 152
datasheet 7 8 testability ..................................................................................................................153 8.1 xor chains ......................................................................................................154 figures 1-1 intel ? e7500 chipset platform block diagram ....................................................13 2-1 mch interface signals ........................................................................................18 3-1 pam registers ....................................................................................................48 4-1 system address map ........................................................................................111 4-2 detailed extended memory range address map .............................................112 7-1 intel ? e7500 mch ballout (top view) ..............................................................131 7-2 intel ? e7500 mch ballout (left half of top view) ............................................132 7-3 intel ? e7500 mch ballout (right half of top view)..........................................133 7-4 mch package dimensions (top view) .............................................................141 7-5 mch package dimensions (side view) ............................................................142 tables 1-1 supported dimm configuration...........................................................................15 2-1 system bus interface signals .............................................................................19 2-2 ddr channel_a interface signals ......................................................................22 2-3 ddr channel_b interface signals ......................................................................23 2-4 hi _a signals.......................................................................................................24 2-5 hi_b signals........................................................................................................25 2-6 hi_c signals .......................................................................................................26 2-7 hi_d signals .......................................................................................................27 2-8 clocks, reset, power, and miscellaneous signals .............................................28 3-1 intel ? e7500 mch logical configuration resources ..........................................33 3-2 dram controller register map (hi_a?d0:f0) ..................................................37 3-3 pam associated attribute bits.............................................................................48 3-4 dram controller register map (hi_a?d0:f1) ..................................................59 3-5 hi_b virtual pci-to-pci bridge register map (hi_a?d2:f0) ............................82 3-6 hi_b virtual pci-to-pci bridge register map (hi_a?d2:f1) ............................97 4-1 smm address range ........................................................................................119 6-1 absolute maximum ratings...............................................................................123 6-2 mch package thermal resistance ..................................................................123 6-3 thermal power dissipation (vcc1_2 = 1.2 v 5%)..........................................124 6-4 dc characteristics functional operating range (vcc1_2 = 1.2 v 5%).........124 6-5 signal groups system bus interface ................................................................125 6-6 signal groups ddr interface............................................................................125 6-7 signal groups hub interface 2.0 (hi_b?d) .......................................................126 6-8 signal groups hub interface 1.5 (hi_a)............................................................126 6-9 signal groups smbus .......................................................................................126 6-10 signal groups reset and miscellaneous ..........................................................126 6-11 operating condition supply voltage (vcc1_2 = 1.2 v 5%)............................127 6-12 system bus interface (vcc1_2 = 1.2 v 5%)...................................................127 6-13 ddr interface (vcc1_2 = 1.2 v 5%) ..............................................................128 6-14 hub interface 2.0 configured for 50 ? (vcc1_2 = 1.2 v 5%).........................129 6-15 hub interface 1.5 with parallel buffer mode configured for 50 ? (vcc1_2 = 1.2 v 5%)......................................................................................130
8 datasheet 7-1 mch signal list ................................................................................................ 134 7-2 example normalization table ........................................................................... 143 7-3 mch l pkg data for the system bus ................................................................. 144 7-4 mch l pkg data for ddr channel a................................................................. 145 7-5 mch l pkg data for ddr channel b................................................................. 148 7-6 mch l pkg data for hub interface_a ................................................................ 151 7-7 mch l pkg data for hub interface_b ................................................................ 151 7-8 mch l pkg data for hub interface_c ................................................................ 152 7-9 mch l pkg data for hub interface_d ................................................................ 152 8-1 xor chains ...................................................................................................... 154
datasheet 9 revision history rev. description date -001 initial release february 2002
10 datasheet intel ? e7500 mch features processor/host bus support ?intel ? xeon? processor with 512-kb l2 cache ? 400 mhz system bus (2x address, 4x data) ? symmetric multiprocessing protocol (smp) for up to two processors at 400 mt/s ? system bus dynamic bus inversion (dbi) ? 36-bit system bus addressing ? 12-deep in-order queue ? agtl+ bus driver technology with on-die termination resistors ? parity protection on system bus data, address/request, and response signals memory system ? one 144-bit wide ddr memory port (with chipkill* technology ecc) ? peak memory bandwidth of 3.2 gb/s ? supports 64 mb, 128 mb, 256 mb, 512 mb dram densities ? supports a maximum of 16 gb of memory using (x4) double-sided dimm ? supports x72, registered, ecc ddr dimms (in pairs) hub interface_a to intel ? ich3-s ? supports connection to ich3-s via hub interface 1.5 ? 266 mb/s point-to-point hub interface 1.5 interface to ich3-s ? parity protected ? 66 mhz base clock running 4x (533 mb/s) data transfer ? isochronous support ? parallel termination mode only ? 64-bit addressing on inbound transactions (maximum 16 gb memory decode space) hub interface_b, hub interface_c, and hub interface_d ? supports connection to intel ? p64h2 via hi 2.0 ? each hub interface is an independent 1 gb/s point-to-point 16-bit connection ? ecc protected ? 66 mhz base clock running 8x (1 gb/s) data transfers ? supports snooped and non-snooped inbound accesses ? parallel termination mode ? 64-bit inbound addressing ? 32-bit outbound addressing supported for pci-x pci / pci-x ? supports 33 mhz pci on ich3-s ? supports 33 mhz and 66 mhz pci on p64h2 ? supports 66 mhz, 100 mhz or 133 mhz pci-x on p64h2 rasum ? supports s4ec/d4ed ecc ? provides x4 chipkill technology ecc support ? correct any number of errors contained in a 4-bit nibble ? detect all errors contained entirely within two 4-bit nibbles ? hub interface_a protected by parity ? hub interface_b?d protected by ecc ? memory auto-initialization by hardware implemented to allow main memory to be initialized with valid ecc ? memory scrubbing supported ? smbus target interface access to mch error registers ? p64h2 and ich3-s have smbus target interface for access to registers ? ich3-s master smbus interface reads serial presence detect (spd) on dimms package ? 1005-ball, 42.5 mm fc-bga package
datasheet 11 introduction introduction 1 the intel ? e7500 chipset is targeted for the server market, both front-end and general purpose low- to mid-range. it is intended to be used with the intel ? xeon? processor with 512-kb l2 cache. the e7500 chipset consists of three major components: the intel ? e7500 memory controller hub ( m c h ), t h e i n t e l ? i / o c o n t r o l l e r h u b 3 ( i c h 3 - s ) , a nd t h e pc i / p c i - x 6 4 - b i t h u b 2 . 0 ( p 6 4 h 2 ). the mch provides the system bus interface, memory controller, hub interface for legacy i/o, and three high-performance hub interfaces for pci/pci-x bus expansion. this document describes the e7500 memory controller hub (mch). section 1.3, ?intel? e7500 chipset system architecture? on page 1-12 provides an overview of each of the components of the e7500 chipset. for details on other components of the chipset, refer to that component?s datasheet. 1.1 glossary of terms term description dbi dynamic bus inversion. ddr double data rate memory technology. dp dual processor. full reset the term ?a full mch reset? is used in this document when rstin# is asserted. hi hub interface. the proprietary hub interconnect that ties the mch to the ich3-s and p64h2. in this document hi cycles originating from or destined for the primary pci interface on the ich3-s are generally referred to as hi/pci_a or simply hi_a cycles. cycles originating from or destined for any target on the second, third or fourth hi interfaces are described as hi_b, hi_c, and hi_d cycles respectively. note that there are two versions of hi used on the intel ? e7500 mch: an 8-bit hi 1.5 protocol is implemented on hi_a and a 16-bit hi 2.0 protocol is used for the hi_b, hi_c and hi_d. host this term is used synonymously with processor. ib inbound, refers to traffic moving from pci or other i/o toward dram or the system bus. ich3-s the i/o controller hub 3-s component that contains the primary pci interface, lpc interface, usb, ata-100, and other legacy functions. it communicates with the mch over a proprietary interconnect called the hub interface. intel ? xeon? processor with 512-kb l2 cache the processor supported by the intel ? e7500 chipset. this processor is the second generation of processors based on the intel ? netburst? microarchitecture. this processor delivers performance levels that are significantly higher than previous generations of ia-32 processors. this processor supports 1-2 processors on a single system bus and has a 512 kb integrated l2 cache. mch the memory controller hub component that contains the processor interface and dram interface. it communicates with the i/o controller hub 3-s (ich3-s) and p64h2 over a proprietary interconnect called the hub interface (hi). ob outbound, refers to traffic moving from the system bus to pci or other i/o. intel ? p64h2 pci/pci-x 64-bit hub 2.0 component. the bus controller hub component has a 16-bit hub interconnect 2.0 on its primary side and two, 64-bit pci-x bus segments on the secondary side.
12 datasheet introduction 1.2 reference documents note: refer to the intel ? xeon? processor with 512-kb l2 cache and intel ? e7500 chipset platform design guide for an expanded set of reference documents. 1.3 intel ? e7500 chipset system architecture the e7500 chipset is optimized for the intel xeon processor with 512-kb l2 cache. the architecture of the chipset provides the performance and feature-set required for dual-processor based severs in the entry-level and mid-range, front-end and general-purpose server market segments. a new chipset component interconnect, the hub interface 2.0 (hi2.0), is designed into the e7500 chipset to provide more efficient communication between chipset components for high- speed i/o. each hi2.0 provides 1.066 gb/s i/o bandwidth. the e7500 chipset has three hi2.0 connections, delivering 3.2 gb/s bandwidth for high-speed i/o, which can be used for pci-x. the system bus, used to connect the processor with the e7500 chipset, utilizes a 400 mt/s transfer rate for data transfers, delivering a bandwidth of 3.2 gb/s. the e7500 chipset architecture supports a 144-bit wide, 200 mhz double data rate (ddr) memory interface also capable of transferring data at 3.2 gb/s. in addition to these performance features, e7500 chipset-based platforms also provide the rasum (reliability, availability, serviceability, usability, and manageability) features required for entry- level and mid-range servers. these features include: chipkill* technology ecc for memory, ecc for all high-performance i/o, out-of-bound manageability through smbus target interfaces on all major components, memory scrubbing and auto-initialization, processor thermal monitoring, and hot-plug pci/pci-x. primary pci or pci_a the physical pci bus that is driven directly by the ich3-s component. it supports 5 v, 32-bit, 33 mhz pci 2.2 compliant components. communication between pci_a and the mch occurs over hi_a. note that even though the primary pci bus is referred to as pci_a it is not pci bus #0 from a configuration standpoint. rasum reliability, availability, serviceability, usability and manageability. document document number intel ? xeon? processor with 512 kb l2 cache and intel ? e7500 chipset platform design guide 298649 intel ? 82801ca i/o controller hub 3-s (ich3-s) datasheet 290733 intel ? 82870p2 pci/pci-x 64-bit hub 2 (p64h2) datasheet 290732 intel ? e7500 chipset: e7500 memory controller hub (mch) thermal and mechanical design guidelines 298647 intel ? pci/pci-x 64-bit hub 2 (p64h2) thermal and mechanical design guidelines 298648 intel ? 82802b/ac firmware hub (fwh) datasheet 290658 intel ? xeon? processor with 512-kb l2 cache datasheet term description
datasheet 13 introduction the e7500 chipset consists of three major components: the memory controller hub (mch), the i/o controller hub 3-s (ich3-s), and the pci/pci-x 64-bit hub 2.0 (p64h2). the chipset components communicate via hub interfaces (his). the mch provides four hub interface connections: one for the ich3-s and three for high-speed i/o using p64h2 bridges. the hub interfaces are point-to-point and therefore only support two agents (the mch plus one i/o device), providing connections for up to 3 p64h2 bridges. the p64h2 provides bridging functions between hub interface_b?d and the pci/pci-x bus. up to six pci-x busses are supported. each pci-x bus is 66 mhz, 100 mhz, and 133 mhz pci-x capable. additional platform features supported by the e7500 chipset include four ata/100 ide drives, low pin count interface (lpc), integrated lan controller, audio codec, and universal serial bus (usb). the e7500 chipset is also acpi compliant and supports full-on, stop grant, suspend to disk, and soft-off power management states. through the use of an appropriate lan device, the e7500 chipset also supports wake-on-lan* for remote administration and troubleshooting. 1.3.1 intel ? 82801ca i/o controller hub 3-s (ich3-s) the ich3-s is a highly-integrated, multi-functional i/o controller hub that provides the interface to the pci bus and integrates many of the functions needed in today?s pc platforms. the mch and ich3-s communicate over a dedicated hub interface. intel 82801ca ich3-s functions and capabilities include: ? pci local bus specification , revision 2.2-compliant with support for 33 mhz pci operations. ? pci slots (supports up to 6 req/gnt pairs) ? acpi power management logic support ? enhanced dma controller, interrupt controller, and timer functions ? integrated ide controller supports ultra ata100/66/33 figure 1-1. intel ? e7500 chipset platform block diagram mch processor processor main memory (16 gb max) ddr channel a ddr channel b 200 mhz interface intel ? p64h2 p64h2 p64h2 hot plug pci-x pci-x hot plug pci-x pci-x hot plug pci-x pci-x intel ? ich3-s 16-bit hi 2.0 16-bit hi 2.0 16-bit hi 2.0 usb 1.1 (6 ports) ata-100 (4 drives) ac '97 10/100 lan controller smbus 1.1 gpios fwh (1-4) pci bus 8-bit hi 1.5
14 datasheet introduction ? usb host interface with support for 6 usb ports; 3 uhci host controllers ? integrated lan controller ? system management bus (smbus) specification , version 1.1 with additional support for i 2 c devices ? audio codec ?97, revision 2.2 specification (a.k.a., ac ?97 component specification , rev. 2.2) compliant link for audio and telephony codecs (up to 6 channels) ? low pin count (lpc) interface ? firmware hub (fwh) interface support ? alert on lan* (aol) and alert on lan 2* (aol2) 1.3.2 intel ? 82870p2 pci/pci-x 64-bit hub 2 (p64h2) the 82870p2 pci/pci-x 64-bit hub 2 (p64h2) is a peripheral chip that performs pci bridging functions between the mch hub interface and the pci -x busses. the p64h2 interfaces to the mch via a 16-bit hub interface. each p64h2 has two independent 64-bit pci bus interfaces that can be configured to operate in pci or pci-x mode. each pci bus interface contains an i/oapic with 24 interrupts and a hot-plug controller. functions and capabilities include: ? 16-bit hub interface to mch ? two pci bus interfaces ? pci specification, revision 2.2 compliant ? pci-pci bridge specification, revision 1.1 compliant ? pci-x specification, revision 1.0 compliant ? pci hot plug 1.0 compliant ? smbus interface ? hot-plug controller for each pci bus segment ? i/oapic for each pci bus segment 1.4 intel ? e7500 mch overview the mch provides the processor interface, main memory interface, and hub interfaces in an e7500 chipset-based server platform. it supports intel xeon processor with 512 kb l2 cache processor. the mch is offered in a 1005-ball, 42.5 mm fc-bga package and has the following functionality: ? supports single or dual processor configurations at 400 mt/s ? agtl+ host bus with integrated termination supporting 36-bit host addressing ? 144-bit wide ddr channel supporting 200 mhz dual data rate operation ? 16 gb ddr dram (512 mb devices) support ? 8-bit, 66 mhz 4x hub interface a to ich3-s ? three 16-bit, 66 mhz 8x hub interface ? distributed arbitration for highly concurrent operation
datasheet 15 introduction 1.4.1 processor system interface the e7500 mch is optimized for use with processors based on the intel ? netburst? microarchitecture. it supports the following features: ? 400 mhz system bus (2x address, 4x data) ? symmetric multiprocessing protocol (smp) for up to two processors at 400 mt/s ? system bus dynamic bus inversion (dbi) ? 36-bit system bus addressing ? 12-deep in-order queue ? agtl+bus driver technology with on die termination resistors ? parity protection on system bus data, address/ request, and response signals 1.4.2 main memory interface the mch directly supports two channels of ddr dram operating in lock-step. these channels are organized to provide minimum latency for the critical segment of data. the mch ddr channels run at 200 mhz. the mch supports 64-mb, 128-mb, 256-mb, or 512-mb memory technology. the mch provides ecc error checking with chipkill technology, on x4 dimms to ensure dram data integrity. the mch supports x72, registered, ecc ddr dimms. the mch memory interface supports the following operations: ? provides x4 chipkill technology ecc support ? corrects any number of errors contained in a 4-bit nibble ? detects all errors contained entirely within two 4-bit nibbles ? 8 kb?64 kb page sizes support 64 mb to 512 mb dram devices the supported dimm configurations are listed in table 1-1 . note: dimms must be populated in pairs, and the dimms in a pair must be identical. 1.4.3 hub interface_a (hi_a) the 8-bit hi_a connects the mch to the ich3-s. all communication between the mch and the ich3-s occurs over hi_a, running at 66 mhz base clock 4x (266 mb/s). hi_a supports upstream 64-bit addressing and downstream 32-bit addressing. all incoming accesses on hi_a are snooped. hi_a provides preferential treatment for isochronous transfers. the interface supports parallel termination only. table 1-1. supported dimm configuration density 64 mbit 128 mbit 256 mbit 512 mbit device width x4 x8x4x8x4x8x4x8 single / double ss / ds ss / ds ss / ds ss / ds ss / ds ss / ds ss / ds ss / ds 184 pin ddr dimm capacity 128 mb / 256 mb 64 mb/ 128 mb 256 mb / 512 mb 128 mb / 256 mb 512 mb / 1024 mb 256 mb / 512 mb 1024mb/ 2048mb 512mb/ 1024 mb
16 datasheet introduction 1.4.4 hub interface_b?d (hi_b?d) the mch supports three 16-bit hub interfaces that run at 66 mhz 8x (1 gb/s). the 16-bit hi 2.0 interfaces support 32-bit downstream addressing and 64-bit upstream addressing. for hub interface_b?d to main memory accesses, memory read and write accesses are supported. for processor to hub interface_b?d accesses, memory reads, memory writes, i/o reads, and i/o writes are supported. the 16-bit hub interfaces 2.0 support parallel termination only. the 16-bit hi 2.0 may or may not be connected to a device. the mch detects the presence of a device on each 16-bit hub. if a hub interface is not connected to a valid hub interface device, the bridge configuration register space for that interface is disabled. 1.4.5 mch clocking the mch has the following clock input pins: ? differential hclkinp/hclkinn for the host interface ? 66 mhz clock input for the hi_a, hi_b, hi_c, hi_d interfaces clock synthesizer chip(s) generate the system bus clock and hub interface clock. the system bus interface clock speed is 100 mhz. the mch does not require any relationship between the hclkin host clock and the 66 mhz clock generated for hub interfaces. the hi_a, hi_b, hi_c and hi_d interfaces run at a 66 mhz base clock frequency. hi_a runs at 4x, hi_b, hi_c, and hi_d run at 8x. the ddr clocks generated by the mch have a 1:1 relationship with the system bus. 1.4.6 smbus interface the smbus address for the mch is 011_0000. this interface has no configuration registers associated with it. the smbus controller has access to all internal mch registers. it does not allow access to devices on the hub interface or pci buses. the smbus port can read all mch error registers. it can only write a special set of ?shadowed? error registers. these error registers are an exact copy of what the processor has access to. this allows the processor to read and clear its set of error registers independently from the set the smbus port controls. the smbus port can only write the error registers to clear them; the only supported write operation is a byte write. reads are always performed as 4-byte accesses.
datasheet 17 signal description signal description 2 this section provides a detailed description of mch signals. the signals are arranged in functional groups according to their associated interface. the ?#? symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. when ?#? is not present after the signal name the signal is asserted when at the high voltage level. the following notations are used to describe the signal type: i input pin o output pin i/o bidirectional input/output pin as/t/s active sustained tristate. this applies to some of the hub interface (hi) signals. this pin is weakly driven to its last driven value 2x double-pump clocking. addressing at 2x of hclkinx 4x quad-pump clocking. data transfer at 4x of hclkinx sstl-2 stub series terminated logic for 2.5 volts. refer to the jedec specification d8-9a for complete details the signal description also includes the type of buffer used for the particular signal: agtl+ open drain agtl+ interface signal. refer to the agtl+ i/o specification for complete details. the mch integrates agtl+ termination resistors cmos cmos buffers note: certain signals are logically inverted signals. the logical values are the inversion of the electrical values on the system bus.
signal description 18 datasheet figure 2-1. mch interface signals cb_a[7:0] dq_a[63:0] dqs_a[17:0] cmdclk_a[3:0], cmdclk_a[3:0]# ma_a[12:0] ba_a[1:0] ras_a# cas_a# we_a# cs_a[7:0]# cke_a rcvenin_a# rcvenout_a# ddrcomp_a ddrcvoh_a ddrcvol_a ddrvref_a[5:0] hub interface a hi_a[11:0] hi_stbf hi_stbs hircomp_a hiswng_a hivref_a clk66 processor system bus interface ha[35:3]# hd[63:0]# ads# bnr# bpri# dbsy# defer# drdy# hit# hitm# hlock# hreq[4:0]# htrdy# rs[2:0]# cpurst# breq0# dbi[3:0]# hadstb[1:0]# hdstbp[3:0]#/hdstbn[3:0]# ap[1:0]# xerr# binit# dp[3:0]# rsp# hclkinp, hlckinn hdvref[3:0] havref[1:0] hccvref hxswng, hyswng hxrcomp, hyrcomp ddr channel a rstin# xormode# pwrgood smb_clk smb_data clocks and reset cb_b[7:0] dq_b[63:0] dqs_b[17:0] cmdclk_a[3:0], cmdclk_b[3:0]# ma_b[12:0] ba_b[1:0] ras_b# cas_b# we_b# cs_b[7:0]# cke_b rcvenin_b# rcvenout_b# ddrcomp_b ddrcvoh_b ddrcvol_b ddrvref_b[5:0] ddr channel b hub interface b hi_b[21:20] hi_b[18:0] pstrbf_b pstrbs_b pustrbf_b pustrbs_b hircomp_b hiswng_b hivref_b clk66 hub interface c hi_c[21:20] hi_c[18:0] pstrbf_c pstrbs_c pustrbf_c pustrbs_c hircomp_c hiswng_c hivref_c clk66 hub interface d hi_d[21:20] hi_d[18:0] pstrbf_d pstrbs_d pustrf_d pustrs_d hircomp_d hiswng_d hivref_d clk66
datasheet 19 signal description 2.1 system bus interface signals table 2-1. system bus interface signals (sheet 1 of 3) signal name type description ads# i/o agtl+ address strobe: the system bus owner asserts ads# to indicate the first of two cycles of a request phase. ap[1:0]# i/o agtl+ address parity: the ap[1:0]# lines are driven by the request initiator and provide parity protection for the request phase signals. ap[1:0]# are common clock signals and are driven one common clock after the request phase. address parity is correct if there are an even number of electrically low signals (low voltage) in the set consisting of the covered signals plus the parity signal. note that the mch only connects to ha[35:3]#. xerr# i agtl+ bus error: this signal may be connected to the mcerr# signal or ierr# signal, depending on system usage. the mch detects an electrical high to low transition on this input and set the correct error bit. the mch will take no other action except setting that bit. binit# i agtl+ bus initialize: this signal indicates an unrecoverable error occurred and can be driven by the processor. it is latched by the mch. bnr# i/o agtl+ block next request: bnr# is used to block the current request bus owner from issuing a new requests. this signal is used to dynamically control the system bus pipeline depth. bpri# o agtl+ priority agent bus request: the mch is the only priority agent on the system bus. it asserts this signal to obtain ownership of the address bus. the mch has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the hlock# signal is asserted. breq0# i/o agtl+ bus request 0: the mch pulls the processor bus breq0# signal low during cpurst#. the signal is sampled by the processors on the active-to-inactive transition of cpurst#. the minimum setup time for this signal is four hclks. the minimum hold time is two hclks and the maximum hold time is 20 hclks. breq0# should be tristate after the hold time requirement has been satisfied. cpurst# o agtl+ cpu reset: the mch asserts cpurst# while rstin# (pcirst# from ich3-s) is asserted and for approximately 1 ms after rstin# is deasserted. cpurst# allows the processors to begin execution in a known state. dbsy# i/o agtl+ data bus busy: this signal is used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# o agtl+ defer: when asserted, the mch will terminate the transaction currently being snooped with either a deferred response or with a retry response. dp[3:0]# i/o agtl+ host data parity: the dp[3:0]# signals provide parity protection for hd[63:0]#. the dp[3:0]# signals are common clock signals and are driven one common clock after the data phases they cover. dp[3:0]# are driven by the same agent driving hd[63:0]#. data parity is correct if there are an even number of electrically low signals (low voltage) in the set consisting of the covered signals plus the parity signal. dbi[3:0]# i/o agtl+ 4x dynamic bus inversion: the dbi[3:0]# signals are driven along with the hd[63:0]# signals. they indicate when the associated signals are inverted. dbi[3:0]# are asserted such that the number of data bits driven electrically low (low voltage) within the corresponding 16 bit group never exceeds 8. drdy# i/o agtl+ data ready: this signal is asserted for each cycle that data is transferred.
signal description 20 datasheet ha[35:3]# i/o gtl+ 2x host address bus: ha[35:3]# connect to the system address bus. during processor cycles, ha[35:3]# are inputs. the mch drives ha[35:3]# during snoop cycles on behalf of hub interface initiators. hadstb[1:0]# i/o agtl+ 2x host address strobe: the source synchronous strobes are used to latch ha[35:3]# and hreq[4:0]#. hd[63:0]# i/o agtl+ 4x host data: these signals are connected to the system data bus. hdstbp[3:0]# hdstbn[3:0]# i/o agtl+ 4x differential host data strobes: the differential source synchronous strobes are used to latch hd[63:0]# and dbi[3:0]#. strobe data bits associated hdstbp3#, hdstbn3# hd[63:48]#, dbi3# hdstbp2#, hdstbn2# hd[47:32]#, dbi2# hdstbp1#, hdstbn1# hd[31:16]#, dbi1# hdstbp0#, hdstbn0# hd[15:0]#, dbi0# hit# i/o agtl+ hit: hit# indicates that a caching agent holds an unmodified version of the requested line. this signal is also driven in conjunction with hitm# by the target to extend the snoop window. hitm# i/o agtl+ hit modified: hitm# indicates that a caching agent holds a modified version of the requested line and that this agent assumes responsibility for providing the line. hitm# is driven in conjunction with hit# to extend the snoop window. hlock# i agtl+ host lock: all system bus cycles are sampled with the assertion of hlock# and ads#, until the negation of hlock#. this operation is atomic. hreq[4:0]# i/o agtl+ 2x host request command: hreq[4:0]# defines the attributes of the request. these signals are asserted by the requesting agent during both halves of a request phase. in the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second half the signals carry additional information to define the complete transaction type. htrdy# o agtl+ host target ready: htrdy# indicates that the target of the processor transaction is able to enter the data transfer phase. rs[2:0]# o agtl+ response signals: rs[2:0]# indicate the type of response according to the following table: rs[2:0] response type 000 idle state 001 retry response 010 deferred response 011 reserved (not driven by mch) 100 hard failure (not driven by mch) 101 no data response 110 implicit writeback 111 normal data response rsp# o agtl+ response parity: rsp# provides parity protection for the rs[2:0]# signals. rsp# is always driven by the mch and must be valid on all clocks. response parity is correct when there are an even number of low signals (low voltage) in the set consisting of the rs[2:0]# signals and the rsp# signal itself. hclkinp, hlckinn i cmos differential host clock in: these input pins receive a differential host clock from the external clock synthesizer. the clock is used by all the mch logic in the host clock domain. hdvref[3:0] i analog host data reference voltage: rhdvref[3:0] are the reference voltage inputs for the 4x data signals of the host gtl interface. table 2-1. system bus interface signals (sheet 2 of 3) signal name type description
datasheet 21 signal description havref[1:0] i analog host address reference voltage: havref[1:0] are the reference voltage inputs for the 2x address signals of the host gtl interface. hccvref i analog host common clock reference voltage: hccvref is the reference voltage input for the common clock signals of the host gtl interface hxswng, hyswng i analog host voltage swing: these signals provide a reference voltage used by the system bus rcomp circuit. hxrcomp, hyrcomp i analog host rcomp: these signals are used to calibrate the host agtl+ i/o buffers. table 2-1. system bus interface signals (sheet 3 of 3) signal name type description
signal description 22 datasheet 2.2 ddr channel a signals table 2-2. ddr channel_a interface signals signal name type description cb_a[7:0] i/o sstl-2 ddr channel a check bits: these check bits are required to provide ecc support. dq_a[63:0] i/o sstl-2 ddr channel a data bus: the ddr data bus provides the data interface for the dram devices. dqs_a[17:0] i/o sstl-2 ddr channel a data strobes: dqs_a[17:0] are the ddr data strobes. each data strobe is used to strobe a set of 4 or 8 data signals. cmdclk_a[3:0], cmdclk_a[3:0]# o cmos ddr channel a command clock: these signals are the ddr command clocks used by the ddr drams to latch ma[12:0], ba[1:0], ras#, cas#, we#, cke#, and cs# signals. ma_a[12:0] o sstl-2 ddr channel a memory address: ma_a[12:0] are the ddr memory address signals. ba_a[1:0] o sstl-2 ddr channel a bank address: ba_a[1:0] are the ddr bank address signals. these bits select the bank within the ddr dram. ras_a# o sstl-2 ddr channel a row address strobe: ras_a# is used to indicate a valid row address and open a row. cas_a# o sstl-2 ddr channel a column address strobe: cas_a# is used to indicate a valid column address and initiate a transaction. we_a# o sstl-2 ddr channel a write enable: we_a# is used to indicate a write cycle. cs_a[7:0]# o sstl-2 ddr channel a chipselect: the chip select signals are used to indicate which dram device cycles are targeted. cke_a o sstl-2 ddr channel a clock enable: cke_a is the ddr clock enable signal. rcvenin_a# i sstl-2 receive enable input: rcvenin_a# is used for dram timing. rcvenout_a# o sstl-2 receive enable output: rcvenout_a# is used for dram timing. ddrcomp_a i cmos compensation for ddr a: this signal is used to calibrate the ddr buffers. ddrcvoh_a i analog compensation for ddr a: this signal is used to calibrate the ddr buffers. ddrcvol_a i analog compensation for ddr a: this signal is used to calibrate the ddr buffers. ddrvref_a[5:0] i analog ddr channel a voltage reference: ddr reference voltage input.
datasheet 23 signal description 2.3 ddr channel b signals table 2-3. ddr channel_b interface signals signal name type description cb_b[7:0] i/o sstl-2 ddr channel b check bits: these check bits are required to provide ecc support. dq_b[63:0] i/o sstl-2 ddr channel b data bus: the ddr data bus provides the data interface for the dram devices. dqs_b[17:0] i/o sstl-2 ddr channel b data strobes: dqs_b[17:0] are the ddr data strobes. each data strobe is used to strobe a set of 4 or 8 data signals. cmdclk_b[3:0], cmdclk_b[3:0]# o cmos ddr channel b command clock: these signals are the ddr command clocks used by the ddr drams to latch ma[12:0], ba[1:0], ras#, cas#, we#, cke#, and cs# signals. ma_b[12:0] o sstl-2 ddr channel b memory address: ma_b[12:0] are the ddr memory address signals. ba_b[1:0] o sstl-2 ddr channel b bank address: ba_b[1:0] are the ddr bank address signals. these bits select the bank within the ddr dram. ras_b# o sstl-2 ddr channel b row address strobe: ras_b# is used to indicate a valid row address and open a row. cas_b# o sstl-2 ddr channel b column address strobe: cas_b# is used to indicate a valid column address and initiate a transaction. we_b# o sstl-2 ddr channel b write enable: we_b# is used to indicate a write cycle. cs_b[7:0]# o sstl-2 ddr channel b chipselect: the chip select signals are used to indicate which dram device cycles are targeted. cke_b o sstl-2 ddr channel b clock enable: cke_b is the ddr clock enable signal. rcvenin_b# i sstl-2 receive enable input: rcvenin_b# is used for dram timing. rcvenout_b# o sstl-2 receive enable output: rcvenout_b# is used for dram timing. ddrcomp_b i/o cmos compensation for ddr b: this signal is used to calibrate the ddr buffers. ddrcvoh_b i analog compensation for ddr a: this signal is used to calibrate the ddr buffers. ddrcvol_b i analog compensation for ddr a: this signal is used to calibrate the ddr buffers. ddrvref_b[5:0] i analog ddr channel b voltage reference: ddr reference voltage input.
signal description 24 datasheet 2.4 hub interface_a signals notes: 1. clk66 is being shared by hi_a-d. physically there is one clk 66 pin on the mch. table 2-4. hi _a signals signal name type description hi_a[11:0] i/o (as/t/s) cmos hi_a signals: hi_a[11:0] are the signals used for the hub interface between the ich3-s and the mch. hi_stbf i/o (as/t/s) cmos hi_a strobe: hi_stbf is one of the two strobe signals used to transmit and receive packet data over hi_a. note :in normal buffer mode (hi 1.0) the hi_stbf signal is called hi_stb#. refer to the platform design guide and the mch documentation for appropriate hub interface strobe signals. hi_stbs i/o (as/t/s) cmos hi_a strobe compliment: hi_stbs is one of the two strobes signals used to transmit or receive packet data over hi_a. note : in normal buffer mode (hi 1.0) the hi_stb# signal is called hi_stb. refer to the platform design guide and the mch documentation for appropriate hub interface strobe signals. hircomp_a i analog compensation for hi_a: this signal is used to calibrate the hi_a i/o buffers. hiswng_a i analog hi_a voltage swing: this signal provides a reference voltage used by the hi_a rcomp circuit. hivref_a i analog hi_a reference: hivref_a is a reference voltage input for the hi_a interface. clk66 1 i cmos 66 mhz clock in: . this pin receives a 66 mhz clock from the clock synthesizer. this clock is shared by the hi_a, hi_b, hi_c, and hi_d.
datasheet 25 signal description 2.5 hub interface_b signals 1) notes: 1. clk66 is being shared by hi_a-d. physically there is one clk 66 pin on the mch. table 2-5. hi_b signals signal name type description hi_b[21:20] i/o (as/t/s) cmos hi_b signals: hi_b[21:20] are the ecc signals used for connection between the 16-bit hub and the mch. hi_b[18:0] i/o (as/t/s) cmos hi_b signals: the hi_b[18:0] signals are used for connection between the 16-bit hub and the mch. pstrbf_b i/o (as/t/s) cmos hi_b strobe first: pstrbf_b is one of two strobes signal pairs used to transmit or receive lower 8-bit data over hi_b. pstrbs_b i/o (as/t/s) cmos hi_b strobe second: pstrbs_b is one of two strobes signal pairs used to transmit or receive lower 8-bit packet data over hi_b. pustrbf_b i/o (as/t/s) cmos hi_b upper strobe first: pustrbf_b is one of two strobes signal pairs used to transmit or receive upper 8-bit packet data over hi_b. pustrbs_b i/o (as/t/s) cmos hi_b upper strobe second: pustrbs_b is one of two strobes signal pairs used to transmit or receive upper 8-bit packet data over hi_b. hircomp_b i/o cmos compensation for hi_b: this signal is used to calibrate the hi_b i/o buffers. hiswng_b i analog hi_b voltage swing: this signal provides a reference voltage used by the hi_b rcomp circuit. hivref_b i analog hi_b reference: hivref_b is a reference voltage input for the hi_b interface. clk66 1 i cmos 66 mhz clock in: this pin receives a 66 mhz clock from the clock synthesizer. this clock is shared by the hi_a, hi_b, hi_c and hi_d.
signal description 26 datasheet 2.6 hub interface_c signals notes: 1. clk66 is being shared by hi_a-d. physically there is one clk 66 pin on the mch. table 2-6. hi_c signals signal name type description hi_c[21:20] i/o (as/t/s) cmos hi_c signals: hi_c[21:20] are the ecc signals used for connection between the 16-bit hub and the mch. hi_c[18:0] i/o (as/t/s) cmos hi_c signals: hi_c[18:0] are the signals used for the connection between the 16-bit hub and the mch. pstrbf_c i/o (as/t/s) cmos hi_c strobe first: pstrbf_c is one of two strobe signal pairs used to transmit or receive lower 8-bit data over hi_c. pstrbs_c i/o (as/t/s) cmos hi_c strobe second: pstrbs_c is one of two strobe signals pairs used to transmit or receive lower 8-bit data over hi_c. pustrbf_c i/o (as/t/s) cmos hi_c upper strobe first: pustrbf_c is one of two strobe signals pairs used to transmit or receive upper 8-bit data over hi_c. pustrbs_c i/o (as/t/s) cmos hi_c upper strobe second: pustrbs_c is one of two strobe signals pairs used to transmit or receive upper 8-bit data over hi_c. hircomp_c i/o cmos compensation for hi_c: this signal is used to calibrate the hi_c i/o buffers. hiswng_c i analog hi_c voltage swing: this signal provides a reference voltage used by the hi_c rcomp circuit. hivref_c i analog hi_c reference: hivref_c is a reference voltage input for the hi_c interface. clk66 1 i cmos 66 mhz clock in: . this pin receives a 66 mhz clock from the clock synthesizer. this clock is shared by the hi_a, hi_b, hi_c and hi_d.
datasheet 27 signal description 2.7 hub interface_d signals notes: 1. clk66 is being shared by hi_a-d. physically there is one clk 66 pin on the mch. table 2-7. hi_d signals signal name type description hi_d[21:20] i/o (as/t/s) cmos hi_d signals: hi_d[21:20] are ecc signals used for connection between the 16-bit hub and the mch. hi_d[18:0] i/o (as/t/s) cmos hi_d signals: hi_d[18:0] are the signals used for the connection between the 16-bit hub and the mch. pstrbf_d i/o (as/t/s) cmos hi_d strobe first: pstrbf_d is one of two strobe signal pairs used to transmit or receive lower 8-bit data over hi_d. pstrbs_d i/o (as/t/s) cmos hi_d strobe second: pstrbs_d is one of two strobe signal pairs used to transmit or receive lower 8-bit data over hi_d. pustrf_d i/o (as/t/s) cmos hi_d upper strobe first: pustrf_d is one of two strobe signal pairs used to transmit or receive upper 8-bit data over hi_d. pustrs_d i/o (as/t/s) cmos hi_d upper strobe second: pustrs_d is one of two strobe signal pairs used to transmit or receive upper 8-bit data over hi_d. hircomp_d i/o cmos compensation for hi_d: this signal is used to calibrate the hi_d i/o buffers. hiswng_d i analog hi_d voltage swing: this signal provides a reference voltage used by the hi_drcomp circuit. hivref_d i analog hi_d reference: hivref_d is the reference voltage input for the hi_d interface. clk66 1 i cmos 66 mhz clock in: . this pin receives a 66 mhz clock from the clock synthesizer. this clock is shared by the hi_a, hi_b, hi_c and hi_d.
signal description 28 datasheet 2.8 clocks, reset, power, and miscellaneous signals the voltage reference pins are described in the signal description sections for the associated interface. 2.9 pin states during and after reset this section provides the signal states during reset (assertion of rstin#) and immediately following reset (deassertion of rstin#). table 2-8. clocks, reset, power, and miscellaneous signals signal name type description rstin# i cmos reset in: when asserted, rstin# asynchronously resets the mch logic. this signal is connected to the pcirst# output of the ich3-s. xormode# i cmos test input: when xormode# is asserted, the mch places all outputs in xor mode for board-level testing. pwrgood i power good: this signal resets the mch component, including ?sticky? logic. it is driven by external logic to indicate all power rails are present. smb_clk i/o smbus clock: this is the clock pin for the smbus interface. smb_data i/o smbus data: this is the data pin for the smbus interface. vcc1_2 power: these pins are 1.2 v power input pins for hi_a?d, and the mch core. vcca1_2 power: these pins are 1.2 v analog power input pins. vccahi1_2 power: this pin is a 1.2 v analog power input pin. vccacpu1_2 power: this pin is a 1.2 v analog power input pin. vcc_cpu power: for the system bus interface. vcc2_5 power: these pins are 2.5 v power input pins for ddr. vss ground: ground pin. legend interpretation drive strong drive (to normal value supplied by core logic, if not otherwise stated term normal termination devices on lv low voltage hv high voltage in input buffer enabled iso isolate inputs in inactive states tri tri-state pu weak pull-up pd weak pull-down
signal description datasheet 29 signal name state during rstin# assertion state after rstin# deassertion system bus interface cpurst# drive lv term hv (after 1ms) ha[35:3]# term hv 1 term hv 2 hadstb[1:0]# term hv term hv ap[1:0]# term hv term hv hd[63:0]# term hv term hv hdstbp[3:0]# term hv term hv hdstbn[3:0]# term hv term hv dep[3:0]# term hv term hv dbi[3:0]# term hv term hv ads# term hv term hv bnr# term hv term hv bpri# term hv term hv dbsy# term hv term hv defer# term hv term hv drdy# term hv term hv hit# term hv term hv hitm# term hv term hv hlock# term hv term hv hreq[4:0]# term hv term hv htrdy# term hv term hv rs[2:0]# term hv term hv rsp# term hv term hv berr# term hv term hv breq0# term hv drive lv 3 hdvref[3:0] in in havref[1:0] in in hccvref in in hxrcomp tri tri after rcomp hyrcomp tri tri after rcomp hxswng in in hyswng in in ddr channel a interface cb_a[7:0] tri tri dq_a[63:0] tri tri dqs_a[17:0] tri tri cmdclk_a[3:0] lv starts to toggle cmdclk_a[3:0]# lv starts to toggle ma_a[12:0] note 4 note 4 ba_a[1:0] note 4 note 4 ras_a# lv lv cas_a# hv hv we_a# hv hv cs_a[7:0]# hv hv cke_a lv note 6 rcvenin_a# in in rcvenout_a# hv hv ddr channel b interface cb_b[7:0] tri tri dq_b[63:0] tri tri dqs_b[17:0] tri tri cmdclk_b[3:0] lv starts to toggle cmdclk_b[3:0]# lv starts to toggle ma_b[12:0] note 4 note 4 ba_b[1:0] note 4 note 4 ras_b# lv lv cas_b# hv hv we_b# hv hv cs_b[7:0]# hv hv cke_b lv note 6 rcvenin_b# in in rcvenout_b# hv hv signal name state during rstin# assertion state after rstin# deassertion
signal description 30 datasheet notes: 1. drive lv if poc or straps are set 2. any signals driven lv from poc register go to term hv two clocks after cpurst# deasserts 3. drive lv and hold until two clocks after cpurst# is deasserted, and then term hv. 4. active 0 or 1, either is ok 5. weak pu for swizzle; weak pd for non-swizzle 6. remains low and is asserted after 256 clocks hub interface_a hi7_a weak pu term lv hi_a[11:8,6:0] weak pd term lv hi_stbf weak pd term lv hi_stbs weak pd term lv hircomp_a tri tri after rcomp hivref_a in in hiswng_a in in hub interface_b?d hi_x[21:17,15:0] weak pd term lv hi16_x note 5 term lv pstrbf_x, pustrbf_x weak pd term lv pstrbs_x, pustrbs_x weak pd term lv hircomp_x tri tri after rcomp hivref_x in in hiswng_x in in signal name state during rstin# assertion state after rstin# deassertion clocks and miscellaneous hclkin[n:p] in in clk66 in in rstin# in in xormode# in in pwrgood in in signal name state during rstin# assertion state after rstin# deassertion
datasheet 31 register description register description 3 the mch contains two sets of software accessible registers, accessed via the host processor i/o address space: ? control registers ? these registers are i/o mapped into the processor i/o space, which control access to pci configuration space (see section 3.5, ?i/o mapped registers? on page 3-35 ) ? internal configuration registers ? these registers, which reside within the mch, are partitioned into multiple logical device register sets (?logical? since they reside within a single physical device). one register set is dedicated to host-hi bridge functionality (controls pci_a, dram configuration, other chipset operating parameters, and optional features). other sets of registers map to hi_b, hi_c and hi_d. the mch supports pci configuration space accesses using the mechanism denoted as configuration mechanism #1 in the pci specification. the mch internal registers (i/o mapped and configuration registers) are accessible by the host. the registers can be accessed as byte (8-bit), word (16-bit), or dword (32-bit) quantities, with the exception of the conf_addr register, which can only be accessed as a dword. all multi-byte numeric fields use ?little-endian? ordering (i.e., lower addresses contain the least significant parts of the field). 3.1 register terminology term description ro read only. in some cases, if a register is read only, writes to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. wo write only. in some cases, if a register is write only, reads to this register location have no effect. however, in other cases, two separate registers are located at the same location where a read accesses one of the registers and a write accesses the other register. see the i/o and memory map tables for details. r/w read/write. a register with this attribute can be read and written. r/wc read/write clear. a register bit with this attribute can be read and written. however, a write of 1 clears (sets to 0) the corresponding bit and a write of 0 has no effect. r/w/l read/write/lock. a register with this attribute can be read, written and locked. r/wo read/write once. a register (bit) with this attribute can be written only once after power up. after the first write, the register (bit) becomes read only. l lock. a register bit with this attribute becomes read only after a lock bit is set.
32 datasheet register description 3.2 platform configuration the mch and the ich3-s are physically connected by hi_a. from a configuration standpoint, hi_a is logically pci bus 0. as a result, all devices internal to the mch and ich3-s appear to be on pci bus 0. the system?s primary pci expansion bus is physically attached to the ich3-s and, from a configuration perspective appears to be a hierarchical pci bus behind a pci-to-pci bridge and therefore has a programmable pci bus number. note: the primary pci bus is referred to as pci_a in this document and is not pci bus 0 from a configuration standpoint. the 16-bit hub interface ports appear to system software to be real pci buses behind pci-to-pci bridges resident as devices on pci bus 0. the mch decodes multiple pci device numbers. the configuration registers for the devices are mapped as devices residing on pci bus 0. each device number may contain multiple functions. ? device 0 : host-hi_a bridge/dram controller. logically this appears as a pci device residing on pci bus 0. physically device 0 contains the standard pci bridge registers, dram registers, configuration for hi_a, and other mch specific registers. ? device 2 : host-hi_b bridge. logically this bridge appears to be a pci-to-pci bridge device residing on pci bus 0. physically, device 2 contains the standard pci bridge registers and configuration registers for hi_b. ? device 3 : host-hi_c bridge. logically this bridge appears to be a pci-to-pci bridge device residing on pci bus 0. physically, device 3 contains the standard pci bridge registers and configuration registers for hi_c. ? device 4 : host-hi_d bridge. logically this bridge appears to be a pci-to-pci bridge device residing on pci bus 0. physically, device 4 contains the standard pci bridge registers and configuration registers for hi_d. reserved bits some of the mch registers described in this chapter contain reserved bits. these bits are labeled reserved (rsvd). software must deal correctly with fields that are reserved. on reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. on writes, software must ensure that the values of reserved bit positions are preserved. that is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back. note the software does not need to perform read, merge, and write operations for the configuration address register. reserved registers the mch contains address locations in the configuration space of the host-hi bridge entity that are marked ?reserved?. registers that are marked as ?reserved? must not be modified by system software. writes to ?reserved? registers may cause system failure. reads to ?reserved? registers may return a non-zero value. default value upon reset upon a reset, the mch sets its internal configuration registers to predetermined default states. at reset, some register values are determined by external strapping options. a register?s default value represents the minimum functionality feature set required to successfully bring up the system. hence, it does not represent the optimal system configuration. it is the responsibility of the system initialization software (usually bios) to properly determine the dram configurations, operating parameters and optional system features that are applicable, and to program the mch registers accordingly. term description
datasheet 33 register description table 3-1 shows the device # assignment for the various internal mch devices. all of these devices are on bus #0. 3.3 general routing configuration accesses the mch supports up to four hub interfaces: hi_a, hi_b, hi_c, and hi_d. pci configuration cycles are selectively routed to one of these interfaces. the mch is responsible for routing pci configuration cycles to the proper interface. pci configuration cycles to ich3-s internal devices and primary pci (including downstream devices) are routed to the ich3-s via hi_a. pci configuration cycles to any of the 16-bit hub interfaces are routed to hi_b, hi_c, and hi_d. routing of configuration accesses to hi_b, hi_c, and hi_d is controlled via the standard pci-pci bridge mechanism using information contained within the primary bus number, the secondary bus number, and the subordinate bus number registers of the corresponding pci-pci bridge device. a detailed description of the mechanism for translating processor i/o bus cycles to configuration cycles on one of the buses is described below. note: the mch supports a variety of connectivity options. when any of the mch?s interfaces are disabled, the associated interface?s device registers are not visible. configuration cycles to these registers will return all 1s for a read and master abort for a write. 3.3.1 standard pci configuration mechanism the pci bus defines a slot-based configuration space that allows each device to contain up to eight functions; each function contains up to 256, 8-bit configuration registers. the pci specification defines two bus cycles to access the pci configuration space: configuration read and configuration write. memory and i/o spaces are supported directly by the processor. configuration space is supported by a mapping mechanism implemented within the mch. the pci specification defines two mechanisms to access configuration space, mechanism 1 and mechanism 2. the mch supports only mechanism 1 . the configuration access mechanism makes use of the conf_addr register and conf_data register. to reference a configuration register a dword i/o write cycle is used to place a value into conf_addr that specifies the pci bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. conf_addr[31] must be 1 to enable a configuration cycle. conf_data then becomes a window into the four table 3-1. intel ? e7500 mch logical configuration resources intel ? mch function device #, function # dram controller (8 bit hi_a) device 0, function 0 dram controller error reporting (8 bit hi_a) device 0, function 1 host-to-hi_b bridge controller (16 bit pci2pci) device 2, function 0 host-to-hi_b bridge error reporting (16 bit pci2pci) device 2, function 1 host-to-hi_c bridge controller (16 bit pci2pci) device 3, function 0 host-to-hi_c bridge error reporting (16 bit pci2pci) device 3, function 1 host-to-hi_d bridge controller (16 bit pci2pci) device 4, function 0 host-to-hi_d bridge error reporting (16 bit pci2pci) device 4, function 1
34 datasheet register description bytes of configuration space specified by the contents of conf_addr. any read or write to conf_data results in the mch translating the conf_addr into the appropriate configuration cycle. the mch is responsible for translating and routing the processor?s i/o accesses to the conf_addr and conf_data registers to internal mch configuration registers for hi_a, hi_b, hi_c, and hi_d. 3.3.2 logical pci bus 0 configuration mechanism the mch decodes the bus number (bits 23:16) and the device number fields of the conf_addr register. when the bus number field of conf_addr is 0, the configuration cycle is targeting a pci bus 0 device. ? the host-hi_a bridge entity within the mch is hardwired as device 0 on pci bus 0. ? the host-hi_b bridge entity within the mch is hardwired as device 2 on pci bus 0. ? the host-hi_c bridge entity within the mch is hardwired as device 3 on pci bus 0. ? the host-hi_d bridge entity within the mch is hardwired as device 4 on pci bus 0. configuration cycles to any of the mch?s enabled internal devices are confined to the mch and not sent over hi_a. accesses to devices 8 to 31 are forwarded over hi_a as type 0. the ich3-s decodes the type 0 access and generates a configuration access to the selected internal device. 3.3.3 primary pci downstream configuration mechanism when the bus number in the conf_addr is non-zero, and does not lie between the secondary bus number registers and the subordinate bus number registers for one of the hi_16, the mch will generate a type 1 hi_a configuration cycle. when the cycle is forwarded to the ich3-s via hi_a, the ich3-s compares the non-zero bus number with the secondary bus number and subordinate bus number registers of its pci- pci bridges to determine if the configuration cycle is meant for primary pci, or a downstream pci bus. 3.3.4 hi_b, hi_c, hi_d bus configuration mechanism from the chipset configuration perspective, hi_b, hi_c and hi_d are seen as pci bus interfaces residing on a secondary bus side of the ?virtual? pci-pci bridges referred to as the mch host- hi_b, hi_c and hi_d bridge. note: there is no requirement that the secondary and subordinate bus number values from one hub interface be contiguous with any other hub interfaces. it is possible that hi_b will decode buses 2 through 5, hi_c will decode buses 8 through 12, and hi_d will decode buses 13 through 15. in this case there is a gap where buses 6 and 7 are subtractively decoded to hi_a. when the bus number is non-zero, greater than the value programmed into the secondary bus number register, and less than or equal to the value programmed into the corresponding subordinate bus number register, the configuration cycle is targeting a pci bus downstream of the targeted hub interface. the mch generates a type 1configuration cycle on the appropriate hub interface.
datasheet 35 register description 3.4 sticky registers certain registers in the mch are sticky through a hard-reset. they will only be reset on a power- good reset. these registers in general are the error logging registers and a few special cases. the error command registers are not sticky. the following registers are sticky: ? device 0, function 1 error registers ? device 2, function 1 error registers ? device 3, function 1 error registers ? device 4, function 1 error registers ? others that are determined to need to hold state through reset for function or test purposes 3.5 i/o mapped registers the mch contains two registers that reside in the processor i/o address space; the configuration address (conf_addr) register and the configuration data (conf_data) register. the configuration address register enables/disables the configuration space and determines what portion of configuration space is visible through the configuration data window. 3.5.1 conf_addr?configuration address register i/o address: 0cf8h accessed as a dword default value: 00000000h access: r/w size: 32 bits conf_addr is a 32-bit register that can be accessed only as a dword. a byte or word reference will pass through the configuration address register and hi_a onto the pci_a bus as an i/o cycle. the conf_addr register contains the bus number, device number, function number, and register number that a subsequent configuration access is intended. bit descriptions 31 configuration enable (cfge). 0 = disable 1 = enable 30:24 reserved (these bits are read only and have a value of 0). 23:16 bus number. contains the bus number being targeted by the config cycle. 15:11 device number. selects one of the 32 possible devices per bus. 10:8 function number. selects one of 8 possible functions within a device. 7:2 register number: this field selects one register within a particular bus, device, and function as specified by the other fields in the configuration address register. this field is mapped to a[7:2] during hi_a?d configuration cycles. 1:0 reserved.
36 datasheet register description 3.5.2 conf_data?configuration data register i/o address: 0cfch default value: 00000000h access: read/write size: 32 bits conf_data is a 32-bit read/write window into configuration space. the portion of configuration space that is referenced by conf_data is determined by the contents of conf_addr. bit descriptions 31:0 configuration data window (cdw). if bit 31 of conf_addr is 1, any i/o access to the conf_data register are mapped to configuration space using the contents of conf_addr.
datasheet 37 register description 3.6 dram controller registers (device 0, function 0) the dram controller registers are in device 0 (d0), function 0 (f0). table 3-2 provides the register address map for this device, function. warning: address locations that are not listed the table are considered reserved register locations. writes to ?reserved? registers may cause system failure. reads to ?reserved? registers may return a non- zero value. table 3-2. dram controller register map (hi_a?d0:f0) offset mnemonic register name default type 00?01h vid vendor id 8086h ro 02?03h did device id 2540h ro 04?05h pcicmd pci command 0006h ro, r/w 06?07h pcists pci status 0090h ro, r/wc 08h rid revision id 02h ro 0ah subc sub class code 00h ro 0bh bcc base class code 06h ro 0dh mlt master latency timer 00h ? 0eh hdr header type 00h ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 50?51h mchcfg mch configuration 0004h r/w 52?53h mchcfgns mch memory scrub and init configuration 0000h ro, r/w 58h fdhc fixed dram hole control 00h r/w 59?5fh pam[0:6] programmable attribute map (7 registers) 00h r/w 60?6fh drb dram row boundary 00h r/w 70?77h dra dram row attribute 00h r/w 78?7bh drt dram timing 00000010h r/w 7c?7fh drc dram controller mode 00440009h r/w 8ch clock_dis ck/ck# disable 00h r/w 9dh smram system management ram control 02h ro, r/w, l 9eh esmramc extended system management ram control 38h r/w, r/wc, r/w/l c4?c5h tolm top of low memory 0800h r/w c6?c7h remapbase remap base address 03ffh r/w c8?c8h remaplimit remap limit address 0000h r/w de?dfh skpd scratchpad data 0000h r/w e0?e1h dvnp device not present 1d1fh r/w
38 datasheet register description 3.6.1 vid?vendor identification register (d0:f0) the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. 3.6.2 did?device identification register (d0:f0) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. address offset: 00?01h default: 8086h access: ro size: 16 bits bits default, access description 15:0 8086h ro vendor identification (vid). this register field contains the pci standard identification for intel (vid=8086h). address offset: 02?03h default: 2540h access: ro size: 16 bits bits default, access description 15:0 2540h ro device identification number (did). this is a 16-bit value assigned to the mch host- hi bridge function 0.
datasheet 39 register description 3.6.3 pcicmd?pci command register (d0:f0) since mch device 0 does not physically reside on a physical pci bus portions of this register are not implemented. address offset: o4?05h default: 0006h access: ro, r/w size: 16 bits bits default, access description 15:10 00h reserved 9 0b ro fast back-to-back enable (fb2b). hardwired to 0. this bit controls whether or not the master can do fast back-to-back writes. since device 0 is strictly a target this bit is not implemented. 8 0b r/w serr enable (serre). this is a global enable bit for device 0 serr messaging. the mch does not have an serr signal. the mch communicates the serr condition by sending an serr message over hi_a to the ich3-s. 0 = disable. serr message is not generated by the mch for device 0. 1 = enable. the mch is enabled to generate serr messages over hi_a for specific device 0 error conditions that are individually enabled in the errcmd register. the error status is reported in the errstat and pcists registers. when serre is cleared, the serr message is not generated by the mch for device 0. note: this bit only controls serr messaging for the device 0. devices 2?4 have their own serr bits to control error reporting for error conditions occurring on their respective devices. the control bits are used in a logical or configuration to enable the serr hi message mechanism. 7 0b ro address/data stepping enable (adstep). hardwired to 0. address/data stepping is not implemented in the mch. 6 0b r/w parity error enable (perre). 0 = disable. mch takes no action when it detects a parity error on hi_a. 1 = enable. mch generates an serr message over hi_a to the ich3-s when an address or data parity error is detected by the mch on hi_a (dpe set in pcists). 5 0b ro vga palette snoop enable (vgasnoop). hardwired to 0. the mch does not implement this bit. 4 0b ro memory write and invalidate enable (mwie). hardwired to 0. the mch will never issue memory write and invalidate commands. 3 0b ro special cycle enable (sce). hardwired to 0. the mch does not implement this bit. 2 1b ro bus master enable (bme). hardwired to 1. the mch is always enabled as a master on hi_a. 1 1b ro memory access enable (mae). hardwired to 1. the mch always allows access to main memory. 0 0b ro i/o access enable (ioae). hardwired to 0. this bit is not implemented in the mch.
40 datasheet register description 3.6.4 pcists?pci status register (d0:f0) pcists is a 16-bit status register that reports the occurrence of error events on device 0?s pci interface. all other bits are read only. since mch device 0 does not physically reside on a pci bus, many of these bits are not implemented. note: software must write a 1 to clear bits that are set. address offset: 06?07h default: 0090h access: ro, r/wc size: 16 bits bits default, access description 15 0b r/wc detected parity error (dpe). 0 = no parity error detected. 1 = mch detected an address or data parity error on the hi_a interface. 14 0b r/wc signaled system error (sse). 0 = no serr generated by mch device 0. 1 = mch device 0 generates an serr message over hi_a for any enabled device 0 error condition. device 0 error conditions are enabled in the pcicmd and errcmd registers. device 0 error flags are read/reset from the pcists or errstat registers. 13 0b ro received master abort status (rmas). hardwired to 0. the ich3-s never sends a master abort completion. 12 0b r/wc received target abort status (rtas). 0 = no received target abort generated by mch. 1 = mch generated a hi_a request that received a target abort. 11 0b ro signaled target abort status (stas). hardwired to 0. the mch will not generate a target abort on hi_a. this bit is not implemented. 10:9 00b ro devsel timing (devt). these bits are hardwired to 00. device 0 does not physically connect to pci_a. these bits are set to 00 (fast decode) so that optimum devsel timing for pci_a is not limited by the mch. 8 0b ro master data parity error detected (dpd). hardwired to 0. perr signaling and messaging are not implemented by the mch. 7 1b ro fast back-to-back (fb2b). hardwired to 1. device 0 does not physically connect to pci_a. this bit is set to 1 (indicating fast back-to-back capability) so that the optimum setting for pci_a is not limited by the mch. 6:0 00h reserved
datasheet 41 register description 3.6.5 rid?revision identification register (d0:f0) this register contains the revision number of the mch device 0. 3.6.6 subc?sub-class code register (d0:f0) this register contains the sub-class code for the mch device 0. 3.6.7 bcc?base class code register (d0:f0) this register contains the base class code of the mch device 0. address offset: 08h default: see table below access: ro size: 8 bits bits default, access description 7:0 00h ro revision identification number (rid). this is an 8-bit value that indicates the revision identification number for the mch device 0. 02h = a2 stepping address offset: 0ah default: 00h access: ro size: 8 bits bits default, access description 7:0 00h ro sub-class code (subc). this is an 8-bit value that indicates the category of bridge into which the mch falls. 00h = host bridge. address offset: 0bh default: 06h access: ro size: 8 bits bits default, access description 7:0 06h ro base class code (basec). this is an 8-bit value that indicates the base class code for the mch. 06h = bridge device.
42 datasheet register description 3.6.8 mlt?master latency timer register (d0:f0) device 0 in the mch is not a pci master. therefore, this register is not implemented. 3.6.9 hdr?header type register (d0:f0) this register identifies the header layout of the configuration space. 3.6.10 svid?subsystem vendor identification register (d0:f0) this value is used to identify the vendor of the subsystem. address offset: 0dh default: 00h access: reserved size: 8 bits bits default, access description 7:0 00h reserved address offset: 0eh default: 00h access: ro size: 8 bits bits default, access description 7:0 00h ro pci header (hdr). this register returns 00 when device 0, function 1 is disabled. if device 0, function 1 is enabled via the dvnp register, this register (hdr) returns 80h. address offset: 2c?2dh default: 0000h access: r/wo size: 16 bits bits default, access description 15:0 0000h r/wo subsystem vendor id (subvid). this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only.
datasheet 43 register description 3.6.11 sid?subsystem identification register (d0:f0) this value is used to identify a particular subsystem. 3.6.12 mchcfg?mch configuration register (d0:f0) this register controls how the mch tracks and routes system bus transactions. address offset: 2e?2fh default: 0000h access: r/wo size: 16 bits bits default, access description 15:0 0000h r/wo subsystem id (subid). this field should be programmed during bios initialization. after it has been written once, it becomes read only. address offset: 50?51h default: 0004h access: r/w size: 16 bits bits default, access description 15:13 000b, r/w number of stop grant cycles (nsg). these bits indicate the number of stop grant transactions expected on the system bus before a stop grant acknowledge packet is sent to the ich3-s. this field is programmed by the bios after it has enumerated the processors and before it has enabled stop clock generation in the ich3-s. once this field has been set, it should not be modified. 000 = hi_a stop grant generated after 1 stop grant 001 = hi_a stop grant generated after 2 stop grant 010 = hi_a stop grant generated after 3 stop grant 011 = hi_a stop grant generated after 4 stop grant others = reserved 12:6 000000b reserved
44 datasheet register description 5 0b r/w mda present (mdap). this bit works with the vga enable bits in the bctrl registers of devices 2?4 to control the routing of processor initiated transactions targeting mda compatible i/o and memory address ranges. this bit should not be set if none of the vga enable bits are set. when none of the vga enable bits are set, accesses to i/o address range x3bch?x3bfh are forwarded to hi_a. when the vga enable bit is not set, accesses to i/o address range x3bch?x3bfh are treated just like any other i/o accesses. that is, the cycles are forwarded to hi_b?d if the address is within the corresponding iobase and iolimit and isa enable bit is not set; otherwise, they are forwarded to hi_a. mda resources are defined as the following: memory: 0b0000h ? 0b7fffh i/o: 3b4h, 3b5h, 3b8h, 3b9h, 3bah, 3bfh, (including isa address aliases, a[15:10] are not used in decode) any i/o reference that includes the i/o locations listed above, or their aliases, will be forwarded to the hub interface, even if the reference includes i/o locations not listed above. the following shows the behavior for all combinations of mda and vga: vgamdabehavior 0 0 all references to mda and vga go to hi_a 0 1 illegal combination (do not use) 1 0 all references to vga go to device with vga enable set. mda-only references (i/ o address 3bfh and aliases) will go to hi_a. 1 1 vga references go to the hub interface that has its vgaen bit set. mda references go to hi_a 4 0b r/w throttled-write occurred. 0 =writing a zero clears this bit. 1 =this bit is set when a write is throttled. this bit is set when the maximum allowed number of writes has been reached during a time-slice and there is at least one more write to be completed. 3 0b reserved 2 0b ro in-order queue depth (ioqd). this bit reflects the value sampled on ha7# on the deassertion of the cpurst#. it indicates the depth of the processor bus in-order queue. 0 = when ioqd is set to 0 (ha7# is sampled asserted; i.e., 1; or an electrical low), the depth of the ioq is set to 1 (i.e., no pipelining support on the processor bus). ha7# may be driven low during cpurst# by an external source. 1 = when ioqd is set to 1 (ha7# sampled as 0; an electrical high), the depth of the processor bus in-order queue is configured to the maximum allowed by the processor protocol (i.e., 12). 1:0 00b reserved bits default, access description
datasheet 45 register description 3.6.13 mchcfgns?mch memory scrub and initialization configuration register (d0:f0) this register controls the mode and status of the dram memory scrubber. address offset: 52?53h default: 0000h access: ro, r/w size: 16 bits bits default, access description 15:4 000h reserved 3 0b ro valid ecc initialization complete. bios should poll this bit after enabling auto- initialization to determine when all the ecc values have been written to dram. 1 = the scrub unit sets this bit to 1 after it has completed placing valid ecc data in each line of memory. 2 0b r/w initialization/scrub mode select. this bit determines if the mch is initializing memory (with valid ecc data) or running standard memory scrubbing. in the initialization mode, the mch issues memory writes as quickly as possible and places valid ecc in each memory location. in scrubbing mode, the mch scrubs a memory location (read a memory line and correct any ecc errors) every 32,000 clocks. this scrubs an entire 16 gb memory array in approximately 1 day. 0 = valid ecc init mode 1 = ecc scrub mode bios should set this bit to 0, enable scrubbing via bit 0, wait until bit 3 (valid ecc init complete) is set, and set this bit to 1 (or disable scrubbing). 1 0b reserved 0 0b r/w memory initialization/scrub enable. this bit enables valid ecc init mode or ecc scrub mode depending on the value in bit 2 (init/scrub mode select). 0 = disable 1 = enable
46 datasheet register description 3.6.14 fdhc?fixed dram hole control register (d0:f0) this 8-bit register controls a fixed dram hole from 15 mb ?16 mb address offset: 58h default: 00h sticky: no access: r/w size: 8 bits bit field default and access description 7 0b rw hole enable (hen). this field enables a memory hole in dram space. the dram that lies "behind" this space is not remapped. 0 =no memory hole 1 =memory hole from 15 mb to 16 mb. accesses to this range will be sent to hi_a. 6:0 00h reserved
datasheet 47 register description 3.6.15 pam[0:6]?programmable attribute map registers (d0:f0) the mch allows programmable memory attributes on 13 legacy memory segments of various sizes in the 640 kb to 1 mb address range. seven programmable attribute map (pam) registers support these features. however, not all seven of these registers are identical. pam 0 controls only one segment (high), while pam 1:6 controls two segments (high and low) each. cacheability of these areas is controlled via the mtrr registers in the processor. two bits are used to specify memory attributes for each memory segment. these bits only apply to host initiator access to the pam areas. the mch forwards to main memory any hub interface_a?d initiated accesses to the pam areas. at the time that hub interface accesses to the pam region may occur, the targeted pam segment must be programmed to be both readable and writeable. it is illegal to issue a hub initiated transaction to a pam region with the associated pam register not set to 11. each of these regions has a 2-bit field. the two bits that control each region have the same encoding. as an example, consider bios that is implemented on the expansion bus. during the initialization process, bios can be shadowed in main memory to increase the system performance. when bios is shadowed in main memory, it should be copied to the same address location. to shadow the bios, the attributes for that address range should be set to write only. the bios is shadowed by first doing a read of that address. this read is forwarded to the expansion bus. the host then does a write of the same address, which is directed to main memory. after the bios is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus. table 3-3 and figure 3-1 show the pam registers and the associated attribute bits: address offset: 59?5fh (pam0?pam6) default value: 00h access: r/w size: 8 bits each bits default, access description 7:6 00b reserved 5:4 00b r/w attribute register (hienable). this field controls the steering of read and write cycles that address the bios. 00 = dram disabled - all accesses are directed to hi_a 01 = read only - all reads are serviced by dram. all writes are forwarded to hi_a. 10 = write only - all writes are sent to dram. reads are serviced by hi_a. 11 = normal dram operation - all reads and writes are serviced by dram 3:2 0h reserved 1:0 00b r/w attribute register (loenable). this field controls the steering of read and write cycles that address the bios. 00 =dram disabled - all accesses are directed to hi_a 01 =read only - all reads are serviced by dram. all writes are forwarded to hi_a. 10 =write only - all writes are sent to dram. reads are serviced by hi_a. 1 1 =normal dram operation - all reads and writes are serviced by dram note: the lo segment for pam0 is reserved as shown in figure 3-1 .
48 datasheet register description figure 3-1. pam registers table 3-3. pam associated attribute bits pam reg attribute bits memory segment comments offset pam0 3:0, 7:6 reserved ? ? 59h pam0 5:4 r r we re 0f0000h?0fffffh bios area 59h pam1 3:2, 7:6 ? ? ? ? ? reserved 5ah pam1 1:0 r r we re 0c0000h?0c3fffh bios area 5ah pam1 5:4 r r we re 0c4000h?0c7fffh bios area 5ah pam2 3:2, 7:6 ? ? ? ? ? reserved 5bh pam2 1:0 r r we re 0c8000h?0cbfffh bios area 5bh pam2 5:4 r r we re 0cc000h?0cffffh bios area 5bh pam3 3:2, 7:6 ? ? ? ? ? reserved 5ch pam3 1:0 r r we re 0d0000h?0d3fffh bios area 5ch pam3 5:4 r r we re 0d4000h?0d7fffh bios area 5ch pam4 3:2, 7:6 ? ? ? ? ? reserved 5dh pam4 1:0 r r we re 0d8000h?0dbfffh bios area 5dh pam4 5:4 r r we re 0dc000h?0dffffh bios area 5dh pam5 3:2, 7:6 ? ? ? ? ? reserved 5eh pam5 1:0 r r we re 0e0000h?0e3fffh bios extension 5eh pam5 5:4 r r we re 0e4000h?0e7fffh bios extension 5eh pam6 3:2, 7:6 ? ? ? ? ? reserved 5fh pam6 1:0 r r we re 0e8000h?0ebfffh bios extension 5fh pam6 5:4 r r we re 0ec000h?0effffh bios extension 5fh pam6 5fh pam1 pam2 pam3 pam4 pam5 5ah 5bh 5ch 5dh 5eh offset we r r re r we re r 70 1 2 3 4 5 6 reserved reserved w rite enable (r/w ) 1 = enable 0 = disable read enable (r/w) 1 = enable 0 = disable reserved reserved w rite enable (r/w ) 1 = enable 0 = disable read enable (r/w ) 1 = enable 0 = disable 59h pam0 hi segment lo segment reserved
datasheet 49 register description 3.6.16 drb?dram row boundary register (d0:f0) the dram row boundary register defines the upper boundary address of each dram row with a granularity of 64 mb. a row is 144 bits wide (72 bits per channel). each row has its own single- byte drb register. for example, a value of 1 in drb0 indicates that 64 mb of dram has been populated in the first row. note: the mch dram row boundary registers (drb registers) are 8-bits wide, and define the upper boundary address for each dram row with a granularity of 64 mb. the drb registers are cumulative; therefore, drb7 will contain the total memory contained in all eight dram rows. by this definition, the system is only allowed to report 16 gb?64 mb of memory populated. row 0 = 60h row 1 = 61h row 2 = 62h row 3 = 63h row 4 = 64h row 5 = 65h row 6 = 66h row 7 = 67h 68h to 6fh are reserved drb0 = total memory in row 0 (in 64 mb increments) drb1 = total memory in row 0 + row 1 (in 64 mb increments) drb3 = total memory in row 0 + row 1 + row 2 + row 3 (in 64 mb increments) the row referred to by this register is defined by the dimm chip select used. double-sided dimms use both row 0 and row 1 (for cs0# and cs1#), even though there is one physical slot for the dimm. single-sided dimms use only the even row number, since single-sided dimms only support cs0#. for single-sided dimms, the value bios places in the odd row should equal the same value as what was placed in the even row field. a row is defined as 128-bit (144 bit with ecc) wide interface consisting of two identical dimms. address offset: 60?6fh default: 00h access: r/w size: 8 bits bits default, access description 7:0 00h r/w dram row boundary address. this 8-bit value defines the upper and lower addresses for each row of dram. this 8-bit value is compared against a set of address lines to determine the upper address limit of a particular row.
50 datasheet register description 3.6.17 dra?dram row attribute register (d0:f0) the dram row attribute register defines the page sizes to be used for each row of memory. each nibble of information in the dra registers describes the page size and device width of a row. for this register, a row is defined by the chip select used by the dimm, so that a double-sided dimm would have both an even and an odd entry. for single-sided dimms, only the even side is used. row 0, 1 = 70h row 2, 3 = 71h row 4, 5 = 72h row 6, 7 = 73h address offset: 70?77h default: r/w size: 8 bits default: 00h bits default, access description 7 0b r/w device width for odd-numbered row. this bit defines whether the ddr-sdram devices populated in this row are 4 bits wide (x4) or 8 bits wide. 0 =8 bits wide. 1 =4 bits wide (x4). 6:4 000b r/w row attribute for odd-numbered row. this 3-bit field defines the page size of the corresponding row. 010 = 8 kb 011 = 16 kb 100 = 32 kb 101 = 64 kb others = reserved 3 0b r/w device width for even-numbered row. this bit defines whether the ddr-sdram devices populated in this row are 4 bits wide (x4) or 8 bits wide. 0 =8 bits wide. 1 =4 bits wide (x4). 2:0 000b r/w row attribute for even-numbered row. this 3-bit field defines the page size of the corresponding row. 010 = 8 kb 011 = 16 kb 100 = 32 kb 101 = 64 kb others = reserved
datasheet 51 register description 3.6.18 drt?dram timing register (d0:f0) this register controls the timing of the dram interface. address offset: 78?7bh access: r/w size: 32 bits default: 00000010h bits default, access description 31:30 00b reserved 29 0b r/w back to back write-read turn around. this field determines the minimum number of cmdclk (command clocks, at 100 mhz) between write-read commands. it applies to wr-rd pairs to different rows. the wr-rd pair to the same row has sufficient turnaround due to the t wtr timing parameter. the purpose of this bit is to control the turnaround time on the dq bus. 0 = 3 clocks between wr-rd commands (2 turnaround clocks on dq) 1 = 2 clocks between wr-rd commands (1 turnaround clock on dq) 28 0b r/w back to back read-write turn around. this field determines the minimum number of cmdclk (command clocks, at 100 mhz) between read-write commands. it applies to rd-wr pairs to any destination, in same or different rows. the purpose of this bit is to control the turnaround time on the dq bus. 0 = 5 clocks between rd-wr commands (2 turnaround clocks on dq) 1 = 4 clocks between rd-wr commands (1 turnaround clock on dq) 27 0b r/w back to back read turn around. this field determines the minimum number of cmdclk (command clocks, at 100 mhz) between two reads destined to different rows. the purpose of this bit is to control the turnaround time on the dq bus. 0 = 4 clocks between rd commands to different rows (2 turnaround clocks on dq) 1 = 3 clocks between rd commands to different rows (1 turnaround clock on dq) 26:24 000b r/w read delay (t rd ). this field controls the number of 100 mhz clocks elapsed from the read command latched on the system bus until the returned data is set to be driven on the system bus. the following t rd values are supported. 000 = 7 clocks 001 = 6 clocks 010 = 5 clocks others = reserved 23:11 00000b reserved 10:9 00b r/w activate to precharge delay (t ras ). this bit controls the number of dram clocks for t ras . 00 = 7 clocks 01 = 6 clocks 10 = 5 clocks 11 = reserved 8:6 0000b reserved 5:4 01b r/w cas# latency (t cl ). the number of clocks between the rising edge used by dram to sample the read command and the rising edge used by the dram to drive read data. 00 = 2.5 clocks 01 = 2 clocks 10 = 1.5 clocks 11 = reserved
52 datasheet register description 3.6.19 drc?dram controller mode register (d0:f0) this register controls the mode of the dram controller. 3 0b r/w write ras# to cas# delay (t rcd ). this bit controls the number of clocks inserted between a row activate command and write command to that row. 0 = 3 dram clocks 1 = 2 dram clocks 2 0b reserved 1 0b r/w read ras# to cas# delay (t rcd) . this bit controls the number of clocks inserted between a row activate command and a read command to that row. 0 = 3 dram clocks 1 = 2 dram clocks 0 0b r/w dram ras# precharge (t rp ). this bit controls the number of clocks that are inserted between a row precharge command and an activate command to the same row. 0 = 3 dram clocks 1 = 2 dram clocks address offset: 7c?7fh default: 0044_0009h access: r/w size: 32 bits bits default, access description bits default, access description 31:30 00b reserved 29 0b r/w initialization complete (ic). this bit is used for communicating the software state between the memory controller and the bios. it indicates that the dram interface has been initialized. this bit must be set and the refresh mode select (drc[9:8]) must be set to enable refresh. if this bit is clear, no refresh will occur regardless of the rms (drc[9:8]) setting. 28:22 00h reserved 21:20 00b r/w dram data integrity mode (ddim). these bits select one of two dram data integrity modes. 00 =disable. no ecc correction is performed and no errors are flagged in dram_ferr or dram_nerr. 01 =reserved 10 =error checking, using chip-kill, with correction 11 =reserved 19:18 01b reserved 17 0b reserved 16 0b r/w command per clock ? address/control assertion rule (cpc). this bit defines the number of clock cycles the ma, ras#, cas#, we# are asserted. 0 = 2n rule: (ma [12:0]}, ras#, cas#, we# asserted for 2 clock cycles) 1 = 1n rule (ma [12:0]}, ras#, cas#, we# asserted for 1 clock cycle) 15:10 00b reserved
datasheet 53 register description 3.6.20 clock_dis?ck/ck# disable register (d0:f0) this register controls the ddr clocks for each dimm. 9:8 00b r/w refresh mode select (rms). this field determines whether refresh is enabled and, if so, at what rate refreshes will be executed. 00 = refresh disabled 01 = refresh enabled. refresh interval 15.6 sec 10 = refresh enabled. refresh interval 7.8 sec 11 = refresh enabled. refresh interval 64 sec 7 0b reserved 6:4 000b r/w mode select (sms). these bits select the special operational mode of the dram interface. the special modes are intended for initialization at power up. 000 =self refresh. in this mode ckes are deasserted and the drams are in self-refresh mode. all other combinations of sms bits result in assertion of one or more ckes, except when the device is in c3 or s1 state, where all devices are in self-refresh, without regard to the value in sms. 001 =nop command enable. all processor cycles to dram result in a nop command on the dram interface. 010 =all banks precharge enable. all processor cycles to dram result in an ?all banks precharge? command on the dram interface. 011 =mode register set enable. all processor cycles to dram result in a ?mode register? set command on the dram interface. host address lines are mapped to sdram address lines in order to specify the command sent. host address lines 15:3 are typically mapped to ma[12:0]. 100 = extended mode register set enable. all processor cycles to sdram result in an ?extended mode register set? command on the dram interface (ddr only). host address lines are mapped to sdram address lines in order to specify the command sent. host address lines 15:3 are typically mapped to ma[12:0]. 101 =reserved. 110 =cbr refresh enable. in this mode all processor cycles to dram result in a cbr cycle on the sdram interface 111 =normal operation 3:0 0000b reserved address offset: 8ch default: 00h sticky: no access: r/w size: 8 bits bits default, access description bit default, access description 7:4 0h reserved 3:0 0h r/w ck/ck# disable. each bit of this four bit field corresponds to a pair of ck/ck# pins on both channels. bit 0 corresponds to ck0 and ck0# while bit 3 corresponds to ck3 and ck3#. 1 = these bits turn off the corresponding ck/ck# pair. ck is driven low and ck# is driven high. this feature is intended to reduce emi due to clocks toggling to dimms which are not populated.
54 datasheet register description 3.6.21 smram?system management ram control register (d0:f0) the smramc register controls how accesses to compatible and extended smram spaces are treated. the open, close, and lock bits function only when g_smrame bit is set to 1. the open bit must be reset before the lock bit is set. address offset: 9dh default: 02h access: ro, r/w, l size: 8 bits bits default, access description 7 0b reserved 6 0b r/w smm space open (d_open). when d_open=1 and d_lck=0, the smm space dram is made visible even when smm decode is not active. this is intended to help bios initialize smm space. software should ensure that d_open=1 and d_cls=1 are not set at the same time. 5 0b r/w smm space closed (d_cls). when d_cls = 1 smm space dram is not accessible to data references, even if smm decode is active. code references may still access smm space dram. this will allow smm software to reference through smm space to update the display even when smm is mapped over the vga range. software should ensure that d_open=1 and d_cls=1 are not set at the same time. note that the d_cls bit only applies to compatible smm space. 4 0b r/w smm space locked (d_lck). when d_lck is set to 1, d_open is reset to 0 and d_lck, d_open, c_base_seg, h_smram_en, tseg_sz and tseg_en become read only. d_lck can be set to 1 via a normal configuration space write but can only be cleared by a full reset. the combination of d_lck and d_open provide convenience and security. the bios can use the d_open function to initialize smm space and then use d_lck to ?lock down? smm space in the future so that no application software (or the bios itself) can violate the integrity of smm space, even if the program has knowledge of the d_open function. 3 0b l global smram enable (g_smrame). if set to 1, then compatible smram functions are enabled, providing 128 kb of dram accessible at the a0000h address while in smm (ads# with smm decode). to enable extended smram function this bit must be set to 1. refer to section 4.3, ?smm space? on page 4-117 for more details regarding smm. once d_lck is set, this bit becomes read only. 2:0 010b ro compatible smm space base segment (c_base_seg). this field indicates the location of smm space. smm dram is not remapped. it is simply made visible if the conditions are right to access smm space, otherwise the access is forwarded to the hub interface. since the mch supports only the smm space between a0000h and bffffh, this field is hardwired to 010.
datasheet 55 register description 3.6.22 esmramc?extended system management ram control register (d0:f0) the extended smram register controls the configuration of extended smram space. the extended smram (e_smram) memory provides a write-back cacheable smram memory space that is above 1 mb. address offset: 9eh default: 38h access: r/w, r/wc, r/w/l size: 8 bits bits default, access description 7 0b r/w/l enable high smram (h_smrame). controls the smm memory space location (i.e., above 1 mb or below 1 mb) when g_smrame is 1 and h_smrame is set to 1, the high smram memory space is enabled. smram accesses within the range 0ffea0000h to 0ffeaffffh are remapped to dram addresses within the range 000a0000h to 000bffffh. once d_lck has been set, this bit becomes read only. 6 0b r/wc invalid smram access (e_smerr). 1 =this bit is set when the processor has accessed the defined memory ranges in extended smram (high memory and t-segment) while not in smm space and with the d-open bit = 0. it is software?s responsibility to clear this bit. note: software must write a 1 to this bit to clear it. 5:3 111b reserved 2:1 00b r/w tseg size (tseg_sz). selects the size of the tseg memory block if enabled. memory from the top of main memory space (tolm - tseg_sz) to tolm is partitioned away so that it may only be accessed by the processor interface and only then when the smm bit is set in the request packet. non-smm accesses to this memory region are sent to the hub interface when the tseg memory block is enabled. encodingdescription 00 (tolm?128 kb) to tolm 01 (tolm?256 kb) to tolm 10 (tolm?512 kb) to tolm 11 (tolm?-1 mb) to tolm 0 0b r/w/l tseg enable (tseg_en). enables smram memory for extended smram space only. when g_smrame =1 and tseg_en = 1, the tseg is enabled to appear in the appropriate physical address space. note that once d_lck is set, this bit becomes read only.
56 datasheet register description 3.6.23 tolm?top of low memory register (d0:f0) this register contains the maximum address below 4 gb that should be treated as main memory, and is defined on a 128-mb boundary. normally, it is set below the areas configured for the hub interface and pci memory. note that the memory address found in drb7 reflects the top of total memory. in the event that the total of pci space to main memory combined is less than 4 gb, these two registers will be set the same. 3.6.24 remapbase?remap base address register (d0:f0) this register specifies the lower boundary of the remap window. refer to section 4.4 for more information. address offset: c4?c5h default: 0800h access: r/w size: 16 bits bits default, access description 15:11 00001b r/w top of low memory (tolm). this register contains the address that corresponds to bits 31:27 of the maximum dram memory address that lies below 4 gb. 10:0 000h reserved address offset: c6?c7h default: 03ffh access: r/w size: 16 bits bits default, access description 15:10 000000b reserved 9:0 3ffh r/w remap base address [35:26]. the value in this register defines the lower boundary of the remap window. the remap window is inclusive of this address. a[25:0] of the remap base address are assumed to be 0s. thus, the bottom of the defined memory range will be aligned to a 64-mb boundary. when the value in this register is greater than the value programmed into the remap limit register, the remap window is disabled. this field defaults to ffh.
datasheet 57 register description 3.6.25 remaplimit?remap limit address register (d0:f0) this register specifies the upper boundary of the remap window 3.6.26 skpd?scratchpad data register (d0:f0) this register contains bits that can be used for general purpose storage. address offset: c8?c9h default: 0000h access: r/w size: 16 bits bits default, access description 15:10 000000b reserved 9:0 000h r/w remap base address [35:26]. the value in this register defines the upper boundary of the remap window. the remap window is inclusive of this address. a[25:0] of the remap limit address are assumed to be fs. thus, the top of the defined memory range will be one less than a 64-mb boundary. when the value in this register is less than the value programmed into the remap base register, the remap window is disabled. address offset: de?dfh default: 0000h access: r/w size: 16 bits bits default, access description 15:0 0000h r/w scratchpad (scrtch). these bits are r/w storage bits that have no effect on the mch functionality.
58 datasheet register description 3.6.27 dvnp?device not present register (d0:f0) this register is used to control whether the function 1 portions of the pci configuration space for devices 0, 2, 3, and 4 is visible to software. if a device?s function 1 is disabled, that device will appear to have only 1 function (function 0). address offset: e0?e1h default: 1d1fh access: r/w size: 16 bits bits default, access description 15:5 0e8h reserved 4 1b r/w device 4, function 1 present. 0 = present 1 = not present 3 1b r/w device 3, function 1 present. 0 = present 1 = not present 2 1b r/w device 2, function 1 present. 0 = present 1 = not present 1 1b reserved 0 1b r/w device 0, function 1 present. 0 = present 1 = not present
datasheet 59 register description 3.7 dram controller error reporting registers (device 0, function 1) this section describes the dram controller registers for device 0 (d0), function 1 (f1). table 3-4 provides the register address map for this device, function. warning: address locations that are not listed in the table are considered reserved register locations. writes to ?reserved? registers may cause system failure. reads to ?reserved? registers may return a non- zero value. table 3-4. dram controller register map (hi_a?d0:f1) offset mnemonic register name default type 00?01h vid vendor id 8086h ro 02?03h did device id 2541h ro 04?05h pcicmd pci command 0000h r/w 06?07h pcists pci status 0000h r/wc 08h rid revision id 02h ro 0ah subc sub class code 00h ro 0bh bcc base class code ffh ro 0dh mlt master latency timer 00h ? 0eh hdr header type 00h or 80h ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 40?43h ferr_global global error 00000000h r/wc 44?47h nerr_global global error 00000000h r/wc 50h hia_ferr hub interface_a first error 00h r/wc 52h hia_nerr hub interface_a next error 00h r/wc 58h scicmd_hia sci command 00h r/w 5ah smicmd_hia smi command 00h r/w 5ch serrcmd_hia serr command 00h r/w 60h sysbus_ferr system bus first error 00h r/wc 62h sysbus_nerr system bus next error 00h r/wc 68h scicmd_sysbus sci command 00h r/w 6ah smicmd_sysbus smi command 00h r/w 6ch serrcmd_sysbus serr command 00h r/w 80h dram_ferr dram first error 00h r/wc 82h dram_nerr dram next error 00h r/wc 88h scicmd_dram sci command 00h r/w 8ah smicmd_dram smi command 00h r/w 8ch serrcmd_dram serr command 00h r/w
60 datasheet register description 3.7.1 vid?vendor identification register (d0:f1) the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. 3.7.2 did?device identification register (d0:f1) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. a0?a3h dram_celog_add dram firs correctable memory error address 00000000h ro b0?b3h dram_uelog_add dram firs uncorrectable memory error address 00000000h ro d0?d1h dram_celog_ syndrome dram first correctable memory error 0000h ro address offset: 00?01h default: 8086h sticky no access: ro size: 16 bits table 3-4. dram controller register map (hi_a?d0:f1) (continued) offset mnemonic register name default type bits default, access description 15:0 8086h ro vendor identification device (vid). this register field contains the pci standard identification for intel (vid=8086h). address offset: 02?03h default: 2541h sticky: no access: ro size: 16 bits bits default, access description 15:0 2541h ro device identification number (did). this is a 16-bit value assigned to the mch host-hi bridge.
datasheet 61 register description 3.7.3 pcicmd?pci command register (d0:f1) since mch device 0 does not physically reside on a physical pci bus portions of this register are not implemented. 3.7.4 pcists?pci status register (d0:f1) pcists is a 16-bit status register that reports the occurrence of error events on device 0s pci interface. since mch device 0 does not physically reside on a pci bus, this register is not implemented. address offset: 04-05h default: 0000h sticky: no access: r/w size: 16 bits bits default, access description 15:9 00h reserved 8 0b r/w serr enable (serre). this bit is a global enable bit for device 0 serr generations. 0 =disable. serr is not generated by the mch for device 0. 1 =enable. the mch is enabled to generate an serr for specific device 0 error conditions that are individually enabled in the serrcmd register. 7:0 00h reserved address offset: 06-07h default: 0000h sticky: no access: r/wc size: 16 bits bits default, access description 15 0b reserved 14 0b r/wc signaled system error (sse). 0 = serr not generated by mch device 0 1 = mch device 0 generated a serr. note: software sets this bit to 0 by writing a 1 to it. 13:0 0000h reserved
62 datasheet register description 3.7.5 rid?revision identification register (d0:f1) this register contains the revision number of the mch device 0. 3.7.6 subc?sub-class code register (d0:f1) this register contains the sub-class code for the mch device 0, function 1. address offset: 08h default: see table below sticky: no access: ro size: 8 bits bits default, access description 7:0 02h ro revision identification number (rid). this is an 8-bit value that indicates the revision identification number for the mch device 0. this number should always be the same as the rid for device 0, function 0. 02h = a2 stepping address offset: 0ah default: 00h sticky: no access: ro size: 8 bits bits default, access description 7:0 00h ro sub-class code (subc). this is an 8-bit value that indicates sub-class code for the mch device 0, function 1. the code is 00h.
datasheet 63 register description 3.7.7 bcc?base class code register (d0:f1) this register contains the base class code of the mch device 0, function 1. 3.7.8 mlt?master latency timer register (d0:f1) device 0 in the mch is not a pci master. therefore, this register is not implemented. address offset: 0bh default: ffh sticky: no access: ro size: 8 bits bits default, access description 7:0 ffh ro base class code (basec). this is an 8-bit value that indicates the base class code for the mch. ffh =non-defined device. since this function is used for error conditions, it does not fall into any other class. address offset: 0dh default: 00h sticky: no access: reserved size: 8 bits bits default, access description 7:0 00h reserved
64 datasheet register description 3.7.9 hdr?header type (d0:f1) this register identifies the header layout of the configuration space. it is hardwired to 80h to indicate a multi-function device. address offset: 0eh default: 00h or 80h sticky: no access: ro size: 8 bits bits default, access description 7:0 00h or 80h ro pci header (hdr). this read only field always returns 00h or 80h (value depends on device not present register) to indicate that the mch is a multi-function device with standard header layout.
datasheet 65 register description 3.7.10 svid?subsystem vendor identification register (d0:f1) this value is used to identify the vendor of the subsystem. 3.7.11 sid?subsystem identification register (d0:f1) this value is used to identify a particular subsystem. address offset: 2ch default: 0000h sticky: no access: r/wo size: 16 bits bits default, access description 15:0 0000h r/wo subsystem vendor id (subvid). this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only. address offset: 2eh default: 0000h sticky: no access: r/wo size: 16 bits bits default, access description 15:0 0000h r/wo subsystem id (subid). this field should be programmed during bios initialization. after it has been written once, it becomes read only.
66 datasheet register description 3.7.12 ferr_global?global error register (d0:f1) this register is used to report various error conditions. an serr is generated on a 0-to-1 transition of any of these flags (if enabled by the errcmd and pcicmd registers). these bits are set regardless of whether or not the serr is enabled and generated. this register stores the first global error. any future errors (next errors) will be set in the nerr_global register. no further error bits in this register will be set until the existing error bit is cleared. note: to prevent the same error from being logged twice in ferr_global and nerr_global, a ferr_global bit being set blocks the respective bit in the nerr_global register from being set. in addition, bits [18:16] are grouped such that if any of these bits are set in the ferr_global register, none of the bits [18:16] can be set in the nerr_global register. for example, if hi_a causes its respective ferr_global bit to be set, any subsequent ddr, fsb, or hi_a error will not be logged in the nerr_global register. each of these three bits are part of device 0 status and having any one of them set in ferr_global represents a "device 0 first error" occurred. this implementation blocks logging in nerr_global of any subsequent "device 0" errors, and allows only logging of subsequent errors that are from other devices. note: software must write a 1 to clear bits that are set. address offset: 40?43h default: 0000_0000h sticky: yes access: r/wc size: 32 bits bits default, access description 31:19 0000h reserved 18 0b r/wc dram interface error detected. 0 = no dram interface error. 1 = mch detected an error on the dram interface. 17 0b r/wc hi_a error detected. 0 = no hi_a interface error. 1 = mch detected an error on the hi_a. 16 0b r/wc system bus error detected. 0 = no system bus interface error. 1 = mch detected an error on the system bus. 15:5 000h reserved 4 0b r/wc hi_d error detected. 0 = no hi_d interface error. 1 = mch detected an error on hi_d. 3 0b r/wc hi_c error detected. 0 = no hi_c interface error. 1 = mch detected an error on hi_c. 2 0b r/wc hi_b error detected. 0 = no hi_b interface error. 1 = mch detected an error on hi_b. 1:0 00b reserved
datasheet 67 register description 3.7.13 nerr_global?global error register (d0:f1) the first global error will be stored in ferr_global. this register stores all future global errors. multiple bits in this register may be set. note: to prevent the same error from being logged twice in ferr_global and nerr_global, a ferr_global bit being set blocks the respective bit in the nerr_global register from being set. in addition, bits [18:16] are grouped such that if any of these bits are set in the ferr_global register, none of the bits [18:16] can be set in the nerr_global register. for example, if hi_a causes its respective ferr_global bit to be set, any subsequent ddr, fsb, or hi_a error will not be logged in the nerr_global register. each of these three bits are part of device 0 status and having any one of them set in ferr_global represents a "device 0 first error" occurred. this implementation blocks logging in nerr_global of any subsequent "device 0" errors, and allows only logging of subsequent errors that are from other devices. note: software must write a 1 to clear bits that are set. address offset: 44?47h default: 0000_0000h sticky: yes access: r/wc size: 32 bits bits default, access description 31:19 0000h reserved 18 0b r/wc dram interface error detected. 0 = no dram interface error detected. 1 = the mch has detected an error on the dram interface. 17 0b r/wc hi_a error detected. 0 = no hi_a interface error detected. 1 = the mch has detected an error on the hi_a. 16 0b r/wc system bus error detected. 0 = no system bus interface error detected. 1 = the mch has detected an error on the system bus. 15:5 000h reserved 4 0b r/wc hi_d error detected. 0 = no hi_d interface error detected. 1 = the mch has detected an error on hi_d. 3 0b r/wc hi_c error detected. 0 = no hi_c interface error detected. 1 = the mch has detected an error on hi_c. 2 0b r/wc hi_b error detected. 0 = no hi_b interface error detected. 1 = the mch has detected an error on hi_b. 1:0 00b reserved
68 datasheet register description 3.7.14 hia_ferr?hub interface_a first error register (d0:f1) this register stores the first error related to the hi_a. only 1 error bit will be set in this register. any future errors (next errors) will be set the hia_nerr register. no further error bits in this register will be set until the existing error bit is cleared. note: software must write a 1 to clear bits that are set. address offset: 50h default: 00h sticky: yes access: r/wc size: 8 bits bits default, access description 7 0b reserved 6 0b r/wc hi_a target abort. 0 = no target abort on mch originated hi_a cycle detected. 1 = mch detected that an mch originated hi_a cycle was terminated with a target abort. 5 0b reserved 4 0b r/wc hi_a data parity error detected. 0 = no data parity error detected. 1 = mch detected a parity error on a hi_a data transfer. 3:1 000b reserved 0 0b r/wc hi_a address/command error detected. 0 = no address or command parity error detected. 1 = mch detected a parity error on a hi_a address or command.
datasheet 69 register description 3.7.15 hia_nerr?hub interface_a next error register (d0:f1) the first hi_a error will be stored in the hia_ferr register. this register stores all future hi_a errors. multiple bits in this register may be set. note: software must write a 1 to clear bits that are set. address offset: 52h default: 00h sticky: yes access: r/wc size: 8 bits bits default, access description 7 0b reserved 6 0b r/wc hi_a target abort. 0 = no target abort on mch originated hi_a cycle terminated. 1 = mch originated hi_a cycle was terminated with a target abort. 5 0b reserved 4 0b r/wc hi_a data parity error detected. 0 = no data parity error detected. 1 = parity error on a hi_a data transfer. 3:1 000b reserved 0 0b r/wc hi_a data address/command error detected. 0 = no address or command parity error detected. 1 = parity error on a hi_a address or command.
70 datasheet register description 3.7.16 scicmd_hia?sci command register (d0:f1) this register determines whether sci will be generated when the associated flag is set in the hia_ferr or hia_nerr register. when an error flag is set in the hia_ferr or hia_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 58h default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b reserved 6 0b r/w sci on hi_a target abort enable. 0 = no sci generation 1 = generate sci if bit 6 is set in hia_ferr or hia_nerr 5 0b reserved 4 0b r/w sci on hi_a data parity error detected enable. 0 = no sci generation 1 = generate sci if bit 4 is set in hia_ferr or hia_nerr 3:1 000b reserved 0 0b r/w sci on hi_a data address/comment error detected enable. 0 = no sci generation 1 = generate sci if bit 0 is set in hia_ferr or hia_nerr
datasheet 71 register description 3.7.17 smicmd_hia?smi command register (d0:f1) this register determine whether smi will be generated when the associated flag is set in either the hia_ferr or hia_nerr register. when an error flag is set in the hia_ferr or hia_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 5ah default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b reserved 6 0b r/w smi on hi_a target abort enable. 0 = no smi generation 1 = generate smi if bit 6 is set in hia_ferr or hia_nerr 5 0b reserved 4 0b r/w smi on hi_a data parity error detected enable. 0 = no smi generation 1 = generate smi if bit 4 is set in hia_ferr or hia_nerr 3:1 000b reserved 0 0b r/w smi on hi_a data address/comment error detected enable. 0 = no smi generation 1 = generate smi if bit 0 is set in hia_ferr or hia_nerr
72 datasheet register description 3.7.18 serrcmd_hia?serr command register (d0:f1) this register determine whether serr will be generated when the associated flag is set in either the hia_ferr or hia_nerr register. when an error flag is set in the hia_ferr or hia_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 5ch default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b reserved 6 0b r/w serr on hi_a target abort enable. 0 = no serr generation 1 = generate serr if bit 6 is set in hia_ferr or hia_nerr 5 0b reserved 4 0b r/w serr on hi_a data parity error detected enable. 0 = no serr generation 1 = generate serr if bit 4 is set in hia_ferr or hia_nerr 3:1 000b reserved 0 0b r/w seer on hi_a data address/comment error detected enable. 0 = no serr generation 1 = generate serr if bit 0 is set in hia_ferr or hia_nerr
datasheet 73 register description 3.7.19 sysbus_ferr?system bus first error register (d0:f1) this register stores the first error related to the system bus interface. any future errors (next errors) will be set in the sysbus_nerr register. no further error bits in this register will be set until the existing error bit is cleared. note: software must write a 1 to clear bits that are set. address offset: 60h default: 00h sticky: yes access: r/wc size: 8 bits bits default, access description 7 0b r/wc system bus binit# detected. 0 = no system bus bint# detected. 1 = this bit is set on an electrical high-to-low transition (0-to-1) of binit#. 6 0b r/wc system bus xerr# detected. 0 = no system bus xerr# detected. 1 = this bit is set on an electrical high-to-low transition (0 to 1) of xerr# on the system bus. 5 0b r/wc non-dram lock error (ndlock). 0 = no dram lock error detected. 1 = mch detected a lock operation to memory space that did not map into dram. 4 0b r/wc system bus address above tom (sbatom). 0 = no system bus address above tom detected. 1 = mch detected an address above drb7, which is the top of memory and above 4 gb. 3 0b r/wc system bus data parity error (sbdpar). 0 = no system bus data parity error detected. 1 = the mch has detected a data parity error on the system bus. 2 0b r/wc system bus address strobe glitch detected (sbagl). 0 = no system bus address strobe glitch detected. 1 = the mch has detected a glitch on one of the system bus address strobes. 1 0b r/wc system bus data strobe glitch detected (sbdgl). 0 = no system bus data strobe glitch detected. 1 = the mch has detected a glitch on one of the system bus data strobes. 0 0b r/wc system bus request/address parity error (sbrpar). 0 = no system bus request/address parity error detected. 1 = mch detected a parity error on either the address or request signals of the system bus.
74 datasheet register description 3.7.20 sysbus_nerr?system bus next error register (d0:f1) the first system bus error will be stored in the sysbus_ferr register. this register stores all future system bus errors. multiple bits in this register may be set. note: software must write a 1 to clear bits that are set. address offset: 62h default: 00h sticky: yes access: r/wc size: 8 bits bits default, access description 7 0b r/wc system bus binit# detected. 0 = no system bus binit# detected. 1 = this bit is set on an electrical high-to-low transition (0 to 1) of binit#. 6 0b r/wc system bus xerr# detected. 0 = no system bus xerr# detected. 1 = this bit is set on an electrical high-to-low transition (0 to 1) of xerr# on the system bus. 5 0b r/wc non-dram lock error (ndlock). 0 = no non-dram lock error detected. 1 = the mch has detected a lock operation to memory space that did not map into dram. 4 0b r/wc system bus address above tom (sbatom). 0 = no system bus address above tom detected. 1 = mch detected an address above drb7, which is the top of memory and above 4 gb. 3 0b r/wc system bus data parity error (sbdpar). 0 = no system bus data parity error detected. 1 = mch detected a data parity error on the system bus. 2 0b r/wc system bus address strobe glitch detected (sbagl). 0 = no system bus address strobe glitch detected. 1 = mch detected a glitch on one of the system bus address strobes. 1 0b r/wc system bus data strobe glitch detected (sbdgl). 0 = no system bus data strobe glitch detected. 1 = mch detected a glitch on one of the system bus data strobes. 0 0b r/wc system bus request/address parity error (sbrpar). 0 = no system bus request/address parity error detected. 1 = mch detected a parity error on either the address or request signals of the system bus.
datasheet 75 register description 3.7.21 scicmd_sysbus?sci command register (d0:f1) this register determine whether sci will be generated when the associated flag is set in either the sysbus_ferr or sysbus_nerr register. when an error flag is set in the sysbus_ferr or sysbus_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 68h default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b r/w sci on system bus binit# detected enable. 0 = no sci generation 1 = generate sci if bit 7 is set in sysbus_ferr or sysbus_nerr 6 0b r/w sci on system bus xerr# detected enable. 0 = no sci generation 1 = generate sci if bit 6 is set in sysbus_ferr or sysbus_nerr 5 0b r/w sci on non-dram lock error enable. 0 = no sci generation 1 = generate sci if bit 5 is set in sysbus_ferr or sysbus_nerr 4 0b r/w sci on system bus address above tom enable. 0 = no sci generation 1 = generate sci if bit 4 is set in sysbus_ferr or sysbus_nerr 3 0b r/w sci on system bus data parity error enable. 0 = no sci generation 1 = generate sci if bit 3 is set in sysbus_ferr or sysbus_nerr 2 0b r/w sci on system bus address strobe glitch detected enable. 0 = no sci generation 1 = generate sci if bit 2 is set in sysbus_ferr or sysbus_nerr 1 0b r/w sci on system bus data strobe glitch detected enable. 0 = no sci generation 1 = generate sci if bit 1 is set in sysbus_ferr or sysbus_nerr 0 0b r/w sci on system bus request/address parity error enable. 0 = no sci generation 1 = generate sci if bit 0 is set in sysbus_ferr or sysbus_nerr
76 datasheet register description 3.7.22 smicmd_sysbus?smi command register (d0:f1) this register determines whether smi will be generated when the associated flag is set in either the sysbus_ferr or sysbus_nerr register. when an error flag is set in the sysbus_ferr or sysbus_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 6ah default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b r/w smi on system bus binit# detected enable. 0 = no smi generation 1 = generate smi if bit 7 is set in sysbus_ferr or sysbus_nerr 6 0b r/w smi on system bus xerr# detected enable. 0 = no smi generation 1 = generate smi if bit 6 is set in sysbus_ferr or sysbus_nerr 5 0b r/w smi on non-dram lock error enable. 0 = no smi generation 1 = generate smi if bit 5 is set in sysbus_ferr or sysbus_nerr 4 0b r/w smi on system bus address above tom enable. 0 = no smi generation 1 = generate smi if bit 4 is set in sysbus_ferr or sysbus_nerr 3 0b r/w smi on system bus data parity error enable. 0 = no smi generation 1 = generate smi if bit 3 is set in sysbus_ferr or sysbus_nerr 2 0b r/w smi on system bus address strobe glitch detected enable. 0 = no smi generation 1 = generate smi if bit 2 is set in sysbus_ferr or sysbus_nerr 1 0b r/w smi on system bus data strobe glitch detected enable. 0 = no smi generation 1 = generate smi if bit 1 is set in sysbus_ferr or sysbus_nerr 0 0b r/w smi on system bus request/address parity error enable. 0 = no smi generation 1 = generate smi if bit 0 is set in sysbus_ferr or sysbus_nerr
datasheet 77 register description 3.7.23 serrcmd_sysbus?serr command register (d0:f1) this register determines whether serr will be generated when the associated flag is set in either the sysbus_ferr or sysbus_nerr register. when an error flag is set in the sysbus_ferr or sysbus_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 6ch default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b r/w serr on system bus binit# detected enable. 0 = no serr generation 1 = generate serr if bit 7 is set in sysbus_ferr or sysbus_nerr 6 0b r/w serr on system bus xerr# detected enable. 0 = no serr generation 1 = generate serr if bit 6 is set in sysbus_ferr or sysbus_nerr 5 0b r/w serr on non-dram lock error enable. 0 = no serr generation 1 = generate serr if bit 5 is set in sysbus_ferr or sysbus_nerr 4 0b r/w serr on system bus address above tom enable. 0 = no serr generation 1 = generate serr if bit 4 is set in sysbus_ferr or sysbus_nerr 3 0b r/w serr on system bus data parity error enable. 0 = no serr generation 1 = generate serr if bit 3 is set in sysbus_ferr or sysbus_nerr 2 0b r/w serr on system bus address strobe glitch detected enable. 0 = no serr generation 1 = generate serr if bit 2 is set in sysbus_ferr or sysbus_nerr 1 0b r/w serr on system bus data strobe glitch detected enable. 0 = no serr generation 1 = generate serr if bit 1 is set in sysbus_ferr or sysbus_nerr 0 0b r/w serr on system bus request/address parity error enable. 0 = no serr generation 1 = generate serr if bit 0 is set in sysbus_ferr or sysbus_nerr
78 datasheet register description 3.7.24 dram_ferr?dram first error register (d0:f1) this register stores the first ecc error on the dram interface. only 1 error bit will be set in this register. any future errors (next errors) will be set in the dram_nerr register. no further error bits in this register will be set until the existing error bit is cleared. note: software must write a 1 to clear bits that are set. 3.7.25 dram_nerr?dram next error register (d0:f1) the first memory ecc error will be stored in the dram_ferr register. this register stores all future memory ecc errors. multiple bits in this register may be set. note: software must write a 1 to clear bits that are set. address offset: 80h default: 00h sticky: yes access: r/wc size: 8 bits bits default, access description 7:2 00h reserved 1 0b r/wc uncorrectable memory error detected. 0 = no uncorrectable memory error detected. 1 = mch detected an ecc error on the memory interface that is not correctable. 0 0b r/wc correctable memory error detected. 0 = no correctable memory error detected. 1 = mch detected and corrected an ecc error on the memory interface. address offset: 82h default: 00h sticky: yes access: r/wc size: 8 bits bits default, access description 7:2 00h reserved 1 0b r/wc uncorrectable memory error detected. 0 = no uncorrectable memory error detected. 1 = the mch has detected an ecc error on the memory interface that is not correctable. 0 0b r/wc correctable memory error detected. 0 = no correctable memory error detected. 1 = the mch has detected and corrected an ecc error on the memory interface.
datasheet 79 register description 3.7.26 scicmd_dram?sci command register (d0:f1) this register determines whether sci will be generated when the associated flag is set in either the dram_ferr or dram_nerr register. when an error flag is set in the dram_ferr or dram_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. 3.7.27 smicmd_dram?smi command register (d0:f1) this register determines whether smi will be generated when the associated flag is set in the dram_ferr or dram_nerr register. when an error flag is set in the dram_ferr or dram_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: 88h default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:2 000000b reserved 1 0b r/w sci on multiple-bit dram ecc error (dmerr). 0 = disable. 1 = enable. the mch generates an sci when it detects a multiple-bit error reported by the dram controller. 0 0b r/w sci on single-bit dram ecc error (dserr). 0 = disable. 1 = enable. the mch generates an sci when the dram controller detects a single-bit error. address offset: 8ah default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:2 000000b reserved 1 0b r/w smi on multiple-bit dram ecc error (dmerr). 0 = disable. 1 = enable. the mch generates an smi when it detects a multiple-bit error reported by the dram controller. 0 0b r/w smi on single-bit dram ecc error (dserr). 0 = disable. 1 = enable. the mch generates an smi when the dram controller detects a single-bit error.
80 datasheet register description 3.7.28 serrcmd_dram?serr command register (d0:f1) this register determines whether serr will be generated when the associated flag is set in either the dram_ferr or dram_nerr register. when an error flag is set in the dram_ferr or dram_nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. 3.7.29 dram_celog_add?dram first correctable memory error address register (d0:f1) this register contains the address of the first correctable memory error. this register is locked when bits in either the dram_ferr or dram_nerr registers are set. if the bits in both registers are set to 0, the dram_celog_add can be updated; however, if a bit in either register is set to 1, then dram_celog_add will retain its value for logging purposes. this register is only valid if a bit in either the dram_ferr or dram_nerr register is set. address offset: 8ch default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:2 000000b reserved 1 0b r/w serr on multiple-bit dram ecc error (dmerr). 0 = disable. 1 = enable. the mch generates an serr when it detects a multiple-bit error reported by the dram controller. 0 0b r/w serr on single-bit dram ecc error (dserr). 0 = disable. 1 = enable. the mch generates an serr when the dram controller detects a single-bit error. address offset: a0?a3h default: 0000_0000h sticky: yes access: ro size: 32 bits bits default, access description 31:28 0h reserved 27:6 000000h ro ce address. this field contains address bits 33:12 of the first correctable memory error. the address bits are a physical address. 5:0 00h reserved
datasheet 81 register description 3.7.30 dram_uelog_add?dram first uncorrectable memory error address register (d0:f1) this register contains the address of the first uncorrectable memory error. when a bit in either the dram_ferr or dram_nerr register is set, this register is locked. this register is only valid if a bit in either the dram_ferr or dram_nerr register is set. 3.7.31 dram_celog_syndrome?dram first correctable memory error register (d0:f1) this register contains the syndrome of the first correctable memory error. this register is locked when a bit in either the dram_ferr or dram_nerr register is set. if the bits in both registers are set to 0, the dram_celog_syndrome can be updated; however, if a bit in either register is set to 1, then dram_celog_syndrome will retain its value for logging purposes. this register is only valid if a bit in either the dram_ferr or dram_nerr register is set. address offset: b0?b3h default: 0000_0000h sticky: yes access: ro size: 32 bits bits default, access description 31:28 0h reserved 27:6 000000h ro ue address. this field contains address bits 33:12 of the first uncorrectable memory error. the address bits are a physical address. 5:0 00h reserved address offset: d0?d1h default: 0000h sticky: yes access: ro size: 16 bits bits default, access description 15:0 0000h ro ecc syndrome for correctable errors.
82 datasheet register description 3.8 hi_b virtual pci-to-pci bridge registers (device 2, function 0) this section provides the register descriptions for the hi_b virtual pci-to-pci bridge (device 2, function 0). table 3-5 provides the register address map for this device, function. warning: address locations that are not listed the table are considered reserved register locations. writes to ?reserved? registers may cause system failure. reads to ?reserved? registers may return a non- zero value. table 3-5. hi_b virtual pci-to-pci bridge register map (hi_a?d2:f0) offset mnemonic register name default type 00?01h vid2 vendor id 8086h ro 02?03h did2 device id 2543h ro 04?05h pcicmd2 pci command 0000h ro, r/w 06?07h pcists2 pci status 00a0h ro, r/wc 08h rid2 revision id 02h ro 0ah subc2 sub class code 04h ro 0bh bcc2 base class code 06h ro 0dh mlt2 master latency timer 00h r/w 0eh hdr2 header type 01h or 81h ro 18h pbusn2 primary bus number 00h ro 19h busn2 secondary bus number 00h r/w 1ah subusn2 subordinate bus number 00h r/w 1bh smlt2 secondary bus master latency timer 00h reserved 1ch iobase2 i/o base address f0h r/w 1dh iolimit2 i/o limit address 00h r/w 1e?1fh sec_sts2 secondary status 0160 ro, r/wc 20?21h mbase2 memory base address fff0h r/w 22?23h mlimit2 memory limit address 0000h r/w 24?25h pmbase2 prefetchable memory base address fff0h ro, r/w 26?27h pmlimit2 prefetchable memory limit address 0000h ro, r/w 3eh bctrl2 bridge control 00h ro, r/w
datasheet 83 register description 3.8.1 vid2?vendor identification register (d2:f0) the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identify any pci device. 3.8.2 did2?device identification register (d2:f0) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. address offset: 00?01h default: 8086h sticky: no access: ro size: 16 bits bits default, access description 15:0 8086h ro vendor identification device 2 (vid2). this register field contains the pci standard identification for intel (vid=8086h). address offset: 02?03h default: 2543h sticky: no access: ro size: 16 bits bits default, access description 15:0 2543h ro device identification number (did). this is a 16-bit value assigned to the mch device 2.
84 datasheet register description 3.8.3 pcicmd2?pci command register (d2:f0) since mch device 0 does not physically reside on a physical pci bus, portions of this register are not implemented. address offset: 04?05h default: 0000h sticky: no access: ro r/w size: 16 bits bits default, access description 15:10 00h reserved 9 0b ro fast back-to-back enable (fb2b). not applicable; hardwired to 0. 8 0b r/w serr message enable (serre). this bit is a global enable bit for device 2 serr messaging. the mch does not have an serr# signal. the mch communicates the serr# condition by sending an serr message to the ich3-s. 0 = serr message is not generated by the mch for device 2. 1 = the mch is enabled to generate serr messages over hi_a for specific device 2 error conditions. 7 0b ro address/data stepping (adstep). not applicable; this bit is hardwired to 0. 6 0b ro parity error enable (perre). hardwired to 0. parity checking is not supported on the primary side of this device. 5 0b reserved 4 0b ro memory write and invalidate enable (mwie). not applicable; hardwired to 0. 3 0b ro special cycle enable (sce). not applicable; hardwired to 0. 2 0b r/w bus master enable (bme). this bit is not functional. it is a r/w bit for compatibility with compliance testing software. 1 0b r/w memory access enable (mae). 0 = disable. all of device 2?s memory space is disabled. 1 = enable. this bit must be set to 1 to enable the memory and prefetchable memory address ranges defined in the mbase2, mlimit2, pmbase2, and pmlimit2 registers. 0 0b r/w io access enable (ioae). 0 = disable. all of device 2?s i/o space is disabled. 1 = enable. this bit must be set to 1 to enable the i/o address range defined in the iobase2 and iolimit2 registers.
datasheet 85 register description 3.8.4 pcists2?pci status register (d2:f0) pcists2 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the ?virtual? pci-pci bridge embedded within the mch. address offset: 06h default: 00a0h sticky: no access: ro, r/wc size: 16 bits bits default, access description 15 0b ro detected parity error (dpe). hardwired to 0. parity is not supported on the primary side of this device. 14 0b r/wc signaled system error (sse). 0 =no serr generated by mch device 2. 1 =mch device 2 generates an serr message over hi_a for any enabled device 2 error condition. note: software clears this bit by writing a 1 to it. 13 0b ro received master abort status (rmas). hardwired to 0. the concept of master abort does not exist on primary side of this device. 12 0b ro received target abort status (rtas). hardwired to 0. the concept of target abort does not exist on primary side of this device. 11 0b ro signaled target abort status (stas). hardwired to 0. the concept of target abort does not exist on primary side of this device. 10:9 00b ro devsel# timing (devt). the mch does not support subtractive decoding devices on bus 0. this bit field is therefore hardwired to 00 to indicate that device 2 uses the fastest possible decode. 8 0b ro master data parity error detected (dpd). hardwired to 0. parity is not supported on the primary side of this device. 7 1b ro fast back-to-back (fb2b). hardwired to 1. fast back to back writes are always supported on this interface. 6 0b reserved 5 1b ro 66/60mhz capability (cap66). hardwired to 1. since hi_b is capable of delivering data at a rate equal to that of any pci66 device this bit is hardwired to a 1 so that configuration software understands that downstream devices may also be effectively enabled for 66 mhz operation. 4:0 00h reserved
86 datasheet register description 3.8.5 rid2?revision identification register (d2:f0) this register contains the revision number of the mch device 2. 3.8.6 subc2?sub-class code register (d2:f0) this register contains the sub-class code for the mch device 2. address offset: 08h default: see table below sticky: no access: ro size: 8 bits bits default, access description 7:0 02h ro revision identification number (rid). this is an 8-bit value that indicates the revision identification number for the mch device 2. 02h = a2 stepping address offset: 0ah default: 04h sticky: no access: ro size: 8 bits bits default, access description 7:0 04h ro sub-class code (subc). this is an 8-bit value that indicates the category of bridge into which device 2 of the mch falls. 04h = pci-to-pci bridge.
datasheet 87 register description 3.8.7 bcc2?base class code register (d2:f0) this register contains the base class code of the mch device 2. 3.8.8 mlt2?master latency timer register (d2:f0) this functionality is not applicable. it is described here since these bits should be implemented as read/write to ensue proper execution of standard pci-to-pci bridge configuration software. address offset: 0bh default: 06h sticky: no access: ro size 8 bits bits default, access description 7:0 06h ro base class code (basec). this is an 8-bit value that indicates the base class code for the mch device 2. 06h = bridge device address offset: 0dh default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:3 00h r/w scratchpad mlt (na7.3). these bits return the value with which they are written; however, they have no internal function and are implemented as a scratchpad. 2:0 000b reserved
88 datasheet register description 3.8.9 hdr2?header type register (d2:f0) this register identifies the header layout of the configuration space. 3.8.10 pbusn2?primary bus number register (d2:f0) this register identifies that ?virtual? pci-pci bridge is connected to bus 0. address offset: 0eh default: 01h or 81h sticky: no access: ro size: 8 bits bits default, access description 7:0 01h or 81h ro header type register (hdr). when function 1 is enabled, this read only field returns 81h to indicate that mch device 2 is a multi-function device with bridge header layout. when function 1 is disabled, 01h is returned to indicate that mch device 2 is a single- function device with bridge layout. writes to this location have no effect. address offset: 18h default: 00h sticky: no access: ro size: 8 bits bits default, access description 7:0 00h ro primary bus number (busn). configuration software typically programs this field with the number of the bus on the primary side of the bridge. since device 2 is an internal device and its primary bus is always 0, these bits are read only and are hardwired to 0.
datasheet 89 register description 3.8.11 busn2?secondary bus number register (d2:f0) this register identifies the bus number assigned to the second bus side of the ?virtual? pci-pci bridge (the hi_b connection). this number is programmed by the pci configuration software to allow mapping of configuration cycles to a second bridge device connected to hi_b. 3.8.12 subusn2?subordinate bus number register (d2:f0) this register identifies the subordinate bus (if any) that resides at the level below the secondary hi. this number is programmed by the pci configuration software to allow mapping of configuration cycles to devices subordinate to the secondary hi. address offset: 19h default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:0 00h r/w secondary bus number (busn). this field is programmed by configuration software with the lowest bus number of the busses connected to hi_b. since both bus 0, device 2 and the pci to pci bridge on the other end of the hi are considered by configuration software to be pci bridges, this bus number will always correspond to the bus number assigned to hi_b. address offset: 1ah default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:0 00h r/w subordinate bus number (busn). this register is programmed by configuration software with the number of the highest subordinate bus that lies behind the device 2 bridge.
90 datasheet register description 3.8.13 smlt2?secondary bus master latency timer register (d2:f0) this register is not implemented. address offset: 1bh default: 00h sticky: no access: reserved size: 8 bits bits default, access description 7:0 00h reserved
datasheet 91 register description 3.8.14 iobase2?i/o base address register (d2:f0) this register controls the processor-to-hi_b i/o access routing based on the following formula: io_base < address < io_limit only the upper 4 bits are programmable. for the purpose of address decode, address bits a[11:0] are treated as 0. thus, the bottom of the defined i/o address range will be aligned to a 4-kb boundary. 3.8.15 iolimit2?i/o limit address register (d2:f0) this register controls the processor to hi_b i/o access routing based on the following formula: io_base< address 92 datasheet register description 3.8.16 sec_sts2?secondary status register (d2:f0) ssts2 is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e., hi_b side) of the ?virtual? pci-pci bridge embedded within the mch. note: software must write a 1 to clear bits that are set. address offset: 1e?1fh default: 0160h sticky: no access: ro, r/wc size: 16 bits bits default, access description 15 0b r/wc detected parity error (2dpe). 0 = no parity error detected. 1 = mch detected a parity error in the address or data phase of hi_b bus transactions. 14 0b r/wc received system error (2rse). 0 = no system error received. 1 = this bit is set to 1 when the mch receives an serr message on hi_b. 13 0b r/wc received master abort status (2rmas). 0 = no master abort received. 1 = the mch received a master abort completion packet on hi_b. 12 0b r/wc received target abort status (2rtas). 0 = no target abort received. 1 = the mch received a target abort completion packet on hi_b. 11 0b ro signaled target abort status (stas). hardwired to 0. the mch does not generate target aborts on hi_b. 10:9 01b ro devsel# timing (devt). hardwired to 01. this concept is not supported on hi_b. 8 0b ro master data parity error detected (dpd). hardwired to 0. the mch does not implement perr messaging on hi_b. 7 1b ro fast back-to-back (fb2b). hardwired to 1. this function is not supported on hi_b. 6 0b reserved 5 1b ro 66/60 mhz capability (cap66). hardwired to 1. hi_b is enabled for 66 mhz operation. 4:0 00h reserved
datasheet 93 register description 3.8.17 mbase2?memory base address register (d2:f0) this register controls the processor to hi_b non-prefetchable memory access routing based on the following formula: memory_base < address < memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32 bit address. the bottom 4 bits of this register are read-only and return 0s when read. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be 0. the bottom of the defined memory address range will be aligned to a 1-mb boundary. address offset: 20?21h default: fff0h sticky: no access: r/w size: 16 bits bits default, access description 15:4 fffh r/w memory address base (mbase). this field corresponds to a[31:20] of the lower limit of the memory range that will be passed by the device 2 bridge to hi_b. 3:0 0h reserved
94 datasheet register description 3.8.18 mlimit2?memory limit address register (d2:f0) this register controls the processor to hi_b non-prefetchable memory access routing based on the following formula: memory_base < address < memory_limit the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 32-bit address. the bottom four bits of this register are read-only and return 0s when read. this register must be initialized by the configuration software. for the purpose of address decode, address bits a[19:0] are assumed to be fffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. note: the memory range covered by the mbase and mlimit registers are used to map non- prefetchable hi_b address ranges (typically where control/status memory-mapped i/o data structures of the graphics controller will reside) and pmbase and pmlimit are used to map prefetchable address ranges (typically graphics local memory). this segregation allows application of uswc space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved hi memory access performance. configuration software is responsible for programming all address range registers (prefetchable, non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap with each other and/or with the ranges covered with the main memory). there is no provision in the mch hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed. address offset: 22?23h default: 0000h sticky: no access: r/w size: 16 bits bits default, access description 15:4 000h r/w memory address limit (milimit). this field corresponds to a[31:20] of the memory address that corresponds to the upper limit of the range of memory accesses that will be passed by the device 2 bridge to hi_b 3:0 0h reserved
datasheet 95 register description 3.8.19 pmbase2?prefetchable memory base address register (d2:f0) this register controls the processor to hi_b prefetchable memory accesses. see pm64base2 for usage. the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 36-bit address. for the purpose of address decode, bits a[19:0] are assumed to be 0. thus, the bottom of the defined memory address range will be aligned to a 1-mb boundary. 3.8.20 pmlimit2?prefetchable memory limit address register (d2:f0) this register controls the processor to hi_b prefetchable memory accesses. see pm64base2 for usage. the upper 12 bits of the register are read/write and correspond to the upper 12 address bits a[31:20] of the 36-bit address. for the purpose of address decode, bits a[19:0] are assumed to be ffffh. thus, the top of the defined memory address range will be at the top of a 1-mb aligned memory block. address offset: 24?25h default: fff0h sticky: no access: ro, r/w size: 16 bits bits default, access description 15:4 fffh r/w prefetchable memory address base (pmbase). this field corresponds to a[31:20] of the lower limit of the address range passed by bridge device 2 across hi_b. 3:0 0h ro 64-bit addressing support. hardwired to 0. the mch does not support outbound 64-bit addressing. address offset: 26h default: 0000h sticky: no access: ro, r/w size: 16 bits bits default, access description 15:4 000h r/w prefetchable memory address limit (pmlimit). this field corresponds to a[31:20] of the upper limit of the address range passed by bridge device 2 across hi_b. 3:0 0h ro 64-bit addressing support. hardwired to 0. the mch does not support outbound 64-bit addressing.
96 datasheet register description 3.8.21 bctrl2?bridge control register (d2:f0) this register provides extensions to the pcicmd2 register that are specific to pci-pci bridges. the bctrl provides additional control for the secondary interface (i.e., hi_b) as well as some bits that affect the overall behavior of the ?virtual? pci-pci bridge in the mch (e.g., vga compatible address range mapping). address offset: 3eh default: 00h sticky: no access: ro, r/w size: 8 bits bits default, access description 7 0b ro fast back-to-back enable (fb2ben). hardwired to 0. the mch does not generate fast back-to-back cycles as a master on hi_b. 6 0b ro secondary bus reset (sreset). hardwired to 0. the mch does not support generation of reset via this bit on the hi_b. 5 0b ro master abort mode (mamode). hardwired to 0. thus, when acting as a master on hi_b, the mch will drop writes on the floor and return all 1s during reads when a master abort occurs. 4 0b reserved 3 0b r/w vga enable (vgaen). this bit controls the routing of processor-initiated transactions targeting vga compatible i/o and memory address ranges. the following must be enforced via software. 0 = this bit is set to 0 if the video device is not present behind the bridge. 1 = if video device is behind the bridge, this bit is set to 1. note: only one of device 2?4?s vgaen bits are allowed to be set. 2 0b r/w isa enable (isaen). modifies the response by the mch to an i/o access issued by the processor that target isa i/o addresses. this applies only to i/o addresses that are enabled by the iobase and iolimit registers. 0 = all addresses defined by the iobase and iolimit for processor i/o transactions will be mapped to hi_b. 1 = mch does not forward to hi_b any i/o transactions addressing the last 768 bytes in each 1 kb block, even if the addresses are within the range defined by the iobase and iolimit registers. instead of going to hi_b, these cycles are forwarded to hi_a where they can be subtractively or positively claimed by the isa bridge. 1 0b r/w serr enable (2serren). this bit enables or disables forwarding of serr messages from hi_b to hi_a, where they can be converted into interrupts that are eventually delivered to the processor. 0 = disable 1 = enable 0 0b r/w parity error response enable (2peren). controls the mch?s response to data phase parity errors on hi_b. 0 = address and data parity errors on hi_b are not reported via the mch hi_a serr messaging mechanism. 1 = address and data parity errors on hi_b are reported via the hi_a serr messaging mechanism, if further enabled by 2serren. note: other types of error conditions can still be signaled via serr messaging independent of this bit?s state.
datasheet 97 register description 3.9 hi_b virtual pci-to-pci bridge registers (device 2, function 1) this section provides the register descriptions for the hi_b virtual pci-to-pci bridge (device 2, function 1). table 3-6 provides the register address map for this device, function. warning: address locations that are not listed in the table are considered reserved register locations. writes to ?reserved? registers may cause system failure. reads to ?reserved? registers may return a non- zero value. table 3-6. hi_b virtual pci-to-pci bridge register map (hi_a?d2:f1) offset mnemonic register name default type 00?01h vid vendor id 8086h ro 02?03h did device id 2544h ro 04?05h pcicmd pci command 0000h ro, r/w 06?07h pcists pci status 0000h r/wc 08h rid revision id 02h ro 0ah subc sub class code 00h ro 0bh bcc base class code ffh ro 0eh hdr header type 00h or 80h ro 2c?2dh svid subsystem vendor identification 0000h r/wo 2e?2fh sid subsystem identification 0000h r/wo 80h hib_ferr hub interface_b first error 00h r/wc 82h hib_nerr hub interface_b next error 00h r/wc a0h serrcmd2 serr command 00h r/w a2h smicmd2 smi command 00h r/w a4h scicmd2 sci command 00h r/w
98 datasheet register description 3.9.1 vid?vendor identification register (d2:f1) the vid register contains the vendor identification number. this 16-bit register combined with the device identification register uniquely identifies any pci device. 3.9.2 did?device identification register (d2:f1) . address offset: 00h default: 8086h sticky: no smb shadowed: yes access: ro size: 16 bits bits default, access description 15:0 8086h ro vendor identification (vid). this register field contains the pci standard identification for intel (vid=8086h). address offset: 02h default: 2544h sticky: no smb shadowed: yes access: ro size: 16 bits bits default, access description 15:0 2544h ro device identification number (did). this is a 16-bit value assigned to the mch host-hi bridge function 1. the value is 2544h.
datasheet 99 register description 3.9.3 pcicmd?pci command register (d2:f1) since mch device 0 does not physically reside on a physical pci bus portions of this register are not implemented. 3.9.4 pcists?pci status register (d2:f1) pcists is a 16-bit status register that reports the occurrence of error events on device 0?s pci interface. bit 14 is read/write clear. all other bits are read only. since mch device 0 does not physically reside on pci_a many of the bits are not implemented. address offset: 04h default: 0000h sticky: no smb shadowed: yes access: r/w size: 16 bits bits default, access description 15:9 00h reserved 8 0b r/w serr enable (serre). this bit is global enable bit for device 2 serr messaging. 0 = disable. serr is not generated by the mch for device 2. 1 = enable. the mch is enabled to generate serr over hi_a for specific device 2 error conditions that are individually enabled in the errcmd register. the error status is reported in the errstat and pcists registers. 7:0 00h reserved address offset: 06h default: 0000h sticky: no smb shadowed: yes access: r/wc size: 16 bits bits default, access description 15 0b reserved 14 0b r/wc signaled system error (sse). 0 = no signaled system error generated. 1 = mch device 2 generated an serr over hi_a for any enabled device 2 error condition. device 2 error conditions are enabled in the pcicmd and errcmd registers. device 2 error flags are read/reset from the pcists or errstat registers. note: software sets this bit to 0 by writing a 1 to it. 13:0 000h reserved
100 datasheet register description 3.9.5 rid?revision identification register (d2:f1) this register contains the revision number of the mch device 0. 3.9.6 subc?sub-class code register (d2:f1) this register contains the sub-class code for the mch device 0. address offset: 08h default: see table below sticky: no smb shadowed: yes access: ro size: 8 bits bits default, access description 7:0 02h ro revision identification number (rid). this is an 8-bit value that indicates the revision identification number for the mch device 0. this value should always be the same as the rid for device0, function 0. 02h = a2 stepping address offset: 0ah default: 00h sticky: no smb shadowed: yes access: ro size: 8 bits bits default, access description 7:0 00h ro sub-class code (subc). this is an 8-bit value that indicates the category of undefined. 00h = undefined device.
datasheet 101 register description 3.9.7 bcc?base class code register (d2:f1) this register contains the base class code of the mch device 2. 3.9.8 hdr?header type register (d2:f1) this register identifies the header layout of the configuration space. no physical register exists at this location. address offset: 0bh default: ffh sticky: no smb shadowed: yes access: ro size: 8 bits bits default, access description 7:0 ffh ro base class code (basec). this is an 8-bit value that indicates the base class code for the mch. ffh =non-defined device. since this function is used for error conditions, it does not fall into any other class. address offset: 0eh default: 00h or 80h sticky: no smb shadowed: yes access: ro size: 8 bits bits default, access description 7:0 00h or 80h ro pci header (hdr). this read only field always returns 00h or 80h to indicate that the mch is a multi-function device with standard header layout.
102 datasheet register description 3.9.9 svid?subsystem vendor identification register (d2:f1) this value is used to identify the vendor of the subsystem. 3.9.10 sid?subsystem identification register (d2:f1) this value is used to identify a particular subsystem. address offset: 2c?2dh default: 0000h sticky: no smb shadowed: yes access: r/wo size: 16 bits bits default, access description 15:0 0000h r/wo subsystem vendor id (subvid). this field should be programmed during boot-up to indicate the vendor of the system board. after it has been written once, it becomes read only. address offset: 2e?2fh default: 0000h sticky: no smb shadowed: yes access: r/wo size: 16 bits bits default, access description 15:0 0000h r/wo subsystem id (subid). this field should be programmed during bios initialization. after it has been written once, it becomes read only.
datasheet 103 register description 3.9.11 hib_ferr?hub interface_b first error register (d2:f1) this register store the first error related to hi_b. only one error bit will be set in this register. any future errors (next errors) will be set. no further error bits in this register will be set until the existing error bit is cleared. note: software must write a 1 to clear bits that are set. address offset: 80h default: 00h sticky: yes smb shadowed: yes access: r/wc size: 8 bits bits default, access description 7 0b reserved 6 0b r/wc mch received serr from hi_b. 0 = no serr from hi_b detected. 1 = mch detected a serr on hub interface_b. 5 0b r/wc mch master abort on hi_b (hibma). mch did a master abort to a hi_b request. 0 = no master abort on hi_b detected. 1 = mch detected an invalid address that will be master aborted. this bit is set even when the mch does not respond with the master abort completion packet. 4 0b r/wc received target abort on hi_b. 0 = no target abort on hi_b detected. 1 = mch detected that an mch originated cycle was terminated with a target abort completion packet. 3 0b r/wc correctable error on header/address from hi_b. 0 = no correctable error on header/address from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a single bit correctable error. 2 0b r/wc correctable error on data from hi_b. 0 = no correctable error on data from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a single bit correctable error. 1 0b r/wc uncorrectable error on header/address from hi_b. 0 = no uncorrectable error on header/address from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a multi-bit uncorrectable error. 0 0b r/wc uncorrectable error on data transfer from hi_b. 0 = no uncorrectable error on data from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a multi-bit uncorrectable error.
104 datasheet register description 3.9.12 hib_nerr?hub interface_b next error register (d2:f1) the first error related to hi_b will be stored in the hib_ferr register. this register store all future errors related to the hi_b. multiple bits in this register may be set. note: software must write a 1 to clear bits that are set. address offset: 82h default: 00h sticky: yes smb shadowed: yes access: r/wc size: 8 bits bits default, access description 7 0b reserved 6 0b r/wc mch received serr from hi_b. 0 = no serr from hi_b received. 1 = mch received serr from hi_b. 5 0b r/wc mch master abort on hi_b (hibma). mch did a master abort to a hi_b request. 0 = no master abort on hi_b detected. 1 = the mch detected an invalid address that will be master aborted. this bit is set even when the mch does not respond with the master abort completion packet. 4 0b r/wc received target abort on hi_b. 0 = no target abort detected. 1 = the mch has detected that an mch originated cycle was terminated with a target abort completion packet. 3 0b r/wc correctable error on header/address from hi_b. 0 = no correctable error on header/address from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a single bit correctable error. 2 0b r/wc correctable error on data from hi_b. 0 = no correctable error on data from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a single bit correctable error. 1 0b r/wc uncorrectable error on header/address from hi_b. 0 = no uncorrectable error on header/address from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a multi-bit uncorrectable error. 0 0b r/wc uncorrectable error on data transfer from hi_b. 0 = no uncorrectable error on data from hi_b detected. 1 = even when error correction is turned off, this bit may be set if a packet is received that has a multi-bit uncorrectable error.
datasheet 105 register description 3.9.13 serrcmd2?serr command register (d2:f1) this register determines whether serr will be generated when the associated flag is set in the ferr or nerr register. when an error flag is set in the ferr or nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: a0h default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7:6 00b reserved 5 0b r/w serr on mch master abort to a hi_b request enable. 0 = no serr generation 1 = generate serr if bit 5 is set in hib_ferr or hib_nerr 4 0b r/w serr on received target abort on hi_b enable. 0 = no serr generation 1 = generate serr if bit 4 is set in hib_ferr or hib_nerr 3 0b r/w serr on correctable error on header/address from hi_b enable. 0 = no serr generation 1 = generate serr if bit 3 is set in hib_ferr or hib_nerr 2 0b r/w serr on correctable error on data from hi_b enable. 0 = no serr generation 1 = generate serr if bit 2 is set in hib_ferr or hib_nerr 1 0b r/w serr on uncorrectable error on header/address from hi_b enable. 0 = no serr generation 1 = generate serr if bit 1is set in hib_ferr or hib_nerr 0 0b r/w serr on uncorrectable error on data transfer from hi_b enable. 0 = no serr generation 1 = generate serr if bit 0 is set in hib_ferr or hib_nerr
106 datasheet register description 3.9.14 smicmd2?smi command register (d2:f1) this register determines whether smi will be generated when the associated flag is set in the ferr or nerr register. when an error flag is set in the ferr or nerr register, it can generate an serr, smi, or sci when enabled in the serrcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: a2h default: 00h sticky: no access: r/w size: 8 bits bits default, access description 7 0b reserved 6 0b r/w smi on mch received serr from hi_b enable. 0 = no smi generation 1 = generate smi if bit 6 is set in hib_ferr or hib_nerr 5 0b r/w smi on mch master abort to a hi_b request enable. 0 = no smi generation 1 = generate smi if bit 5 is set in hib_ferr or hib_nerr 4 0b r/w smi on received target abort on hi_b enable. 0 = no smi generation 1 = generate serr if bit 4 is set in hib_ferr or hib_nerr 3 0b r/w smi on correctable error on header/address from hi_b enable. 0 = no smi generation 1 = generate smi if bit 3 is set in hib_ferr or hib_nerr 2 0b r/w smi on correctable error on data from hi_b enable. 0 = no smi generation 1 = generate smi if bit 2 is set in hib_ferr or hib_nerr 1 0b r/w smi on uncorrectable error on header/address from hi_b enable. 0 = no smi generation 1 = generate smi if bit 1is set in hib_ferr or hib_nerr 0 0b r/w smi on uncorrectable error on data transfer from hi_b enable. 0 = no smi generation 1 = generate smi if bit 0 is set in hib_ferr or hib_nerr
datasheet 107 register description 3.9.15 scicmd2?sci command register (d2:f1) this register determines whether sci will be generated when the associated flag is set in the ferr or nerr register. when an error flag is set in the ferr or nerr register, it can generate an serr, smi, or sci when enabled in the errcmd, smicmd, or scicmd registers, respectively. only one message type can be enabled. address offset: a4h default: 00h sticky: yes access: r/w size: 8 bits bits default, access description 7 0b reserved 6 0b r/w sci on mch received serr from hi_b enable. 0 = no sci generation 1 = generate sci if bit 6 is set in hib_ferr or hib_nerr 5 0b r/w sci on mch master abort to a hi_b request enable. 0 = no sci generation 1 = generate sci if bit 5 is set in hib_ferr or hib_nerr 4 0b r/w sci on received target abort on hi_b enable. 0 = no sci generation 1 = generate sci if bit 4 is set in hib_ferr or hib_nerr 3 0b r/w sci on correctable error on header/address from hi_b enable. 0 = no sci generation 1 = generate sci if bit 3 is set in hib_ferr or hib_nerr 2 0b r/w sci on correctable error on data from hi_b enable. 0 = no sci generation 1 = generate sci if bit 2 is set in hib_ferr or hib_nerr 1 0b r/w sci on uncorrectable error on header/address from hi_b enable. 0 = no sci generation 1 = generate sci if bit 1is set in hib_ferr or hib_nerr 0 0b r/w sci on uncorrectable error on data transfer from hi_b enable. 0 = no sci generation 1 = generate sci if bit 0 is set in hib_ferr or hib_nerr
108 datasheet register description 3.10 hi_c virtual pci-to-pci bridge registers (device 3, function 0,1) device 3 is the hi_c virtual pci-to-pci bridge. the register descriptions for device 3 are the same as device 2 (except for the did registers). this section contains the did register descriptions for device 3, function 0,1. for other register descriptions, refer to section 3.8 and section 3.9 . 3.10.1 did?device identification register (d3:f0) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. 3.10.2 did?device identification register (d3:f1) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. address offset: 02?03h default: 2545h access: ro size: 16 bits bits default, access description 15:0 2545h ro device identification number (did). this is a 16-bit value assigned to the mch device 3. address offset: 02?03h default: 2546h access: ro size: 16 bits bits default, access description 15:0 2546h ro device identification number (did). this is a 16-bit value assigned to the mch device 3.
datasheet 109 register description 3.11 hi_d virtual pci-to-pci bridge registers (device 4, function 0,1) device 4 is the hi_d virtual pci-to-pci bridge. the register descriptions for device 4 are the same as device 2 (except for the did registers). this section contains the did register descriptions for device 4, function 0,1. for other register descriptions, refer to section 3.8 and section 3.9 . 3.11.1 did?device identification register (d4:f0) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. 3.11.2 did?device identification register (d4:f1) this 16-bit register combined with the vendor identification register uniquely identifies any pci device. writes to this register have no effect. address offset: 02?03h default: 2547h access: ro size: 16 bits bits default, access description 15:0 2547h ro device identification number (did). this is a 16-bit value assigned to the mch device 4. address offset: 02?03h default: 2548h access: ro size: 16 bits bits default, access description 15:0 2548h ro device identification number (did). this is a 16-bit value assigned to the mch device 4.
110 datasheet register description this page is intentionally left blank.
datasheet 111 system address map system address map 4 a system based on the e7500 chipset supports 16 gb of host-addressable memory space and 64 kb + 3 bytes of host-addressable i/o space. the i/o and memory spaces are divided by system configuration software into regions. the memory ranges are useful either as system memory or as specialized memory, while the i/o regions are used solely to control the operation of devices in the system. 4.1 system memory spaces there are four basic regions of memory in the system: ? high memory range. memory above 4 gb. this memory range is for additional main memory (1_0000_0000h to 3_ffff_ffffh). ? memory between 1 mb and the top of low memory (tolm) register. this is a main memory address range (0_0100_0000h to tolm). ? memory between the tolm register and 4 gb. this range is used for mapping apic and hub interface_a?d. programmable non-overlapping i/o windows can be mapped to this area. ? dos compatible memory area. memory below 1 mb (0_0000_0000h to 0_0009_ffffh). figure 4-1. system address map these address ranges are always mapped to system memory, regardless of the system configuration. memory may be allocated from the main memory segment 0_0100_0000h to tolm for use by system management mode (smm) hardware and software. the top of main memory is defined by the top of low memory (tolm) register. note that the address of the highest 64 mb quantity of valid memory in the system is placed into the drb7 register. for systems with a total dram space and pci memory-mapped space of less than 4 gb, this value will be the same as the one programmed into the tolm register. for other memory configurations, the two are unlikely to be the same, since the pci configuration portion of the bios software will program the tolm dos legacy address range main memory address range pci memory address range top of low memory 1 mb 4 gb hub interface_a?d i/o aperture apics independently programmable non-overlapping windows additional main memory address range 16 gb
112 datasheet system address map register to the maximum value that is less than 4 gb and also allows enough room for all populated pci devices. figure 4-2 shows the segments within the extended memory segment (1 mb to 4 gb). figure 4-2. detailed extended memory range address map = main memory region = optional main memory region 1_0000_0000 (4 gb) fef0_0000 fee0_0000 fed0_0000 top of low memory (tolm) fec0_0000 fec8_0000 ff00_0000 100a_0000 100c_0000 00f0_0000 (15 mb) 0100_0000 (16 mb) 0010_0000 (1 mb) tem - tseg high bios, optional extended smram dd 3 isa hole (optional) extended smram space local apic space hub interface_b?d, i/o apic space hub interface_a, i/o apic space hub interface_b?d windows hub interface_a (always) hub interface_a (always)
datasheet 113 system address map 4.1.1 vga and mda memory spaces video cards use these legacy address ranges to map a frame buffer or a character-based video buffer. the address ranges in this memory space are: ? vgaa 0_000a_0000h to 0_000a_ffffh ? mda 0_000b_0000h to 0_000b_7fffh ? vgab 0_000b_8000h to 0_000b_ffffh by default, accesses to these ranges are forwarded to hub interface_a. however, if the vga_en bit is set in the bctrl 2?4 configuration registers, then transactions within the vga and mda spaces are sent to hub interface_b, c, d, respectively. note: the vga_en bit may be set in one and only one of the bctrl registers. software must not set more than one of the vga_en bits. if the configuration bit mchcfg.mdap is set, accesses that fall within the mda range will be sent to hub interface_a without regard for the vgaen bits. legacy support requires the ability to have a second graphics controller (monochrome) in the system. in a e7500 chipset system, accesses in the standard vga range are forwarded to hub interface_b, c, d (depending on configuration bits). since the monochrome adapter may be on the hi_a/pci (or isa) bus, the mch must decode cycles in the mda range and forward them to hub interface_a. this capability is controlled by a configuration bit (mdap bit). in addition to the memory range b0000h to b7fffh, the mch decodes i/o cycles at 3b4h, 3b5h, 3b8h, 3b9h, 3bah and 3bfh and forwards them to hub interface_a. an optimization allows the system to reclaim the memory displaced by these regions. when smm memory space is enabled by smram.g_smrame and either the smram.d_open bit is set or the system bus receives an smm-encoded request for code (not data), the transaction is steered to system memory rather than hi_a. under these conditions, both of the vgaen bits and the mdap bit are ignored.
114 datasheet system address map 4.1.2 pam memory spaces the address ranges in this space are: ? pamc0 0_000c_0000 to 0_000c_3fff ? pamc4 0_000c_4000 to 0_000c_7fff ? pamc8 0_000c_8000 to 0_000c_bfff ? pamcc 0_000c_c000 to 0_000c_ffff ? pamd0 0_000d_0000 to 0_000d_3fff ? pamd4 0_000d_4000 to 0_000d_7fff ? pamd8 0_000d_8000 to 0_000d_bfff ? pamdc 0_000d_c000 to 0_000d_ffff ? pame0 0_000e_0000 to 0_000e_3fff ? pame4 0_000e_4000 to 0_000e_7fff ? pame8 0_000e_8000 to 0_000e_bfff ? pamec 0_000e_c000 to 0_000e_ffff ? pamf0 0_000f_0000 to 0_000f_ffff the 256 kb pam region is divided into three parts: ? isa expansion region: 128 kb area between 0_000c_0000h and 0_000d_ffffh ? extended bios region: 64 kb area between 0_000e_0000h and 0_000e_ffffh, ? system bios region: 64 kb area between 0_000f_0000h and 0_000f_ffffh. the isa expansion region is divided into eight, 16-kb segments. each segment can be assigned one of four read/write states: read-only, write-only, read/write, or disabled. typically, these blocks are mapped through the mch and are subtractively decoded to isa space. the extended system bios region is divided into four, 16-kb segments. each segment can be assigned independent read and write attributes so it can be mapped either to main memory or to hub interface_a. typically, this area is used for ram or rom. the system bios region is a single, 64-kb segment. this segment can be assigned read and write attributes. it is by default (after reset) read/write disabled and cycles are forwarded to hub interface_a. by manipulating the read/write attributes, the mch can shadow bios into the main memory. note that the pam region can be accessed by hub interface_a?d. all reads or writes from any hub interface that hits the pam area is sent to main memory. if the system is setup so that there are hub interface accesses to the pam regions, then the pam region being accessed must be programmed to be both readable and writable by the processor. if the accessed pam region is programmed for either reads or writes to be forwarded to hub interface_a, and there are hub interface accesses to that pam, the system may fault.
datasheet 115 system address map 4.1.3 isa hole memory space bios software may optionally open a ?window? between 15 mb and 16 mb (0_00f0_0000 to 0_00ff_ffff) that relays transactions to hub interface_a instead of completing them with a system memory access. this window is opened with the fdhc.hen configuration field. 4.1.4 i/o apic memory space the i/o apic spaces are used to communicate with i/o apic interrupt controllers that may be populated on hub interface_a through hub interface_d. since it is difficult to relocate an interrupt controller using plug-and-play software, fixed address decode regions have been allocated for them. the address ranges are: ? i/oapic0 (hi_a) 0_fec0_0000h to 0_fec7_ffffh ? i/oapic1 (hi_b) 0_fec8_0000h to 0_fec8_0fffh ? i/oapic2 (hi_c) 0_fec8_1000h to 0_fec8_1fffh ? i/oapic3 (hi_d) 0_fec8_2000h to 0_fec8_2fffh processor accesses to the i/oapic0 region are always sent to hub interface_a. processor accesses to the i/oapic1 region are always sent to hub interface_b and so on. 4.1.5 system bus interrupt memory space the system bus interrupt space (0_fee0_0000h to 0_feef_ffffh) is the address used to deliver interrupts to the system bus. any device on hub interface_a?d may issue a double-word memory write to 0feex_xxxxh. the mch will forward this memory write along with the data to the system bus as an interrupt message transaction. the mch terminates the system bus transaction by providing the response and asserting trdy#. this memory write cycle does not go to dram. the processors may also use this region to send inter-processor interrupts (ipi) from one processor to another. 4.1.6 device 2 memory and prefetchable memory plug-and-play software configures the hi_b memory window to provide enough memory space for the devices behind this pci-to-pci bridge. accesses that have addresses that fall within this window are decoded and forwarded to hub interface_b for completion. the address ranges are: ? m2 mbase2 to mlimit2 ? pm2 pmbase2 to pmlimit2 note that these registers must be programmed with values that place the hub interface_b memory space window between the value in the tolm register and 4 gb. in addition, neither region should overlap with any other fixed or relocatable area of memory.
116 datasheet system address map 4.1.7 device 3 memory and prefetchable memory plug-and-play software configures the hub interface_c memory window to provide enough memory space for the devices behind this pci-to-pci bridge. accesses that have addresses that fall within this window are decoded and forwarded to hub interface_c for completion. ? m3 mbase3 to mlimit3 ? pm3 pmbase3 to pmlimit3 note that these registers must be programmed with values that place the hub interface_c memory space window between the value in the tolm register and 4 gb. in addition, neither region should overlap with any other fixed or relocatable area of memory. 4.1.8 device 4 memory and prefetchable memory plug-and-play software configures the hub interface_d memory window to provide enough memory space for the devices behind this pci-to-pci bridge. accesses that have addresses that fall within this window are decoded and forwarded to hub interface_d for completion. ? m4 mbase4 to mlimit4 ? pm4 pmbase4 to pmlimit4 note that these registers must be programmed with values that place the hub interface_d memory space window between the value in the tolm register and 4 gb. in addition, neither region should overlap with any other fixed or relocatable area of memory. 4.1.9 hi_a subtractive decode all accesses that fall between the value programmed into the tolm register and 4 gb (i.e., tolm and 4 gb) are subtractively decoded and forwarded to hub interface_a if they do not decode to a space that corresponds to another device. 4.1.10 main memory addresses the high memory and extended memory address regions are together called main memory. main memory is composed of address segments that refer to sdram system memory. main memory addresses are mapped to sdram channels, devices, banks, rows, and columns in different ways depending upon the type of memory being used and the density or organization of the memory. refer to section 1.4.2 for supported dimm configurations.
datasheet 117 system address map 4.2 i/o address space the mch does not support the existence of any other i/o devices on the system bus. the mch generates hub interface_a?d bus cycles for all processor i/o accesses. the mch contains two internal registers in the processor i/o space, configuration address register (conf_addr) and the configuration data register (conf_data). these locations are used to implement the configuration space access mechanism and are described in device configuration registers section. the processor allows 64 kb + 3 bytes to be addressed within the i/o space. the mch propagates the processor i/o address without any translation to the targeted destination bus. note that the upper three locations can be accessed only during i/o address wrap-around when signal a16# is asserted on the system bus. a16# is asserted on the system bus whenever a dword i/o access is made from address 0fffdh, 0fffeh, or 0ffffh. in addition, a16# is asserted when software attempts a two bytes i/o access from address 0ffffh. the i/o accesses (other than ones used for configuration space access) are forwarded normally to hub interface_a?d. all i/o cycles receive a defer response. the mch never posts an i/o write. the mch never responds to i/o or configuration cycles initiated on any of the hub interfaces. hub interface transactions requiring completion are terminated with ?master abort? completion packets on the hub interfaces. hub interface i/o write transactions not requiring completion are dropped. 4.3 smm space 4.3.1 system management mode (smm) memory range the e7500 chipset supports the use of main memory as system management ram (smm ram), which enables the use of system management mode. the mch supports three smm options: ? compatible smram (c_smram) ? high segment (hseg) ? top of memory segment (tseg). system management ram space provides a memory area that is available for the smi handlers and code and data storage. this memory resource is normally hidden from the system operating system so the processor has immediate access to this memory space upon entry to smm. the mch provides three smram options: ? below 1-mb option that supports compatible smi handlers. ? above 1-mb option that allows new smi handlers to execute with write-back cacheable smram. ? optional larger write-back cacheable tseg area from 128 kb to 1 mb in size above 1 mb that is reserved below the 4 gb in system dram memory space. the above 1-mb solutions require changes to compatible smram handler code to properly execute above 1 mb.
118 datasheet system address map 4.3.2 tseg smm memory space the tseg smm space (tolm ? tseg to tolm) allows system management software to partition a region of main memory just below the top of low memory (tolm) that is accessible only by system management software. this region may be 128 kb, 256 kb, 512 kb, or 1 mb in size, depending upon the esmramc.tseg_sz field. this space must be below 4 gb, so it is below tolm and not the top of physical memory, smm memory is globally enabled by smram.g_smrame. requests may access smm system memory when either smm space is open (smram.d_open) or the mch receives an smm code request on its system bus. to access the tseg smm space, tseg must be enabled by esmramc.t_en. when all of these conditions are met, a system bus access to the tseg space (between tolm?tseg and tolm) is sent to system memory. when the high smram is not enabled or if the tseg is not enabled, memory requests from all interfaces are forwarded to system memory. when the tseg smm space is enabled, and an agent attempts a non-smm access to tseg space, then the transaction is specially terminated. hub interface originated accesses are not allowed to smm space. 4.3.3 high smm memory space the highsmm space (0_feda_0000h to 0_fedb_ffffh) allows cacheable access to the compatible smm space by remapping valid smm accesses between 0_feda_0000h and 0_fedb_ffffh to accesses between 0_000a_0000h and 0_000b_ffffh. the accesses are remapped when smram space is enabled; an appropriate access is detected on the system bus, and when esmramc.h_smrame allows access to high smram space. smm memory accesses from any hub interface are specially terminated: reads are provided with the value from address 0 while writes are ignored entirely. 4.3.4 smm space restrictions when any of the following conditions are violated, the results of smm accesses are unpredictable and may cause undesirable system behavior: 1. the compatible smm space must not be setup as cacheable. 2. both d_open and d_close must not be set to 1 at the same time. 3. when tseg smm space is enabled, the tseg space must not be reported to the operating system as available dram. this is a bios responsibility.
datasheet 119 system address map 4.3.5 smm space definition smm space is defined by its addressed smm space and its dram smm space. the addressed smm space is defined as the range of bus addresses used by the processor to access smm space. dram smm space is defined as the range of physical dram memory locations containing the smm code. smm space can be accessed at one of three transaction address ranges: compatible, high, and tseg. the compatible and tseg smm space is not remapped and, therefore, the addressed and dram smm space is the same address range. since the high smm space is remapped, the addressed and dram smm space is a different address range. note that the high dram space is the same as the compatible transaction address space. table 4-1 describes three unique address ranges: ? compatible transaction address ? high transaction address ? tseg transaction address table 4-1. smm address range notes: 1. high smm: this is different than in previous chipsets. in previous chipsets the high segment was the 384 kb region from a_0000h to f_ffffh. however, c_0000h to f_ffffh was not practically useful so it is deleted in the mch. 2. tseg smm: this is different than in previous chipsets. in previous chipsets the tseg address space was offset by 256 mb to allow for simpler decoding and the tseg was remapped to just under the tolm. in the mch the tseg region is not offset by 256 mb and it is not remapped. smm space enabled transaction address space dram space compatible a0000h to bffffh a0000h to bffffh high 0feda0000h to 0fedbffffh a0000h to bffffh tseg (tolm?tseg_sz) to tolm (tolm?tseg_sz) to tolm
120 datasheet system address map 4.4 memory reclaim background the following memory-mapped i/o devices are typically located below 4 gb: ? high bios ? hseg ? xapic ? local apic ? system bus interrupts ? hi_b, hi_c, hi_d bars in previous generation mchs, the physical main memory overlapped by the logical address space allocated to these memory-mapped i/o devices was unusable. in server systems the memory allocated to memory-mapped i/o devices could easily exceed 1 gb. the result is that a large amount of physical memory would not be usable. the mch provides the capability to re-claim the physical memory overlapped by the memory mapped i/o logical address space. the mch re-maps physical memory from the top of low memory (tolm) boundary up to the 4 gb boundary (or drb7 if less than 4 gb) to an equivalent sized logical address range located just above the top of physical memory 4.4.1 memory re-mapping an incoming address (referred to as a logical address) is checked to see if it falls in the memory re- map window. the bottom of the re-map window is defined by the value in the remapbase register. the top of the re-map window is defined by the value in the remaplimit register. an address that falls within this window is remapped to the physical memory starting at the address defined by the tolm register.
datasheet 121 reliability, availability, serviceability, usability, and manageability (rasum) reliability, availability, serviceability, usability, and manageability (rasum) 5 the e7500 chipset-based platforms provide the rasum (reliability, availability, serviceability, usability, and manageability) features required for entry-level and mid-range servers. these features include: chipkill technology ecc for memory, ecc for all high-performance i/o, out-of- band manageability through smbus target interfaces on all major components, memory scrubbing and auto-initialization, processor thermal monitoring, and hot-plug pci. 5.1 dram ecc the ecc used for dram provides chipkill technology protection for x4 sdrams. drams that are x8 use the same algorithm but will not have chipkill technology protection, since at most only four bits can be corrected with this ecc. 5.2 dram scrubbing a special dram scrub algorithm will walk through all of main memory doing reads followed by writes back to the same location. correctable errors found by the read are corrected and then the good data is written back to dram. a write is done in all cases, whether there were errors or not. this looks like a read-modify-write of 0 bytes to the system. the scrub unit starts at address 0 upon reset. periodically, the unit will scrub one line and then increment the address counter by 64 bytes or one line. a 16-gb memory array would be completely scrubbed in approximately one day. 5.3 dram auto-initialization the dram auto-initialization algorithms initialize memory at reset to ensure that all lines have valid ecc. 5.4 smbus access the processor will be able to access all configuration registers through host configuration cycles. access via smbus will be r/w to a shadowed set of the rasum registers in the mch, and read- only to all non-rasum registers in the mch. the smbus can not use the mch?s sm-port to access any registers outside the mch. the p64h2 and ich3-s each have their own smbus target port. a test mode will be provided to allow the processor to access the shadowed register set. shadowing the rasum registers ensures that bios code and system management asic firmware code can execute independently, without interference or synchronization efforts. pci legacy registers associated with error reporting will not deviate from prior implementations. smbus will have read-only access to the pci legacy registers.
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datasheet 123 electrical characteristics electrical characteristics 6 this chapter provides the absolute maximum ratings, thermal characteristics, and dc characteristics for the mch. 6.1 absolute maximum ratings warning: stressing the device beyond the ?absolute maximum ratings? may cause permanent damage. these are stress ratings only. operating beyond the ?operating conditions? is not recommended and extended exposure beyond ?operating conditions? may affect reliability. 6.2 thermal characteristics the mch is designed for operation at die temperatures between 0 c and 110 c. the thermal resistance of the package is given in table 6-2 . notes: 1. typical value measured in accordance with eia/jesd 51-2 testing standard. 2. 1 meter/second is equivalent to 196.9 linear feet/minute table 6-1. absolute maximum ratings symbol parameter min max unit notes t storage storage temperature -55 150 c vcc_mch 1.2 v supply voltage with respect to vss -0.38 2.1 v vtt_agtl supply voltage input with respect to vss -0.38 2.1 v vdd_ddr ddr buffer supply voltage 2 3 v table 6-2. mch package thermal resistance parameter air flow no air flow (0 meter/second) 1.0 meter/second 2 psi jt ( c/watt) 1 0.5 1.0 theta ja ( c/watt) 1 13.0 11.2
124 datasheet electrical characteristics 6.3 power characteristics notes: 1. tdp typ is the thermal design power (11.6 w) and it is the estimated maximum possible expected power generated in a component by a realistic application. it is based on extrapolations in both hardware and software technology over the life of the component. it does not represent the expected power generated by a power virus. studies by intel indicate that no useful application will cause thermally significant power dissipation exceeding the tdp typ specification, although it is possible to concoct higher power synthetic workloads as reflected in the tdp max specification. table 6-3. thermal power dissipation (vcc1_2 = 1.2 v 5%) symbol parameter min typ max unit notes p mch thermal power dissipation for mch 11.6 15.6 w 1 table 6-4. dc characteristics functional operating range (vcc1_2 = 1.2 v 5%) symbol parameter min typ max unit notes i cc 1.2 v plumas core and hi 3.1 a i vtt 1.55 v agtl 2.0 a i dd_ddr 2.5 v vdd ddr (2 channel) 7 a
datasheet 125 electrical characteristics 6.4 i/o interface signal groupings the signal description includes the type of buffer used for the particular signal: ? agtl+ open drain agtl+ interface signal. refer to the agtl+ i/o specification for complete details. the mch integrates agtl+ termination resistors. ? cmos 1.2 v cmos buffers. ? ddr ddr sdram signaling interface notes: 1. x = a, b ddr channel table 6-5. signal groups system bus interface signal group signal type signals notes (a) agtl+ i/o ap[1:0]#, ads#, bnr#, dbsy#, dp[3:0]#, drdy#, ha[35:3]#, hadstb[1:0] #, hd[63:0] #, hdstbp[3:0]#, hdstbn[3:0]#, hit#, hitm#, hreq[4:0]#, breq0#, dbi[3;0]# (b) agtl+ output bpri#, cpurst#, defer#, htrdy#, rs [2:0]#, rsp# (c) agtl+ input hlock#, xerr# (d) host reference voltage hdvref[3:0], havref[1:0], hccvref (e) host voltage swing hxswing, hyswing (f) host compensation hxrcomp, hyrcomp (g) clk inputs hclkinn, hclkinp (h) agtl + termination voltage vtt table 6-6. signal groups ddr interface signal group signal type signals notes (i) ddr i/o dq_x [63:0], cb_x [7:0], dqs_x [17:0] 1 (j) ddr output cmdclk_x [3:0], cmdclk_x#[3:0], ma_x [12:0], ba_x [1:0], ras_x#, cas_x#, we_x#, cs_x [7:0]#, cke_x, rcvenout_x# 1 (k) ddr input rcvenin_x# 1 (l) ddr compensation cmos i/o ddrcomp_x 1 (m) ddr compensation for impedance control ddrcvoh_x, ddrcvol_x 1 (n) ddr reference voltage ddrvref_x [5:0] 1
126 datasheet electrical characteristics notes: 1. x = b, c, d (referencing hub interface_b?d). 2. clk66 is shared on hi 1.5 and hi 2.0 notes: 1. clk66 is shared on hi 1.5 and hi 2.0 table 6-7. signal groups hub interface 2.0 (hi_b?d) signal group signal type signals notes (o) hub interface cmos i/o hi_x [21:0], pstrbf_x, pstrbs_x 1 (p) hub interface cmos input clock clk66 2 (q) hub interface reference voltage input hivref_x 1 (r) hub interface voltage swing hiswng_x 1 (s) hub interface compensation cmos i/o hircomp_x 1 table 6-8. signal groups hub interface 1.5 (hi_a) signal group signal type signals notes (t) hub interface cmos i/o hi_a [11:0], hi_stbf, hi_stbs (u) hub interface cmos input clock clk66 1 (v) hub interface reference voltage input hivref_a (w) hub interface voltage swing hiswng_a (x) hub interface compensation cmos i/o hircomp_a table 6-9. signal groups smbus signal group signal type signals notes (y) smbus i/o buffer smb_clk, smb_data table 6-10. signal groups reset and miscellaneous signal group signal type signals notes (z) miscellaneous cmos input rstin#, pwrgood, xormode#
datasheet 127 electrical characteristics 6.5 dc characteristics table 6-11. operating condition supply voltage (vcc1_2 = 1.2 v 5%) symbol signal group parameter min nom max unit notes vtt (h) host agtl+ termination voltage 1.15 1.3 1.45 v vdd_ddr ddr buffer voltage 2.3 2.5 2.7 v vcc_mch 1.2 v supply voltage 1.14 1.2 1.26 v table 6-12. system bus interface (vcc1_2 = 1.2 v 5%) symbol signal group parameter min nom max unit notes v il_h (a), (c) host agtl+ input low voltage (2/3 x vtt) ? 0.1gtlref v v ih_h (a), (c) host agtl+ input high voltage (2/3 x vtt) + 0.1gtlref v v ol_h (a), (b) host agtl+ output low voltage 1/3 x vtt (1/3 x vtt) + 0.1gtlref v v oh_h (a), (b) host agtl+ output high voltage vtt?0.1 vtt v rtt host termination resistance 46 50 54 w i ol_h (a), (b) host agtl+ output low leakage (2/3 x vttmax) / rtt min a i l_h (a), (c) host agtl+ input leakage current 10 a c pad (a), (c) host agtl+ input capacitance 1 3.5 pf ccvref (d) host common clock reference voltage 2/3 x vtt v hxvref (d) host address and data reference voltage 2/3 x vtt v hxswng, hyswng (e) host compensation reference voltage 1/3 x vtt v
128 datasheet electrical characteristics table 6-13. ddr interface (vcc1_2 = 1.2 v 5%) symbol signal group parameter min nom max unit notes v il (dc) (i), (k) ddr input low voltage ddrvref ? 0.150 v v ih (dc) (i), (k) ddr input high voltage ddrvref + 0.150 v v il (ac) (i), (k) ddr input low voltage ddrvref ?0.310 v ih (ac) (i), (k) ddr input high voltage ddrvref +0.310 v ol (i), (j) ddr output low voltage 0 0.7 v v oh (i), (j) ddr output high voltage 1.7 vdd_ddr v c out (i), (k) ddr input pin capacitance 2.5 5 pf i ol (dc) (i), (j) ddr output low current -50 ma i oh (i), (j) ddr output high current 50 ma i ol (ac) (i), (j) ddr output low current 50 ma i oh (ac) (i), (j) ddr output high current 50 ma i leak (i), (k) input leakage current 50 a c in (i), (k) input pin capacitance 2.5 5 pf ddrvref (n) ddr reference voltage vdd_ddr/2 v
datasheet 129 electrical characteristics notes: 1. v ol is measured at iout = 1.0 ma 2. there are two v oh specifications. v oht applies when the pin is in receive (terminating) mode and tests the strength of the terminator / pull-down device. v oht is measured with the specified pull-up resistor tied to v ddhi . v ohd applies when the pin is driving a high level and tests the strength of the pull-up device. v ohd is measured into a standard resistive load to ground representing the target impedance of the receiver terminator (z targ ). the output driver is also responsible for not driving the receiver higher than the maximum vih. this represents the absolute maximum allowed voltage allowed on the receiver pin (i.e., v oh due to incomplete impedance updates on the drivers and terminator). this specification allows inter-operation between devices over many process generations. a given platform where the devices have higher voltage tolerances may specify a higher v ih (max). table 6-14. hub interface 2.0 configured for 50 ? (vcc1_2 = 1.2 v 5%) symbol signal group parameter min nom max unit notes v il_hi (o) hub interface input low voltage 0 hivref?0.1 v v ih_hi (o) hub interface input high voltage hivref +0.1 0.7 ? v v ol_hi (o) hub interface output low voltage -0.03 0 0.05 v 1 v oht_hi (o) hub interface terminator high voltage hiswng ?0.50 hiswng +0.50 v2 v ohd_hi (o) hub interface output high voltage hiswng ?0.50 hiswng +0.50 v2 i il_hi (o) hub interface input leakage current 25 a c in_hi (o) hub interface input pin capacitance 3.5 pf ? c in strobe to data pin capacitance delta -0.50 0.50 pf l pin pin inductance (signal) 5 nh z pd pull-down impedance 45 50 55 ? z pu pull-up impedance 22.5 25 27.5 ? v ccp i/o supply voltage 1.2 v c clk (p) clk66 pin capacitance 0.025 v hivref_x (q) hub interface reference voltage 0.343 0.35 0.357 v hiswng_x (r) hub interface swing reference voltage 0.8 v hircomp_x (s) hub interface compensation resistance 24.75 25 25.25 ?
130 datasheet electrical characteristics notes: 1. v ol is measured at i out = 1.0 ma 2. there are two v oh specifications. v oht applies when the pin is in receive (terminating) mode and tests the strength of the terminator / pull-down device. v oht is measured with the specified pull-up resistor tied to v ddhi . v ohd applies when the pin is driving a high level and tests the strength of the pull-up device. v ohd is measured into a standard resistive load to ground representing the target impedance of the receiver terminator (z targ ). the output driver is also responsible for not driving the receiver higher than the maximum vih. this represents the absolute maximum allowed voltage allowed on the receiver pin (i.e., v oh due to incomplete impedance updates on the drivers and terminator). this specification allows inter-operation between devices over many process generations. a given platform where the devices have higher voltage tolerances may specify a higher v ih (max). 3. for hub interface 1.5, a hiswng of 0.8 v is recommended, but a value of 0.7 v is allowed as long as system validation is performed. table 6-15. hub interface 1.5 with parallel buffer mode configured for 50 ? (vcc1_2 = 1.2 v 5%) symbol signal group parameter min nom max unit notes v il_hi (t) hub interface input low voltage 0 hivref?0.1 v v ih_hi (t) hub interface input high voltage hivref+0.1 0.7 ? v v ol_hi (t) hub interface output low voltage -0.03 0 0.05 v 1 v oht_hi (t) hub interface terminator voltage hiswng?0.50 hiswng+0.50 v 2 v ohd_hi (t) hub interface output high voltage hiswng?0.50 hiswng+0.50 v 2 i il_hi (t) hub interface input leakage current 25 a c in_hi (t) hub interface input pin capacitance 3.5 pf ? c in strobe to data pin capacitance delta -0.50 0.50 pf l pin pin inductance (signal) 5 nh z pd pull-down impedance 45 50 55 ? z pu pull-up impedance 22.5 25 27.5 ? v ccp i/o supply voltage 1.2 v c clk (u) clk66 pin capacitance 0.025 v hivref_a (v) hub interface reference voltage 0.343 0.35 0.357 v hiswng_a (w) hub interface swing reference voltage 0.8 v 3 hircomp_a (x) hub interface compensation resistance 24.75 25 25.25 ?
datasheet 131 ballout and package specifications ballout and package specifications 7 this chapter provides the ballout and package dimensions for the e7500 mch. in addition, internal component package trace lengths to enable trace length compensation are listed. 7.1 ballout figure 7-1 shows a top view of the ballout footprint. figure 7-2 and figure 7-3 expand the detail of the ballout footprint to list the signal names for each ball. table 7-1 lists the mch ballout with the listing organized alphabetically by signal name. figure 7-1. intel ? e7500 mch ballout (top view) an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e e c b a 10 16 20 3 5 7 9 11 13 15 17 19 4 6 18 8 12 14 22 21 24 23 26 25 28 27 30 29 31 2 32 33 1
ballout and package specifications 132 datasheet figure 7-2. intel ? e7500 mch ballout (left half of top view) 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 an vss vcc2_5 dq4_a dq1_a vss vcc2_5 dq8_a ras_a# vss vcc2_5 dq30_a dq20_a vss vcc2_5 dq18_a am vcc2_5 ma12_a ma9_a vss dq5_a dqs0_a vss dq12_a dq9_a vss rcvenin _a# dq26_a vss dq21_a reserved vss al vss dq60_b ba0_a vss ma7_a ma6_a vss dq6_a dq7_a vcc2_5 dqs1_a dq14_a vss dq27_a dq17_a vss dq22_a ak vcc2_5 cs1_b# vss ma11_a ma8_a vss ddrvref 4_a ma1_a vss dq13_a dqs10_a vss ddrv ref3_a dqs12_a dq16_a dqs11_a ddrc voh_a aj vss vss dq61_b dq56_b vcc2_5 ddrvref 5_a ma3_a vcc2_5 cmdclk1 _a ma10_a vcc2_5 dq15_a dq29_a vcc2_5 dq31_a dq23_a vcc2_5 ah dq55_b dq50_b dq51_b vss cs0_b# ma5_a vss ma2_a cmdclk1 _a# vss ba1_a dq3_a vss dq28_a dq25_a vss ddrcom p_a ag dq38_b ddrv ref1_b vss dq54_b dq57_b vcc2_5 ma4_a cmdclk2 _a vss cmdclk0 _a cmdclk0 _a# vcc2_5 dq10_a rcven out_a# vcc2_5 dqs2_a cb5_a af vcc2_5 vss dq34_b cs2_b# vss dqs16_b cs3_b# vss cmdclk2 _a# ma0_a vcc2_5 dq0_a dqs9_a vss dq24_a dq19_a vss ae dq33_b dqs4_b cs4_b# vcc2_5 vss dqs6_b dqs7_b cs5_b# cmdclk3 _a cmdclk3 _a# we_a# cas_a# dq2_a dq11_a cke_a dqs3_a cb4_a ad vcc2_5 dq37_b dq43_b vss vcc2_5 cs6_b# dqs15_b vss vcc2_5 vcc2_5 vss vcc2_5 vss vcc2_5 vss vcc2_5 vss ac vss vss dqs5_b dqs13_b vss dq52_b dq62_b vss ddr vref0_b vss vcc2_5 vss vcc2_5 vss vcc2_5 vss vcc2_5 ab dq41_b dq45_b vcc2_5 dqs14_b dq46_b vss dq49_b dq63_ b dq58_b vcc2_5 vss aa cb3_b cb7_b cb6_b vss dq40_b dq36_b vcc2_5 dq53_b dq59_b vss vcc2_5 y vcc2_5 vss cb2_b dqs17_b vcc2_5 dq44_b cs7_b# vss dq48_b vcc2_5 vss vcca1_2 vss vcca1_2 vss w vss ddr cvoh_b vss ddr comp_b dqs8_b vss dq32_b dq39_b dq35_b vss vcc2_5 vss vcc1_2 vss vcc1_2 v dq22_b ras_b# dq23_b vss ddrc vol_b cb0_b vss dq42_b dq47_b vcc2_5 vss vcca1_2 vss vcc1_2 vss u dqs2_b vss dqs11_b dq18_b vcc2_5 cb4_b cb5_b ddr vref2_b cb1_b vss vcc2_5 vss vcc1_2 vss vcc1_2 t vcc2_5 dq27_b vcc2_5 dq17_b dq16_b vss dq21_b dq19_b dq31_b vcc2_5 vss vcca1_2 vss vcc1_2 vss r vss dq20_b dqs12_b vss dqs3_b dq30_b vss dq26_b rcven out_b# vss vcc2_5 vss vcc1_2 vss vcc1_2 p dq25_b vss dq29_b dq24_b vcc2_5 dq15_b dq10_b dq14_b dq11_b vcc2_5 vss vcca1_2 vss vcc1_2 vss n ddr vref3_b dq28_b vss rcvenin _b# dqs10_b vss dq4_b dq7_b dq3_b vss vcc2_5 m vcc2_5 cke_b dqs1_b vss dq6_b cmdclk1 _b# vss ma0_b ddr vref4_b vcc2_5 vss l vss vss dq13_b dqs0_b vcc2_5 cmdclk1 _b cmdclk3 _b# vcc2_5 ma10_b vss vcc2_5 vcc1_2 vss vcc1_2 vss vcc1_2 vss k reserved dq9_b vcc2_5 dq1_b ma1_b vss cmdclk3 _b ba0_b cmdclk2 _b# vcc2_5 vcc1_2 vss vcc1_2 vss vcc1_2 vss vcc1_2 j dq8_b dq2_b dq12_b vss cmdclk0 _b cmdclk0 _b# vss cmdclk2 _b smb_clk vss vss hi vref_d vss vss vss vss vss h vcc2_5 vss dqs9_b ma2_b vcc2_5 cas_b# ba1_b vss hi17_d hi6_d hi16_d vss hi21_d vcc1_2 vcc1_2 hi20_c hiswng _c g vss dq5_b vss ma3_b ma5_b vss vcc2_5 hi2_d hi1_d hi4_d vss hi8_d hircomp _d vss vss hi2_c vss f dq0_b ma4_b ma6_b vss ma9_b vss vss hi3_d hi18_d hiswng _d hi14_d hi15_d vss hi18_c hi5_c vss hi15_c e ma7_b vss ma8_b ddr vref5_b vcc2_5 rstin# hi20_d vcc1_2 vss hi9_d hi13_d vcc1_2 hi7_c hi4_c vcc1_2 hi14_c pustrbs _c d vcc2_5 we_b# vss vss reserved hi0_d pstrbf _d pstrbs _d vss hi11_d vss hi0_c hi6_c vss hi8_c pustrbf _c vss c vss ma12_b ma11_b vss xor mode# vss vss hi7_d pustrbs _d hi17_c pstrbf _c hi3_c vss hircomp _c hi11_c hi13_c hi2_b b vcc2_5 smb _data reserved vss vcc1_2 vss vss pustrbf _d hi1_c pstrbs _c vss hi16_c hi10_c vss hi12_c hi17_b a vss vcc1_2 vss pwr good hi5_d vcc1_2 hi10_d hi12_d vss vcc1_2 hivref _c hi9_c vss vcc1_2 hi4_b 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
datasheet 133 ballout and package specifications figure 7-3. intel ? e7500 mch ballout (right half of top view) 16151413121110987654321 ddrcvol _a vss vcc2_5 dq37_a dq42_a vss vcc2_5 vss cs4_a# vcc2_5 vss dq51_a vcc2_5 vss an ddr vref2_a cb6_a vss dq33_a dqs5_a vss dq47_a dq54_a vss dqs15_a dq55_a vss dq63_a dq58_a dq59_a am cb2_a vcc2_5 dq32_a dqs4_a vss dq43_a cs2_a# ddr vref1_a dqs6_a vss dqs7_a dq62_a vss cs6_a# cs7_a# vcc2_5 al vss cb3_a dq36_a vss dqs14_a cs1_a# vcc2_5 vss vcc2_5 cs5_a# vss ap1# rsp# vss xerr# vss ak dqs8_a dq34_a vcc2_5 dqs13_a dq46_a vcc2_5 vss dq57_a vss ddr vref0_a ap0# vcc_cpu ha27# havref1 vss ha34# aj cb1_a vss dq38_a dq41_a vss dq49_a dq60_a dqs16_a cs3_a# vss ha33# ha31# vss ha21# ha20# vcc_cpu ah vss cb7_a dq39_a vcc2_5 dq52_a dq50_a dq56_a vss binit# ha32# vss ha35# ha26# vcc_cpu ha22# vss ag dqs17_a dq35_a vss dq45_a dq53_a vss vss breq0# vss ha30# ha23# vcc_cpu havref0 ha29# vss ha25# af cb0_a dq44_a dq40_a cs0_a# dq48_a dq61_a vcc2_5 vss ha28# vcc_cpu ha14# ha10# vss ha15# ha11# hadstb0# ae vcc2_5 vss vcc2_5 vss vcc2_5 vss vss vss ha24# hadstb1# vss ha16# ha9# vss ha6# vcc_cpu ad vss vcc2_5 vss vcc2_5 vss vss vcc_cpu ha19# vss ha18# ha12# vcc_cpu ha8# ha5# vss vss ac vcc_cpu vss ha13# ha17# vss ha7# vss vss hreq3# hreq0# ha4# ab vss vcc_cpu vss ha3# hreq2# vss dp2# dp3# vss dp1# hreq1# aa vcca1_2 vss vcca1_2 vcc_cpu vss hreq4# vss ads# hccvref vcc_cpu dp0# drdy# vss vcc_cpu y vss vcc1_2 vss vss vcc_cpu cpurst# defer# vcc_cpu dbsy# hitm# vss htrdy# vss vss w vcc1_2 vss vcc1_2 vcc_cpu vss vss hxswing hlock# vss rs1# hxrcomp vss rs0# bnr# v vss vcca cpu1_2 vss vss vcc_cpu vss vss hd59# bpri# vcc_cpu rs2# hclkinn vss hit# u vcc1_2 vss vcc1_2 vcc_cpu vss hd60# hd63# hdvref3 hd57# hd61# vss hd58# hclkinp vcc_cpu t vss vcc1_2 vss vss vcc_cpu vss hd47# hd46# vss hd62# hdstbn3# vcc_cpu hd56# vss r vccahi1 _2 vss vcc1_2 vcc_cpu vss hd42# vss hd44# hdvref2 vcc_cpu hd50# hdstbp3# vss dbi3# p vss vcc_cpu vss hdvref1 hd45# hd40# vss hd49# hd54# hd53# hd55# n vcc_cpu vss vss hd24# hd31# vss vss hd43# vss hd51# vcc_cpu m vcc1_2 vss vcc1_2 vss vcc1_2 vss vcc_cpu vss vss hd17# hd18# vcc_cpu dbi2# hd48# hd52# vss l vss vcc1_2 vss vcc1_2 vss vcc1_2 vss vcc_cpu vss vcc_cpu hdstbn1# hyswing vss hd35# hd38# hd39# k clk66 vss hi15_b hi8_a vss hi6_a hi9_a vss hd14# hd15# vss hd41# hdstbp2# vss hdstbn2# hd37# j vss pstrbs_b hi16_b vss hiswng _a hircomp _a vss hi7_a vss hd12# hdstbp1# vcc_cpu hd32# hd33# vss vcc_cpu h hi1_b pstrbf_b vss hi21_b hi11_a vss hi2_a hivref_a vss vss hd20# hyrcomp vss hd36# hd34# vss g hi21_c vss hi20_b hi9_b vss hi10_a hi3_a vss dbi0# hd16# vss hd22# hd26# vcc_cpu hd28# hd30# f vcc1_2 hircomp _b hi18_b vcc1_2 hi13_b hi0_a vcc1_2 hi5_a hd4# vcc_cpu hd19# vss hd23# hd29# vss hd25# e hi0_b hi7_b vss hivref_b hi12_b vss hi_stbs hi4_a vss hd11# hd21# vcc_cpu vss hd27# dbi1# vcc_cpu d hi3_b vss hi8_b hi11_b vss hi14_b hi_stbf vss hd7# hd10# vss hdvref0 hd9# vcc_cpu hd13# vss c vss hiswng _b hi6_b vss pustrbs _b hi1_a vss hd0# hdstbp0# vss hdstbn0# hd3# vss hd5# vss b hi5_b vss vcc1_2 hi10_b pustrbf _b vss vcc1_2 hd1# hd8# vss vcc_cpu hd6# hd2# vss a 16151413121110987654321
ballout and package specifications 134 datasheet table 7-1. mch signal list signal name ball # ads# y7 ap0# aj6 ap1# ak5 ba0_a al31 ba0_b k26 ba1_a ah23 ba1_b h27 binit# ag8 bnr# v1 bpri# u6 breq0# af9 cas_a# ae22 cas_b# h28 cb0_a ae16 cb0_b v28 cb1_a ah16 cb1_b u25 cb2_a al16 cb2_b y31 cb3_a ak15 cb3_b aa33 cb4_a ae17 cb4_b u28 cb5_a ag17 cb5_b u27 cb6_a am15 cb6_b aa31 cb7_a ag15 cb7_b aa32 cke_a ae19 cke_b m32 clk66 j16 cmdclk0_a ag24 cmdclk0_a# ag23 cmdclk0_b j29 cmdclk0_b# j28 cmdclk1_a aj25 cmdclk1_a# ah25 cmdclk1_b l28 cmdclk1_b# m28 cmdclk2_a ag26 cmdclk2_a# af25 cmdclk2_b j26 cmdclk2_b# k25 cmdclk3_a ae25 cmdclk3_a# ae24 cmdclk3_b k27 cmdclk3_b# l27 cpurst# w9 cs0_a# ae13 cs0_b# ah29 cs1_a# ak11 cs1_b# ak32 cs2_a# al10 cs2_b# af30 cs3_a# ah8 cs3_b# af27 cs4_a# an8 cs4_b# ae31 cs5_a# ak7 cs5_b# ae26 cs6_a# al3 cs6_b# ad28 cs7_a# al2 cs7_b# y27 dbi0# f8 dbi1# d2 dbi2# l4 dbi3# p1 dbsy# w6 ddrcomp_a ah17 ddrcomp_b w30 ddrcvoh_a ak17 ddrcvoh_b w32 ddrcvol_a an16 ddrcvol_b v29 ddrvref0_a aj7 ddrvref0_b ac25 ddrvref1_a al9 ddrvref1_b ag32 ddrvref2_a am16 ddrvref2_b u26 ddrvref3_a ak21 ddrvref3_b n33 ddrvref4_a ak27 ddrvref4_b m25 ddrvref5_a aj28 ddrvref5_b e30 defer# w8 dp0# y4 dp1# aa2 dp2# aa5 dp3# aa4 dq0_a af22 dq0_b f33 dq1_a an28 dq1_b k30 dq2_a ae21 dq2_b j32 dq3_a ah22 dq3_b n25 dq4_a an29 table 7-1. mch signal list signal name ball # dq4_b n27 dq5_a am28 dq5_b g32 dq6_a al26 dq6_b m29 dq7_a al25 dq7_b n26 dq8_a an25 dq8_b j33 dq9_a am24 dq9_b k32 dq10_a ag21 dq10_b p27 dq11_a ae20 dq11_b p25 dq12_a am25 dq12_b j31 dq13_a ak24 dq13_b l31 dq14_a al22 dq14_b p26 dq15_a aj22 dq15_b p28 dq16_a ak19 dq16_b t29 dq17_a al19 dq17_b t30 dq18_a an17 dq18_b u30 dq19_a af18 dq19_b t26 dq20_a an20 dq20_b r32 dq21_a am19 dq21_b t27 dq22_a al17 dq22_b v33 dq23_a aj18 dq23_b v31 dq24_a af19 dq24_b p30 dq25_a ah19 dq25_b p33 dq26_a am21 dq26_b r26 dq27_a al20 dq27_b t32 dq28_a ah20 dq28_b n32 dq29_a aj21 dq29_b p31 table 7-1. mch signal list signal name ball #
ballout and package specifications datasheet 135 dq30_a an21 dq30_b r28 dq31_a aj19 dq31_b t25 dq32_a al14 dq32_b w27 dq33_a am13 dq33_b ae33 dq34_a aj15 dq34_b af31 dq35_a af15 dq35_b w25 dq36_a ak14 dq36_b aa28 dq37_a an13 dq37_b ad32 dq38_a ah14 dq38_b ag33 dq39_a ag14 dq39_b w26 dq40_a ae14 dq40_b aa29 dq41_a ah13 dq41_b ab33 dq42_a an12 dq42_b v26 dq43_a al11 dq43_b ad31 dq44_a ae15 dq44_b y28 dq45_a af13 dq45_b ab32 dq46_a aj12 dq46_b ab29 dq47_a am10 dq47_b v25 dq48_a ae12 dq48_b y25 dq49_a ah11 dq49_b ab27 dq50_a ag11 dq50_b ah32 dq51_a an5 dq51_b ah31 dq52_a ag12 dq52_b ac28 dq53_a af12 dq53_b aa26 dq54_a am9 dq54_b ag30 dq55_a am6 table 7-1. mch signal list signal name ball # dq55_b ah33 dq56_a ag10 dq56_b aj30 dq57_a aj9 dq57_b ag29 dq58_a am3 dq58_b ab25 dq59_a am2 dq59_b aa25 dq60_a ah10 dq60_b al32 dq61_a ae11 dq61_b aj31 dq62_a al5 dq62_b ac27 dq63_a am4 dq63_b ab26 dqs0_a am27 dqs0_b l30 dqs1_a al23 dqs1_b m31 dqs2_a ag18 dqs2_b u33 dqs3_a ae18 dqs3_b r29 dqs4_a al13 dqs4_b ae32 dqs5_a am12 dqs5_b ac31 dqs6_a al8 dqs6_b ae28 dqs7_a al6 dqs7_b ae27 dqs8_a aj16 dqs8_b w29 dqs9_a af21 dqs9_b h31 dqs10_a ak23 dqs10_b n29 dqs11_a ak18 dqs11_b u31 dqs12_a ak20 dqs12_b r31 dqs13_a aj13 dqs13_b ac30 dqs14_a ak12 dqs14_b ab30 dqs15_a am7 dqs15_b ad27 dqs16_a ah9 dqs16_b af28 table 7-1. mch signal list signal name ball # dqs17_a af16 dqs17_b y30 drdy# y3 ha3# aa8 ha4# ab1 ha5# ac3 ha6# ad2 ha7# ab6 ha8# ac4 ha9# ad4 ha10# ae5 ha11# ae2 ha12# ac6 ha13# ab9 ha14# ae6 ha15# ae3 ha16# ad5 ha17# ab8 ha18# ac7 ha19# ac9 ha20# ah2 ha21# ah3 ha22# ag2 ha23# af6 ha24# ad8 ha25# af1 ha26# ag4 ha27# aj4 ha28# ae8 ha29# af3 ha30# af7 ha31# ah5 ha32# ag7 ha33# ah6 ha34# aj1 ha35# ag5 hadstb0# ae1 hadstb1# ad7 havref0 af4 havref1 aj3 hccvref y6 hclkinn u3 hclkinp t2 hd0# b9 hd1# a9 hd2# a4 hd3# b5 hd4# e8 hd5# b3 hd6# a5 hd7# c8 table 7-1. mch signal list signal name ball #
ballout and package specifications 136 datasheet hd8# a8 hd9# c4 hd10# c7 hd11# d7 hd12# h7 hd13# c2 hd14# j8 hd15# j7 hd16# f7 hd17# l7 hd18# l6 hd19# e6 hd20# g6 hd21# d6 hd22# f5 hd23# e4 hd24# m8 hd25# e1 hd26# f4 hd27# d3 hd28# f2 hd29# e3 hd30# f1 hd31# m7 hd32# h4 hd33# h3 hd34# g2 hd35# k3 hd36# g3 hd37# j1 hd38# k2 hd39# k1 hd40# n6 hd41# j5 hd42# p9 hd43# m4 hd44# p7 hd45# n7 hd46# r7 hd47# r8 hd48# l3 hd49# n4 hd50# p4 hd51# m2 hd52# l2 hd53# n2 hd54# n3 hd55# n1 hd56# r2 hd57# t6 hd58# t3 table 7-1. mch signal list signal name ball # hd59# u7 hd60# t9 hd61# t5 hd62# r5 hd63# t8 hdstbn0# b6 hdstbn1# k6 hdstbn2# j2 hdstbn3# r4 hdstbp0# b8 hdstbp1# h6 hdstbp2# j4 hdstbp3# p3 hdvref0 c5 hdvref1 n8 hdvref2 p6 hdvref3 t7 hi_stbf c10 hi_stbs d10 hi0_a e11 hi0_b d16 hi0_c d22 hi0_d d28 hi1_a b11 hi1_b g16 hi1_c b24 hi1_d g25 hi2_a g10 hi2_b c17 hi2_c g18 hi2_d g26 hi3_a f10 hi3_b c16 hi3_c c22 hi3_d f26 hi4_a d9 hi4_b a17 hi4_c e20 hi4_d g24 hi5_a e9 hi5_b a16 hi5_c f19 hi5_d a27 hi6_a j11 hi6_b b14 hi6_c d21 hi6_d h24 hi7_a h9 hi7_b d15 hi7_c e21 hi7_d c26 table 7-1. mch signal list signal name ball # hi8_a j13 hi8_b c14 hi8_c d19 hi8_d g22 hi9_a j10 hi9_b f13 hi9_c a20 hi9_d e24 hi10_a f11 hi10_b a13 hi10_c b20 hi10_d a25 hi11_a g12 hi11_b c13 hi11_c c19 hi11_d d24 hi12_b d12 hi12_c b18 hi12_d a24 hi13_b e12 hi13_c c18 hi13_d e23 hi14_b c11 hi14_c e18 hi14_d f23 hi15_b j14 hi15_c f17 hi15_d f22 hi16_b h14 hi16_c b21 hi16_d h23 hi17_b b17 hi17_c c24 hi17_d h25 hi18_b e14 hi18_c f20 hi18_d f25 hi20_b f14 hi20_c h18 hi20_d e27 hi21_b g13 hi21_c f16 hi21_d h21 hircomp_a h11 hircomp_b e15 hircomp_c c20 hircomp_d g21 hiswng_a h12 hiswng_b b15 hiswng_c h17 hiswng_d f24 table 7-1. mch signal list signal name ball #
ballout and package specifications datasheet 137 hit# u1 hitm# w5 hivref_a g9 hivref_b d13 hivref_c a21 hivref_d j22 hlock# v7 hreq0# ab2 hreq1# aa1 hreq2# aa7 hreq3# ab3 hreq4# y9 htrdy# w3 hxrcomp v4 hxswing v8 hyrcomp g5 hyswing k5 ma0_a af24 ma0_b m26 ma1_a ak26 ma1_b k29 ma2_a ah26 ma2_b h30 ma3_a aj27 ma3_b g30 ma4_a ag27 ma4_b f32 ma5_a ah28 ma5_b g29 ma6_a al28 ma6_b f31 ma7_a al29 ma7_b e33 ma8_a ak29 ma8_b e31 ma9_a am30 ma9_b f29 ma10_a aj24 ma10_b l25 ma11_a ak30 ma11_b c31 ma12_a am31 ma12_b c32 pstrbf_b g15 pstrbf_c c23 pstrbf_d d27 pstrbs_b h15 pstrbs_c b23 pstrbs_d d26 pustrbf_b a12 pustrbf_c d18 table 7-1. mch signal list signal name ball # pustrbf_d b25 pustrbs_b b12 pustrbs_c e17 pustrbs_d c25 pwrgood a28 ras_a# an24 ras_b# v32 rcvenin_a# am22 rcvenin_b# n30 rcvenout_a# ag20 rcvenout_b# r25 reserved b30 reserved am18 reserved k33 reserved d29 rs0# v2 rs1# v5 rs2# u4 rsp# ak4 rstin# e28 smb_clk j25 smb_data b31 vcc_cpu ac5 vcc_cpu ag3 vcc_cpu aj5 vcc_cpu af5 vcc_cpu ah1 vcc_cpu k7 vcc_cpu f3 vcc_cpu p5 vcc_cpu r3 vcc_cpu w7 vcc_cpu h5 vcc_cpu l5 vcc_cpu u5 vcc_cpu y5 vcc_cpu ae7 vcc_cpu k9 vcc_cpu ad1 vcc_cpu d1 vcc_cpu h1 vcc_cpu m1 vcc_cpu t1 vcc_cpu y1 vcc_cpu a6 vcc_cpu e7 vcc_cpu aa10 vcc_cpu ab11 vcc_cpu ac10 vcc_cpu c3 vcc_cpu d5 table 7-1. mch signal list signal name ball # vcc_cpu l10 vcc_cpu m11 vcc_cpu n10 vcc_cpu p11 vcc_cpu r10 vcc_cpu t11 vcc_cpu u10 vcc_cpu v11 vcc_cpu w10 vcc_cpu y11 vcc1_2 l18 vcc1_2 l20 vcc1_2 l22 vcc1_2 b28 vcc1_2 h20 vcc1_2 a10 vcc1_2 a14 vcc1_2 a18 vcc1_2 a22 vcc1_2 e10 vcc1_2 e13 vcc1_2 e16 vcc1_2 e19 vcc1_2 e22 vcc1_2 k13 vcc1_2 k15 vcc1_2 k17 vcc1_2 k19 vcc1_2 k21 vcc1_2 k23 vcc1_2 p14 vcc1_2 p18 vcc1_2 r17 vcc1_2 r19 vcc1_2 t14 vcc1_2 t16 vcc1_2 t18 vcc1_2 u17 vcc1_2 u19 vcc1_2 v16 vcc1_2 v18 vcc1_2 w15 vcc1_2 w17 vcc1_2 w19 vcc1_2 a26 vcc1_2 a30 vcc1_2 r15 vcc1_2 v14 vcc1_2 e26 vcc1_2 h19 vcc1_2 k11 table 7-1. mch signal list signal name ball #
ballout and package specifications 138 datasheet vcc1_2 l12 vcc1_2 l14 vcc1_2 l16 vcc2_5 r23 vcc2_5 an4 vcc2_5 an7 vcc2_5 aa23 vcc2_5 ac13 vcc2_5 ac15 vcc2_5 ac17 vcc2_5 ac19 vcc2_5 u23 vcc2_5 w23 vcc2_5 ab24 vcc2_5 ad12 vcc2_5 ad14 vcc2_5 ad16 vcc2_5 ad18 vcc2_5 ad20 vcc2_5 ad25 vcc2_5 ad29 vcc2_5 ad33 vcc2_5 ae10 vcc2_5 ae30 vcc2_5 af33 vcc2_5 aj11 vcc2_5 aj14 vcc2_5 aj17 vcc2_5 aj20 vcc2_5 aj23 vcc2_5 ak33 vcc2_5 an10 vcc2_5 an14 vcc2_5 an18 vcc2_5 an22 vcc2_5 an26 vcc2_5 h33 vcc2_5 l29 vcc2_5 m33 vcc2_5 p24 vcc2_5 p29 vcc2_5 t24 vcc2_5 t33 vcc2_5 u29 vcc2_5 v24 vcc2_5 y24 vcc2_5 y29 vcc2_5 y33 vcc2_5 aa27 vcc2_5 ag13 vcc2_5 ag19 table 7-1. mch signal list signal name ball # vcc2_5 ag22 vcc2_5 ak10 vcc2_5 ak8 vcc2_5 al1 vcc2_5 al15 vcc2_5 al24 vcc2_5 g27 vcc2_5 ac21 vcc2_5 ac23 vcc2_5 l23 vcc2_5 n23 vcc2_5 ad22 vcc2_5 ad24 vcc2_5 aj26 vcc2_5 aj29 vcc2_5 an30 vcc2_5 d33 vcc2_5 e29 vcc2_5 h29 vcc2_5 k24 vcc2_5 m24 vcc2_5 af23 vcc2_5 ag28 vcc2_5 am32 vcc2_5 b32 vcc2_5 l26 vcc2_5 ab31 vcc2_5 k31 vcc2_5 t31 vcca1_2 p20 vcca1_2 t20 vcca1_2 v20 vcca1_2 y14 vcca1_2 y16 vcca1_2 y18 vcca1_2 y20 vccacpu1_2 u15 vccahi1_2 p16 vss ad11 vss ad13 vss ad15 vss ad17 vss ad19 vss ad21 vss ad23 vss ad26 vss ad30 vss ae29 vss ae9 vss af10 vss af11 table 7-1. mch signal list signal name ball # vss af14 vss af17 vss af20 vss af26 vss af29 vss af32 vss ag16 vss ag25 vss ag31 vss ah12 vss ah15 vss ah18 vss ah21 vss ah24 vss ah27 vss ah30 vss aj32 vss aj33 vss ak13 vss ak16 vss ak22 vss ak25 vss ak28 vss ak31 vss al12 vss al18 vss al21 vss al27 vss al30 vss al33 vss am11 vss am14 vss am17 vss am20 vss am23 vss am26 vss am29 vss an11 vss ak9 vss am8 vss ac8 vss g7 vss d30 vss af8 vss aa9 vss j6 vss v3 vss f28 vss ag6 vss ah7 vss ah4 table 7-1. mch signal list signal name ball #
ballout and package specifications datasheet 139 vss an15 vss an19 vss an23 vss an27 vss an3 vss an31 vss an6 vss b10 vss b13 vss b16 vss b19 vss b22 vss b26 vss b29 vss b4 vss b7 vss c1 vss c12 vss c15 vss c21 vss c27 vss c30 vss c33 vss c6 vss c9 vss d11 vss d14 vss d17 vss d20 vss d23 vss d31 vss d8 vss e25 vss e32 vss f12 vss f15 vss f18 vss f21 vss f27 vss f30 vss f6 vss f9 vss g1 vss g11 vss g14 vss g17 vss g20 vss g23 vss g28 vss g31 vss g33 table 7-1. mch signal list signal name ball # vss al4 vss aj2 vss ak3 vss ad6 vss ak6 vss al7 vss am5 vss af2 vss ad3 vss ag1 vss ak1 vss u9 vss e2 vss h2 vss k4 vss j3 vss k8 vss l8 vss g4 vss m6 vss p2 vss m3 vss m9 vss p8 vss n9 vss u2 vss r6 vss t4 vss v6 vss w4 vss w2 vss y2 vss aa3 vss aa6 vss y8 vss j19 vss j20 vss g19 vss e5 vss j23 vss ab5 vss d4 vss ae4 vss ac2 vss ag9 vss l9 vss c28 vss b27 vss ab4 vss ab7 vss ad9 table 7-1. mch signal list signal name ball # vss g8 vss h10 vss h13 vss h16 vss h22 vss h26 vss h32 vss h8 vss j12 vss j15 vss j18 vss j21 vss j24 vss j27 vss j30 vss j9 vss k12 vss k14 vss k16 vss k18 vss k20 vss k22 vss k28 vss l1 vss l24 vss l32 vss l33 vss m23 vss m27 vss m30 vss n5 vss n24 vss n28 vss n31 vss p15 vss p17 vss p19 vss p23 vss p32 vss r1 vss r14 vss r18 vss r20 vss r24 vss r27 vss r30 vss r33 vss r9 vss t15 vss t17 vss t19 table 7-1. mch signal list signal name ball #
ballout and package specifications 140 datasheet vss aa11 vss ab10 vss ac11 vss ad10 vss an9 vss m10 vss m5 vss n11 vss p10 vss r11 vss t10 vss u11 vss v10 vss w11 vss y10 vss b2 vss j17 table 7-1. mch signal list signal name ball # vss k10 vss l11 vss l13 vss l15 vss l17 vss l19 vss l21 vss r16 vss ac29 vss aj10 vss d25 vss a11 vss a15 vss a19 vss a23 vss a29 vss a3 vss a31 vss a7 vss aa24 vss aa30 vss ab23 vss ab28 vss ac1 vss ac12 vss ac14 vss ac16 vss ac18 vss ac20 vss ac22 vss ac24 vss ac26 vss ac32 vss ac33 vss t23 table 7-1. mch signal list signal name ball # vss t28 vss u14 vss u16 vss u18 vss u20 vss u24 vss u32 vss u8 vss v15 vss v17 vss v19 vss v23 vss v27 vss v30 vss v9 vss w1 vss w14 vss w16 vss w18 vss w20 vss w24 vss w28 vss w31 vss w33 vss y15 vss y17 vss y19 vss y23 vss y26 vss y32 vss aj8 we_a# ae23 we_b# d32 xerr# ak2 xormode# c29 table 7-1. mch signal list signal name ball #
datasheet 141 ballout and package specifications 7.2 package specifications figure 7-4 and figure 7-5 provide the package specifications for the mch. note: 1. all dimensions are in millimeters. 2. all dimensions and tolerances conform to ansi y14.5m-1982. figure 7-4. mch package dimensions (top view) an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e e c b a 10 16 20 3 5 7 9 11 13 15 19 4 6 18 8 12 14 22 21 24 23 26 25 28 27 30 29 31 32 (n)x 0.025 min metal edge (n)x ? 0.790 0.025 solder resist opening (n)x 0.650 0.040 detail a ? ? ? ? 00.071 l c ? ? ? ? 00.200 l c a s b 33 1 2 1.270 20.320 40.640 2x 42.500 0.100 0.200 a b 1.270 21.250 detail a 17
ballout and package specifications 142 datasheet notes: 1. all dimensions are in millimeters. 2. substrate thickness and package overall height are thicker than standard 492-l-pbga 3. primary datum ?c? and seating plane are defined by the spherical crowns of the solder balls. 4. all dimensions and tolerances conform to ansi y14.5m-1982. figure 7-5. mch package dimensions (side view) 1.10 0.10 mm die substrate 0.60 0.10 mm seating plane 1.940 0.150 mm 0.20 ?c? see note 3.
datasheet 143 ballout and package specifications 7.3 chipset interface trace length compensation in this section, detailed information is given about the internal component package trace lengths to enable trace length compensation. trace length compensation is required for platform design. these lengths must be considered when matching trace lengths as described in the intel ? xeon? processor with 512-kb l2 cache and intel ? e7500 chipset platform design guide. note that these lengths represent the actual lengths from pad to ball. the data given can be normalized from a particular reference ball to simplify routing. if the longest trace is used as the reference for normalization, use equation 7-1 . equation 7-1. l ref is the nominal package length of the reference signal used for normalization. ? l pkg is the nominal ? package trace length of the mch from the reference trace. to calculate the ? l pcb for signals from the mch to the device, use equation 7-2 . equation 7-2. ? l pcb is the nominal ? pcb trace length to be added on the pcb. ? l pkg is the nominal ? package trace length of the mch (refer to equation 1). v pkg is the mch package trace delay due to signal velocity. the nominal value is 150 ps/in. v pcb is the pcb trace delay due to signal velocity. the nominal value is 175 ps/in on the recommended stackup. note: use care when converting delays and velocities (x ps/in is a delay, y in/ps is a velocity). table 7-2 shows example values when signal memory1 trace length is used for normalization. pkg ref pkg l l l ? = ? pcb pkg pkg pcb v v l l ? = ? table 7-2. example normalization table l pkg (mils) ? l pkg (mils) ? l pcb (mils) target l pcb (mils) memory1 175.984 0.000 0.000 3500.000 memory2 152.364 23.620 20.246 3520.246 memory3 130.315 45.669 39.145 3539.145 memory4 118.897 57.087 48.932 3548.932 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? memoryn 102.756 73.228 62.767 3562.767
ballout and package specifications 144 datasheet 7.3.1 mch system bus signal package trace length data table 7-3 is the mch package trace length information for the system bus. table 7-3. mch l pkg data for the system bus (sheet 1 of 2) signal ball no. l pkg (mils) signal ball no. l pkg (mils) hadstb0# ae1 797.99 hdstbn0# b6 842.99 ha3# aa8 296.14 hdstbp0# b8 739.72 ha4# ab1 692.09 hd0# b9 682.48 ha5# ac3 602.24 hd1# a9 775.98 ha6# ad2 761.50 hd2# a4 955.20 ha7# ab6 469.09 hd3# b5 933.07 ha8# ac4 569.02 hd4# e8 648.77 ha9# ad4 631.65 hd5# b3 1044.33 ha10# ae5 612.17 hd6# a5 930.87 ha11# ae2 781.97 hd7# c8 732.77 ha12# ac6 469.44 hd8# a8 763.54 ha13# ab9 578.15 hd9# c4 909.13 ha14# ae6 576.69 hd10# c7 779.65 ha15# ae3 702.60 hd11# d7 765.00 ha16# ad5 512.91 hd12# h7 535.59 hreq0# ab2 665.47 hd13# c2 1059.96 hreq1# aa1 684.80 hd14# j8 398.46 hreq2# aa7 397.91 hd15# j7 457.64 hreq3# ab3 591.46 dbi0# f8 596.13 hreq4# y9 308.86 hdstbn1# k6 480.24 hadstb1# ad7 430.11 hdstbp1# h6 562.32 ha17# ab8 334.72 hd16# f7 617.72 ha18# ac7 390.55 hd17# l7 378.98 ha19# ac9 379.57 hd18# l6 450.04 ha20# ah2 860.71 hd19# e6 762.64 ha21# ah3 732.09 hd20# g6 680.20 ha22# ag2 772.17 hd21# d6 771.73 ha23# af6 567.76 hd22# f5 809.84 ha24# ad8 403.50 hd23# e4 859.72 ha25# af1 798.46 hd24# m8 334.68 ha26# ag4 690.75 hd25# e1 1030.20 ha27# aj4 695.39 hd26# f4 851.54 ha28# ae8 413.27 hd27# d3 892.64 ha29# af3 736.10 hd28# f2 945.08 ha30# af7 521.58 hd29# e3 905.20 ha31# ah5 619.72 hd30# f1 1031.89 ha32# ag7 497.28 hd31# m7 400.67 ha33# ah6 601.73 dbi1# d2 981.89 ha34# aj1 877.87 ha35# ag5 611.77 hclkinn u3 639.53 hclkinp t2 639.61
datasheet 145 ballout and package specifications 7.3.1.1 mch ddr channel a signal package trace length data table 7-4 is the mch package trace length information for channel a of the ddr memory interface. hdstbn2# j2 783.19 hdstbn3# r4 529.41 hdstbp2# j4 726.26 hdstbp3# p3 605.71 hd32# h4 715.47 hd48# l3 669.41 hd33# h3 803.03 hd49# n4 596.42 hd34# g2 865.59 hd50# p4 584.80 hd35# k3 723.94 hd51# m2 723.07 hd36# g3 818.54 hd52# l2 729.17 hd37# j1 803.50 hd53# n2 707.44 hd38# k2 740.32 hd54# n3 605.91 hd39# k1 821.65 hd55# n1 760.00 hd40# n6 419.37 hd56# r2 613.43 hd41# j5 720.87 hd57# t6 534.25 hd42# p9 315.91 hd58# t3 580.20 hd43# m4 622.60 hd59# u7 367.72 hd44# p7 373.34 hd60# t9 271.46 hd45# n7 351.31 hd61# t5 479.33 hd46# r7 332.80 hd62# r5 451.46 hd47# r8 306.89 hd63# t8 312.87 dbi2# l4 649.69 dbi3# p1 686.77 table 7-3. mch l pkg data for the system bus (sheet 2 of 2) signal ball no. l pkg (mils) signal ball no. l pkg (mils) table 7-4. mch l pkg data for ddr channel a (sheet 1 of 3) signal ball no. l pkg (mils) signal ball no. l pkg (mils) dqs0_a am27 760.59 dqs2_a ag18 338.67 dqs9_a af21 291.45 dqs11_a ak18 477.64 dq0_a af22 345.91 dq16_a ak19 499.02 dq1_a an28 853.78 dq17_a al19 583.11 dq2_a ae21 284.59 dq18_a an17 674.17 dq3_a ah22 447.83 dq19_a af18 297.50 dq4_a an29 867.36 dq20_a an20 697.09 dq5_a am28 817.76 dq21_a am19 630.75 dq6_a al26 707.24 dq22_a al17 534.80 dq7_a al25 642.13 dq23_a aj18 455.77 dqs1_a al23 602.87 dqs3_a ae18 226.03 dqs10_a ak23 552.99 dqs12_a ak20 500.71 dq8_a an25 761.06 dq24_a af19 300.32 dq9_a am24 712.95 dq25_a ah19 423.19 dq10_a ag21 371.89 dq26_a am21 625.04 dq11_a ae20 273.13 dq27_a al20 578.15 dq12_a am25 737.68 dq28_a ah20 440.20 dq13_a ak24 607.13 dq29_a aj21 503.66 dq14_a al22 578.43 dq30_a an21 703.07 dq15_a aj22 475.71 dq31_a aj19 438.58
ballout and package specifications 146 datasheet dqs4_a al13 595.67 dqs7_a al6 733.15 dqs13_a aj13 473.62 dqs16_a ah9 483.27 dq32_a al14 586.58 dq56_a ag10 446.54 dq33_a am13 662.60 dq57_a aj9 572.13 dq34_a aj15 512.60 dq58_a am3 957.28 dq35_a af15 350.43 dq59_a am2 990.51 dq36_a ak14 516.50 dq60_a ah10 527.88 dq37_a an13 730.83 dq61_a ae11 337.46 dq38_a ah14 447.76 dq62_a al5 779.02 dq39_a ag14 358.19 dq63_a am4 882.36 dqs5_a am12 693.27 dqs8_a aj16 432.48 dqs14_a ak12 531.46 dqs17_a af16 281.57 dq40_a ae14 402.72 cb0_a ae16 256.61 dq41_a ah13 453.46 cb1_a ah16 412.22 dq42_a an12 704.45 cb2_a al16 559.57 dq43_a al11 666.30 cb3_a ak15 560.08 dq44_a ae15 270.32 cb4_a ae17 375.28 dq45_a af13 344.49 cb5_a ag17 359.80 dq46_a aj12 506.22 cb6_a am15 656.14 dq47_a am10 703.35 cb7_a ag15 371.50 dqs6_a al8 676.58 dqs15_a am7 755.79 dq48_a ae12 278.66 dq49_a ah11 463.74 dq50_a ag11 441.73 dq51_a an5 898.50 dq52_a ag12 412.05 dq53_a af12 377.68 dq54_a am9 742.17 dq55_a am6 855.47 table 7-4. mch l pkg data for ddr channel a (sheet 2 of 3) signal ball no. l pkg (mils) signal ball no. l pkg (mils)
datasheet 147 ballout and package specifications cmdclk0_a ag24 447.35 cmdclk2_a ag26 459.06 cmdclk0_a# ag23 405.28 cmdclk2_a# af25 367.24 ba0_a al31 789.29 ba0_a al31 789.29 ba1_a ah23 427.72 ba1_a ah23 427.72 cas_a# ae22 411.22 cas_a# ae22 411.22 cke_a ae19 249.80 cke_a ae19 249.80 cs0_a# ae13 434.96 cs4_a# an8 805.28 cs1_a# ak11 594.41 cs5_a# ak7 716.34 ma0_a af24 340.16 ma0_a af24 340.16 ma1_a ak26 640.55 ma1_a ak26 640.55 ma2_a ah26 512.01 ma2_a ah26 512.01 ma3_a aj27 568.58 ma3_a aj27 568.58 ma4_a ag27 466.97 ma4_a ag27 466.97 ma5_a ah28 595.79 ma5_a ah28 595.79 ma6_a al28 791.89 ma6_a al28 791.89 ma7_a al29 735.71 ma7_a al29 735.71 ma8_a ak29 698.35 ma8_a ak29 698.35 ma9_a am30 827.80 ma9_a am30 827.80 ma10_a aj24 572.17 ma10_a aj24 572.17 ma11_a ak30 712.64 ma11_a ak30 712.64 ma12_a am31 865.00 ma12_a am31 865.00 ras_a# an24 757.84 ras_a# an24 757.84 we_a# ae23 298.19 we_a# ae23 298.19 cmdclk1_a aj25 544.88 cmdclk3_a ae25 359.80 cmdclk1_a# ah25 473.52 cmdclk3_a# ae24 322.68 ba0_a al31 789.29 ba0_a al31 789.29 ba1_a ah23 427.72 ba1_a ah23 427.72 cas_a# ae22 411.22 cas_a# ae22 411.22 cke_a ae19 249.80 cke_a ae19 249.80 cs2_a# al10 641.10 cs6_a# al3 892.80 cs3_a# ah8 622.17 cs7_a# al2 917.36 ma0_a af24 340.16 ma0_a af24 340.16 ma1_a ak26 640.55 ma1_a ak26 640.55 ma2_a ah26 512.01 ma2_a ah26 512.01 ma3_a aj27 568.58 ma3_a aj27 568.58 ma4_a ag27 466.97 ma4_a ag27 466.97 ma5_a ah28 595.79 ma5_a ah28 595.79 ma6_a al28 791.89 ma6_a al28 791.89 ma7_a al29 735.71 ma7_a al29 735.71 ma8_a ak29 698.35 ma8_a ak29 698.35 ma9_a am30 827.80 ma9_a am30 827.80 ma10_a aj24 572.17 ma10_a aj24 572.17 ma11_a ak30 712.64 ma11_a ak30 712.64 ma12_a am31 865.00 ma12_a am31 865.00 ras_a# an24 757.84 ras_a# an24 757.84 we_a# ae23 298.19 we_a# ae23 298.19 table 7-4. mch l pkg data for ddr channel a (sheet 3 of 3) signal ball no. l pkg (mils) signal ball no. l pkg (mils)
ballout and package specifications 148 datasheet 7.3.1.2 mch ddr channel b signal package trace length data table 7-5 is the mch package trace length information for channel b of the ddr memory interface. f table 7-5. mch l pkg data for ddr channel b (sheet 1 of 3) signal ball no. l pkg (mils) signal ball no. l pkg (mils) dqs0_b l30 545.94 dqs3_b r29 445.98 dqs9_b h31 698.39 dqs12_b r31 541.50 dq0_b f33 870.43 dq24_b p30 523.82 dq1_b k30 639.33 dq25_b p33 694.80 dq2_b j32 695.67 dq26_b r26 287.40 dq3_b n25 275.85 dq27_b t32 586.46 dq4_b n27 344.82 dq28_b n32 655.83 dq5_b g32 796.61 dq29_b p31 587.64 dq6_b m29 488.98 dq30_b r28 415.72 dq7_b n26 329.65 dq31_b t25 307.72 dqs1_b m31 586.65 dqs4_b ae32 756.46 dqs10_b n29 459.05 dqs13_b ac30 609.57 dq8_b j33 765.35 dq32_b w27 375.75 dq9_b k32 724.84 dq33_b ae33 825.12 dq10_b p27 361.38 dq34_b af31 780.55 dq11_b p25 246.21 dq35_b w25 627.56 dq12_b j31 710.35 dq36_b aa28 499.10 dq13_b l31 635.83 dq37_b ad32 766.85 dq14_b p26 322.21 dq38_b ag33 863.70 dq15_b p28 423.86 dq39_b w26 328.87 dqs2_b u33 660.43 dqs5_b ac31 692.56 dqs11_b u31 545.16 dqs14_b ab30 598.03 dq16_b t29 441.22 dq40_b aa29 567.36 dq17_b t30 511.14 dq41_b ab33 769.02 dq18_b u30 523.03 dq42_b v26 288.03 dq19_b t26 318.23 dq43_b ad31 746.26 dq20_b r32 631.77 dq44_b y28 421.18 dq21_b t27 366.58 dq45_b ab32 743.46 dq22_b v33 697.36 dq46_b ab29 590.71 dq23_b v31 556.89 dq47_b v25 633.50
datasheet 149 ballout and package specifications dqs6_b ae28 569.17 dqs8_b w29 470.79 dqs15_b ad27 502.05 dqs17_b y30 551.26 dq48_b y25 247.68 cb0_b v28 422.40 dq49_b ab27 417.01 cb1_b u25 262.04 dq50_b ah32 865.47 cb2_b y31 639.37 dq51_b ah31 860.08 cb3_b aa33 724.06 dq52_b ac28 547.40 cb4_b u28 421.42 dq53_b aa26 339.80 cb5_b u27 356.31 dq54_b ag30 780.12 cb6_b aa31 605.00 dq55_b ah33 946.54 cb7_b aa32 701.69 dqs7_b ae27 488.39 dqs16_b af28 548.74 dq56_b aj30 741.93 dq57_b ag29 692.99 dq58_b ab25 480.35 dq59_b aa25 260.73 dq60_b al32 924.06 dq61_b aj31 816.65 dq62_b ac27 478.39 dq63_b ab26 360.59 table 7-5. mch l pkg data for ddr channel b (sheet 2 of 3) signal ball no. l pkg (mils) signal ball no. l pkg (mils)
ballout and package specifications 150 datasheet cmdclk0_b j29 595.43 cmdclk2_b j26 397.24 cmdclk0_b# j28 539.65 cmdclk2_b# k25 313.50 ba0_b k26 370.75 ba0_b k26 370.75 ba1_b h27 430.16 ba1_b h27 430.16 cas_b# h28 542.21 cas_b# h28 542.21 cke_b m32 660.59 cke_b m32 660.59 cs0_b# ah29 693.82 cs4_b# ae31 739.72 cs1_b# ak32 899.92 cs5_b# ae26 463.94 ma0_b m26 333.74 ma0_b m26 333.74 ma1_b k29 540.43 ma1_b k29 540.43 ma2_b h30 659.69 ma2_b h30 659.69 ma3_b g30 705.39 ma3_b g30 705.39 ma4_b f32 793.19 ma4_b f32 793.19 ma5_b g29 612.68 ma5_b g29 612.68 ma6_b f31 747.72 ma6_b f31 747.72 ma7_b e33 892.05 ma7_b e33 892.05 ma8_b e31 728.54 ma8_b e31 728.54 ma9_b f29 603.94 ma9_b f29 603.94 ma10_b l25 435.71 ma10_b l25 435.71 ma11_b c31 794.25 ma11_b c31 794.25 ma12_b c32 813.07 ma12_b c32 813.07 ras_b# v32 651.06 ras_b# v32 651.06 we_b# d32 818.43 we_b# d32 818.43 cmdclk1_b l28 417.28 cmdclk3_b k27 423.70 cmdclk1_b# m28 405.28 cmdclk3_b# l27 400.43 ba0_b k26 370.75 ba0_b k26 370.75 ba1_b h27 430.16 ba1_b h27 430.16 cas_b# h28 542.21 cas_b# h28 542.21 cke_b m32 660.59 cke_b m32 660.59 cs2_b# af30 739.06 cs6_b# ad28 575.79 cs3_b# af27 515.04 cs7_b# y27 353.35 ma0_b m26 333.74 ma0_b m26 333.74 ma1_b k29 540.43 ma1_b k29 540.43 ma2_b h30 659.69 ma2_b h30 659.69 ma3_b g30 705.39 ma3_b g30 705.39 ma4_b f32 793.19 ma4_b f32 793.19 ma5_b g29 612.68 ma5_b g29 612.68 ma6_b f31 747.72 ma6_b f31 747.72 ma7_b e33 892.05 ma7_b e33 892.05 ma8_b e31 728.54 ma8_b e31 728.54 ma9_b f29 603.94 ma9_b f29 603.94 ma10_b l25 435.71 ma10_b l25 435.71 ma11_b c31 794.25 ma11_b c31 794.25 ma12_b c32 813.07 ma12_b c32 813.07 ras_b# v32 651.06 ras_b# v32 651.06 we_b# d32 818.43 we_b# d32 818.43 table 7-5. mch l pkg data for ddr channel b (sheet 3 of 3) signal ball no. l pkg (mils) signal ball no. l pkg (mils)
datasheet 151 ballout and package specifications 7.3.1.3 mch hub interface_a signal package trace length data table 7-6 is the mch package trace length information for hub interface_a. 7.3.1.4 mch hub interface_b signal package trace length data table 7-7 is the mch package trace length information for hub interface_b. table 7-6. mch l pkg data for hub interface_a signal ball no. l pkg (mils) hi_stbf c10 659.09 hi_stbs d10 623.43 hi0_a e11 519.92 hi1_a b11 743.78 hi2_a g10 468.03 hi3_a f10 501.54 hi4_a d9 633.62 hi5_a e9 543.11 hi6_a j11 317.83 hi7_a h9 426.55 table 7-7. mch l pkg data for hub interface_b signal ball no. l pkg (mils) signal ball no. l pkg (mils) pstrbf_b g15 333.78 pustrbf_b a12 678.70 pstrbs_b h15 300.32 pustrbs_b b12 645.75 hi0_b d16 482.83 hi8_b c14 591.54 hi1_b g16 478.27 hi9_b f13 433.19 hi2_b c17 544.45 hi10_b a13 702.76 hi3_b c16 571.54 hi11_b c13 568.78 hi4_b a17 677.56 hi12_b d12 518.46 hi5_b a16 679.33 hi13_b e12 504.53 hi6_b b14 597.40 hi14_b c11 611.77 hi7_b d15 531.18 hi15_b j14 272.14 hi20_b f14 414.53 hi21_b g13 386.58
ballout and package specifications 152 datasheet 7.3.1.5 mch hub interface_c signal package trace length data table 7-8 is the mch package trace length information for hub interface_c. 7.3.1.6 mch hub interface_d signal package trace length data table 7-9 is the mch package trace length information for hub interface_d. table 7-8. mch l pkg data for hub interface_c signal ball no. l pkg (mils) signal ball no. l pkg (mils) pstrbf_c c23 681.10 pustrbf_c d18 514.80 pstrbs_c b23 732.52 pustrbs_c e17 464.80 hi0_c d22 635.32 hi8_c d19 557.40 hi1_c b24 757.96 hi9_c a20 728.98 hi2_c g18 360.95 hi10_c b20 665.71 hi3_c c22 696.42 hi11_c c19 616.69 hi4_c e20 495.43 hi12_c b18 650.47 hi5_c f19 394.84 hi13_c c18 561.77 hi6_c d21 609.57 hi14_c e18 453.94 hi7_c e21 516.69 hi15_c f17 379.61 hi20_c h18 294.76 hi21_c f16 416.61 table 7-9. mch l pkg data for hub interface_d signal ball no. l pkg (mils) signal ball no. l pkg (mils) pstrbf_d d27 720.08 pustrbf_d b25 760.04 pstrbs_d d26 731.54 pustrbs_d c25 716.14 hi0_d d28 772.84 hi8_d g22 496.18 hi1_d g25 565.51 hi9_d e24 588.62 hi2_d g26 538.23 hi10_d a25 816.22 hi3_d f26 592.94 hi11_d d24 618.90 hi4_d g24 517.40 hi12_d a24 808.66 hi5_d a27 902.48 hi13_d e23 526.58 hi6_d h24 416.58 hi14_d f23 494.53 hi7_d c26 745.28 hi15_d f22 497.05 hi20_d e27 700.00 hi21_d h21 502.40
datasheet 153 testability testability 8 in the mch, the ability for automated test equipment (ate) board-level testing has been implemented as an xor chain. an xor chain is a chain of xor gates, each with one input pin connected to it. the mch uses the xormode# pin to activate the xor test mode. the method to put the mch in xor test is to assert the xormode# signal. when the following conditions are met, the chip will be in xor test mode. if any of the following are not met, then xor test will not be enabled. 1. assert pwrgood 2. assert rstin# for 128 clocks beyond the assertion of pwrgood (rstin# may be held asserted before pwrgood is asserted). 3. deassert rstin# 4. assert xormode# and hold asserted. 5. the clocks may be held at the 0 or 1 state; or be fully running. since hclkinp/hclkinn is a differential pair, the 2 clock inputs should be held in opposite states. 6. as long as xormode# is asserted the mch is in xor test. as soon as xormode# is asserted and 2 hclkinp/hclkinn cycles have occurred, all the xor chains are functional. 7. after deasserting xormode#, the mch should be reset before any other testing is done. there are eight chains of xors divided up functionally. note: for all test modes except asynchronous xor mode, input pin xormode# should be driven high.
154 datasheet testability 8.1 xor chains the xor chain outputs (xor chains 8 through 1) are visible on hi_a[7:0]. in long xor chain mode the delay through the 4 pad ring chains (chains 1, 2, 3, 4) may be observed on hi4_a. rstin# is not part of any xor chain. this is in addition to hi_a[7:0]. the chain partitioning is listed in table 8-1 . when signals are grouped in table 8-1 (e.g., dq_a[63:0]), the chain order is the same as the ascending numerical name of the pin name (i.e., the chain order for dq_a[63:0] is dq_a0, dq_a1, dq_a2, ... dq_a63). table 8-1. xor chains chain #1 chain #2 chain #3 chain #4 chain #5 chain #6 chain #7 chain #8 dq_a[63:0] dqs_a[17:0] dq_b[63:0] dqs_b[17:0] hi_stbf hi_b[17:0] hd[63:0]# ads# cb_a[7:0] cmdclk_a [3:0] cb_b[7:0] cmdclk_b [3:0] hi_stbs pstrbf_b dp[3:0]# ap[1:0]# cmdclk_a [3:0]# cmdclk_b [3:0]# hi10_a pstrbs_b binit# ma_a[12:0] ma_b[12:0] hi8_a pustrbf_b bnr# ba_a[1:0] ba_b[1:0] hi9_a pustrbs_b bpri# ras_a# ras_b# hi11_a hi18_b breq0# cas_a# cas_b# smb_clk hi16_b cpurst# we_a# we_b# smb_data hi17_b dbsy# cs_a[7:0]# cs_b[7:0]# hi_c[17:0] defer# cke_a[1:0] cke_b[1:0] pstrbf_c dbi[3:0]# rcvenins _a# rcvenin _b# pstrbs_c drdy# rcvenout _a# rcvenout _b# pustrbf_c ha[35:3]# pustrbs_c hadstb [1:0]# hi18_c hreq[4:0]# hi16_c hdstbp [3:0]# hi17_c hdstbn [3:0]# hi_d[17:0] hit# pstrbf_d hitm# pstrbs_d hlock# pustrbf_d htrdy# pustrbs_d xerr# hi18_d rs[2:0]# hi16_d rsp# hi17_d out = hi1_a out = hi2_a out = hi3_a out = hi4_a out = hi5_a out = hi6_a out = hi7_a out = hi8_a

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