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- 1 - K8P5516UZB rev. 1.3, may. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. 256mb b-die nor flash 56tsop, 64fbga, page mode 2.7v ~ 3.6v datasheet
- 2 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 revision history revision no. history draft date remark editor 0.0 initial draft mar.03,2008 target - 0.1 description of hardwre protection in figure 8: enhanced block pro- tection/unprotection is changed from"a outermost block on both ends of flash array locked" to "h ighest or lowest block locked" dc characteristics table is revised. - "read while program current"(i2) and "read while erase cur- rent"(i3) are deleted. - "wp /acc input leakage current" is changed to "a9 input leakage current". - "active write current " is changed to " vcc active read current". - "v io non-active output", i io 2 is added. - "voltage for wp /acc block temporarily unprotect and program acceleration" is changed to "voltage for program acceleration ". - "voltage for autoselect and temporary sector unprotect", v id is added. feature is revised. - "read while program/erase operation" is deleted. - "read while program or read while erase current : 55ma " is deleted. figure : write buffer program command sequence is revised. cfi table is revised. - address 30h data changed from 0001h to 0002h. - address 34h data changed from 0004h to 0000h. may.15,2008 target - 0.2 feature is revised. - 64mbitx256 is changed to 64kwordx256. june 12, 2008 target - 0.3 - 64fbga package demension is added. - endurance is added. - indicator bit codes table description is corrected june 27, 2008 target - 0.4 -"the data is dq6 = "1" for customer locked and dq7 = "1" for factory locked." is changed to " the dq7 is "1" for factory locked." - device id data is revised from 227eh, 2264h and 2260h to xx7eh, xx64h and xx60h on command sequences(x8) table. - byte mode address is added to cfi table. cfi table is revised. - address 38h data changed from 0001h to 0000h. - "blocks must be unprotected before raising wp /acc to v hh . " is added to accelerated program operation. - "when the wp /acc pin is asserted as v hh , the device automatically enters the unlock bypass mode, temporarily unprotecting any pro- tected blocks, and reduces the progr am operation time." is changed to "when the wp /acc pin is asserted as v hh , the device automati- cally enters the unlock bypass mode, and reduces the program oper- ation time. " - 64fbga package demension is revised. - ordering information is revised. july 04,2008 target - 1.0 - deleted speed code for 4c / 4d. dec. 11, 2008 final - - ac parameter table for speed code 4c and 4d is deleted. - min. vih dc value is changed from 2.0v to vcc x 0.7v. - icc6 is changed from typ. 6ma and max. 10ma to typ. 10ma and max. 15ma
- 3 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 1.1 - note is deleted. related note is below. apr. 02, 2009 final - note : the device supports only 4e at vio = 1.7~1.95v. - package dimension of 56-tsop is revised. 1.2 - revised hardware sequence flags table. jun. 02, 2009 final - - deleted dq6 as customer otp lock information in 12. otp block region. 1.3 - correct typo may 12, 2010 final -
- 4 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 table of contents 256mb b-die nor flash 1.0 features................................................................................................................... .............................................. 5 2.0 general description ........................................................................................................ ................................. 5 3.0 pin description ............................................................................................................ ........................................ 6 4.0 56tsop pin configuration ................................................................................................... ............................. 7 5.0 64 ball fbga top view (ball down) .......................................................................................... ......................... 7 6.0 functional block diagram ................................................................................................... ........................... 8 7.0 ordering information ....................................................................................................... ............................... 9 8.0 product introduction....................................................................................................... ............................... 10 9.0 command definitions ........................................................................................................ ................................. 11 10.0 device operation .......................................................................................................... .................................... 16 10.1 read mode ................................................................................................................. ........................................... 16 10.2 standby mode .............................................................................................................. ......................................... 16 10.3 output disable............................................................................................................ ........................................... 16 10.4 automatic sleep mode ..................................... ................................................................. .................................... 16 10.5 autoselect mode........................................................................................................... ......................................... 16 10.6 write (program/erase) mode................................................................................................ ................................. 17 10.6.1 program ............. .................................................................................................... ......................................... 17 10.6.2 writer buffer programming ........................ ....................................................................... .............................. 18 10.6.3 accelerated program operation................... ........................................................................ ........................... 19 10.6.4 unlock bypass ................. .......................................................................................... ..................................... 20 10.6.5 chip erase ..................... ......................................................................................... ........................................ 20 10.6.6 block erase .......................................... ................................................................... ........................................ 20 10.7 erase suspend / resume.................................................................................................... .................................. 21 10.8 program suspend / resume .................................................................................................. ............................... 21 10.9 write protect (wp)........................................................................................................ ......................................... 22 10.10 software reset ........................................................................................................... ......................................... 22 10.11 hardware reset........................................................................................................... ........................................ 22 10.12 power-up protection ...................................................................................................... ...................................... 23 10.13 low vcc write inhibit .................................................................................................... ....................................... 23 10.14 write pulse glitch protection............................................................................................ ................................... 23 10.15 logical inhibit...................................... .................................................................... ............................................. 23 11.0 common flash memory interface ............................................................................................. ................. 24 12.0 otp block region .......................................................................................................... .......................................... 24 12.1 otp block protection ...................................................................................................... ...................................... 24 13.0 enhanced block protection / unprotection ......... ......................................................................... ...... 25 13.1 block protection.......................................................................................................... ........................................... 26 13.1.1 lock register .......................................... ................................................................. ....................................... 26 13.2 persistent protection bits ................................................................................................ ...................................... 26 13.3 dynamic protection bits ................................................................................................... ..................................... 27 13.4 persistent protection bit lock bit ............... ......................................................................... .................................. 27 13.5 password protection method................................................................................................ ................................. 27 13.6 master locking bit set .................................................................................................... ......................................... 28 14.0 device status flags....................................................................................................... .................................. 36 15.0 absolute maximum ratings ..... .............. .............. .............. .............. .............. .............. ......... ......................... 39 16.0 recommended operating conditions ( voltage reference to gnd )......................................................... 39 17.0 dc characteristics ........................................................................................................ .................................. 40 17.1 capacitance (ta = 25 c, vcc = 3.0v, f = 1.0mhz) . ............. .............. .............. ........... ........... .......... ............. 40 18.0 ac test condition......................................................................................................... ..................................... 41 19.0 ac characteristics ........................................................................................................ .................................. 41 19.1 read operations ........................................................................................................... ........................................ 41 19.2 write(erase/program)operations ............................................................................................ .............................. 44 20.0 erase and program performance.. .............. .............. .............. .............. .............. ........... .......... ................ 45 21.0 package dimensions........................................................................................................ ................................. 58
- 5 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 256m bit (16m x16, 32mb x8) page mode / page nor flash memory 1.0 features ? single voltage, 2.7v to 3.6v for read and write operations ? organization 16m x16 bit (word mode) 32m x 8 bit (byte mode) ? fast read access time : 80ns ? page mode operation 8 words page access allows fast asychronous read page read access time : 30ns ? uniform block architectures 64kword x 256 (uniform) ? otp block : extra 256 word - 128word for factory and 128word for customer otp ? power consumption (typical value) - active read current : 30ma (@5mhz) - program/erase current : 25ma - standby mode/auto sleep mode : 20ua ? support single & 32word buffer program ? wp /acc input pin - allows special protection of fi rst or last block of flash array at v il , regardless of block protect status - removes special protection at v ih, the first or last block of flash array return to normal block protect status - reduce program time at v hh : 6us/word at write buffer ? erase suspend/resume ? program suspend/resume ? unlock bypass mode ? hardware reset pin ? command register operation ? supports common flash memory interface ? industrial temperature : -40 c to 85 c ? extended temperature : -25 c to 85 c ? endurance : 100kcycle ? vio options at 1.8v and 3v i/o ? package options - 56 pin tsop (20x14mm) - 64 ball fbga (11x13, 1.0mm ball pitch) 2.0 general description the K8P5516UZB featuring single 3.0v power supply, is an 256mbit nor- type flash memory organized as 32m x 8 or 16m x16. the memory archi- tecture of the device is designed to divi de its memory arrays into 256 blocks with independent hardware protection. this block architecture provides highly flexible erase and program ca pability. the K8P5516UZB nor flash consists of uniform block. the K8P5516UZB offers page access time of 30ns with random access time of 80ns. the device s fast access times allow high speed microproces- sors to operate without wait states. the device performs a program opera- tion in unit of 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed within typi- cally 0.7 sec. the device requires 25ma as program/erase current in the commercial and extended temperature ranges. the K8P5516UZB nor flash memory is created by using samsung's advanced cmos process technology. th is device is available in 64fbga and 56 pin tsop. the device is compatible with eprom applications to require high-density and cost-effective nonvolatile read/write storage solu- tions.
- 6 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 3.0 pin name pin function a0 - a23 address inputs dq0 - dq14 data inputs / outputs dq15/a-1 dq15 - data inputs / outputs in word mode a-1 - address input in byte mode ce chip enable oe output enable reset hardware reset pin byte word/byte selection ry/ by ready/busy output we write enable wp/acc hardware write protection/program acceleration vcc power supply v ss ground nc no connection pin description
- 7 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 4.0 56tsop pin configuration 56-pin tsop1 standard type 14mm x 20mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 nc nc a1 a2 a3 a23 a6 a22 a4 a5 a10 a11 a12 a14 nc nc a16 byte vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq10 dq2 dq9 dq1 dq8 dq0 oe vss ce 25 26 27 a13 a15 32 31 30 a0 nc vio a9 a8 a19 a20 we reset a21 ry/by a18 wp /acc a17 a7 28 29 dq3 5.0 64 ball fbga top view (ball down) 1 2 3 4 5 6 a b c d e f 7 8 h g nc nc a19 dq5 a22 a23 vio vss nc nc a12 a14 a15 a16 byte dq15/a-1 a13 vss a8 a10 a11 dq7 dq14 dq13 a9 dq6 reset a21 dq12 vcc we dq4 wp /acc a18 dq10 dq11 ry/by dq3 a17 a6 a5 dq0 dq8 dq9 a7 dq1 a4 a2 a1 a0 ce oe a3 vss nc nc nc nc vio nc nc nc a20 dq2
- 8 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 6.0 functional block diagram interface x dec y dec latch & control erase control program control high voltage gen. address cell array block inform i/o vcc vss ce oe we reset ry/by a0(a-1)~a23 dq0~dq15 wp /acc byte
- 9 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 7.0 ordering information k8 p 55 16 u z b - p i 4e samsung nor flash memory device type p : page mode density 55 : 256mbits, single bank operating temperature range c : commercial temp. (0 qc to 70 qc) e : extended temp. (-25 q c to 85 qc) i : industrial temp. (-40 q c to 85 qc) block architecture z : uniform block version b : 3th generation access time 4e : 80ns/30ns operating voltage range u : 2.7 v to 3.6v package e : fbga(lead free, 1.0mm ball pitch) p : tsop1(lead free) organization 16 : x16 , x8 organization [table 1] product line-up [table 2] K8P5516UZB device block divisions [table 3] otp block after entering otp block, any issued addresses should be in the range of otp block address 4e vcc 2.7v~3.6v vio 1.7v~vcc max. address access time (ns) 80ns max. ce access time (ns) 80ns max. oe access time (ns) 30ns max. page access time (ns) 30ns mbit block sizes 256 mbit 64 kw x 256 otp block address a23~a8 area block size address range 0000h factory-locked area 128 words 000000h-00007fh customer-locked area 128 words 000080h-0000ffh
- 10 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 8.0 product introduction the K8P5516UZB is 256mbit nor-type flash memory. the device feat ures single voltage power supply operating within the range of 2.7v to 3. 6 v. the device is programmed by using the channel hot electron (che) injection mechanism which is used to program eproms. the device is erased electri - cally by using fowler-nordheim tunneling mechanism. to provi de highly flexible erase and program capability, the device adapts a block memory archi - tecture that divides its memory array into 256 blocks (64 kw x 256 ). programming is done in units of 16 bits (word) or 8 bits ( byte). all bits of data in one or multiple blocks can be erased simult aneously when the device executes the erase operation. the device offers page access tim e of 30ns with random access time of 80ns supporting high speed microproc essors to operate without any wait states. the command set of K8P5516UZB is fully compatible with stan dard flash devices. the device is controlled by chip enable ( ce ), output enable ( oe ) and write enable ( we ). device operations are executed by selective command codes . the command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. the command codes serve as inputs to an intern al state machine which controls the program/erase circuitry. regi ster contents also internally latch addres ses and data necessary to execute the progr am and erase operations. the K8P5516UZB is implemented with internal program/erase algori thms to execute the program/era se operations. the internal pro gram/erase algo - rithms are invoked by program/erase comm and sequences. the internal program algorithm automatically programs and verifies data at specified addresses. the internal erase algorithm aut omatically pre-programs the memory cell which is not programmed and then executes th e erase operation. the K8P5516UZB has means to indicate the status of completion of program/erase operations. the status can be indicated via the ry/ by pin, data poll - ing of dq7, or the toggle bit (dq6). once the operations have bee n completed, the device automatically resets itself to the rea d mode. [table 4] operations table l = v il (low), h = v ih (high), a in = address in, d in = data in, d out = data out, x = don't care. note : 1) wp /acc must be v ih when writing on the outermost block. (ba0 or ba255) 2) address for word mode is amax:0. address for byte mode is amax:a-1. operation ce oe we wp /acc a0(a-1) ~ a23 dq0 ~ dq7 dq8 ~ dq15 reset byte = v ih byte = v il read l l h x a in dout dout dq8 ~ 14 = high-z dq15 = a-1 h stand-by vcc 0.3v x x h x high-z high-z high-z vcc 0.3v output disable l h h x x high-z high-z high-z h reset x x x x x high-z high-z high-z l write l h l x 1) a in din din dq8 ~ 14 = high-z dq15 = a-1 h
- 11 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 9.0 command definitions the K8P5516UZB operates by selecting and ex ecuting its operational modes. each operational mode has its own command set. in ord er to select a cer - tain mode, a proper command with specific address and data sequenc es must be written into the command register. writing incorre ct information which include address and data or writing an improper command will reset the device to the read mode. the defined valid register comm and sequences are stated in table 5. [table 5] command sequences (x16) command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle read addr 1 r a data rd reset addr 1 xxxh data f0h autoselect manufacturer id 1), 2) addr 4 555h 2aah 555h x00h data aah 55h 90h ech autoselect device id 1), 2), 3) addr 6 555h 2aah 555h x01h x0eh x0fh data aah 55h 90h 227eh 2264h 2260h autoselect block protect ver- ify 1), 2) addr 4 555h 2aah 555h ba / x02h data aah 55h 90h (see table 7) autoselect indicator bit 1), 2) addr 4 555h 2aah 555h x03h data aah 55h 90h (see table 7) autoselect master locking bit 1), 2) addr 4 555h 2aah 555h x07h data aah 55h 90h (see table 7) program addr 4 555h 2aah 555h pa data aah 55h a0h pd write to buffer 4) addr 6 555h 2aah ba ba wbl wbl data aah 55h 25h wc pd pd program buffer to flash addr 1 ba data 29h write to buffer abort reset 4) addr 3 555h 2aah 555h data aah 55h f0h unlock bypass addr 3 555h 2aah 555h data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass block erase addr 2 xxxh ba data 80h 30h unlock bypass chip erase addr 2 xxxh xxxh data 80h 10h unlock bypass reset addr 2 xxxh xxxh data 90h 00h chip erase addr 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase addr 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h block erase suspend 5), 6) addr 1 xxxh data b0h block erase resume addr 1 xxxh data 30h
command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle program suspend 7) ,8) addr 1 xxxh data b0h program resume addr 1 xxxh data 30h cfi query 9) addr 1 x55h data 98h enter otp block region addr 3 555h 2aah 555h data aah 55h 88h otp block program addr 4 555h 2aah 555h pa data aah 55h a0h pd otp block read addr 1 ra data rd exit otp block region addr 4 555h 2aah 555h xxxh data aah 55h 90h 00h - 12 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 note : x ra : read address, pa : program address, rd : read data, pd : program data, wbl : write buffer location x ba : block address (a16 - a23), abp : address of the block to be protected or unprotected, x = don?t care . x dq 8 - dq15 are don?t care in command sequence, except for rd and pd x a 14 - a23 are also don?t care, except for the case of special notice. 1) to terminate the autoselect mode, it is necessary to write reset command to the register. 2) the 4th cycle data of autoselect mode is output data. 3) device id must be read across cycles 4, 5 and 6. device id data : x0eh = "2264h", x0fh = "2260h" for 256mb uniform block device 4) command sequence resets device for next command after write-to-buffer operation. 5) the read / program operations at non-erasing blocks and t he autoselect mode are allowed in the erase suspend mode. 6) the erase suspend command is applic able only to the block erase operation. 7) the read operation is allowed in the program suspend mode. 8) the program suspend command is applicable to program and erase suspend - program operation. 9) command is valid when the device is in read mode or autoselect mode.
- 13 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 6] table 5 : command sequences (x8) command sequence cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle read addr 1 r a data rd reset addr 1 xxxh data f0h autoselect manufacturer id 1), 2) addr 4 aaah 555h aaah x00h data aah 55h 90h ech autoselect device id 1), 2), 3) addr 6 aaah 555h aaah x02h x1ch x1eh data aah 55h 90h xx7eh xx64h xx60h autoselect block protect ver- ify 1), 2) addr 4 aaah 555h aaah ba / x04h data aah 55h 90h (see table 7) autoselect indicator bit 1), 2) addr 4 aaah 555h aaah x06h data aah 55h 90h (see table 7) program addr 4 aaah 555h aaah pa data aah 55h a0h pd write to buffer 4) addr 6 aaah 555h ba ba wbl wbl data aah 55h 25h wc pd pd program buffer to flash addr 1 ba data 29h write to buffer abort reset 4) addr 3 aaah 555h 555h data aah 55h f0h unlock bypass addr 3 aaah 555h aaah data aah 55h 20h unlock bypass program addr 2 xxxh pa data a0h pd unlock bypass block erase addr 2 xxxh ba data 80h 30h unlock bypass chip erase addr 2 xxxh xxxh data 80h 10h unlock bypass reset addr 2 xxxh xxxh data 90h 00h chip erase addr 6 aaah 555h aaah aaah 555h aaah data aah 55h 80h aah 55h 10h block erase addr 6 aaah 555h aaah aaah 555h ba data aah 55h 80h aah 55h 30h block erase suspend 5), 6) addr 1 xxxh data b0h block erase resume addr 1 xxxh data 30h
command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle program suspend 7) ,8) addr 1 xxxh data b0h program resume addr 1 xxxh data 30h cfi query 9) addr 1 aah data 98h enter otp block region addr 3 aaah 555h aaah data aah 55h 88h otp block program addr 4 aaah 555h aaah pa data aah 55h a0h pd otp block read addr 1 ra data rd exit otp block region addr 4 aaah 555h aaah xxxh data aah 55h 90h 00h - 14 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 note : x ra : read address, pa : program address, rd : read data, pd : program data, wbl : write buffer location x ba : block address (a16 - a23), abp : address of the block to be protected or unprotected, x = don?t care . x dq 8 - dq15 are don?t care in command sequence, except for rd and pd x a 14 - a23 are also don?t care, except for the case of special notice. 1) to terminate the autoselect mode, it is necessary to write reset command to the register. 2) the 4th cycle data of autoselect mode is output data. 3) device id must be read across cycles 4, 5 and 6. device id data : x0eh = "2264h", x0fh = "2260h" for 256mb top and boot block device 4) command sequence resets device for next command after write-to-buffer operation. 5) the read / program operations at non-erasing blocks and t he autoselect mode are allowed in the erase suspend mode. 6) the erase suspend command is applic able only to the block erase operation. 7) the read operation is allowed in the program suspend mode. 8) the program suspend command is applicable to program and erase suspend - program operation. 9) command is valid when the device is in read mode or autoselect mode.
- 15 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 7] K8P5516UZB autoselect codes note : 1) l=logic low=v il , h=logic high=v ih , vid = 8.5v to 9.5v, ba=block address, x=don?t care . outermost block : ba255 or ba000 ce oe we a23 - a16 a15 - a10 a8 ~ a7 a6 a5 ~ a4 a3 a2 a1 a0 dq15 - dq8 dq7 - dq0 byte = v ih byte = v il manufacturer id l l h x x x l x llll x ech device id read cycle1 l lh x x xlxlllh 22h 7eh read cycle2 l l h x x x l x h h h l 22h 64h read cycle3 l l h x x x l xhhhh 22h 60h block protection verification llh ba x xlxllhl x 01h : (protected : either dyb or ppb locked) indicator bit(2) l l h x x x l x l l h h x 99h : factory locked, highest block conrolled by wp 19h : not factory locked, high- est block conrolled by wp 89h : factory locked, lowest block conrolled by wp 09h : not factory locked, low- est block conrolled by wp dq7 : factory lock bit master locking bit indicator bit l l h ba x l l l lhhh x 01h : protected, 00h : unprotected
- 16 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 10.0 device operation 10.1 read mode the K8P5516UZB is controlled by chip enable ( ce ), output enable ( oe ) and write enable ( we ). when ce and oe are low and we is high, the data stored at the specified address location,will be the output of the device. the outputs are in high impedance state whenever ce or oe is high. the K8P5516UZB is available for 8-word page mode. page mode provides fast access time for high performance system. after address access time(taa), eight data words are loaded into an inter nal page buffer. a0 (a-1 in byte mode)~a2 bits determi ne which page word is output during a read operation. a3~a23 bits must be stable thro ughout the page read access. figur e 13 shows the asynchronous p age read more timing. 10.2 standby mode the K8P5516UZB features stand-by mode to reduce power consumpti on. this mode puts the device on hold when the device is deselec ted by making ce high ( ce = v ih ). refer to the dc characteristics for more details on stand-by modes. 10.3 output disable the device outputs are disabled when oe is high ( oe = v ih ). the output pins are in high impedance state. 10.4 automatic sleep mode the K8P5516UZB features automatic sleep mode to minimize the device power consumption. when addresses remain steady for t aa +30ns, the device automatically activates the automatic sleep mode. in the sleep mode, output data is latched and always available to the system. when addresses are changed, the device provides new data without wait time. data outputs t aa + 30ns data auto sleep mode address data data data data figure 1: auto sleep mode operation 10.5 autoselect mode the K8P5516UZB offers the autoselect mode to identify manufacturer, device type and block protection verification by reading a binary code. the autoselect mode allows programming equipment to automatically match the device to be programmed with its corresponding programm ing algorithm. the manufacturer, device code ,block protec tion verification and indicator bit can be read via the command register. the comman d sequence is shown in table 6 and figure 2. in addition, below table 7 shows indicator bit in detail. the autoselect operation of block protection ve rification is init iated by first writing two unlock cycle. to terminate the autoselect operation, write reset command (f0h) into the command register. note : to access the autoselect codes, the host system must issue the autoselect command. the autoselect command sequence can be wr itten to an address within a device that is either in the read or erase-suspend-read mode. the autoselect command cannot be written while the device is actively pr ogramming or erasing. autoselect does not support page modes. the system must write the reset command to return to the read mode (or erase-suspend read mode if the devic e was previously in erase suspend). [table 8] indicator bit codes . description dq15 to dq8 dq7 dq6 to dq5 dq4 dq3 dq2 dq1 dq0 indicator bit l 1=factory-locked 0=not locked l 0 = wp protects block 255 1 = wp protects block 0 hllh
we 555h 2aah 555h aah 55h 90h 00h 01h ech manufacturer id device id address dq15 a dq0 ( K8P5516UZB ) 227eh 0eh 2264h 0fh 2260h - 17 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 note : please refer to table 6 for device code. figure 2: autoselect operation (by command sequence method) 10.6 write (program/erase) mode the K8P5516UZB executes its program/erase operations by writing commands into the command register. in order to write the comma nds to the register, ce and we must be low and oe must be high. addresses are latched on the falling edge of ce or we (whichever occurs last) and the data are latched on the rising edge of ce or we (whichever occurs first). the device uses standard microprocessor write timing. 10.6.1 program the K8P5516UZB can be programmed in units of a word. programming is writing 0's into the memory array by executing the interna l program routine. in order to perform the internal program routine, a four-cyc le command sequence is necessary. t he first two cycles are unlock c ycles. the third cycle is assigned for the program setup command. in the last cycle, the address of the memory location and the data to be programmed at that location are writ - ten. the device automatically generates adequate program pulses and veri fies the programmed cell margin by the internal program routine. during the execution of the routine, the system is not r equired to provide further controls or timings. during the internal program routine, commands written to the dev ice will be ignored. note that a hardware reset during a progra m operation will cause data corruption at the corresponding location. we 555h 2aah 555h aah 55h a0h program program program start dq15-dq0 address data ry/by address figure 3: program command sequence
- 18 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 in accross block boundaries and any sequence programming is allowed. a bit cannot be programmed from ?0? back to ?1?. if attemp ting to do, it may cause that device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeedin g read will show that the data is still ?0?. only erase operat ions can convert a ?0? to a ?1?. 10.6.2 writer buffer programming write buffer programming allows the system write to a maximum of 32 words in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is in iti-ated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the block address in which programming will occur. the fourth cycle writes the block address and the number of word locations, minus one, to be programmed. for example, if the system will program 19 unique address locations, then 12h should be written to the device. this tell s the device how many write buffer addresses will be loaded with data. the number of loca - tions to program cannot exceed the size of the write buffer or the oper ation will abort. the fifth cycle writes the first addre ss location and data to be pro - grammed. t he write-buffer-page is selected by address bits a23(max.) ~ a5 entered at fifth cycle . all subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit a23(max.) ~ a5 as those entered at fifth cycle. write buffer locations may be loaded in any order. once the specified number of write buffer locations have been loaded, the system must then write the "program buffer to flash" com mand at the block address. any other command address/data combination aborts the wr ite buffer programming operation. the device then begins progr amming. data poll - ing should be used while monitoring the last address location load ed into the write buffer. dq7, dq6, dq5, and dq1 can be monit ored to determine the device status during write buffer programming. the write-buff er programming operation can be suspended using the standard progr am suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command . note also that an address loaction cannot be loaded more than once into the write-buffer-page. we 555h 2aah aah 55h 25h program start dq15-dq0 wbl 12h pd 29h ry/by address block address block address block address wbl pd | | | | figure 4: write buffer program command sequence the write buffer programming sequence can be aborted in the following ways: x lo ading a value that is greater than the buffer size(32-wo rd) during then number of word locations to program step. (in case, wc > 1fh @table6) x t he number of program address/data pairs entered is different to the number of word locations initially defined with wc (@tab le 5) x w riting a program address to have a different write-buffer-page with selected write-buffer-page ( address bits a23(max) ~ a5 are different) x w riting non-exact "program buffer to flash" command the abort condition is indicated by dq1 = 1, dq7 = data (for the last address location loaded), dq6 = toggle, and dq5=0. a "write-to-buffer-abort reset" command sequence must be written to reset the device for t he next operation. note that the third cycle of write-to-buffe r-abort reset command sequence is required when using write-buffer-pr ogramming features in unlock bypass mode. and from the third cycle to the last cycle of write to buffer command is also required when us ing write-buffer-programming feat ures in unlock bypass mode.
- 19 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 10.6.3 accelerated program operation accelerated program operation reduces the program time through th e acc function. this is one of two functions provided by the wp /acc pin. when the wp /acc pin is asserted as v hh , the device automatically enters t he unlock bypass mode, and reduces t he program operation time. removing v hh from the wp /acc pin returns the device to normal operation. blocks must be unprotected before raising wp /acc to v hh . recommend that the wp /acc pin must not be asserted at v hh except on accelerated program operation, or the device may be damaged. in addition, the wp /acc pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction. single word accelerated program operation the system would use two-cycle program s equence (one-cycle (xxx - a0h) is for single word program command, and next one-cycle ( pa - pd) is for program address and data ). accelerated write buffer programming in accelerated write buffer program mode, the system must enter "write to buffer" and "program buffer to flash" command sequen ce to be same as them of normal write buffer programming and only can reduce the pr ogram time. note that the third cycle of "write to buffer abo rt reset" command sequence is required in an accelerated mode. when the wp /acc pin is asserted as v hh , the device automatically enters t he unlock bypass mode, and reduces the program operation time. removing v hh from the wp /acc pin returns the device to normal operation. ? program/erase cycling must be limited below 100cycles for optimum performance. ? ambient temperature requirements : t a = 30 c10 c ? the device automatically generates adequate program pulses and ignores other command after program command
- 20 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 10.6.4 unlock bypass the K8P5516UZB provides the unloc k bypass mode to save its operation time. this mode is possible for pr ogram, cfi, block erase and chip erase oper - ation. there are two methods to enter the unlock bypass mode. the mode is invoked by the unloc k bypass command sequence. unlike the standard pro - gram/erase command sequence that contains four to six bus cycles, the unlock bypass program/erase command sequence comprises on ly two bus cycles. the unlock bypass mode is engaged by issuing the unlock by pass command sequence which is co mprised of three bus cycles. writing first two unlock cycles is foll owed by a third cycle containing the unlock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. the unlock bypass progr am command sequence is comprised of only two bus cycles; wr iting the unlock bypass program command (a0h) is followed by the program addr ess and data. this command sequence is the only valid one for progr amming the device in the unlock bypass mode. the unlock bypass cfi command sequenc e is comprised of only one bus cy cle; writing the unlock bypass program command (98h). this command sequence is the only valid one for programmi ng the device in the unlock bypass mode. also, the unlock bypas s erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80h-30h) or writing the unlock bypass ch ip erase com - mand(80h-10h). this command sequences are t he only valid ones for erasing the device in the unlock bypass mode. the unlock bypa ss reset command sequence is the only valid co mmand sequence to exit the unlock bypass mode. th e unlock bypass reset command sequence consists o f two bus cycles. the first cycle must contain the data (90h). the second cycle co ntains only the data (00h). then, the device returns to the rea d mode. 10.6.5 chip erase to erase a chip is to write 1 c s into the entire memory array by executing the internal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is wr itten after first two "unlock" cycles. t hen, there are two more write cycles pr ior to writing the chip erase command. the internal erase routine automatically pre-progr ams and verifies the entire memory for an all zero data pattern prior to erasing. the automatic erase begins on the rising edge of the last we or ce pulse in the command sequence and terminates w hen dq7 is "1". after that the device returns to the read mode. we 555h 2aah 555h aah 55h 80h 555h chip erase start dq15-dq0 2aah aah 55h 10h ry/by 555h address figure 5: chip erase command sequence 10.6.6 block erase to erase a block is to write 1 c s into the desired memory block by executing the internal erase routine. the block erase requi res six bus cycles to write the command sequence shown in table 5. after the first two "unlock" cycles, the erase set up command (80h) is written at the third c ycle. then there are two more "unlock" cycles followed by the bl ock erase command. the internal erase routine automatically pre-programs and verifies th e entire memory prior to erasing it. the block address is latched on the falling edge of we or ce , while the block erase command is latched on the rising edge of we or ce . multiple blocks can be erased sequentially by writing the six bus-cycle. upon completion of the last cycle for the block erase, additional block address and the block erase command (30h) can be written to perform the mu lti-block erase. an 50us (typical) "time window" is required between the block erase command writes. the block erase command must be written wi thin the 50us "time window", otherwise the block erase command will be ignored. the 50us "time window" is reset when the falling edge of the we occurs within the 50us of "time window" to latch the block erase command. during the 50us of "time window", any command other than the block erase or the erase suspend command written to the device will reset the device to read mode. after the 50us of "time window", the block erase command will in itiate the internal erase routine to erase the selected blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the er ase suspend command.
we 555h 2aah 555h aah 55h 80h 555h block erase start dq15-dq0 2aah block address aah 55h 30h ry/by address - 21 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 figure 6: block erase command sequence 10.7 erase suspend / resume the erase suspend command interrupts the block erase to read or prog ram data in a block that is not being erased. the erase sus pend command is only valid during the block erase operation including the time window of 50us. the er ase suspend command is not valid while the chip erase or the internal program routine sequence is running. when the erase suspend command is written durin g a block erase operation, the device r equires a maximum of 20us to suspend the erase operation. but, when the erase suspend command is written during the block eras e time window (50us) , the dev ice immediately terminates th e block erase time window and suspends the erase operation. after the erase operation has been suspended, the device is availble for reading or programming data in a block that is not bei ng erased. the system may also write the autoselect command sequence when the device is in the erase suspend mode. when the erase resume command is executed, the block erase operat io n will resume. when the erase suspend or erase resume comman d is exe - cuted, the addresses are in don't care state. while erase can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. in the erase suspend mode, protect/unprotect command is prohibited. we dq15-dq0 address 555h block address aah 30h xxxh erase resume xxxh b0h 30h erase suspend block erase start block erase command sequence figure 7: erase suspend/resume command sequence 10.8 program suspend / resume the program suspend command interrupts the program operation. also the program suspend command interrupts the program operation during erase suspend mode. the read operation is available only during program suspend. when the pr ogram suspend command is written during a program oper - ation, the device requires a maximum of 10us to suspend the program operation. the system may also write the autoselect command sequence when the device is in the program suspend mode. when the program resume command is executed, the program operation will resume. when the program suspend or program resume command is executed, the addresses are in don't care state. while program can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. in the program suspend mode, protect/unprotect command is prohibited.
- 22 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 10.9 write protect ( wp ) the wp /acc pin has two useful functions. the one is that certain block is protected by the hardware method not to use v id . the other is that program operation is accelerated to reduce the program time (refer to accelerated program operation paragraph). when the wp /acc pin is asserted at vil, the device can not perform progra m and erase operation in the outermost 64 kword block (ba255 or ba0) on end of the flash array independently of whether that block was protected or unprotected. the write protected blocks can only be read. this is useful method to preserve an important program data. when the wp /acc pin is asserted at v ih , the device reverts the outermost 64kword block on an end to default protection state. note that the wp /acc pin must not be at v hh , for operations other than accelerated programming, or device damage may result. 10.10 software reset the reset command provides that the device is reseted to read mode or erase-suspend-read mode. the addresses are in don't care state. the reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequen ce before pro - gramming begins. this resets the device in which was operating to read mode. if the device is be erasing or programming, the re set command is invalid until the operation is completed. also, the reset command is valid between the sequence cycles in an autoselect command sequenc e. in the autoselect mode, the reset command returns the device to read mode. if a devi ce entered the autoselect mode in the erase suspend mode, th e reset command returns the device to erase-suspend-read mode. if dq5 is high on er ase or program operation, the reset command return the devic e to read mode or erase-suspend-read mode if the device was in the erase suspend state. 10.11 hardware reset the K8P5516UZB offers a reset feature by driving the reset pin to v il . when the reset pin is held low(v il ) for at least a period of t rp , the device immediatley terminates any operation in progress, tristates all outputs, and ignores all read/write commands for duration of th e reset pulse. the device also resets the internal state machine to asynchronous read mode. if a hardware reset occurs during a program operation, the da ta at that particular loca - tion will be lost. once the reset pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. also, note that all the data output pins are tri-stated for the duration of the reset pulse. the reset pin may be tied to the system reset pin. if a system reset occurs dur - ing the internal program and erase routi ne, the device will be automatically reset to the read mode ; this will enable the syst ems microprocessor to read the boot-up firmware from the flash memory.
- 23 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 10.12 power-up protection to avoid initiation of a write cycle during vcc power-up, reset low must be asserted during power-up. after reset goes high, the device is reset to the read mode. 10.13 low vcc write inhibit to avoid initiation of a write cycle dur ing vcc power-up and power-down, a write cycle is locked out for vcc less than 2.3v. if vcc < v lko (lock-out volt - age), the command register and all internal program/erase circuits are disabled. under this conditi on the device will reset its elf to the read mode. subse - quent writes will be ignored until the vcc level is greater than v lko . it is the user s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when vcc is above 2.3v. 10.14 write pulse glitch protection noise pulses of less than 5ns(typical) on ce , oe , or we will not initiate a write cycle. 10.15 logical inhibit writing is inhibited under any one of the following conditions : oe = v il , ce = v ih or we = v ih . to initiate a write, ce and we must be "0", while oe is "1".
- 24 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 11.0 common flash memory interface common flash momory interface is contrived to increase the compatibility of host syst em software. it provides the specific inf ormation of the device, such as memory size, word configuration, and electrical feat ures. once this information has been obtained, the system software will know which com - mand sets to use to enable flash writes, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h in word mode, the device enters the cfi mode. and then if the syste m writes the address shown in table 11, the system can read the cfi data. qu ery data are always presented on the lowest-order data outputs(d q0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to termi nate this operation, the system must write the reset command. 12.0 otp block region the otp block feature provides a 256-word flash memory region that enables permanent part identification through an electronic serial number (esn). the otp block is customer lockable and shipped with itself unlocke d, allowing customers to untilize the that block in any manne r they choose. indicator bit dq6 are used to indicate the factory-locked of the part. the dq7 is "1" for factory locked. the system accesses the otp block thr ough a command sequence (see "enter otp bloc k / exit otp block command sequence" at table 5 on page 11 ). after the system has written the "enter otp block" comm and sequence, it may read the otp block by using the addresses (000000h~0000ffh) normally and may check the protection verify bit (dq7) by using the "autoselec t indicator bit" command sequen ce with otp block address. this mode of operation continues un til the system issues the "exit otp bloc k" command suquence, a hardware reset or un til power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to main blocks. note that t he accelerated function and unlock bypass modes are not avai lable when the otp block is enabled. 12.1 otp block protection in a customer lockable device, the otp bl ock is one-time programmable and can be lo cked only once. locking operation to the otp block is started by writing the "enter otp block lock register region" command sequenc e, and then the "otp block lock register bit program" command sqeunce (table 5) with data that have zero(setting to 0) in dq0. note that the other dqs except dq0 will be ignored. the locking operat ion has to be above 100us. after that timing, "exit otp block lock register region" command sequence or hard ware reset must be issued in order to e xit otp block mode and revert the device to read mode in main array. ? the otp block lock operation must be used with caution since, once locked, there is no procedure available for unlocking and n one of the bits in the otp block space can be modified in any way. ? suspend and resume operation are not supported during otp protect, nor is otp protect supported during any suspend operation.
- 25 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 13.0 enhanced block protection / unprotection the enhanced block protection / unprotection feature disables or enables programming or erase operations in any or all blocks a nd can be implemented through software and/or hardware methods, which are independent of each other. lock register (one time programmable) password method (dq2) persistent method (dq1) 64-bit password (one time protect) ppb lock bit 1),2),3) 0 = ppbs locked 1 = ppbs unlocked dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 7),8),9) ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent block 0 block 1 block 2 block n-2 block n-1 block n 4) memory array protection bit (ppb) 5),6) software methods hardware methods #wp = vil (highest or lowest block locked) note : 1) bit is volatile, and defaults to 1 on reset. 2) programming to 0 locks all ppbs to their current state. 3) once programmed to 0, requires hardware reset to unlock. 4) n = highest address block. 5) 0 = sector protected,1 = sector unprotected. 6) ppbs programmed individually, but cleared collectively. 7) 0 = sector protected,1 = sector unprotected. 8) protect effective only if ppb lock bit is un locked and corresponding ppb is 1 (unprotected). 9) volatile bits: defaults to user choice upon power-up (see ordering options). figure 8: enhanced block protection / unprotection
- 26 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 13.1 block protection 13.1.1 lock register as shipped from the factory, all devices default to the persistent mode when power is applied, and all blocks are unprotected. (dyb is default to clear sta - tus : unprotected) for dyb set (protected status) in default, cont act your local sales office for details. the device programme r or host system must then choose which block protection method to use. programming (setting to 0) any one of th e following two one-time programmable, non -volatile bits locks the part permanently in that mode: - lock register persistent protection mode lock bit (dq1) - lock register password protection mode lock bit (dq2) [table 9] lock register . note : 1) if the password mode is chosen, the password must be programmed before setting the corresponding lock register bit. 2) after the lock register bits command set entry command sequence is written, reads and writes for block 0 are disabled, while reads from other blocks are allowed until exit - ing this mode. 3) if both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 4) once the password mode lock bit is programmed, the persistent mode lock bit is permanently disabled, and no changes to the p rotection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. after selecting a block protection me thod, each block can operate in any of the following three states: 1. constantly locked. the selected blocks are protected and c annot be reprogrammed unless ppb lock bit is cleared via a passwor d, hardware reset, or power cycle. 2. dynamically locked. the select ed blocks are protected and can be altered via software commands. 3. unlocked. the blocks are unprotected and can be erased and/or programmed. 13.2 persistent protection bits the persistent protection bits are unique and nonvolatile for eac h block and have the same endurances as the flash memory. prep rogramming and ver - ification prior to erasure are handled by the device, and therefore do not require system monitoring. note : 1) each ppb is individually programmed and all are erased in parallel. 2) entry command disables reads and writes for the block selected. 3) reads within that block 0 return the ppb status for that block. 4) read and write from other blocks than block 0 are allowed. 5) all reads must be performed using the asynchronous mode. 6) the specific block addresses (a23~a16) are wr itten at the same time as the program command. 7) if the ppb lock bit is set, the ppb program or erase comm and does not execute and timesout without programming or erasing th e ppb. 8) there are no means for individually er asing a specific ppb and no specific bl ock address is required for this operation. 9) exit command must be issued after the execution which resets the device to read m ode and re-enables reads and writes for blo ck 0. 10) the programming state of the ppb for a given block can be ve rified by writing a ppb status r ead command to the device as de scribed by the flow chart below. device dq15 to dq4 dq3 dq2 dq1 dq0 K8P5516UZB don?t care ppb one-time programmable bit 0 = all ppb erase command disabled 1 = all ppb erase command enabled password protection mode lock bit persistent protection mode lock bit otp block protection bit
- 27 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 13.3 dynamic protection bits dynamic protection bits are volatile an d unique for each block and can be individually modified. dybs only control the protecti on scheme for unprotected blocks that have their ppbs cleared (erased to 1). by issuing the dyb set or clear command sequences, the dybs are set (program med to 0) or cleared (erased to 1), thus placing each block in the protected or unprotected state respective ly. this feature allows software to easi ly protect blocks against inad - vertent changes yet does not prevent the easy removal of protection when changes are needed. note : 1) the dybs can be set (programmed to 0) or cleared (erased to 1) as often as needed. when the parts are first shipped, the ppb s are cleared (erased to 1) and upon power up or reset, the dybs is cleared. for dyb set (protected status) in default, contact your local sales office for details. 2) if the option to clear the dybs afte r power up is chosen, (erased to 1), then the blocks maybe modified depending upon the p pb state of that block. 3) the blocks would be in the protected state if the option to set the dybs after power up is chosen (programmed to 0). 4) it is possible to have blocks that are persistently locked with blocks that are left in the dynamic state. 5) the dyb set or clear commands for the dy namic blocks signify protected or unprotected state of th e blocks respectively. howe ver, if there is a need to change the status of the persistently locked blocks, a few more steps are required. first, the ppb lock bit must be cleared by either putting the de vice through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again locks the ppbs, and the device op erates normally again. 6) to achieve the best protection, it is recommended to execut e the ppb lock bit set command early in the boot code and protect the boot code by holding wp# = vil. note that the ppb and dyb bits have the same function when wp /acc = vhh as they do when wp /acc = vih. 13.4 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all blocks. when se t (programmed to 0), this bit locks all ppb and when cleared (pro - grammed to 1), unlocks each block. t here is only one ppb lock bit per device. note : 1) no software command sequence unlocks this bit unless the device is in the password protection mode; only a hardware reset or a power-up clears this bit. 2) the ppb lock bit must be set (programmed to 0) only after all ppbs are configured to the desired settings. 13.5 password protection method the password protection method allows an even hi gher level of security than the persis tent block protection mode by requiring a 64-bit password for unlocking the device ppb lock bit. in addition to this password requirement, after power up and reset, the ppb lock bit is set 0 to maintain the password mode of operation. successful execution of the password unlo ck command by entering the entire password clears the ppb lock bit, allowing for block ppbs modifications. note : 1) there is no special addressing order required for programming the password. once the password is written and verified, the p assword mode locking bit must be set to pre - vent access. 2) the password program command is only capable of programming 0s. programming a 1 after a cell is programmed as a 0 results in a time-out with the cell as a 0. 3) the password is all 1s when shipped from the factory. 4) all 64-bit password combinations are valid as a password. 5) there is no means to verify what the password is after it is set. 6) the password mode lock bit, once set, prevents reading t he 64-bit password on the data bus and further password programming. 7) the password mode lock bit is not erasable. 8) the lower two address bits (a1~ a0(a-1 in byte mode)) are valid during the password read, password program, and password unl ock. 9) the exact password must be entered in order for the unlocking function to occur. 10) the password unlock command cannot be issued any faster than 1us at a time to prevent a hacker from running through all the 64-bit combinations in an attempt to cor - rectly match a password. 11) approximately 1us is required for unlocking the device after the valid 64-bit password is given to the device. 12) password verification is only allowed during the password programming operation. 13) all further commands to the password region are disabled and all operations are ignored. 14) if the password is lost after setting the password mode lock bit, there is no way to clear the ppb lock bit. 15) entry command sequence must be issued prior to any of any oper ation and it disables reads and writes for block 0. reads and writes for other blocks excluding block 0 are allowed. 16) if the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. 17) a program or erase command to a protected block enables st atus polling and returns to read mode without having modified the contents of the protected block. 18) the programming of the dyb, ppb, and ppb lock for a given block can be verified by writing individual status read commands dyb status, ppb status, and ppb lock sta - tus to the device.
- 28 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 13.6 master locking bit set this master locking bit can ensure that protected blocks be permanently unalterable. master locking bit is non-volatile bit. master locking bit controls prote ction status of entire bl ocks that is protected by ppb . to make permanent protection block, ppb sho uld be protected first. the usage of the master locking bit command sequ ence is absolutely required to ensure fu ll protection of data from future alter ations. if master locking bit is set ("0"), entire blocks that were protected by ppb are permanently protected. they are not changed and altered by any futur e lock/unlock commands. anyone who uses this fuction needs much att ention. because there is no way to return to unlock status. default status of master locking bit is unlock sta - tus("1"). if master locking bit sets on unprotected block, the block still are remain ing in status of unprotected block. additionally the unprotected block can be protected by ppb pr ogram command. and the n the bl ock is protected permanently. no yes write unlock cycles: address 555h, data aah address 2aah, data 55h unlock cycle 1 unlock cycle 2 write enter lock register command: address 555h, data 40h program lock register data address xxxh, data a0h address 00h, data pd wait 4us perform polling algorithm (see write operation status flowchart) done? dq5=1? pass. write lock register exit command: address xxxh, data 90h address xxxh, data 00h device returns to reading array. fail. write rest command to return to reading array. no xxxh = address don?t care program data (pd): see text for lock register definitions caution: lock data may only be progammed once. error condition (exceeded timing limits) yes figure 9: lock register program algorithm
- 29 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 10] block protection examples unique device ppb lock bit 0 = locked, 1 = unlocked block ppb 0 = protected block dyb 0 = protected block protection status any block 0 0 x protected through ppb any block 0 0 x protected through ppb any block 0 1 1 unprotected any block 0 1 0 protected through dyb any block 1 0 x protected through ppb any block 1 0 x protected through ppb any block 1 1 0 protected through dyb any block 1 1 1 unprotected
- 30 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 11] block protection commands (x16) command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle 7th cycle enter lock register region 25) addr 3 555h 2aah 555h data aah 55h 40h lock register bit read addr 1 00h data rd lock register bit program 26) addr 2 xxxh xxxh data a0h data exit lock register region 27) addr 2 xxxh xxxh data 90h 00h password protection command set entry 25) addr 3 555h 2aah 555h data aah 55h 60h password program addr 2 xxxh pwa0/ pwa1/ pwa2/ data a0h pwd0/ pwd1 /pwd2/ password read addr 4 00h 01h 02h 03h data pwd0 pwd1 pwd2 pwd3 password unlock addr 7 00h 00h 00h 01h 02h 03h 00h data 25h 03h pwd0 pwd1 pwd2 pwd3 29h password protection command set exit 27) addr 2 xxxh xxxh data 90h 00h ppb block protection command set entry 25) addr 3 555h 2aah 555h data aah 55h c0h ppb program addr 2 xxxh ba data a0h 00h all ppb erase 22) addr 2 xxxh 00h data 80h 30h ppb status read addr 1 ba data rd(0) ppb block protection command set exit 27) addr 2 xxxh xxxh data 90h 00h ppb lock bit command set entry 25) addr 3 555h 2aah 555h data aah 55h 50h ppb lock bit set addr 2 xxxh xxxh data a0h 00h ppb lock bit status read addr 1 xxxh data rd(0) ppb lock bit command set exit 27) addr 2 xxxh xxxh data 90h 00h dyb command set entry 25) addr 3 555h 2aah 555h data aah 55h e0h dyb set addr 2 xxxh ba data a0h 00h dyb clear addr 2 xxxh ba data a0h 01h dyb status read addr 1 ba data rd(0) dyb command set exit 28) addr 2 xxxh xxxh data 90h 00h master locking bit set addr 3 555h 2aah 555h data aah 55h f1h
- 31 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 note : ? ra : read address, pa : program address, rd : read data, pd : program data, wbl : write buffer location ? ba : block address (a16 - a23), abp : address of the block to be protected or unprotected, x = don?t care . ? dq8 - dq15 are don?t care in command sequence, except for rd and pd ? a14 - a23 are also don?t care, except for the case of special notice. ? wc = word count. number of write buffer locations to load minus 1. ? pwa3 ~ pwa0 = password address. pwd3 ~ pwd0 = password data. pd3 ~ pd0 present four 16 bit combinations that represent the 64-bit password ? rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. 1) see bus operations description 2) all values are in hexadecimal. 3) except for the following, all bus cycles are write cycle: r ead cycle, fourth through sixth cycles of the autoselect commands , and password verify commands, and any cycle reading at rd(0) and rd(1). 4) data bits dq15 ~ dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ~ pwd0. 5) unless otherwise noted, these address bits are don?t cares: (a23 ~ a14) 6) writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7) no unlock or command cycles required when reading array data. 8) the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase susp end) when the deviceis in the autoselect mode, or if dq5 goes high (while the device is provid ing status information) or performing block lock/unlock. 9) the fourth cycle of the autoselect comm and sequence is a read cycle. see autoselect. 10) the data is 0000h for an unlocked block and 0001h for a locked block. 11) device id data : x0eh = "2264h", x0fh = "2260h" for 256mb uniform block device 12) see autoselect. 13) the unlock bypass command sequence is required prior to this command sequence. 14) the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode.th e system may read and program in non- erasing blocks, or enter the autoselect mo de, when in the erase suspend mode. the er ase suspend command is valid only during a block erase operation. 15) the erase resume command is valid only during the erase suspend mode. 16) command is valid when device is ready to read array data or when device is in autoselect mode. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 17) the entire four bus-cycle sequence must be entered for which portion of the password. 18) the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode.th e system may read and program in non- erasing blocks, or enter the autoselect mo de, when in the erase suspend mode. the er ase suspend command is valid only during a block erase operation. 19) the erase resume command is valid only during the erase suspend mode. 20) command is valid when device is ready to read array data or when device is in autoselect mode. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 21) the entire four bus-cycle sequence must be entered for which portion of the password. 22) the all ppb erase command pre-programs all ppbs before erasure to prevent over-erasure of ppbs. 23) wp /acc must be at vhh during the entire operation of this command. 24) command sequence resets device for next command after write-to-buffer operation. 25) entry commands are needed to enter a specific mode to enable instructions only available within that mode. 26) if both the persistent protection mode locking bit and the password protection mode locking bit are set a the same time, th e command operation aborts and returns the device to the default persistent block protection mode. 27) the exit command must be issued to reset the bloc k 0 of device into read mode. otherwise the device hangs. 28) the exit command must be issued to reset device into read mode. otherwise the device hangs.
- 32 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 12] block protection commands (x8) command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle 7th cycle enter lock register region 25) addr 3 aaah 555h aaah data aah 55h 40h lock register bit read addr 1 00h data rd lock register bit program 26) addr 2 xxxh xxxh data a0h data exit lock register region 27) addr 2 xxxh xxxh data 90h 00h password protection command set entry 25) addr 3 aaah 555h aaah data aah 55h 60h password program addr 2 xxxh pwax data a0h pwdx password read addr 8 00h 01h 02h 03h 04h 05h 06h data pwd0 pwd1 pwd2 pwd3 pwd4 pwd5 pwd6 addr 07h data pwd7 password unlock addr 11 00h 00h 00h 01h 02h 03h 04h data 25h 03h pwd0 pwd1 pwd2 pwd3 pwd4 addr 05h 06h 07h 00h data pwd5 pwd6 pwd7 29 password protection command set exit 27) addr 2 xxxh xxxh data 90h 00h ppb block protection command set entry 25) addr 3 aaah 555h aaah data aah 55h c0h ppb program addr 2 xxxh ba data a0h 00h all ppb erase 22) addr 2 xxxh 00h data 80h 30h ppb status read addr 1 ba data rd(0) ppb block protection command set exit 27) addr 2 xxxh xxxh data 90h 00h ppb lock bit command set entry 25) addr 3 aaah 555h aaah data aah 55h 50h ppb lock bit set addr 2 xxxh xxxh data a0h 00h ppb lock bit status read addr 1 xxxh data rd(0) ppb lock bit command set exit 27) addr 2 xxxh xxxh data 90h 00h dyb command set entry 25) addr 3 aaah 555h aaah data aah 55h e0h dyb set addr 2 xxxh ba data a0h 00h dyb clear addr 2 xxxh ba data a0h 01h dyb status read addr 1 ba data rd(0) dyb command set exit 28) addr 2 xxxh xxxh data 90h 00h master locking bit set addr 3 aaah 555h aaah data aah 55h f1h
- 33 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 note : ? ra : read address, pa : program address, rd : read data, pd : program data, wbl : write buffer location ? ba : block address (a16 - a23), abp : address of the block to be protected or unprotected, x = don?t care . ? dq8 - dq15 are don?t care in command sequence, except for rd and pd ? a14 - a23 are also don?t care, except for the case of special notice. ? wc = word count. number of write buffer locations to load minus 1. ? pwa3 ~ pwa0 = password address. pwd7 ~ pwd0 = password word0, word1, word2, word3 pd3 ~ pd0 present four 16 bit combinat ions that represent the 64-bit password ? rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. 1) see bus operations description 2) all values are in hexadecimal. 3) except for the following, all bus cycles are write cycle: r ead cycle, fourth through sixth cycles of the autoselect commands , and password verify commands, and any cycle reading at rd(0) and rd(1). 4) data bits dq15 ~ dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3 ~ pwd0. 5) unless otherwise noted, these address bits are don?t cares: (a23 ~ a14) 6) writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7) no unlock or command cycles required when reading array data. 8) the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase susp end) when the device is in the autoselect mode, or if dq5 goes high (while the device is provid ing status information) or performing block lock/unlock. 9) the fourth cycle of the autoselect comm and sequence is a read cycle. see autoselect. 10) the data is 0000h for an unlocked block and 0001h for a locked block. 11) device id data : x0eh = "2264h", x0fh = "2260h" for 256mb uniform block device 12) see autoselect. 13) the unlock bypass command sequence is required prior to this command sequence. 14) the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode.th e system may read and program in non- erasing blocks, or enter the autoselect mo de, when in the erase suspend mode. the er ase suspend command is valid only during a block erase operation. 15) the erase resume command is valid only during the erase suspend mode. 16) command is valid when device is ready to read array data or when device is in autoselect mode. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 17) the entire four bus-cycle sequence must be entered for which portion of the password. 18) the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode.th e system may read and program in non- erasing blocks, or enter the autoselect mo de, when in the erase suspend mode. the er ase suspend command is valid only during a block erase operation. 19) the erase resume command is valid only during the erase suspend mode. 20) command is valid when device is ready to read array data or when device is in autoselect mode. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the maximum number of cycles in the command sequence is 37. 21) the entire four bus-cycle sequence must be entered for which portion of the password. 22) the all ppb erase command pre-programs all ppbs before erasure to prevent over-erasure of ppbs. 23) wp /acc must be at vhh during the entire operation of this command. 24) command sequence resets device for next command after write-to-buffer operation. 25) entry commands are needed to enter a specific mode to enable instructions only available within that mode. 26) if both the persistent protection mode locking bit and the password protection mode locking bit are set a the same time, th e command operation aborts and returns the device to the default persistent block protection mode. 27) the exit command must be issued to reset the bloc k 0 of device into read mode. otherwise the device hangs. 28) the exit command must be issued to reset device into read mode. otherwise the device hangs.
- 34 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 13] common flash memory interface code description addresses (word mode) addresses (byte mode) data query unique ascii string "qry" 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h primary oem command set 13h 14h 26h 28h 0002h 0000h address for primary extended table 15h 16h 2ah 2ch 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 2eh 30h 0000h 0000h address for alternate oem extended table (00h = none exists) 19h 1ah 32h 34h 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 36h 0027h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 38h 0036h vpp min. voltage(00h = no vpp pin present) 1dh 3ah 0000h vpp max. voltage(00h = no vpp pin present) 1eh 3ch 0000h typical timeout per single word write 2 n us 1fh 3eh 0006h typical timeout for min. size buffer write 2 n us(00h = not supported) 20h 40h 0006h typical timeout per individual block erase 2 n ms 21h 42h 0009h typical timeout for full chip erase 2 n ms(00h = not supported) 22h 44h 0013h max. timeout for word write 2 n times typical 23h 46h 0003h max. timeout for buffer write 2 n times typical 24h 48h 0005h max. timeout per individual block erase 2 n times typical 25h 4ah 0003h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 4ch 0002h device size = 2 n byte 27h 4eh 0019h flash device interface description 28h 29h 50h 52h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 54h 56h 0006h 0000h number of erase block regions within device 2ch 58h 0001h erase block region 1 information 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00ffh 0000h 0000h 0002h erase block region 2 information 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 3 information 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h
- 35 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 description addresses (word mode) addresses (byte mode) data query-unique ascii string "pri" 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h major version number, ascii 43h 86h 0031h minor version number, ascii 44h 88h 0033h address sensitive unlock(bits 1-0) 0 = required, 1= not required silcon revision number(bits 7-2) 45h 8ah 0014h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 8ch 0002h block protect 00 = not supported, 01 = supported 47h 8eh 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 90h 0000h block protect/unprotect scheme, 08 = enhanced block protection 49h 92h 0008h simultaneous operation 00 = not supported, xx = number of blocks except bank 0 4ah 94h 0000h burst mode type 00 = not supported, 01 = supported 4bh 96h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4ch 98h 0002h acc(acceleration) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4dh 9ah 0085h acc(acceleration) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 4eh 9ch 0095h wp protect 04 = uniform blocks bottom wp protect. 05 = uniform blocks top wp protect. 4fh 9eh 00xxh program suspend 00 = not supported. 01 = supported. 50h a0h 0001h
- 36 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 14.0 device status flags the K8P5516UZB has means to indicate its status of operation in the device where a program or er ase operation is in processes. the status is indicated by raising the device status flag vi a corresponding dq pins or the ry/ by pin. the corresponding dq pins are dq 7, dq6, dq5, dq3, dq2 and dq1. the statues are as follows : [table 14] hardware sequence flags note : 1) dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2) note that dq7 during write-to-buffer-programming indicates the data-bar for dq7 for the last loaded write-buffer address location. dq7 : data polling when an attempt to read the device is made while executing the inter nal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is completed an attempt to access to the device will produce the true data written to dq7 . when a user attempts to read the block being erased, dq7 will be low. if the device is placed in the erase/program suspend mode, the status can be d etected via the dq7 pin. if the system tries to read an address which belongs to a block that is being erase suspended, dq7 will be high. and, if the sy stem tries to read an address which belongs to a block that is being program suspended, the output will be the true data of dq7 itself. if a non-eras e-suspended or non-pro - gram-suspended block address is read, the devic e will produce the true data to dq7. if an attempt is made to program a protecte d block, dq7 outputs complements the data for approximately 1 s and the device then returns to the read mode without changing data in the block. if an attempt is made to erase a protected block, dq7 outputs complement data in approxi mately 100us and the device then returns to the read mode withou t erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or completed. once the device is at a busy st ate, dq6 will toggle. tog- gling dq6 will stop after the device completes its internal routi ne. if the device is in the erase/program suspend mode, an att empt to read an address that belongs to a block that is being eras ed or programmed will produce a high output of dq6. if an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at dq 6. if an attempt is made to program a protected block, dq6 to ggles for approximately 1us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a prote cted block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing the data in the block. status dq7 dq6 dq5 dq3 dq2 dq1 in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 1 erase suspend read erase suspended block 1100 toggle 1) 1 erase suspend read non-erase sus- pended block data data data data data data erase suspend program non-erase sus- pended block dq7 toggle 0 0 1 0 program suspend read program suspended block invalid invalid invalid invalid invalid invalid program suspend read non-program sus- pended block data data data data data data write to buffer 2) busy state dq7 toggle 0 0 no toggle 0 abort state dq7 toggle 0 0 no toggle 1
- 37 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time window expires. in this case, the internal erase routine will initiate the erase operat ion.therefore, the device will not accept further write commands until the erase operation is completed. dq3 is low if the block erase time window is not expired. within the block erase time window , an additional block er ase command (30h) can be accepted. to confirm that the block eras e command has been accepted, the software ma y check the status of dq3 following each block erase com - mand. dq2 : toggle bit 2 the device generates a toggling pulse in dq 2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase routine, dq2 toggles on ly if an erasing block is read. although the internal erase routine is in the exceede d time limits, dq2 toggles only if an erasing block in the exceeded time limits is read. when the device is in t he erase/program suspend mode, dq2 toggles only if an address in the erasing or programming block is read. if a non-erasing or no n-programmed block address is r ead during the erase/program sus pend mode, then dq2 will produce valid data. dq2 will go high if the user trie s to program a non-erase suspend block while the device is in the erase suspend mode. dq1 : buffer program abort indicator dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a "1". the system must issue the write-to-buf- fer-abort-reset command sequence to return the device to reading array data. ry/ by : ready/ busy the pin is an open drain output, allowing two or more ready/ busy outputs to be or-tied. an appropriate pull-up re sistor by system is required for proper operation. the K8P5516UZB has a ready / busy output that indicates either the completion of an operation or the status of internal algorithms. if the output is low, the device is busy with either a program or an erase operation. if the output is high, the device is ready to accept any read/w rite or erase operation. when the ry/ by pin is low, the device will not accept any additional program or erase commands with the exception of the erase suspend comman d. if the K8P5516UZB is placed in an erase suspend mode, the ry/ by output will be high. for programming, the ry/ by is valid (ry/ by = 0) after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase, ry/ by is also valid after the rising edge of we pulse in the six write pulse sequence. for block erase, ry/ by is also valid after the rising edge of the sixth we pulse. rp = v cc ready / busy open drain output device gnd vcc (max.) - v ol (max.) i ol + i l = 3.5 v 2.1ma + i l where i l is the sum of the input currents of all devices tied to the ready / busy pin. rp
- 38 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 figure 10: data polling algorithms figure 11: toggle bit alogorithms start dq7 = data ? no dq5 = 1 ? fail pass yes dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address yes start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes read(dq0~dq7) valid address
- 39 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 15.0 absolute maximum ratings parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to +4.0 v v io v io -0.5 to +4.0 wp /acc v in -0.5 to +9.5 all other pins -0.5 to vcc+0.5 temperature under bias commercial t bias -10 to +125 q c extended -25 to +125 storage temperature t stg -65 to +150 q c short circuit output current i os 5 ma operating temperature t a (industrial temp.) -40 to +85 q c t a (extended temp.) -25 to + 85 q c note : 1) minimum dc voltage is -0.5v on input/ output pins. during tr ansitions, this level may fall to -2.0v for periods <20ns. maxim um dc voltage on input / output pins is vcc+0.5v which, during tr an sitions, may overshoot to vcc+2.0v for periods <20ns. 2) minimum dc voltage is -0.5v on wp /acc pins. during transitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage on wp /acc pins is 9.5v which, during transitions, may overshoot to 10.5v for periods <20ns. 3) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. ex po sure to absolute maximum rating conditions for extended perio ds may affect reliability. 16.0 recommended operating conditions ( voltage reference to gnd ) parameter symbol min typ. max unit supply voltage v cc 2.7 3.0 3.] v v io supply voltage v io 1.65 - v cc v supply voltage v ss 0 0 0 v
- 40 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 17.0 dc characteristics parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc , v cc =v ccmax 1.0 - 1.0 p a output leakage current i lo v out =v ss to v cc ,v cc =v ccmax 1.0 - 1. 0 p a vcc active read current 1) tbd tbd tbd v io non-active output tbd tbd tbd active write current 2) i cc 2 ce=v il , oe=v ih, we=v il - 25 50 ma program while erase suspend current i cc 5 ce =v il , oe =v ih - 27 55 ma page read current i cc 6 oe =vih, 8-word page read 40mhz - 10 15 ma acc accelerated program current i acc ce =v il , oe =v ih - 15 30 ma standby current i sb 1 ce , reset , wp /acc= v cc r 0.3 - 20 40 p a standby current during reset i sb 2 reset = vss r 0.3 - 20 40 p a automatic sleep mode i sb 3 v ih =vcc r 0.3v, v il =v ss r 0.2v - 20 40 p a input low level v il vcc=2.7~3. ] v -0.5 - 0.8 v input high level v ih vcc=2.7~3. ] v v cc x0.7 - vcc+0.3 v voltage for program acceleration 4) v hh vcc = 2.7~3. ] v 8.5 - 9.5 v voltage for autoselect and temporary sector unprotect v id vcc = 2.7~3. ] v 8.5 - 9.5 v output low level v ol iol =100ua,vcc=vccmin - - 0.1 v output high level v oh ioh = -100ua, vcc=vccmin vcc - 0.2 - - v low vcc lock-out voltage 5) v lko 2.3 - 2.5 v note : 1) the i cc current listed includes both the dc operating current and the frequency dependent component(at 5 mhz). 2) i cc active during internal routine(program or erase) is in progress.. 3) the high voltage (v hh ) must be used in the range of vcc = 2.7v ~ 3. ] v 4.)not 100% tested. 17.1 capacitance (ta = 25 q c, vcc = 3.0v, f = 1.0mhz) item symbol test condition min max unit input capacitance c in v in =0v - 10 pf output capacitance c out v out =0v - 10 pf control pin capacitance c in2 v in =0v - 10 pf note : capacitance is periodica lly sampled and not 100% tested.
- 41 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 18.0 ac test condition parameter value input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load c l = 30pf 19.0 ac characteristics 19.1 read operations parameter symbol v cc = 2.7v~3. ] v unit 4e min max read cycle time 1) t rc 80 - ns page read cycle time t prc 30 - ns address access time t aa - 80 ns chip enable access time t ce - 80 ns output enable time t oe - 30 ns page address access time t pa - 30 ns ce & oe disable time 1) t df - 16 ns output hold time from address, ce or oe 1) t oh 5 - ns note : 1) not 100% tested. 0v vcc vcc/2 vcc/2 input pulse and test point input & output test point output load * cl= 30pf including scope c l device and jig capacitance
- 42 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms conventional read operations figure 12: conventional read operation timings page read operations figure 13: page read operation timings oe address t ce t oeh1 ce outputs we high-z output valid t rc address stable t aa t oe t oh high-z t df ry/by high ce a3 to a23 a0(a-1): a2 output oe t rc same page addresses we aa ab t prc t aa t ce t oe t oeh1 t pa t oh t df high-z da db dc dd de df dg dh t pa t oh ac ad ae af ag ah t oh
- 43 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms hardware reset/read operations figure 14: hardware reset/read operation timings parameter symbol 4e unit min max read cycle time t rc 80 - ns address access time t aa -80ns chip enable access time t ce -80ns output hold time from address, ce or oe t oh 5-ns ry/by recovery time t rb 0-ns reset low to standby mode t rpd 20 - s reset pulse width t rp 30 - s reset high time before read t rh 200 - ns reset address ce outputs high-z t rc address stable t aa t ce t oh t rh t rh t rp output valid ry/ by 0v
- 44 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 ac characteristics 19.2 write(erase/program)operations parameter symbol vcc = 2.7v ~ 3. ] v unit 4e min max write cycle time 1), 3) t wc 80 - ns address setup time t as 0 - ns address setup time to oe low during toggle bit polling t aso 15 ns address hold time t ah 35 - ns t aht 0 - ns data setup time t ds 30 - ns data hold time t dh 0 - ns output enable setup time 1) t oes 0 - ns output enable hold time read 1) t oeh1 0 - ns toggle and data polling 1) t oeh2 10 - ns ce setup time t cs 0 - ns ce hold time t ch 0 - ns write pulse width t wp 35 - ns write pulse width high t wph 25 - ns programming operation 2) t pgm 40(typ.) p s accelerated programming operation 2) t accpgm 24(typ.) p s block erase operation 2) t bers 0.7(typ) sec vcc set up time t vcs 250 - p s vhh set up time t vhh 250 - ns acc setup time (during accelerated programming) t vps 1 - us write recovery time from ry/ by t rb 0 - ns program/erase valid to ry/ by delay t busy - 90 ns read recovery time before write t ghwl 0 - ns ce high during toggling bit polling t ceph 20 - ns oe high during toggling bit polling t oeph 10 - ns block erase accept time-out t bea - 50 us erase suspend latency t esl - 20 us program suspend latency t psl - 10 us toggle time during block protection t asp 100(typ) us toggle time during programming within a protected bl ock t psp 1(typ) us note : 1) not 100% tested. 2) the duration of the program or erase operation vari es and is calculated in the internal algorithms. 3) twc : 80ns(min) : 4e option
- 45 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 20.0 erase and program performance parameter condition limits unit comments min typ max block erase time 64 kword v cc - 0.7 3.5 sec includes 00h programming prior to erasure a cc tbd chip erase time v cc - 179.2 sec includes 00h programming prior to erasure a cc tbd word programming time v cc - 40 400 p s excludes system-level overhead a cc 24 240 word programming time with 32- word s buffer v cc - 9.4 94 p s excludes system-level overhead a cc 6 60 total 32-words buffer programming ti me v cc - 300 3000 p s excludes system-level overhead a cc 192 1920 chip programming time with 32- wor d buffer v cc - 157.3 315 sec excludes system-level overhead note : 1) 25q c, vcc = 3.0v 100,000 cycles, typical (checkerboard pattern), all values are subject to change. 2) system-level overhead is defined as the time re quired to execute the four bus cyc le command necessary to program each word. in the preprogramming step of the internal erase routine, all words are programmed to 00h before erasure.
- 46 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms program operations note : 1) dq7 is the output of the complement of the data written to the device. 2) d out is the output of the data written to the device. 3) pa : program address, pd : program data 4) the illustration shows the last two cycles of the program command sequence. figure 15: program operation timings figure 16: accelerated program timings oe address t cs ce data we t ah t oh t df t as t rc t oe t ce t ds t dh t wp t pgm status dout 555h pa pa a0h data polling t ch pd t wph ry/by t busy t rb t wc wp /acc t vhh v il or v ih v hh t vhh v il or v ih
- 47 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms chip/block erase operations figure 17: chip/block erase operation timings note : 1) ba : block address oe address t cs ce data we t ah t as t rc t ds t dh 80h aah aah 55h 30h 10h for chip erase 555h 2aah 555h 555h 2aah ba 555h for chip erase t wph t wp 55h ry/by t wc t vcs vcc vih
- 48 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms data polling during internal routine operation note : dq7=vaild data (the device has completed the internal operation). figure 18: data polling during internal routine operation timings ry/by timing diagram during program/erase operation figure 19: ry/by timing diagram during program/erase operation timings parameter symbol 4e unit min max program/erase valid to ry/ by delay t busy - 90 ns chip enable access time t ce - 80 ns output enable time t oe - 30 ns ce & oe disable time t df - 16 ns output hold time from address, ce or oe t oh 5 - ns oe hold time t oeh2 10 - ns oe t ce t oeh2 ce dq7 we t oe high-z t df dq7 *dq7 = valid data t oh t pgm or t bers high-z valid data dq0-dq6 data in data in status data we the rising edge of the last we signal ce ry/by t busy entire progrming or erase operation
- 49 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms toggle bit during intern al routine operation note : a = valid address ; not required for dq6. the switching waveform shows first two status cycle after command sequence, last stat us read cycle, and array data read cycle ce does not need to go high between status bit reads. note : dq2 is read from the erase-suspended block. figure 20: toggle bit during internal routine operation timings t dh ce address* oe dq6/dq2 we ry/by data in t aht t aht t aa t as t ceph t oeh2 t oeph status data t o e status data status data array data out t aso dq 6 we dq 2 enter embedded erasing erase suspend enter erase suspend program erase suspend program erase resume erase erase suspend read erase erase complete erase suspend read toggle dq 2 and dq 6 with oe or ce
- 50 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms reset timing diagram power-up and reset timing diagram figure 21: power-up and reset timing diagram parameter symbol all speed unit min max reset pulse width t rp 30 - s reset high time before read t rh 200 - ns reset low set-up time t rsts 250 - s reset ce or oe t rh t rp reset t aa vcc address data t rsts vccmin
- 51 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 switching waveforms unlock bypass program operations(accelerated program) unlock bypass block erase operations(accelerated program) note : 1) vhh can be left high for subsequent programming pulses. 2) use setup and hold times from conventional program operations. 3) unlock bypass program/erase commands can be used when the vhh is applied to wp /acc figure 22: unlock bypass operation timings ce oe address wp /acc we dq0-dq15 1us t vps v il or v ih v hh t vhh pa don?t care a0h pd don?t care don?t care ce oe address wp /acc we dq0-dq15 1us t vps v il or v ih v hh t vhh ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase don?t care
- 52 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 [table 15] address table block block size (x16) address range ba255 64 kwords ff0000h-ffffffh ba254 64 kwords fe0000h-feffffh ba253 64 kwords fd0000h-fdffffh ba252 64 kwords fc0000h-fcffffh ba251 64 kwords fb0000h-fbffffh ba250 64 kwords fa0000h-faffffh ba249 64 kwords f90000h-f9ffffh ba248 64 kwords f80000h-f8ffffh ba247 64 kwords f70000h-f7ffffh ba246 64 kwords f60000h-f6ffffh ba245 64 kwords f50000h-f5ffffh ba244 64 kwords f40000h-f4ffffh ba243 64 kwords f30000h-f3ffffh ba242 64 kwords f20000h-f2ffffh ba241 64 kwords f10000h-f1ffffh ba240 64 kwords f00000h-f0ffffh ba239 64 kwords ef0000h-efffffh ba238 64 kwords ee0000h-eeffffh ba237 64 kwords ed0000h-edffffh ba236 64 kwords ec0000h-ecffffh ba235 64 kwords eb0000h-ebffffh ba234 64 kwords ea0000h-eaffffh ba233 64 kwords e90000h-e9ffffh ba232 64 kwords e80000h-e8ffffh ba231 64 kwords e70000h-e7ffffh ba230 64 kwords e60000h-e6ffffh ba229 64 kwords e50000h-e5ffffh ba228 64 kwords e40000h-e4ffffh ba227 64 kwords e30000h-e3ffffh ba226 64 kwords e20000h-e2ffffh ba225 64 kwords e10000h-e1ffffh ba224 64 kwords e00000h-e0ffffh ba223 64 kwords df0000h-dfffffh ba222 64 kwords de0000h-deffffh ba221 64 kwords dd0000h-ddffffh ba220 64 kwords dc0000h-dcffffh ba219 64 kwords db0000h-dbffffh ba218 64 kwords da0000h-daffffh ba217 64 kwords d90000h-d9ffffh ba216 64 kwords d80000h-d8ffffh ba215 64 kwords d70000h-d7ffffh ba214 64 kwords d60000h-d6ffffh
- 53 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 block block size (x16) address range ba213 64 kwords d50000h-d5ffffh ba212 64 kwords d40000h-d4ffffh ba211 64 kwords d30000h-d3ffffh ba210 64 kwords d20000h-d2ffffh ba209 64 kwords d10000h-d1ffffh ba208 64 kwords d00000h-d0ffffh ba207 64 kwords cf0000h-cfffffh ba206 64 kwords ce0000h-ceffffh ba205 64 kwords cd0000h-cdffffh ba204 64 kwords cc0000h-ccffffh ba203 64 kwords cb0000h-cbffffh ba202 64 kwords ca0000h-caffffh ba201 64 kwords c90000h-c9ffffh ba200 64 kwords c80000h-c8ffffh ba199 64 kwords c70000h-c7ffffh ba198 64 kwords c60000h-c6ffffh ba197 64 kwords c50000h-c5ffffh ba196 64 kwords c40000h-c4ffffh ba195 64 kwords c30000h-c3ffffh ba194 64 kwords c20000h-c2ffffh ba193 64 kwords c10000h-c1ffffh ba192 64 kwords c00000h-c0ffffh ba191 64 kwords bf0000h-bfffffh ba190 64 kwords be0000h-beffffh ba189 64 kwords bd0000h-bdffffh ba188 64 kwords bc0000h-bcffffh ba187 64 kwords bb0000h-bbffffh ba186 64 kwords ba0000h-baffffh ba185 64 kwords b90000h-b9ffffh ba184 64 kwords b80000h-b8ffffh ba183 64 kwords b70000h-b7ffffh ba182 64 kwords b60000h-b6ffffh ba181 64 kwords b50000h-b5ffffh ba180 64 kwords b40000h-b4ffffh ba179 64 kwords b30000h-b3ffffh ba178 64 kwords b20000h-b2ffffh ba177 64 kwords b10000h-b1ffffh ba176 64 kwords b00000h-b0ffffh ba175 64 kwords af0000h-afffffh ba174 64 kwords ae0000h-aeffffh ba173 64 kwords ad0000h-adffffh ba172 64 kwords ac0000h-acffffh ba171 64 kwords ab0000h-abffffh ba170 64 kwords aa0000h-aaffffh ba169 64 kwords a90000h-a9ffffh
- 54 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 block block size (x16) address range ba168 64 kwords a80000h-a8ffffh ba167 64 kwords a70000h-a7ffffh ba166 64 kwords a60000h-a6ffffh ba165 64 kwords a50000h-a5ffffh ba164 64 kwords a40000h-a4ffffh ba163 64 kwords a30000h-a3ffffh ba162 64 kwords a20000h-a2ffffh ba161 64 kwords a10000h-a1ffffh ba160 64 kwords a00000h-a0ffffh ba159 64 kwords 9f0000h-9fffffh ba158 64 kwords 9e0000h-9effffh ba157 64 kwords 9d0000h-9dffffh ba156 64 kwords 9c0000h-9cffffh ba155 64 kwords 9b0000h-9bffffh ba154 64 kwords 9a0000h-9affffh ba153 64 kwords 990000h-99ffffh ba152 64 kwords 980000h-98ffffh ba151 64 kwords 970000h-97ffffh ba150 64 kwords 960000h-96ffffh ba149 64 kwords 950000h-95ffffh ba148 64 kwords 940000h-94ffffh ba147 64 kwords 930000h-93ffffh ba146 64 kwords 920000h-92ffffh ba145 64 kwords 910000h-91ffffh ba144 64 kwords 900000h-90ffffh ba143 64 kwords 8f0000h-8fffffh ba142 64 kwords 8e0000h-08effffh ba141 64 kwords 8d0000h-8dffffh ba140 64 kwords 8c0000h-8cffffh ba139 64 kwords 8b0000h-8bffffh ba138 64 kwords 8a0000h-8affffh ba137 64 kwords 890000h-89ffffh ba136 64 kwords 880000h-88ffffh ba135 64 kwords 870000h-87ffffh ba134 64 kwords 860000h-86ffffh ba133 64 kwords 850000h-85ffffh ba132 64 kwords 840000h-84ffffh ba131 64 kwords 830000h-83ffffh ba130 64 kwords 820000h-82ffffh ba129 64 kwords 810000h-81ffffh ba128 64 kwords 800000h-80ffffh ba127 64 kwords 7f0000h-7fffffh ba126 64 kwords 7e0000h-7effffh ba125 64 kwords 7d0000h-7dffffh ba124 64 kwords 7c0000h-7cffffh
- 55 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 block block size (x16) address range ba123 64 kwords 7b0000h-7bffffh ba122 64 kwords 7a0000h-7affffh ba121 64 kwords 790000h-79ffffh ba120 64 kwords 780000h-78ffffh ba119 64 kwords 770000h-77ffffh ba118 64 kwords 760000h-76ffffh ba117 64 kwords 750000h-75ffffh ba116 64 kwords 740000h-74ffffh ba115 64 kwords 730000h-73ffffh ba114 64 kwords 720000h-72ffffh ba113 64 kwords 710000h-71ffffh ba112 64 kwords 700000h-70ffffh ba111 64 kwords 6f0000h-6fffffh ba110 64 kwords 6e0000h-6effffh ba109 64 kwords 6d0000h-6dffffh ba108 64 kwords 6c0000h-6cffffh ba107 64 kwords 6b0000h-6bffffh ba106 64 kwords 6a0000h-6affffh ba105 64 kwords 690000h-69ffffh ba104 64 kwords 680000h-68ffffh ba103 64 kwords 670000h-67ffffh ba102 64 kwords 660000h-66ffffh ba101 64 kwords 650000h-65ffffh ba100 64 kwords 640000h-64ffffh ba99 64 kwords 630000h-63ffffh ba98 64 kwords 620000h-62ffffh ba97 64 kwords 610000h-61ffffh ba96 64 kwords 600000h-60ffffh ba95 64 kwords 5f0000h-5fffffh ba94 64 kwords 5e0000h-5effffh ba93 64 kwords 5d0000h-5dffffh ba92 64 kwords 5c0000h-5cffffh ba91 64 kwords 5b0000h-5bffffh ba90 64 kwords 5a0000h-5affffh ba89 64 kwords 590000h-59ffffh ba88 64 kwords 580000h-58ffffh ba87 64 kwords 570000h-57ffffh ba86 64 kwords 560000h-56ffffh ba85 64 kwords 550000h-55ffffh ba84 64 kwords 540000h-54ffffh ba83 64 kwords 530000h-53ffffh ba82 64 kwords 520000h-52ffffh ba81 64 kwords 510000h-51ffffh ba80 64 kwords 500000h-50ffffh
- 56 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 block block size (x16) address range ba79 64 kwords 4f0000h-4fffffh ba78 64 kwords 4e0000h-4effffh ba77 64 kwords 4d0000h-4dffffh ba76 64 kwords 4c0000h-4cffffh ba75 64 kwords 4b0000h-4bffffh ba74 64 kwords 4a0000h-4affffh ba73 64 kwords 490000h-49ffffh ba72 64 kwords 480000h-48ffffh ba71 64 kwords 470000h-47ffffh ba70 64 kwords 460000h-46ffffh ba69 64 kwords 450000h-45ffffh ba68 64 kwords 440000h-44ffffh ba67 64 kwords 430000h-43ffffh ba66 64 kwords 420000h-42ffffh ba65 64 kwords 410000h-41ffffh ba64 64 kwords 400000h-40ffffh ba63 64 kwords 3f0000h-3fffffh ba62 64 kwords 3e0000h-3effffh ba61 64 kwords 3d0000h-3dffffh ba60 64 kwords 3c0000h-3cffffh ba59 64 kwords 3b0000h-3bffffh ba58 64 kwords 3a0000h-3affffh ba57 64 kwords 390000h-39ffffh ba56 64 kwords 380000h-38ffffh ba55 64 kwords 370000h-37ffffh ba54 64 kwords 360000h-36ffffh ba53 64 kwords 350000h-35ffffh ba52 64 kwords 340000h-34ffffh ba51 64 kwords 330000h-33ffffh ba50 64 kwords 320000h-32ffffh ba49 64 kwords 310000h-31ffffh ba48 64 kwords 300000h-30ffffh ba47 64 kwords 2f0000h-2fffffh ba46 64 kwords 2e0000h-2effffh ba45 64 kwords 2d0000h-2dffffh ba44 64 kwords 2c0000h-2cffffh ba43 64 kwords 2b0000h-2bffffh ba42 64 kwords 2a0000h-2affffh ba41 64 kwords 290000h-29ffffh ba40 64 kwords 280000h-28ffffh ba39 64 kwords 270000h-27ffffh ba38 64 kwords 260000h-26ffffh ba37 64 kwords 250000h-25ffffh ba36 64 kwords 240000h-24ffffh ba35 64 kwords 230000h-23ffffh
- 57 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 block block size (x16) address range ba34 64 kwords 220000h-22ffffh ba33 64 kwords 210000h-21ffffh ba32 64 kwords 200000h-20ffffh ba31 64 kwords 1f0000h-1fffffh ba30 64 kwords 1e0000h-1effffh ba29 64 kwords 1d0000h-1dffffh ba28 64 kwords 1c0000h-1cffffh ba27 64 kwords 1b0000h-1bffffh ba26 64 kwords 1a0000h-1affffh ba25 64 kwords 190000h-19ffffh ba24 64 kwords 180000h-18ffffh ba23 64 kwords 170000h-17ffffh ba22 64 kwords 160000h-16ffffh ba21 64 kwords 150000h-15ffffh ba20 64 kwords 140000h-14ffffh ba19 64 kwords 130000h-13ffffh ba18 64 kwords 120000h-12ffffh ba17 64 kwords 110000h-11ffffh ba16 64 kwords 100000h-10ffffh ba15 64 kwords 0f0000h-0fffffh ba14 64 kwords 0e0000h-0effffh ba13 64 kwords 0d0000h-0dffffh ba12 64 kwords 0c0000h-0cffffh ba11 64 kwords 0b0000h-0bffffh ba10 64 kwords 0a0000h-0affffh ba9 64 kwords 090000h-09ffffh ba8 64 kwords 080000h-08ffffh ba7 64 kwords 070000h-07ffffh ba6 64 kwords 060000h-06ffffh ba5 64 kwords 050000h-05ffffh ba4 64 kwords 040000h-04ffffh ba3 64 kwords 030000h-03ffffh ba2 64 kwords 020000h-02ffffh ba1 64 kwords 010000h-01ffffh ba0 64 kwords 000000h-00ffffh
- 58 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3 21.0 package dimensions 56 - tsop unit :mm 18.40 r 0.10 #28 0.20 +0.07 -0.03 0.50typ #56 #29 14.00 r 0.10 0.10 max 1.00 r 0.05 0.05 min 1.20 max 0.4375 r 0.05 0.125 +0.075 -0.035 0.45~0.75 0 q ~8 q 0.25 typ (0.50) 0.16 +0.03 -0.01 0.4375 r 0.05 (19.00) 20.00 r 0.20
package dimensions 64-ball fine ball grid array package (measured in millimeters) side view 0.10 max 0.50 1.20 13.00 to p vi e w bottom view a b c e g d f h 1.00 x 7=7.00 a 1.00x7= 7.00 3.50 64- ? 0.60solder ball 3.50 1.00 0.2 m a b ? (datum a) (datum b) 1.00 13.00 11.00 b 1 4 2 6 5 3 13.00 11.00 0.50 0.50 7 8 #a1 0.10 0.10 0.10 0.10 0.05 0.10 #a1 index mark (post reflow ? 0.05 ) - 59 - K8P5516UZB-p(e)/i(c)(e)/4e datasheet nor flash memory rev. 1.3

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