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| geometry process details principal device types cmlt6427e cmst6427e gross die per 5 inch wafer 33,085 process CP327V small signal transistor npn - silicon darlington transistor chip process epitaxial planar die size 23 x 23 mils die thickness 7.1 mils base bonding pad area 4.7 x 4.7 mils emitter bonding pad area 4.7 x 4.7 mils top side metalization al-si - 30,000? back side metalization au - 12,000? backside collector r0 www.centralsemi.com r1 (9-september 2010)
process CP327V typical electrical characteristics www.centralsemi.com r1 (9-september 2010) |
Price & Availability of CP327V
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