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?2005 fairchild semiconductor corporation www.fairchildsemi.com rev.1.0.1 features ? internal avalanche rugged sense fet ? low startup current (max 40ua) ? low power consumption under 1 w at 240vac & 0.4w load ? precise fixed operating frequency (66khz) ? frequency modulation for low emi ? pulse by pulse current limiting (adjustable) ? over voltage protection (ovp) ? over load protection (olp) ? thermal shutdown function (tsd) ? auto-restart mode ? under voltage lock out (uvlo) with hysteresis ? built-in soft start (15ms) application ? smps for vcr, svr, stb, dvd & dvcd ? adaptor ? smps for lcd monitor description the FSCM0765R is an integrated pulse width modulator (pwm) and sense fet specifically designed for high performance offline switch mode power supplies (smps) with minimal external components. this device is an integrated high voltage power switching regulator which combine an avalanche rugged sense fet with a current mode pwm control block. the pwm controller includes integrated fixed frequency oscillator, under voltage lockout, leading edge blanking (leb), optimized gate driver, internal soft start, temperature compen sated precise current sources for a loop compensation and self protection circuitry. compared with discrete mosfet and pwm controller solution, it can reduce total cost, component count, size and weight simultaneously increasing efficiency, productivity, and system reliability. this device is a basic platform well suited for cost effective designs of flyback converters. table 1. maximum output power notes: 1. typical continuous power in a non-ventilated enclosed adapter measured at 50 c ambient. 2. maximum practical continuous power in an open frame design at 50 c ambient. 3. 230 vac or 100/115 vac with doubler. typical circuit figure 1. typical flyback application output power table product 230vac 15% (3) 85-265vac adapt- er (1) open frame (2) adapt- er (1) open frame (2) fscm0565rd 50w 65w 40w 50w FSCM0765Rd 65w 70w 50w 60w fscm0565rc 70w 85w 60w 70w FSCM0765Rc 85w 95w 70w 85w drain gnd vfb vcc pwm ac in dc out i limit FSCM0765R green mode fairchild power switch (fps tm )
FSCM0765R 2 internal block diagram figure 2. functional block diagram of FSCM0765R 8v/12v 3 1 2 4 vref internal bias s q q r osc vcc vcc i delay i fb v sd tsd vovp vcc s q q r r 2.5r vcc good vcc drain fb gnd gate driver vcc good 0.3/0.5v leb pwm soft start + - 5 i limit freq. modulation vcc uv reset 0.3k
FSCM0765R 3 pin definitions pin configuration figure 3. pin configuration (top view) pin number pin name pin function description 1drain this pin is the high voltage power sensef et drain. it is designed to drive the transformer directly. 2 gnd this pin is the control ground and the sensefet source. 3vcc this pin is the positive supply voltage input. initially, during start up, the power is supplied through the startup resistor fr om dc link. when vcc reaches 12v, the power is supplied from auxiliary transformer winding. 4 feedback (fb) this pin is internally connected to the inverting input of the pwm comparator. the collector of an optocoupler is typically tied to this pin. for stable operation, a capacitor should be placed between this pin and gnd. if the voltage of this pin reaches 6.0v, the over load protection is activated resulting in shutdown of the fps. 5 i_limit this pin is for the pulse by pulse current limit level programming. by using a resistor to gnd on this pin, the current limit level can be changed. if this pin is left floating, the typical current limit will be 3.0a. FSCM0765Rd 1 : drain 2 : gnd 5 : i_limit 4 : fb 3 : vcc d2-pak-5l FSCM0765Rc 1. drain 2. gnd 3. vcc 4. fb 5. i_limit to-220-5l FSCM0765Rd FSCM0765Rc
FSCM0765R 4 absolute maximum ratings (ta=25 c, unless otherwise specified) notes: 1. t j = 25 c to 150 c 2. repetitive rating: pulse width limi ted by maximum junction temperature 3. l = 30mh, v dd = 50v, r g = 25 ? , starting t j = 25 c 4. l = 13uh, starting t j = 25 c parameter symbol value unit drain-source (gnd) voltage (1) v dss 650 v drain-gate voltage (r gs =1m ? )v dgr 650 v gate-source (gnd) voltage v gs 30 v drain current pulsed (2) i dm 28 a dc single pulsed avalanch energy (3) e as 570 mj avalanch current (4) i as 17 a continuous drain current (to-220) @ tc = 25c @ t c =100 c i d 7a dc i d 4.5 a dc continuous drain current (d2-pak) @ tc = 25c @ t c =100 c i d 4a dc i d 2.6 a dc supply voltage v cc 20 v analog input voltage range v fb -0.3 to v cc v total power dissipation (d2-pak) p d 83 w derating 0.664 w/ c total power dissipation (to-220) p d 145 w derating 1.163 w/ c operating junction temperature t j internally limited c operating ambient temperature t a -25 to +85 c storage temperature range t stg -55 to +150 c esd capability, hbm model (all pins excepts for vstr and vfb) - 2.0 (vcc-vfb=1.0kv) kv esd capability, machine model (all pins excepts for vstr and vfb) - 300 (vcc-vfb=100v) v
FSCM0765R 5 electrical characteristics (ta = 25 c unless otherwise specified) parameter symbol condition min. typ. max. unit sense fet section drain source breakdown voltage bv dss v gs = 0v, i d = 250 a 650 - - v zero gate voltage drain current i dss v ds = max, rating v gs = 0v - - 500 a static drain source on resistance r ds(on) v gs = 10v, i d = 2.3a - 1.4 1.6 ? output capacitance c oss v gs = 0v, v ds = 25v, f = 1mhz - 100 - pf turn on delay time t d(on) v dd = 325v, i d = 5a (mosfet switching time is essentially independent of operating temperature) -25 - ns rise time t r -60 - turn off delay time t d(off) -115 - fall time t f -65 - control section initial frequency f osc v cc =14v, v fb =5v 60 66 72 khz modulated frequency range ? f mod --3-khz frequency modulation cycle t mod --4-ms voltage stability f stable 10v v cc 17v 0 1 3 % temperature stability ? f osc ? 25 c ta +85 c - 5 10 % maximum duty cycle d max -758085% minimum duty cycle d min ---0% start threshold voltage v start v fb =gnd 11 12 13 v stop threshold voltage v stop v fb =gnd 7 8 9 v feedback source current i fb v fb =gnd 0.7 0.9 1.1 ma soft-start time t ss -101520ms leading edge blanking time t leb - - 300 - ns burst mode section burst mode voltages v bh vcc=14v 0.4 0.5 0.6 v vb l vcc=14v 0.24 0.3 0.36 v
FSCM0765R 6 notes: 1. pulse test : pulse width 300 s, duty 2% 2. these parameters, although guaranteed at the design, are not tested in mass production. 3. these parameters, although guaranteed, ar e tested in eds (wafer test) process. 4. these parameters indicate the inductor current. 5. this parameter is the current flowing into the control ic. protection section peak current limit i lim v cc =14v, v fb =5v 2.64 3 3.36 a over voltage protection v ovp -181920v thermal shutdown temperature t sd 130 145 160 c shutdown delay current i delay v fb =4v 3.5 5.3 7 a shutdown feedback voltage v sd v fb > 5.5v 5.5 6 6.5 v total device section startup current i start -2040 a operating supply current i op(min) v cc =10v, v fb =0v -2.55ma i op(max) v cc =20v, v fb =0v
FSCM0765R 7 comparison between fs dm07652r and FSCM0765R function fsdm07652r FSCM0765R frequency modulation n.a. available ? modulated frequency range (df mod ) = 3khz ? frequency modulation cycle (t mod ) = 4ms pulse-by-pulse current limit ? inter nally fixed (2.5a) ? programmable using external resistor (3.0a max) internal startup circuit ? availabl e ? n.a. (requires startup resistor) ? startup current : 40ua (max)
FSCM0765R 8 typical performance characteristics (these characteristic graphs are normalized at ta= 25 c) startup current vs. temp start threshold voltage vs. temp stop threshold voltage vs. temp initial freqency vs. temp maximum duty cycle vs. temp feedback source current vs. temp 0.60 0.80 1.00 1.20 1.40 1.60 -50 -25 0 25 50 75 100 125 junction temperature( ) start up current (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) start threshold voltage (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) stop threshold voltage (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) initial frequency (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) maximum duty cycle (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) fb source current (normalized to 25 )
FSCM0765R 9 typical performance characteristics (continued) (these characteristic graphs are normalized at ta= 25 c) shutdown feedback voltage vs. temp shutdown delay current vs. temp bust mode enable volage vs. temp burst mode disable voltage vs. temp mavimum drain current vs. temp operating supply current vs. temp 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) shutdown fb voltag e (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) shutdown delay curren t (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) burst mode enable voltag e (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction t emperature( ) burst mode disable voltag e (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) maximum drain current (normalized to 25 ) 0.80 0.88 0.96 1.04 1.12 1.20 -50 -25 0 25 50 75 100 125 junction temperature( ) operating supply curren t (normalized to 25 )
FSCM0765R 10 functional description 1. startup : figure 4 shows the typical startup circuit and transformer auxiliary winding for FSCM0765R application. before FSCM0765R begins switching, FSCM0765R consumes only startup current (typically 25ua) and the current supplied from the dc link supply ccurrent consumed by fps (icc) and charges the external capacitor (c a ) that is connected to the vcc pin. when vcc reaches start voltage of 12v (v start ), FSCM0765R begins switching, and the current consumed by FSCM0765R increases to 3ma. then, FSCM0765R continues its normal switching operation and the power required for this device is supplied from the transformer auxiliary winding, unless vcc drops below the stop voltage of 8v (v stop ). to guarantee the stable operation of the control ic, vcc has under voltage lockout (uvlo) with 4v hysteresis. figure 5 shows the relation between the current consumed by fps (icc) and the supply voltage (vcc). figure 4. startup circuit figure 5. relation between operating supply current and vcc voltage the minimum current supplied through the startup resistor is given by where v line min is the minimum input voltage, v start is the start voltage (12v) and r str is the startup resistor. the startup resistor should be chosen so that i sup min is larger than the maximum startup current (40ua). if not, vcc can not be charged to the start voltage and fps will fail to start up. 2. feedback control : FSCM0765R employs current mode control, as shown in figure 6. an opto-coupler (such as the h11a817a) and shunt regulator (such as the ka431) are typically used to implement the feedback network. comparing the feedback voltage with the voltage across the rsense resistor makes it possible to control the switching duty cycle. when the reference pin voltage of the ka431 exceeds the internal reference voltage of 2.5v, the h11a817a led current increases, thus pulling down the feedback voltage and reducing the duty cycle. this event typically happens when the input voltage is increased or the output load is decreased. 2.1 pulse-by-pulse current limit : because current mode control is employed, the peak current through the sense fet is determined by the inverting input of pwm comparator (vfb*) as shown in figure 6. when the current through the opto transistor is zero and the current limit pin (#5) is left floating, the feedback current source (i fb ) of 0.9ma flows only through the internal resistor (r+2.5r=2.8k). in this case, the cathode voltage of diode d2 and the peak drain current have maximum values of 2.5v and 3a, respectively. the pulse-by-pulse current limit can be adjusted using a resistor to gnd on current limit pin (#5). the current limit level using an external resistor (r lim ) is given by figure 6. pulse width modulation (pwm) circuit FSCM0765R rstr vcc ca da i sup ac line (v line min - v line max ) c dc i cc icc vcc vstop=8v 25ua 3ma vstart=12v vz power up power down i sup min 2v line min ? v start ? () 1 r str ----------- - ? = i lim r lim 3a ? 2.8k ? r lim + ------------------------------------ = 4 osc vcc vref i delay i fb v sd r 2.5r gate driver olp d1 d2 + v fb * - vfb ka431 c b vo h11a817a r sense sensefet 5 r li m 0.9ma 0.3k
FSCM0765R 11 2.2 leading edge blanking (leb) : at the instant the internal sense fet is turned on, there usually exists a high current spike through the sense fet, caused by primary-side capacitance and secondary-side rectifier reverse recovery. excessive voltage across the rsense resistor would lead to incorrect feedback operation in the current mode pwm control. to counter this ef fect, the FSCM0765R employs a leading edge blanking (leb) circuit. this circuit inhibits the pwm comparator for a short time (t leb ) after the sense fet is turned on. 3. protection circuit : the FSCM0765R has several self protective functions such as over load protection (olp), over voltage protection (ovp) and thermal shutdown (tsd). because these protection circuits are fully integrated into the ic without external components, the reliability can be improved without increasing cost. once the fault condition occurs, switching is terminated and the sense fet remains off. this causes vcc to fall. when vcc reaches the uvlo stop voltage of 8v, the current consumed by FSCM0765R reduces to the startup current (typically 25ua) and the current supplied from the dc link charges the external capacitor (c a ) that is connected to the vcc pin. when vcc reaches the start voltage of 12v, FSCM0765R resumes its normal operation. in this manner, the auto-restart can alternately enable and disable the switching of the power sense fet until the fault condition is eliminated (see figure 7). figure 7. auto restart operation 3.1 over load protection (olp) : overload is defined as the load current exceeding a pre-set level due to an unexpected event. in this situation, the protection circuit should be activated in order to protect the smps. however, even when the smps is in the normal operation, the over load protection circuit can be activated during the load transition. in order to avoid this undesired operation, the over load protection circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. because of the pulse-by-pulse current limit capability, the maximum peak current through the sense fet is limited, and therefore the maximum input power is restricted with a given input voltage. if the output consumes beyond this maximum power, the output voltage (vo) decreases below the set voltage. this reduces the current through the opto-coupler led, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (vfb). if vfb exceeds 2.5v, d1 is blocked and the 5.3ua current source (i delay ) starts to charge c b slowly up to vcc. in this condition, vfb continues increasing until it reaches 6v, when the switching operation is terminated as shown in figure 8. the delay time for shutdown is the time required to charge c b from 2.5v to 6.0v with 5.3ua (i delay ). in general, a 10 ~ 50 ms delay time is typical for most applications. figure 8. over load protection 3.2 over voltage protection (ovp) : if the secondary side feedback circuit were to malfunction or a solder defect caused an open in the feedback path, the current through the opto-coupler transistor becomes almost zero. then, vfb climbs up in a similar manner to the over load situation, forcing the preset maximum current to be supplied to the smps until the over load protection is activated. because more energy than required is provided to the output, the output voltage may exceed the rated voltage before the over load protection is activated, resulting in the breakdown of the devices in the secondary side. in order to prevent this situation, an over voltage protection (ovp) circuit is employed. in general, vcc is proportional to the output voltage and the FSCM0765R uses vcc instead of directly monitoring the output voltage. if v cc exceeds 19v, an ovp circuit is activated resulting in the termination of the switching operation. in order to avoid undesired activation of ovp during normal operation, vcc should be designed to be below 19v. fault situation 8v 12v vcc vds t fault occurs fault removed normal operation normal operation power on v fb t 2.5v 6.0v over load protection t 12 = cfb*(6.0-2.5)/i delay t 1 t 2
FSCM0765R 12 3.3 thermal shutdown (tsd) : the sense fet and the control ic are built in one package. this makes it easy for the control ic to detect the heat generation from the sense fet. when the temperature exceeds approximately 145 c, the thermal protection is triggered resulting in shutdown of fps. 4. frequency modulation : emi reduction can be accomplished by modulating the switching frequency of a switched power supply. frequency modulation can reduce emi by spreading the energy over a wider frequency range than the band width measured by the emi test equipment. the amount of emi reduction is directly related to the depth of the reference frequency. as can be seen in figure 9, the frequency changes from 63khz to 69khz in 4ms. figure 9. frequency modulation 5. soft start : the FSCM0765R has an internal soft start circuit that increases pwm comparator inverting input voltage together with the sense fet current slowly after it starts up. the typical soft start time is 15msec, the pulse width to the power switching device is progressively increased to establish the correct working conditions for transformers, rectifier diodes and capacitors. the voltage on the output capacitors is progressively increased with the intention of smoothly establishing the required output voltage. it also helps to prevent transformer saturation and reduce the stress on the secondary diode during startup. 6. burst operation : in order to minimize power dissipation in standby mode, the FSCM0765R enters into burst mode operation at light load condition. as the load decreases, the feedback voltage decreases. as shown in figure 10, the device automatically enters into burst mode when the feedback voltage drops below v bl (300mv). at this point switching stops and the output voltages start to drop at a rate dependent on standby current load. this causes the feedback voltage to rise. once it passes v bh (500mv) switching resumes. the feedback voltage then falls and the process repeats. burst mode operation alternately enables and disables switching of the power sense fet thereby reducing switching loss in standby mode. figure 10. waveforms of burst operation t s t s t s drain current f s 66khz 69khz 63khz 4ms t v fb vds 0.3v 0.5v ids vo vo set time switching disable d t1 t2 t3 switching di sable d t4
FSCM0765R 13 typical application circuit features ? high efficiency (>81% at 85vac input) ? low standby mode power consumption (<1w at 240vac input and 0.4w load) ? low component count ? enhanced system reliability through various protection functions ? low emi through frequency modulation ? internal soft-start (15ms) key design notes ? the delay time for over load protection is designed to be a bout 50ms with c106 of 47nf. if a faster triggering of olp is required, c106 can be reduced to 22nf. ? using a resistor r106 on the current limit pin (#5), the pule-by-pulse current limit level is reduced to about 2a. ? zener diode zd102 is used for a safety test such as ul. when the drain pin and feedback pin are shorted, the zener diode fails and remains short, which causes the fuse (f1) blown a nd prevents explosion of the opt o-coupler (ic301). this zener diode also increases the immunity against line surge. 1. schematic application output power input vo ltage output voltage (max current) lcd monitor 40w universal input (85-265vac) 5v (2.0a) 12v (2.5a) 3 4 c102 220nf 275vac lf101 23mh c101 220nf 275vac rt1 5d- 9 f1 fuse 250v 2a c103 100uf 400v r103 56k ? 2w c104 2.2nf 1kv d101 uf 4007 c106 47nf 50v c105 22uf 50v d102 tvr10g r104 5 ? 1 2 3 4 5 t1 eer3016 bd101 2kbp06m3n257 1 2 r101 560k ? 1w FSCM0765Rc i limit vfb vcc drain gnd 1 2 3 4 5 zd101 22v 8 10 d202 mbrf10100 c201 1000uf 25v c202 1000uf 25v l201 12v, 2.5a 6 7 d201 mbrf1045 c203 1000uf 10v c204 1000uf 10v l202 5v, 2a r201 1k ? r202 1.2k ? r204 5.6k ? r203 10k ? c205 47nf r205 5.6k ? c301 4.7nf ic301 h11a817a ic201 ka431 r102 500k ? r105 500k ? r106 5k ? 1/4w zd102 10v
FSCM0765R 14 2. transformer schematic diagram 3.winding specification 4.electrical characteristics 5. core & bobbin core : eer 3016 bobbin : eer3016 ae(mm2) : 96 no pin (s f) wire turns winding method na 4 50.2 1 8 center winding insulation: polyester tape t = 0.050mm, 2layers np/2 2 10.4 1 18 solenoid winding insulation: polyester tape t = 0.050mm, 2layers n 12v 10 80.3 3 7 center winding insulation: polyester tape t = 0.050mm, 2layers n5v 7 60.3 3 3 center winding insulation: polyester tape t = 0.050mm, 2layers np/2 3 20.4 1 18 solenoid winding outer insulation: polyester tape t = 0.050mm, 2layers pin specification remarks inductance 1 - 3 520uh 10% 100khz, 1v leakage inductance 1 - 3 10uh max 2 nd all short eer3016 n p /2 n 12v n a 1 2 3 4 5 6 7 8 9 10 n p /2 n 5v
FSCM0765R 15 6.demo circuit part list part value note part value note fuse c301 4.7nf polyester film cap. f101 2a/250v ntc inductor rt101 5d-9 l201 5uh wire 1.2mm resistor l202 5uh wire 1.2mm r101 560k 1w r102 500k 1/4w r103 56k 2w r104 5 1/4w diode r105 500k 1/4w d101 uf4007 r106 5k 1/4w d102 tvr10g r201 1k 1/4w d201 mbrf1045 r202 10k 1/4w d202 mbrf10100 r203 1.2k 1/4w zd101 22v zener diode r204 5.6k 1/4w zd102 10v zener diode r205 5.6k 1/4w bridge diode bd101 2kbp06m 3n257 bridge diode capacitor c101 220nf/275vac box capacitor line filter c102 220nf/275vac box capacitor lf101 23mh wire 0.4mm c103 100uf/400v electrolytic capacitor ic c104 10nf/1kv ceramic capacitor ic101 FSCM0765Rc fps tm (7a,650v) c105 22uf/50v electrolytic capacitor ic201 ka431(tl431) voltage reference c106 47nf/50v ceramic capacitor ic301 h11a817a opto-coupler c201 1000uf/25v electrolytic capacitor c202 1000uf/25v electrolytic capacitor c203 1000uf/10v electrolytic capacitor c204 1000uf/10v electrolytic capacitor c205 47nf/50v ceramic capacitor
FSCM0765R 16 7. layout figure 11. layout considerations for FSCM0765Rc figure 12. layout considerations for FSCM0765Rc
FSCM0765R 17 package dimensions d2-pak-5l
FSCM0765R 18 package dimensions (continued) to-220-5l(forming)
FSCM0765R 19 ordering information product number package marki ng code bvdss rds(on)max. FSCM0765Rd d2-pak-5l cm0765rd 650v 1.6 ? FSCM0765Rcydtu to-220-5l cm0765rc 650v 1.6 ?
FSCM0765R 2/14/05 0.0m 001 ? 2005 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain li fe, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

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