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| 1 features ? 2,048 512 and 512 x 512 switching among backplane and local streams ? rate conversion between 2.048, 4.096 and 8.192mb/s ? optional sub-rate switch configuration for 2.048 mb/s streams ? per-channel variable or constant throughput delay ? compatible to hmvip and h.100 specifications ? automatic frame offset delay measurement ? per-stream frame delay offset programming ? per-channel message mode ? per-channel direction control ? per-channel high impedance output control ? non-multiplexed microprocessor interface ? connection memory block programming ? 3.3v local i/o with 5v tolerant inputs and ttl-compatible outputs ? ieee-1149.1 (jtag) test port applications ? medium and large switching platforms ? cti application ? voice/data multiplexer ? support st-bus, hmvip and h.100 interfaces description the MT90863 rate conversion switch provides switching capacities of 2,048 512 channels between backplane and local streams, and 512 x 512 channels for local streams. the connected serial inputs and outputs may have 32, 64 and 128 64kb/s channels per frame with data rates of 2.048mb/s, 4.096mb/s and 8.192mb/s respectively. the MT90863 also offers a sub-rate switching configuration which allows 2-bit wide 16kb/s data channels to be switched within the device. the device has features (such as: message mode; input and output offset delay; direction control; and, high impedance output control) that are programmable on per-stream or per-channel basis. february 2003 ordering information MT90863al 128 pin mqfp MT90863ag 144 pin bga -40 c to +85 c MT90863 3v rate conversion digital switch data sheet figure 1 - functional block diagram f0o ds cs r/w a7-a0 dta d15-d0 c16i test port output mux microprocessor interface timing unit internal backplane connection data memory ode v ss v dd tdi tdo reset tck trst tms interface backplane converter p/s & s/p f0i c4i /c8i c4o sto0 sto11 sto12 sto13 sto15 sti0 sti11 sti12 sti13 sti15 (2,048 channels) (2,048 locations) local memory high/low (512 locations) multiple buffer data memory (512 channels) multiple buffer data memory (512 channels) registers ic1 ode p/s converter local interface s/p converter local interface stio0/ stio15/ fei15 fei0 stio16/ stio23/ fei23 fei16 stio24 stio31 ic2 connection memory multiple buffer
MT90863 data sheet 2 zarlink semiconductor inc. figure 2 - mqfp pin connections 79 85 87 89 71 73 75 77 93 67 91 69 65 83 81 95 111 117 119 121 103 105 107 109 125 99 123 101 97 115 113 127 49 47 45 43 41 57 59 55 53 51 39 37 35 61 63 33 17 11 9 725 23 21 19 3 29 52731 13 15 1 d14 d12 d11 d10 d9 d8 d6 d5 d4 d3 d2 dta d13 d15 sti13 sti12 sti11 sti10 sti9 sti8 sti7 sti6 sti4 sti3 sti2 sti1 sti0 sti5 vdd vss vss d7 vdd sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 vss vdd ode sto8 sto9 sto10 sto11 sto12 sto13 sto14 st015 vss vss f0i f0o c4o vss c16i vss vss sti14 sti15 stio0/fei0 stio1/fei1 stio2/fei2 stio3/fei3 stio4/fei4 stio5/fei5 stio6/fei6 stio7/fei7 stio8/fei8 stio9/fei9 stio11/fei11 stio15/fei15 stio10/fei10 stio12/fei12 stio13/fei13 stio14/fei14 stio16/fei16 stio17/fei17 stio18/fei18 stio19/fei19 stio20/fei20 vss vdd stio21/fei21 stio22/fei22 stio23/fei23 stio24 vdd vss vdd vss vdd r/w tck tdo a6 a5 a4 a3 a2 a1 a0 ds a7 tdi d1 d0 vdd trst ic1 tms reset vss stio25 stio26 stio27 stio28 stio29 stio30 stio31 vss vss cs ic2 c4i /c8i 128 pin mqfp 28mm x 28mm pin pitch 0.80mm data sheet MT90863 3 zarlink semiconductor inc. figure 3 - bga pin connections 1 - a1 corner is identified by metallized markings. b c d e f g h j k l m n 12345678910111213 top view 1 a stio25 stio26 stio27 stio28 stio29 stio30 stio31 tms tdi tdo tck trst ic1 reset a0 a1 a2 a3 a4 a5 a6 a7 ds r/w cs d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d14 d13 d15 dta sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 sti8 sti9 sti10 sti11 sti12 sti13 sti14 sti15 ode sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 sto8 sto9 sto10 sto11 sto12 sto13 sto14 sto15 c16i f0i c4i /c8i c4o f0o stio0 stio1 stio2 stio3 stio4 stio5 stio6 stio7 stio8 stio9 stio10 stio11 stio12 stio13 stio14 stio15 stio16 stio17 stio18 stio19 stio20 stio21 stio22 stio23 stio24 vss vss vss vss vss vss vss vdd vdd vdd vdd vdd vdd vss ic2 vdd vss vdd vss vdd vss vss vss vdd vss vdd vss vdd vdd vss vdd vss vss vdd vdd vss vss vdd vss 23mm x 23mm ball pitch 1.5mm MT90863 data sheet 4 zarlink semiconductor inc. pin description 128 mqfp pin# 144 bga pin# name description 30,50,67, 79,97,107, 117,127 c5,c9,d5,d7, d9,e10,f4,g10 ,g11,h4, k3,k4,k6,k8 k10,k11,l8 v dd +3.3 volt power supply 8,17,29,39, 49,68,78,8 8,90,93,96, 106, 116,126 c6,c10,d4,d6, d8,d10,e3,e4, f10,f11,g2, g4,h10,j4, j10,j11,k5 k7,k9,l3,l7 v ss ground 89 d12 c16i master clock (5v tolerant input): serial clock for shifting data in/out on the serial streams. this pin accepts a 16.384 mhz clock. 91 d11 f0i master frame pulse (5v tolerant input): in st-bus mode, this input accepts a 61ns wide negative frame pulse. in ct bus mode, it accepts a 122ns wide negative frame pulse. in hmvip mode, it accepts a 244ns wide negative frame pulse. 92 b13 c4i /c8i hmvip/ct bus clock (5v tolerant input): when hmvip mode is enabled, this pin accepts a 4.096mhz clock for hmvip frame pulse alignment. when ct bus mode is enabled, it accepts a 8.192mhz clock for ct frame pulse alignment. 94 a13 f0o frame pulse (5v tolerant output): a 244ns wide negative frame pulse that is phase locked to the master frame pulse (f0i ). 95 c12 c4o c4 clock (5v tolerant output): a 4.096mhz clock that is phase locked to the master clock (c16i ). 98-105, 108-115 c11, b12, b11, a12, a11, b10, a10, b9, a9, c8, b8, a8, c7, b7, a7, a6, stio0 - 15 fei0 - 15 serial input streams 0 to 15 / frame evaluation inputs 0 to 15 (5v tolerant i/o). in 2mb/s and hmvip modes, these pins accept serial tdm data streams at 2.048 mb/s with 32 channels per stream. in 4mb/s or 8mb/s mode, these pins accept serial tdm data streams at 4.096 or 8.192 mb/s with 64 or 128 channels per stream respectively. in frame evaluation mode (fem), they are frame evaluation inputs. 118-125 b6, a5, b5, a4, b4, c4, a3, b3 stio16 - 23 fei16 - 23 serial input streams 16 to 23 (5v tolerant i/o). in 2mb/s or 4mb/s mode, these pins accept serial tdm data streams at 2.048 or 4.096 mb/s with 32 or 64 channels per stream respectively. in hmvip mode, these pins have a data rate of 8.192mb/s with 128 channels per stream. in frame evaluation mode (fem), they are frame evaluation inputs. 128, 1-7 a2, b2, a1, c3, c2, b1, d3, d2 stio24 - 31 serial input streams 24 to 31 (5v tolerant i/o). these pins are only used for 2mb/s or 4mb/s mode. they accept serial tdm data streams at 2.048 or 4.096 mb/s with 32 or 64 channels per stream respectively. 9c1tms test mode select (3.3v input with internal pull-up): jtag signal that controls the state transitions of the tap controller. 10 d1 tdi test serial data in (3.3v input with internal pull-up): jtag serial test instructions and data are shifted in on this pin. data sheet MT90863 5 zarlink semiconductor inc. 11 e2 tdo test serial data out (3.3v output): jtag serial data is output on this pin on the falling edge of tck. this pin is held in a high impedance state when jtag scan is not enabled. 12 e1 tck test clock (5v tolerant input): provides the clock to the jtag test logic. 13 f2 trst test reset (3.3 v input with internal pull-up): asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low on power-up, or held low continuously, to ensure that the MT90863 is in the normal operation mode. 14 f3 ic1 internal connection 1 (3.3v input with internal pull-down): connect to v ss for normal operation. 15 f1 reset device reset (5v tolerant input): this input (active low) puts the MT90863 in its reset state. this clears the device?s internal counters and registers. 16 g3 ic2 internal connection 2 (3.3v input): connect to v ss for normal operation. 18-25 g1, h1, h2, h3, j2, j1,j3, k1 a0 - a7 address 0 - 7 (5v tolerant input): these lines provide the a0 to a7 address lines to the internal memories. 26 k2 ds data strobe (5v tolerant input): this active low input works in conjunction with cs to enable the read and write operations. 27 l2 r/w read/write (5v tolerant input): this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. 28 l1 cs chip select (5v tolerant input): active low input used by a microprocessor to activate the microprocessor port. 31-38, 40-47 m1, n1, m2, n2, m3, l4, n3, l5, m4, n4, m5, l6, m6, n5, n6, m7, d0 - 7, d8 - d15 data bus 0 -15 (5v tolerant i/o): these pins form the 16-bit data bus of the microprocessor port. 48 n7 dta data transfer acknowledgment (5v tolerant three-state output): this active low output indicates that a data bus transfer is complete. a pull-up resistor is required to hold a high level when the pin is tri-stated. 51-54 n8, m8, n9, n10 sti0 - 3 serial input streams 0 to 3 (5v tolerant inputs): in 2mb/s or subrate switching mode, these inputs accept data rates of 2.048 mb/s with 32 channels per stream. in 8mb/s mode, these inputs accept data rates of 8.192 mb/s with 128 channels per stream. 55-62 m9, n11, l9, m10, l10, n12, m11, n13 sti4 - 11 serial input streams 4 to 11 (5v tolerant inputs): in 2mb/s or sub-rate switching mode, these inputs accept data rates of 2.048mb/s with 32 channels per stream. pin description (continued) 128 mqfp pin# 144 bga pin# name description MT90863 data sheet 6 zarlink semiconductor inc. 1.0 device overview the rate conversion switch (MT90863) can switch up to 2,048 512 channels while also providing a rate conversion capability. it is designed to switch 64 kb/s pcm or n x 64 kb/s data between the backplane and local interfaces. when the device is in the sub-rate switching mode, 2-bit wide 16 kb/s data channels can be switched within the device. the device maintains frame integrity in data applications and minimum throughput delay for voice application on a per channel basis. the backplane interface can operate at 2.048, 4.096 or 8.192 mb/s, arranged in 125 s wide frames that contain 32, 64 or 128 channels, respectively. a built-in rate conversion circuit allows users to interface between backplane interface and the local interface which operates at 2.048 mb/s or 8.192 mb/s. by using mitel?s message mode capability, the microprocessor can access input and output time-slots on a per channel basis. this feature is useful for transferring control and status information for external circuits or other st- bus devices. the frame offset calibration function allows users to measure the frame offset delay for streams stio0 to stio23. the offset calibration is activated by a frame evaluation bit in the frame evaluation register. the evaluation result is stored in the frame evaluation registers and can be used to program the input offset delay for individual streams using internal frame input offset registers. 63 l11 sti12 serial input streams 12 (5v tolerant input): in 2mb/s mode, this input accepts data rate of 2.048mb/s with 32 channels per stream respectively. in sub-rate switching mode, this pin accepts 2.048mb/s with 128 channels per stream for sub-rate switching application. 64-66 m12, m13, l12 sti13 - 15 serial input streams 13 to 15 (5v tolerant inputs): in 2mb/s mode, these inputs accept a data rate of 2.048mb/s with 32 channels per stream. 69 l13 ode output drive enable (5v tolerant input): this is the output enable control for the sto0 to sto15 serial outputs and stio0 to stio31 serial bidirectional outputs. 70-73 k13, k12, j13, j12 sto0 - 3 serial output streams 0 to 3 (5v tolerant three-state outputs): in 2mb/s or sub-rate switching mode, these outputs have data rates of 2.048 mb/s with 32 channels per stream respectively. in 8mb/s mode, these outputs have data rates of 8.192 mb/s with 128 channels per stream 74-77, 80-83 h11, h13, h12, g13, g12, f13, f12, e13 sto4 - 7, sto8 - 11 serial output streams 4 to 11 (5v tolerant three-state outputs): in 2mb/s or sub-rate switching mode, these outputs have data rates of 2.048mb/s with 32 channels per stream 84 e12 sto12 serial output streams 12 (5v tolerant three-state output): in 2mb/s mode, this output has data rate of 2.048mb/s with 32 channels per stream. in sub-rate switching mode, this pin has data rate of 2.048mb/s with 128 channels per stream for sub-rate switching application. 85-87 d13, e11, c13 sto13 - 15 serial output streams 13 to 15 (5v tolerant three-state outputs): in 2mb/s mode, these outputs have a data rate of 2.048mb/s with 32 channels per stream. pin description (continued) 128 mqfp pin# 144 bga pin# name description data sheet MT90863 7 zarlink semiconductor inc. 2.0 functional description a functional block diagram of the MT90863 is shown in figure 1. one end of the MT90863 is used to interface with backplane applications, such as hmvip or h.100 environments, while the other end supports the local switching environments. 2.1 frame alignment timing the device mode selection (dms) register allows users to select three different frame alignment timing modes. in st-bus modes, the master clock (c16i ) is always at 16.384 mhz. the frame pulse (f0i ) input accepts a negative frame pulse at 8khz. the frame pulse goes low at the frame boundary for 61ns. the frame pulse output f0o provides a 244ns wide negative frame pulse and the c4o output provides a 4.094mhz clock. these two signals are used to support local switching applications. see figure 4 for the st-bus timings. in ct bus mode, the c4i /c8i pin accepts 8.192mhz clock for the ct bus frame pulse alignment. the f0i is the ct bus frame pulse input. the ct frame pulse goes low at the frame boundary for 122ns. see figure 5 for the ct bus timing. in hmvip mode, the c4i /c8i pin accepts 4.096mhz clock for the hmvip frame pulse alignment. the f0i is the hmvip frame pulse input. the hmvip frame pulse goes low at the frame boundary for 244ns. see figure 6 for the hmvip timing. table 1 - describes the input timing requirements for st-bus, ct bus and hmvip modes. MT90863 data sheet 8 zarlink semiconductor inc. 3.0 switching configuration the device has four operation modes for the backplane interface and three operation modes for the local interface. these modes can be programmed via the device mode selection (dms) register. mode selections between the backplane and local interfaces are independent. see table 2 and table 3 for the selection of various operation modes via the programming of the dms register. 3.1 backplane interface the backplane interface can be programmed to accept data streams of 2mb/s, 4mb/s or 8mb/s. when 2mb/s mode is enabled, stio0 to stio31 have a data rate of 2.048mb/s. when 4mb/s mode is enabled, stio0 to stio31 have a data rate of 4.096mb/s. when 8mb/s mode is enabled, stio0 to stio15 have a data rate of 8.192mb/s. when hmvip mode is enabled, stio0 to stio15 have a data rate of 2.048mb/s and stio16 to stio23 have a data rate of 8.192mb/s. table 2 describes the data rates and mode selection for the backplane interface. figure 4 - st-bus timing for 2, 4 and 8 mb/s data streams f0i c16i 72 3 4 5 610 0 stio 0 - 15 sti/sto 0 - 15 (8mb/s mode) 1 2 3 4 5 610 7 channel 127 channel 0 0 76 7 0 1 channel 31 channel 0 (2mb/s mode) f0o c4o 01 0 sti12/sto12 (sub-rate bit 1 0 1 channel 127 channel 0 switching) sti/sto 0 - 3 75 64 0 stio 0 - 31 (4mb/s mode) 1 2 307 channel 63 channel 0 stio 0 - 31 data sheet MT90863 9 zarlink semiconductor inc. figure 5 - ct bus mode timing for 2, 4 and 8 mb/s data streams figure 6 - hmvip mode timing for 2 and 8 mb/s data streams f0i c4i/ c8i f0o c4o c16i (8.192mhz) (ct_frame) 72 3 4 5 610 0 stio 0 - 15 sti/sto 0 - 15 (8mb/s mode) 1 2 3 4 5 610 7 channel 127 channel 0 0 76 7 0 1 channel 31 channel 0 (2mb/s mode) 01 0 sti12/sto12 (sub-rate bit 1 0 1 channel 127 channel 0 switching) sti/sto 0 - 3 75 64 0 stio 0 - 31 (4mb/s mode) 1 2 307 channel 63 channel 0 stio 0 - 31 f0i c4i /c8i 72 3 4 5 610 0 stio 16 - 23 (8mb/s mode) 1 2 3 4 5 610 7 channel 127 channel 0 f0o c4o 01 0 sti12/sto12 (sub-rate bit 1 0 1 channel 127 channel 0 c16i switching) (hmvip frame) (4.096mhz) 0 76 7 0 1 channel 31 channel 0 sti/sto 0 - 15 (2mb/s mode) stio 0 - 15 MT90863 data sheet 10 zarlink semiconductor inc. 3.2 local interface three operation modes, 2mb/s, 8mb/s and sub-rate switching mode, can be selected for the local interface. when 2mb/s mode is selected, sti0 to sti15 and sto0 to sto15 have a 2.048mb/s data rate. when 8mb/s mode is selected, sti0 to sti3 and sto0 to sto3 have an 8.192mb/s data rate. when sub-rate switching mode is selected, sti0 to sti11 and sto0 to sto11 have 2.048mb/s data with 64kb/s data channels and sti12 and sto12 have a 2.048mb/s data rate with 16kb/s data channels. table 3 describes the data rates and mode selection for the local interface. 3.3 input frame offset selection input frame offset selection allows the channel alignment of individual backplane input streams, that operate at 8.192mb/s (stio0-23), to be shifted against the input frame pulse (f0i ). this feature compensates for the variable path delays caused by serial backplanes of variable length. such delays can be occur in large centralized and distributed switching systems. each backplane input stream can have its own delay offset value by programming the input delay offset registers (dos0 to dos5). possible adjustment can range up to +4 master clock (c16i ) periods forward with resolution of half master clock period. see table 10 and table 11, and figure 9,figure 9 - for frame input delay offset programming. 3.4 output advance offset selection the MT90863 allows users to advance individual backplane output streams which operate at 8.192mb/s (stio0-23) by half a master clock (c16i ) cycle. this feature is useful in compensating for variable output delays caused by various output loading conditions. the frame output offset registers (for0 & for1) control the output offset delays for each backplane output stream via the ofn bit programming. table 12 and figure 10 detail frame output offset programming. 3.5 serial input frame alignment evaluation the MT90863 provides the frame evaluation inputs, fei0 to fei23, to determine different data input delays with respect to the frame pulse f0i . by using the frame evaluation input select bits (fe0 to fe4) of the frame alignment register (far), users can select one of the twenty-four frame evaluation inputs for the frame alignment measurement. a measurement cycle is started by setting the start frame evaluation (sfe) bit low for at least one frame. then the evaluation starts when the sfe bit in the internal mode selection (ims) register is changed from low to high. one frame later, the complete frame evaluation (cfe) bit of the frame alignment register changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 9 of the far register. the sfe bit must be set to zero before a new measurement cycle is started. timing signals st-bus mode ct bus mode hmvip mode f0i width 61ns 122ns 244ns c4i /c8i not required 8.192mhz 4.096mhz c16i 16.384mhz f0o width 244ns c4o 4.096mhz table 1 - timing signals requirements for various operation modes data sheet MT90863 11 zarlink semiconductor inc. the falling edge of the frame measurement signal (fei) is evaluated against the falling edge of the frame pulse (f0i ). table 8 and figure 8 describe the frame alignment register. dms register bits modes backplane interface data rate bms2 bms1 bms0 0 0 0 2mb/s, st-bus mode stio0 - 31 2.048 mb/s 0 0 1 2mb/s, ct bus mode stio0 - 31 2.048 mb/s 0 1 0 4mb/s, st-bus mode stio0 - 31 4.096 mb/s 0 1 1 4mb/s, ct bus mode stio0 - 31 4.096 mb/s 1 0 0 8mb/s, st-bus mode stio0 - 15 8.192 mb/s stio16 - 31 not available 1 0 1 8mb/s, ct bus mode stio0 - 15 8.192 mb/s stio16 - 31 not available 1 1 0 hmvip mode stio0 - 15 2.048 mb/s stio16 - 23 8.192 mb/s stio24 - 31 not available table 2 - mode selection for backplane interface dms register bits modes local interface data rate lms1 lms0 0 0 2mb/s mode sti0 - 15 2.048 mb/s sto0 - 15 2.048 mb/s 01sub-rate switching mode sti0 - 11 2.048 mb/s sti12 sub-rate switching input stream at 2.048 mb/s sti13 - 15 not available sto0 - 11 2.048 mb/s sto12 sub-rate switching output stream at 2.048mb/s sto13 - 15 not available 1 0 8mb/s mode sti0 - 3 8.192 mb/s sti4 - 15 not available sto0 - 3 8.192 mb/s sto4 - 15 not available table 3 - mode selection for local interface MT90863 data sheet 12 zarlink semiconductor inc. 3.6 memory block programming the MT90863 has two connection memories: the backplane connection memory and the local connection memory. the local connection memory is partitioned into high and low parts. the ims register provides users with the capability of initializing the local connection memory low and the backplane connection memory in two frames. bit 11 to bit 13 of every backplane connection memory location will be programmed with the pattern stored in bit 7 to bit 9 of the ims register. bit 12 to 15 of every local connection memory low location will be programmed with the pattern stored in bits 3 to 6 of the ims register. the block programming mode is enabled by setting the memory block program (mbp) bit of the control register high. when the block programming enable (bpe) bit of the ims register is set to high, the block programming data will be loaded into bits 11 to 13 of every backplane connection memory and bits 12 to 15 of every local connection memory low. the other connection memory bits are loaded with zeros. when the memory block programming is complete, the device resets the bpe bit to zero. see figure 7 for the connection memory contents when the device is in block programming mode. 4.0 delay through the MT90863 the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. for voice applications, select variable throughput delay to ensure minimum delay between input and output data. in wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch. the delay through the device varies according to the type of throughput delay selected in the lv /c and bv /c bits of the local and backplane connection memory as described in table 16 and table 19. 4.1 variable delay mode (lv /c or bv /c bit = 0) the delay in this mode is dependent only on the combination of source and destination channels and is independent of input and output streams. 4.2 constant delay mode (lv /c bit or bv /c= 1) in this mode a multiple data memory buffer is used to maintain frame integrity in all switching configurations. 5.0 microprocessor interface the MT90863 provides a parallel microprocessor interface for non-multiplexed bus structures. this interface is compatible with motorola non-multiplexed buses. the required microprocessor signals are the 16-bit data bus (d0- d15), 8-bit address bus (a0-a7) and 4 control lines (cs , ds , r/w and dta ). see figure 16 - figure 16 for motorola non-multiplexed bus timing. the MT90863 microprocessor port provides access to the internal registers, connection and data memories. all locations provide read/write access except for the data memory and the data read register which are read only. 5.1 memory mapping the address bus on the microprocessor interface selects the internal registers and memories of the MT90863. if the a7 address input is low, then the registers are addressed by a6 to a0 as shown in table 4. if the a7 is high, the remaining address input lines are used to select the serial input or output data streams corresponding to the subsection of memory positions. for data memory reads, the serial inputs are selected. for connection memory writes, the serial outputs are selected. the control, device mode selection and internal mode selection registers control all the major functions of the device. the device mode selection register and internal mode selection register should be programmed data sheet MT90863 13 zarlink semiconductor inc. immediately after system power-up to establish the desired switching configuration as explained in the frame alignment timing and switching configurations sections. the control register is used to control the switching operations in the MT90863. it selects the internal memory locations that specify the input and output channels selected for switching. control register data consists of: the memory block programming bit (mbp): the memory select bits (ms0-2); and, the stream address bits (sta0-4). the memory block programming bit allows users to program the entire connection memory block, (see memory block programming section). the memory select bits control the selection of the connection memory or the data memory. the stream address bits define an internal memory subsections corresponding to serial input or serial output streams. figure 7 - block programming data in the connection memories a7 (note 1) a6 a5 a4 a3 a2 a1 a0 location 0 0000000control register, cr 0 0 0 0 0 0 0 1 device mode selection register, dms 0 0 0 0 0 0 1 0 internal mode selection register, ims 0 0 0 0 0 0 1 1 frame alignment register, far 0 0 0 0 0 1 0 0 input offset selection register 0, dos0 0 0 0 0 0 1 0 1 input offset selection register 1, dos1 0 0 0 0 0 1 1 0 input offset selection register 2, dos2 0 0 0 0 0 1 1 1 input offset selection register 3, dos3 0 0 0 0 1 0 0 0 input offset selection register 4, dos4 0 0 0 0 1 0 0 1 input offset selection register 5, dos5 0 0 0 0 1 0 1 0 frame output offset register, for0 0 0 0 0 1 0 1 1 frame output offset register, for1 0 0 0 0 1 1 0 0 address buffer register, abr table 4 - address memory map 76543210 8 9 10 11 12 13 0 bbpd bbpd bbpd 14 15 0 0 0000000000 2 1 0 backplane connection memory (bcm) 76543210 8 9 10 11 12 13 0 lbpd lbpd 14 15 0 lbpd 0000000000 3 2 1 0 local connection memory low (lcml) 76543210 8 9 10 11 12 13 0 14 15 0 0 0000000000 0 0 local connection memory high (lcmh) 0 lbpd MT90863 data sheet 14 zarlink semiconductor inc. the data in the dms register consists of the local and backplane mode selection bits (lms0-1 and bms0-2) to enable various switching modes for local and backplane interfaces respectively. the data in the ims register consists of block programming bits (lbpd0-3 and bbpd0-2), block programming enable bit (bpe), output standby bit (osb) and start frame evaluation bit (sfe). the block programming enable bit allows users to program the entire backplane and local connection memories, (see memory block programming section). if the ode pin is low, the osb bit enables (if high) or disables (if low) all st-bus output drivers. if the ode pin is high, the contents of the osb bit is ignored and all st-bus output drivers are enabled. see table 5 for the output high impedance control. 5.2 address buffer mode the implementation of the address buffer, data read and data write registers allows faster memory read/write operation for the microprocessor port. see table 6 and following for bit assignments. the address buffer mode is controlled by the ab bit in the control register. the targeted memory for data read/write is selected by the ms0-2 bits in the control register. the data write register (dwr) contains the data to be transferred to the memory. the data read register (drr) contains the data transferred from the memory. the address buffer register (abr) allow users to specify the read or write address by programming the stream address bits (sa0-4) and the channel address bits (ca0-6). data transfer from/to the memory is controlled by the read/write select bits (rs, ws). the complete data access (cda) bit indicates the completion of data transfer between the memory and dwr or drr register. 0 0 0 0 1 1 0 1 data write register, dwr 0 0 0 0 1 1 1 0 data read register, drr 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 1 . 0 1 ch 0 ch 1 . ch 30 ch 31 ( note 2) 1 1 . 1 1 0 0 . 1 1 1 1 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 0 . 1 1 0 1 . 0 1 ch 32 ch 33 . ch 126 ch 127 ( note 3) notes: 1. bit a7 must be high for access to data and connection memory positions. bit a7 must be low for access to registers. 2. channels 0 to 31 are used when serial stream is at 2mb/s. 3. channels 0 to 127 are used when serial stream is at 8mb/s a7 (note 1) a6 a5 a4 a3 a2 a1 a0 location table 4 - address memory map (continued) data sheet MT90863 15 zarlink semiconductor inc. 5.3 write operation using address buffer mode enable the address buffer mode by setting the ab bit from low to high. program the dwr register with data to be transferred to memory. load the abr register with proper channel and stream information. change the ws bit in the abr register from low to high to initiate the data transfer from the dwr register to the memory. after several master clock cycles, the cda bit in the abr register changes from low to high to signal the completion of data transfer and resets the ws bit to low. repeat the above steps for subsequent memory write operations. disable the address buffer write operation by setting the ab bit to low. 5.4 read operation using address buffer mode enable the address buffer mode by setting the ab bit from low to high. program the abr register with proper channel and stream information. change the rs bit in the abr register from low to high to initiate the data transfer from the memory to the drr register. after several master clock cycles, the cda bit in the abr register changes from low to high to signal the completion of data transfer and resets the rs bit to low. read the drr register to obtain the data transferred from the memory. repeat the above steps for subsequent memory read operations. disable the address buffer read operation by setting the ab bit to low. 5.5 backplane connection memory control the backplane connection memory controls the switching configuration of the backplane interface. locations in the backplane connection memory are associated with particular stio output streams. the bv /c (variable/constant delay) bit of each backplane connection memory location allows the per-channel selection between variable and constant throughput delay modes for all stio channels. in message mode, the message channel (bmc) bit of the backplane connection memory enables (if high) an associated stio output channel. if the bmc bit is low, the contents of the backplane connection memory stream address bit (bsab) and channel address bit (bcab) defines the source information (stream and channel) of the time-slot that will be switched to the stio streams. when message mode is enabled, only the lower half (8 least significant bits) of the backplane connection memory is transferred to the stio pins. ode pin osb bit in ims register dc bit in backplane cm stio0-31 output driver status oe bit in local cm sto0-15 output driver status don?t care don?t care 0 per channel high impedance 0 per channel high impedance 0 0 don?t care high impedance don?t care high impedance 0 1 1 enable 1 enable 1 don?t care 1 enable 1 enable table 5 - output high impedance control MT90863 data sheet 16 zarlink semiconductor inc. bit name description 15-11 unused must be zero for normal operation. 10 ab address buffer. when 1, enables the address buffer, data write and data read registers for accessing various memory locations for fast microport access. when 0, disables the address buffer, data write and data read registers. 9ct channel tri-state. when 1, the last bit of each output channel is tri-stated for -22ns against the channel boundary. when 0, the last bit of each channel is not tri-stated. 8mbp memory block program. when 1, the connection memory block programming feature is ready for the programming of bit 11 to 13 for backplane connection memory, bit 12 to 15 for local connection memory low. when 0, this feature is disabled. 7 - 5 ms2-0 memory select bits. these three bits are used to select connection and data memory functions as follows: ms2-0 memory selection 000 local connection memory low read/write, 001 local connection memory high read/write, 010 backplane connection memory read/write, 011 local data memory read, 100 backplane data memory read, 4 - 0 sta4-0 stream address bits . the binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (sta4 = msb, sta0 = lsb) table 6 - control (cr) register bits bit name description 15 - 5 unused reserved 4 - 3 lms local mode selection bit. the binary value expressed by these bits refers to the following backplane interface switching modes: lms1-0 local switching mode 00 2mb/s st-bus mode 01 2mb/s sub-rate switching mode 10 8mb/s st-bus mode table 7 - device mode selection (dms) register bits read/write address: 00 h , reset value: 0000 h . 76543210 8 9 10 11 12 13 sta0 sta1 sta2 sta3 14 15 sta4 ms0 ms1 ms2 mbp ct ab 0 0 0 0 0 read/write address: 01 h , reset value: 0000 h . 76543210 8 9 10 11 12 13 bms0 bms1 0 14 15 0bms2 0 0 0 00lms1 0 0 0 0lms0 data sheet MT90863 17 zarlink semiconductor inc. 5.6 local connection memory control the local connection memory controls the local interface switching configuration. local connection memory is split into high and low parts. locations in local connection memory are associated with particular sto output streams. the l/b (local/backplane select) bit of each local connection memory location allows per-channel selection of source streams from local or backplane interface. the lv /c (variable/constant delay) bit of each local connection memory location allows the per-channel selection between variable and constant throughput delay modes for all sto channels. in message mode, the local connection memory message channel (lmc) bit enables (if high) an associated sto output channel. if the lmc bit is low, the contents of the stream address bit (lsab) and the channel address bit (lcab) of the local connection memory defines the source information (stream and channel) of the time-slot that will be switched to the sto streams. when message mode is enabled, only the lower half (8 least significant bits) of the local connection memory low bits are transferred to the sto pins. when sub-rate switching is enabled, the lsr0-1 bits in the local connection memory high define which bit position contains the sub-rate data. 5.7 dta data transfer acknowledgment pin the dta pin is driven low by internal logic to indicate (to the cpu) that a data bus transfer is complete. when the bus cycle ends, this pin drives high and then switches to the high-impedance state. if a short or signal contention prevents the dta pin from reaching a valid logic high, it will continue to drive for approximately 15nsec before switching to the high-impedance state. 2 - 0 bms2-0 backplane mode selection bits . the binary value expressed by these bits refers to the follow- ing backplane interface switching modes: bms2-0 backplane switching mode 000 2mb/s st-bus mode 001 2mb/s ct bus mode 010 4mb/s st-bus mode 011 4mb/s ct bus mode 100 8mb/s st-bus mode 101 8mb/s ct bus mode 110 hmvip mode note: please refer to table 1 for timing signal requirements bit name description table 7 - device mode selection (dms) register bits (continued) read/write address: 01 h , reset value: 0000 h . 76543210 8 9 10 11 12 13 bms0 bms1 0 14 15 0bms2 0 0 0 00lms1 0 0 0 0lms0 MT90863 data sheet 18 zarlink semiconductor inc. 6.0 initialization of the MT90863 during power up, the trst pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the normal operation mode. a 5k ? pull-down resistor can be connected to this pin so that the device will not enter the jtag test mode during power up. after power up, the contents of the connection memory can be in any state. the ode pin should be held low after power up to keep all serial outputs in a high impedance state until the microprocessor has initialized the switching matrix. this procedure prevents two serial outputs from driving the same stream simultaneously. during the microprocessor initialization routine, the microprocessor should program the desired active paths through the switch. the memory block programming feature can also be used to quickly initialize the dc and oe bit in the backplane and local connection memory respectively. when this process is complete, the microprocessor controlling the matrices can either bring the ode pin high or enable the osb bit in ims register to relinquish the high impedance state control. bit name description 15-10 unused must be zero for normal operation. 9-7 bbpd2-0 backplane block programming data. these bits carry the value to be loaded into the backplane connection memory block when the memory block programming feature is active. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the contents of bits bbpd2-0 are loaded into the bit 13 to bit 11 position of the backplane connection memory. bit 15, bit 14 and bit 10 to bit 0 of the backplane connection memory are zeroed. 6-3 lbpd3-0 local block programming data. these bits carry the value to be loaded into the local connection memory block when the memory block programming feature is active. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the contents of bits lbpd3-0 are loaded into the bit 15 to bit 12 position of the local connection memory. bit 11 to bit 0 of the local connection memory low are zeroed. bit 15 to bit 0 of local connection memory high are zeroed. 2 bpe begin block programming enable. a zero to one transition of this bit enables the memory block programming function. the bpe, bbpd2-0 and lbpd3-0 bits in the ims register must be defined in the same write operation. once the bpe bit is set high, the device requires two frames to complete the block programming. after the programming function has finished, the bpe bit returns to zero to indicate the operation is completed. when the bpe = 1, the bpe or mbp can be set to 0 to abort the programming operation. when bpe = 1, the other bits in the ims register must not be changed for two frames to ensure proper operation. table 8 - internal mode selection (ims) register bits r ea d/w r it e add ress: 02 h , reset value: 0000 h . 76543210 8 9 10 11 12 13 lbpd bbpd bbpd 0 14 15 lbpd 0 bbpd bpe osb sfe 3210 0 0 0 0 lbpd lbpd 210 data sheet MT90863 19 zarlink semiconductor inc. 1osb output stand by. this bit controls the device output drivers. osb bit ode pin oe bit stio0 - 31, sto0 - 15 0 0 1 high impedance state 1 0 1 enable x 1 1 enable x x 0 per-channel high impedance 0sfe start frame evaluation. a zero to one transition in this bit starts the frame evaluation procedure. when the cfe bit in the far register changes from zero to one, the evaluation procedure stops. set this bit to zero for at least one frame (125 s) to start another frame evaluation. bit name description 15-11 fe4-0 frame evaluation input select. the binary value expressed in these bits refers to the frame evaluation inputs, fei0 to fei23. 10 cfe complete frame evaluation. when cfe = 1, the frame evaluation is completed and bits fd9 to fd0 bits contains a valid frame alignment offset. this bit is reset to zero, when sfe bit in the ims register is changed from 1 to 0. this bit is read-only. 9fd9 frame delay bit 11. the falling edge of fe is sampled during the clk-high phase (fd9 = 1) or during the clk-low phase (fd9 = 0). this bit allows the measurement resolution to 1/2 clk cycle. this bit is read-only. 8-0 fd8-0 frame delay bits. the binary value expressed in these bits refers to the measured input offset value. these bits are reset to zero when the sfe bit of the ims register changes from 1 to 0. (fd8 = msb, fd0 = lsb). these bits are also read-only table 9 - frame alignment (far) register bit bit name description table 8 - internal mode selection (ims) register bits (continued) r ea d/w r it e add ress: 02 h , reset value: 0000 h . 76543210 8 9 10 11 12 13 lbpd bbpd bbpd 0 14 15 lbpd 0 bbpd bpe osb sfe 3210 0 0 0 0 lbpd lbpd 210 r ea d/w r it e add ress: 03 h , reset value: 0000 h . 76543210 8 9 10 11 12 13 fd0 fd1 fd2 fd3 fd4 fd5 fd6 fd7 fd8 fd9 cfe fe0 fe1 fe2 fe3 fe4 14 15 MT90863 data sheet 20 zarlink semiconductor inc. figure 8 - example for frame alignment measurement st-bus f0i fei input (fd9 = 0, sample at clk low phase) offset value (fd[8:0] = 06 h ) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c16i hmvip f0i fei input (fd9 = 1, sample at clk high phase) offset value (fd[8:0] = 08 h ) 1 0 2345678910111213141516 c16i c4i data sheet MT90863 21 zarlink semiconductor inc. name (note 1) description ifn2, ifn1, ifn0 input offset bits 2,1 & 0. these three bits define how long the serial interface receiver takes to recognize and store bit 0 from the stio pin: i.e., to start a new frame. the input frame offset can be selected to +4 clock periods from the point where the external frame pulse input signal is applied to the f0i inputs of the device.figure 9 - dlen data latch edge. st-bus mode: dlen =0, if clock rising edge is at the 3/4 point of the bit cell. dlen =1, if clock falling edge is at the 3/4 point of the bit cell. table 10 - frame delay offset (dos) register bits read/write address: 04 h for dos0 register, 05 h for dos1 register, 06 h for dos2 register, 07 h for dos3 register, 08 h for dos4 register, 09 h for dos5 register, reset value: 0000 h for all dos registers. 76543210 8 9 10 11 12 13 dle0 if00 if01 if02 14 15 dle1 if10 if11 if12 dle2 if20 if21 if22 dle3 if30 if31 if32 dos0 register dos1 register 76543210 8 9 10 11 12 13 dle4 if40 if41 if42 14 15 dle5 if50 if51 if52 dle6 if60 if61 if62 dle7 if70 if71 if72 dos2 register 76543210 8 9 10 11 12 13 dle8 if80 if81 if82 14 15 dle9 if90 if91 if92 dle10 if100 if101 if102 dle11 if110 if111 if112 dos3 register 76543210 8 9 10 11 12 13 dle12 if120 if121 if122 14 15 dle13 if130 if131 if132 dle14 if140 if141 if142 dle15 if150 if151 if152 dos4 register 76543210 8 9 10 11 12 13 dle16 if160 if161 if162 14 15 dle17 if170 if171 if172 dle18 if180 if181 if182 dle19 if190 if191 if192 dos5 register 76543210 8 9 10 11 12 13 dle20 if200 if201 if202 14 15 dle21 if210 if211 if212 dle22 if220 if221 if222 dle23 if230 if231 if232 MT90863 data sheet 22 zarlink semiconductor inc. note 1: n denotes a stio stream number from 0 to 23. name (note 1) description table 10 - frame delay offset (dos) register bits read/write address: 04 h for dos0 register, 05 h for dos1 register, 06 h for dos2 register, 07 h for dos3 register, 08 h for dos4 register, 09 h for dos5 register, reset value: 0000 h for all dos registers. 76543210 8 9 10 11 12 13 dle0 if00 if01 if02 14 15 dle1 if10 if11 if12 dle2 if20 if21 if22 dle3 if30 if31 if32 dos0 register dos1 register 76543210 8 9 10 11 12 13 dle4 if40 if41 if42 14 15 dle5 if50 if51 if52 dle6 if60 if61 if62 dle7 if70 if71 if72 dos2 register 76543210 8 9 10 11 12 13 dle8 if80 if81 if82 14 15 dle9 if90 if91 if92 dle10 if100 if101 if102 dle11 if110 if111 if112 dos3 register 76543210 8 9 10 11 12 13 dle12 if120 if121 if122 14 15 dle13 if130 if131 if132 dle14 if140 if141 if142 dle15 if150 if151 if152 dos4 register 76543210 8 9 10 11 12 13 dle16 if160 if161 if162 14 15 dle17 if170 if171 if172 dle18 if180 if181 if182 dle19 if190 if191 if192 dos5 register 76543210 8 9 10 11 12 13 dle20 if200 if201 if202 14 15 dle21 if210 if211 if212 dle22 if220 if221 if222 dle23 if230 if231 if232 data sheet MT90863 23 zarlink semiconductor inc. figure 9 - examples for input offset delay timing input stream offset measurement result from frame delay bits corresponding offset bits fd9 fd2 fd1 fd0 ifn2 ifn1 ifn0 dlen no clock period shift (default) 1 0 0 0 0 0 0 0 + 0.5 clock period shift 0 0 0 0 0 0 0 1 +1.0 clock period shift 1 0 0 1 0 0 1 0 +1.5 clock period shift 0 0 0 1 0 0 1 1 +2.0 clock period shift 1 0 1 0 0 1 0 0 +2.5 clock period shift 0 0 1 0 0 1 0 1 +3.0 clock period shift 1 0 1 1 0 1 1 0 +3.5 clock period shift 0 0 1 1 0 1 1 1 +4.0 clock period shift 1 1 0 0 1 0 0 0 +4.5 clock period shift 0 1 0 0 1 0 0 1 table 11 - offset bits (ifn2, ifn1, ifn0, dlen) & input offset bits (fd9, fd2-0) st-bus f0i c16i stio stream stio stream stio stream stio stream offset=0, dle=0 offset=1, dle=0 offset=0, dle=1 offset=1, dle=1 bit 7 bit 7 bit 7 bit 7 denotes the 3/4 point of the bit cell MT90863 data sheet 24 zarlink semiconductor inc. figure 10 - examples for frame output offset timing bit name (note 1) description 15-0 (for0) 7-0 (for1) ofn output offset bit. when 0, the first bit of the serial output stream has normal alignment with the frame pulse. when 1, the first bit of the serial output stream is advanced by 1/2 clk cycle with respect to the frame pulse. see figure 10 -. 15-8 (for1) unused must be zero for normal operation. note 1: n denotes a stio stream number from 0 to 23 table 12 - frame output offset (for) register bits read/write address: 0a h for for0 register, 0b h for for1 register, reset value: 0000 h for all for registers. 76543210 8 9 10 11 12 13 of00 of01 of02 of03 14 15 of04 of05 of06 of07 of08 of09 of10 of11 of12 of13 of14 of15 for0 register for1 register 76543210 8 9 10 11 12 13 of16 of17 of18 of19 14 15 of20 of21 of22 of23 0 0 0 0 0 0 0 0 st-bus f0i c16i stio stream stio stream offset=0 offset=1 bit 7 bit 7 hmvip f0i c16i sto stream sto stream offset=0 offset=1 bit 7 bit 7 hclk denotes the starting point of the bit cell data sheet MT90863 25 zarlink semiconductor inc. bit name description 15 unused reserved 14 cda complete data access. this bit is read only. this bit changes from 0 to 1 when data transfer is completed between memory and the data read register or data write register. when the rs or ws bit in this register is changed from 1 to 0, this bit is reset to zero. 13 rs read select. a zero to one transition of this bit initiates the data transfer from memory to the data read register. this bit is reset to zero when the cda bit changes from 0 to 1. 12 ws write select. a zero to one transition of this bit initiates the data transfer from the data write register to memory. this bit is reset to zero when the cda bit changes from 0 to 1. 11 - 5 ca6 - ca0 channel address bits. these bits perform the same function as the external address bits when used to access various memory locations. the number (expressed in binary notation) on these bits refers to the input or output data stream channel that corresponds to the subsection of memory. 4 - 0 sa4 - sa0 stream address bits. these bits perform the same function as the sta bits in the control register. the number (in binary notation) on these bits refers to the input or output data stream which corresponds to the subsection of memory. table 13 - address buffer (abr) register bits bit name description 15 - 0 wr15 - wr0 write data bits. data to be transferred to the internal memory locations. table 14 - data write (dwr) register bits read/write address: 0c h for abr register, reset value: 0000 h 76543210 8 9 10 11 12 13 sa0 sa1 sa2 sa3 14 15 sa4 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ws rs cda 0 read/write address: 0d h for dwr register, reset value: 0000 h 76543210 8 9 10 11 12 13 wr0 wr1 wr2 wr3 14 15 wr4 wr5 wr6 wr7 wr8 wr9 wr10 wr11 wr12 wr13 wr14 wr15 MT90863 data sheet 26 zarlink semiconductor inc. bit name description 15 - 0 rd15 - rd0 read data bits. data transferred from one of the internal memory locations. table 15 - data read (drr) register bits bit name description 15,14 unused must be zero for normal operation. 13 bv /c variable /constant throughput delay. this bit is used to select either variable (low) or constant delay (high) modes on a per-channel basis for the local interface streams. 12 bmc message channel. when 1, the backplane connection memory contents are output on the corresponding output channel and stream. only the lower byte (bit 7 - bit 0) will be output to the backplane interface stio pins. when 0, the local data memory address of the switched sti input channel and stream is loaded into the backplane connection memory. 11 dc directional control. this bit enables the stio pindrivers on a per-channel basis. when 1, the stio output driver functions normally. when 0, the stio output driver is in a high-impedance state. 10-7 (note 1) bsab3-0 source stream address bits. the binary value is the number of the data stream for the source of the connection. 6-0 (note 1) bcab6-0 source channel address bits. the binary value identifies the channel for the connection source. note 1: if bit 12 (bmc) of the corresponding backplane connection memory location is 1 (device in message mode), then these entire 8 bits (bsab0, bcab6 - bcab0) are output on the output channel and stream associated with this location. table 16 - blackplane connection memory bits read address: 0e h for drr register, reset value: 0000 h 76543210 8 9 10 11 12 13 rd0 rd1 rd2 rd3 14 15 rd4 rd5 rd6 rd7 rd8 rd9 rd10 rd11 rd12 rd13 rd14 rd15 76543210 8 9 10 11 12 13 bcab bcab bcab bsab bcab bcab bcab bsab bsab bsab dc bmc 14 0 15 bv/c 0 32106543210 bcab data sheet MT90863 27 zarlink semiconductor inc. data rate bsab3 to bsab0 bits used to determine the source stream of the connection 2.048 mb/s sti0 to sti15 8.192 mb/s sti0 to sti3 2.048 mb/s sub-rate switching sti0 to sti12 table 17 - bsab bits programming for different local interface mode data rate bcab bits used to determine the source channel of the connection 2.048 mb/s bcab4 to bcab0 (32 channel/frame) 8.192 mb/s bcab6 to bcab0 (128 channel/frame) 2.048 mb/s sub-rate switching bcab4 to bcab0 (32 channel/frame) bcab6 to bcab0 (128 channel/frame) table 18 - bcab bits programming for different data rates bit name description 15 l/b local/backplane select when 1, the output channel of sto0-15 comes from sti0-15 (local) when 0, the output channel of sto0-15 comes from: stio0-31 (backplane, 2mb/s mode) stio0-31 (backplane, 4mb/s mode) stio0-15 (blackplane, 8mb/s mode) stio0-23 (blackplane, hmvip mode) 14 lv /c variable /constant throughput delay. this bit is used to select either variable (low) or constant delay (high) modes on a per-channel basis for the source streams. 13 lmc message channel. when 1, the contents of the local connection memory are output on the corresponding output channel and stream. only the lower byte (bit 7 - bit 0) will be output to the sto pins of the local interface. when 0, the backplane or local data memory address of the switched input channel and stream is loaded into the local connection memory. 12 oe output enable. this bit enables the drivers of sto pins on a per-channel basis. when 1, the sto output driver functions normally. when 0, the sto output driver is in a high-impedance state. table 19 - local connection memory low bits 76543210 8 9 10 11 12 13 lcab lcab lcab lsab lcab lcab lcab lsab lsab lsab oe 14 l/b 15 bv/c 32106543210 lcab lsab 4 bmc MT90863 data sheet 28 zarlink semiconductor inc. 11-7 (note 1) lsab4-0 source stream address bits. the binary value identifies the data stream for the source of the connection. 6-0 (note 1) lcab6-0 source channel address bits. the binary value identifies the channel for the source of the connection. note 1: if bit 12 (lmc) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8 bits (lsab0, lcab6 - lcab0) are output on the output channel and stream associated with this location. data rate lsab3 to lsab0 bits used to determine the source stream of the connection 2.048 mb/s stio0 to stio31 or sti0 to sti15 4.096 mb/s stio0 to stio31 8.192 mb/s stio0 to stio15 or sti0 to sti3 hmvip stio0 to stio23 2.048 mb/s sub-rate switching sti0 to sti12 table 20 - lsab bits programming for different local interface modes data rate lcab bits used to determine the source channel of the connection 2.048 mb/s lcab4 to lcab0 (32 channel/frame) 4.096 mb/s lcab5 to lcab0 (64 channel/frame) 8.192 mb/s lcab6 to lcab0 (128 channel/frame) hmvip lcab4 to lcab0 (32 channel/frame) lcab6 to lcab0 (128 channel/frame) 2.048 mb/s sub-rate switching lcab4 to lcab0 (32 channel/frame) lcab6 to lcab0 (128 channel/frame) table 21 - lcab bits programming for different data rates bit name description table 19 - local connection memory low bits (continued) 76543210 8 9 10 11 12 13 lcab lcab lcab lsab lcab lcab lcab lsab lsab lsab oe 14 l/b 15 bv/c 32106543210 lcab lsab 4 bmc data sheet MT90863 29 zarlink semiconductor inc. 7.0 jtag support the MT90863 jtag interface conforms to the boundary-scan ieee1149.1 standard. this stan-dard specifies a design-for-testability technique called boundary-scan test (bst). the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. 7.1 test access port (tap) the test access port (tap) accesses the MT90863 test functions. it consists of three input pins and one output pin as follows: ? test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remains independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. ? test mode select input (tms) the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to vdd when it is not driven from an external source. ? test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to vdd when it is not driven from an external source. ? test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) reset the jtag scan structure. this pin is internally pulled to vdd. bit name description 15-2 (note1) unused must be zero for normal operation. 1,0 (note1) lsr1, lsr0 local sub-rate switching bit when 11 bit7-6 will be the output of the subrate switching stream when 10 bit5-4 will be the output of the subrate switching stream when 01 bit3-2 will be the output of the subrate switching stream when 00 bit1-0 will be the output of the subrate switching stream note 1: if bit 12 (lmc) of the corresponding local connection memory location is 1 (device in message mode), then these entire 8 bits (bit7-0) are output on the output channel and stream associated with this location. table 22 - local connection memory high bits 76543210 8 9 10 11 12 13 lsr0 lsr1 0 14 0 15 00 0 000 0 000 0 0 MT90863 data sheet 30 zarlink semiconductor inc. 7.2 instruction register the MT90863 uses the public instructions defined in the ieee 1149.1 standard. the jtag interface contains a two- bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-ir state. these instructions are subsequently de-coded to achieve two basic functions: to select the test data register that may operate while the instruction is current; and, to define the serial test data register path that is used to shift data between tdi and do during data register scan-ning. 7.3 test data register as specified in ieee 1149.1, the MT90863 jtag interface contains three test data registers: ? the boundary-scan registe r the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the MT90863 core logic. ? the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. ? the device identification register the device identification register is a 32-bit register. the register contents are: the lsb bit in the device identification register is the first bit clock out. the MT90863 scan register contains 212 bits. bit 0 in table 23 boundary scan register is the first bit clocked out. all tri-state enable bits are active high. device pin boundary scan bit 0 to bit 213 tri-state control output scan cell input scan cell a0 a1 a2 a3 a4 a5 a6 a7 ds r/w cs 0 1 2 3 4 5 6 7 8 9 10 table 23 - boundary scan register bits msb lsb 0000 0000 1000 0110 0011 0001 0100 1011 data sheet MT90863 31 zarlink semiconductor inc. d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 dta 59 sti0 sti1 sti2 sti3 sti4 sti5 sti6 sti7 60 61 62 63 64 65 66 67 sti8 sti9 sti10 sti11 sti12 sti13 sti14 sti15 ode 68 69 70 71 72 73 74 75 76 sto0 sto1 sto2 sto3 sto4 sto5 sto6 sto7 sto8 sto9 sto10 sto11 sto12 sto13 sto14 sto15 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 c16i f0i c4i /c8i f0o c4o 112 114 113 115 109 110 111 device pin boundary scan bit 0 to bit 213 tri-state control output scan cell input scan cell table 23 - boundary scan register bits (continued) MT90863 data sheet 32 zarlink semiconductor inc. stio0/fe0 stio1/fe1 stio2/fe2 stio3/fe3 stio4/fe4 stio5/fe5 stio6/fe6 stio7/fe7 116 119 122 125 128 131 134 137 117 120 123 126 129 132 135 138 118 121 124 127 130 133 136 139 stio8/fe8 stio9/fe9 stio10/fe10 stio11/fe11 stio12/fe12 stio13/fe13 stio14/fe14 stio15/fe15 140 143 146 149 152 155 158 161 141 144 147 150 153 156 159 162 142 145 148 151 154 157 160 163 stio16/fe16 stio17/fe17 stio18/fe18 stio19/fe19 stio20/fe20 stio21/fe21 stio22/fe22 stio23/fe23 164 167 170 173 176 179 182 185 165 168 171 174 177 180 183 186 166 169 172 175 178 181 184 187 stio24 stio25 stio26 stio27 stio28 stio29 stio30 stio31 reset 188 191 194 197 200 203 206 209 189 192 195 198 201 204 207 210 190 193 196 199 202 205 208 211 212 device pin boundary scan bit 0 to bit 213 tri-state control output scan cell input scan cell table 23 - boundary scan register bits (continued) data sheet MT90863 33 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ac electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. note: 1. maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage (v) * exceeding these values may cause permanent damage. functional operation under these conditions is not implied absolute maximum ratings* parameter symbol min max units 1 supply voltage v dd -0.5 5.0 v 2 input voltage v i -0.5 v dd +0.5 v 3 output voltage v o -0.5 v dd +0.5 v 4 package power dissipation p d 2w 5 storage temperature t s - 55 +125 c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t op -40 +85 c 2 positive supply v dd 3.0 3.6 v 3 input high voltage v ih 0.7v dd v dd v 4 input high voltage on 5v tolerant inputs v ih 5.5 v 5 input low voltage v il v ss 0.3v dd v characteristics sym min typ max units test conditions 1 i n p u t s supply current i dd 52 85 ma output unloaded 2 input high voltage v ih 0.7v dd v 3 input low voltage v il 0.3v dd v 4 input leakage (input pins) input leakage (bi-directional pins) i il i bl 10 50 a a 0 data sheet MT90863 35 zarlink semiconductor inc. ac electrical characteristics - serial streams for backplane and local interfaces note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . figure 11 - st-bus timing for stream rate of 2.048, 4.096 or 8.192 mb/s characteristic sym min typ max units test conditions 1 stio/sti set-up time t sis 0ns 2 stio/sti hold time t sih 6ns 3 sto delay - active to active t sod 51632nsc l =200pf 4 sto delay - active to high-z - high-z to active t zd 35 ns r l =1k, c l =200pf, see note 1 5 output driver enable (ode) delay t ode 35 ns f0i t fpih t fpis v tt v tt f0o c4o 4.096mhz t fpow t fpoh t fpos t c4l t c4h t dc4o t c4p v tt c16i sto/stio (8mb/s) sti/stio (8mb/s) t sod8 t sih8 t ch t cp t sis8 v tt v tt v hm v lm t r t f t f t r t cl v tt bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 0, ch 127 bit 1, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 0, ch 127 bit 1, ch 127 16.384mhz v tt v tt sto/stio (2mb/s) sti/stio (2mb/s) bit 7, ch 0 bit 0, ch 31 t sod2 bit 6, ch 0 output input output input v tt v tt stio (4mb/s) stio (4mb/s) t sih4 t sis4 bit 7, ch 0 bit 0, ch63 bit 7, ch 0 bit 6, ch 0 output input bit 6, ch 0 bit 0, ch 63 t sod4 t sih2 t sis2 bit 7, ch 0 bit 0, ch 31 t fpiw MT90863 data sheet 36 zarlink semiconductor inc. figure 12 - ct bus timing for stream rate of 2.048, 4.096 or 8.192 mb/s t f c4i /c8i t c8h t c8p t r t f v tt 8.192mhz t c8l v tt f0o c4o 4.096mhz t fpow t c4l t c4h t dc4o t c4p v tt c16i st0/stio (8mb/s) sti/stio (8mb/s) t sod8 t sih8 t ch t cp t sis8 v tt v tt v hm v lm t r t f t f t r t cl v tt bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 0, ch 127 bit 1, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 0, ch 127 bit 1, ch 127 16.384mhz v tt v tt sto/stio (2mb/s) sti/stio (2mb/s) bit 7, ch 0 bit 0, ch 31 t sod2 bit 6, ch 0 output input output input v tt v tt stio (4mb/s) stio (4mb/s) t sih4 t sis4 bit 7, ch 0 bit 0, ch63 bit 7, ch 0 bit 6, ch 0 output input bit 6, ch 0 bit 0, ch 63 t sod4 t sih2 t sis2 bit 7, ch 0 bit 0, ch 31 f0i t cfpw t cfph t cfps v tt data sheet MT90863 37 zarlink semiconductor inc. figure 13 - hmvip bus timing for stream rate of 2.048 mb/s or 8.192 mb/s figure 14 - serial output and external control f0i c4i/ c8i 4.096mhz t hfpw t hfph t hfps t dif c16i t ch t cp v tt t r t f t hf t hr t cl v tt 16.384mhz t fpow t c8l v tt f0o c4o 4.096mhz t fpoh t fpos t c4l t c4h t dc4o t c4p v tt stio (8mb/s) stio (8mb/s) t sod8 t sih8 t sis8 v tt v tt v hm v lm t f t r bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 0, ch 127 bit 1, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 0, ch 127 bit 1, ch 127 v tt v tt stio (2mb/s) stio (2mb/s) bit 7, ch 0 bit 0, ch 31 t sod2 bit 6, ch 0 output input output input t sih2 t sis2 bit 7, ch 0 bit 0, ch 31 t hcl t hch t dc4o t hcp v tt v hm v lm t dz sto t zd sto clk v tt v tt hiz valid data v tt hiz valid data MT90863 data sheet 38 zarlink semiconductor inc. figure 15 - output driver enable (ode) note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . ac electrical characteristics - motorola non-multiplexed bus mode characteristics sym min typ max units test conditions 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 10 ns 3 address setup from ds falling t ads 5ns 4cs hold after ds rising t csh 10 ns 5r/w hold after ds rising t rwh 10 ns 6 address hold after ds rising t adh 6ns 7 data setup from dta low on read reading registers reading memory t ddr_reg t ddr_mem 16 440 ns c l =50pf 8 data hold on read t dhr 11 ns c l =50pf, r l =1k note 1 9 data setup on write (fast write) t dsw_reg 2ns 10 valid data delay on write (slow write) t swd 150 ns 11 data hold on write t dhw 5ns 12 acknowledgment delay: reading/writing registers reading/writing memory t akd_reg t akd_mem 40 470 ns c l =50pf 13 acknowledgment hold time t akh 17 ns c l =50pf, r l =1k, note v tt hiz hiz sto ode t ode t ode valid data v tt data sheet MT90863 39 zarlink semiconductor inc. figure 16 - motorola non-multiplexed bus timing ds a0-a7 cs d0-d15 d0-d15 read write t css t csh t adh t dhr t rws r/w t ads t rwh t dhw t akd t swd t ddr t akh dta v tt v tt v tt v tt v tt v tt v tt t dsw valid address valid read data valid write data MT90863 data sheet 40 zarlink semiconductor inc. c zarlink semiconductor 2002 all rights reserved. apprd. issue date acn package code : ga previous package codes: 213935 1 20jan03 www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - 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