 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| advanced and ever advancing mitsubishi electric mitsubishi 8-bit single-chip microcomputer 740 family 740 family mitsubishi electric software manual
keep safety first in your circuit designs ! l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customers application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-partys rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. rev. rev. no. date 1.0 first edition 970829 revision description list 740 family software manual (1/1) revision description preface this software manual is for users of the 740 family. register structures, addressing modes and instructions are introduced in each section. the enhanced instruction set with enhanced data and memory operations enable efficient programming. please refer to the users manual appropriate for the hardware device or the development support tools used. i table of contents chapter 1. overview ............................................................................................ 1 chapter 2. central processing unit (cpu) .............................................. 2 2.1 accumulator (a) ........................................................................................................................ 2 2.2 index register x (x), index register y (y) ........................................................................ 2 2.3 stack pointer (s) ....................................................................................................................... 3 2.4 program counter (pc) ............................................................................................................. 4 2.5 processor status register (ps) .............................................................................................4 chapter 3. instructions .................................................................................... 6 3.1 addressing mode ...................................................................................................................... 6 3.2 instruction set ......................................................................................................................... 26 3.2.1 data transfer instructions ................................................................................................ 26 3.2.2 operating instruction ....................................................................................................... 27 3.2.3 bit managing instructions ...............................................................................................28 3.2.4 flag setting instructions .................................................................................................. 28 3.2.5 jump, branch and return instructions ......................................................................... 28 3.2.6 interrupt instruction (break instruction) ........................................................................ 29 3.2.7 special instructions .......................................................................................................... 29 3.2.8 other instruction .............................................................................................................. 29 3.3 description of instructions ................................................................................................... 30 chapter 4. notes on use ............................................................................... 102 4.1 notes on interrupts .............................................................................................................. 102 4.1.1 setting for interrupt request bit and interrupt enable bit ......................................... 102 4.1.2 switching of detection edge ........................................................................................ 102 4.1.3 distinction of interrupt request bit .............................................................................. 103 4.2 notes on programming ........................................................................................................104 4.2.1 processor status register ........................................................................................... 104 4.2.2 brk instruction .............................................................................................................. 105 4.2.3 decimal calculations ......................................................................................................105 4.2.4 jmp instruction .............................................................................................................. 106 appendix 1. instruction cycles in each addressing mode ........................ 107 appendix 2. 740 family machine language instruction table .................. 173 appendix 3. 740 family list of instruction codes ......................................... 179 table of contents ii table of contents 1 ov erv iew 1. overview the distinctive features of the cmos 8-bit microcomputers 740 familys software are described below: 1) an efficient instruction set and many addressing modes allow the effective use of rom. 2) the same bit management, test, and branch instructions can be performed on the accu- mulator, memory, or i/o area. 3) multiple interrupts with separate interrupt vectors allow servicing of different non-periodic events. 4) byte processing and table referencing can be easily performed using the index addressing mode. 5) decimal mode needs no software correction for proper decimal operation. 6) the accumulator does not need to be used in operations using memory and/or i/o. 2 c en tral proc essin g un it 2. central processing unit (cpu) six main registers are built into the cpu of the 740 family. the program counter (pc) is a sixteen-bit register; however, the accumulator (a), index register x (x), index register y (y), stack pointer (s) and processor status register (ps) are eight-bit registers. + except for the i flag, the contents of these registers are indeterminate after a hardware reset; therefore, initialization is required with some programs (immediately after reset the i flag is set to 1). fig.2.1.1 register configuration accumulator (a) index register x (x), index register y (y) 2.1 accumulator (a) the accumulator, an eight-bit register, is the main register of the microcomputer. this general-purpose register is used most frequently for arithmetic operations, data transfer, temporary memory, conditional judgments, etc. 2.2 index register x (x), index register y (y) the 740 family has an index register x and an index register y, both of which are eight- bit registers. when using addressing modes which use these index registers, the address, which is added the contents of index register to the address specified with operand, is accessed. these modes are extremely effective for referencing subroutine and memory tables. the index registers also have increment, decrement, compare, and data transfer functions; therefore, these registers can be used as simple accumulators. negative flag overflow flag x modified operation mode flag break flag (brk) decimal mode flag interrupt disable flag zero flag carry flag processor status register(ps) program counter(pc) stack pointer(s) index register y(y) index register x(x) accumulator(a) a x y s nvtbd i zc 0 0 0 0 0 0 0 7 7 7 7 7 7 7 h pc l pc 3 2.3 stack pointer (s) the stack pointer is an eight-bit register used for generati ng interrupts and calling subroutines. when an interrupt is received, the following procedure is pe rformed automatically in the indicated sequence: (1) the contents of the high-order eight bits of the program counter (pc h ) are saved to an address using the stack pointer contents for the low-orde r eight bits of the address. (2) the stack pointer contents are decremented by 1. (3) the contents of the low-order eight bits of the program counter (pc l ) are saved to an address using the stack pointer contents for the low-order e ight bits of the address. (4) the stack pointer contents are decremented by 1. (5) the contents of the processor status register (ps) are s aved to an address using the stack pointer contents for the low-order eight bits of the a ddress. (6) the stack pointer contents are decremented by 1. the processor status register is not saved when calling subr outines (items (5) and (6) above are not executed). the processor status register is saved by executing the php instruction in software. to prevent data loss when generating interrupts and calling subroutines, it is necessary to save other registers as well. this is done by executing the proper instruction in software while in the interrupt service routine or subroutine. the high-order eight bits of the address are determined by t he stack page selection bit. for example, the pha instruction is executed to save the con tents of the accumulator. executing the pha instruction saves the accumulator contents to an address using the stack pointer contents as the low-order eight bits of the address. the rti instruction is executed to return from an interrupt routine. when the rti instruction is executed, the following procedur e is performed automatically in sequence. (1) the stack pointer contents are incremented by 1. (2) the contents of an address using the stack pointer conte nts as the low-order eight bits of the address is returned to the processor status register (ps). (3) the stack pointer contents are incremented by 1. (4) the contents of an address using the stack pointer as th e low-order eight bits of the address is returned to the low-order eight bits of the progr am counter (pc l ). (5) the stack pointer contents are incremented by 1. (6) the contents of an address using the stack pointer as th e low-order eight bits of the address is returned to the high-order eight bits of the prog ram counter (pc h ). steps (1) and (2) are not performed when returning from a su broutine using the rts instruction. the processor status register should be restore d before returning from a subroutine by using the plp instruction. the accumulator sho uld be restored before returning from a subroutine or an interrupt servi cing routine by using the pla instruction. the pla and plp instructions increment the stack pointer by 1 and return the contents of an address stored in the stack pointer to the accumulator or pr ocessor status register, respec- tively. + saving data in the stack area gradually fills the ram area with saved data; therefore, caution must exercised concerning the depth of interrupt lev els and subroutine nesting. central processing unit stack pointer (s) 4 2.4 program counter (pc) the program counter is a sixteen-bit counter consisting of pc h and pc l , which are each eight-bit registers. the contetnts of the program counter indicates the address which an instruction to be executed next is stored. the 740 family uses a stored program system; to start a new operation it is necessary to transfer the instruction and relevant data from memory to the cpu. normally the program counter is used to indicate the next memory address. after each instruction is executed, the next instruction required is read. this cycle is repeated until the program is finished. + the control of the program counter of the 740 family is almost fully automatic. however, caution must be exercised to avoid differences between program flow and program counter contents when using the stack pointer or directly altering the contents of the program counter. 2.5 processor status register (ps) the processor status register is an eight-bit register consisting of 5 flags which indicate the status of arithmetic operations and 3 flags which determine operation. each of these flags is described below. table 2.5.1 lists the instructions to set/clear each flag. refer to the section appendix 2 machine language instruction table or 3.3 instructions for details on when these flags are altered. [ carry flag c ] ------------------------------------------------------ bit 0 this flag stores any carry or borrow from the arithmetic logic unit (alu) after an arithmetic operation and is also changed by the shift or rotate instruction. this flag is set by the sec instruction and is cleared by the clc instruction. [ zero flag z ] ------------------------------------------------------- bit 1 this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. [ interrupt disable flag i ] ---------------------------------------- bit 2 this flag disables interrupts when it is set to 1. this flag immediately becomes 1 when an interrupt is received. this flag is set by the sei instruction and is cleared by the cli instruction. [ decimal mode flag d ] ----------------------------------------- bit 3 this flag determines whether addition and subtraction are performed in binary or decimal notation. addition and subtraction are performed in binary notation when this flag is set to 0 and as a 2-digit, 1-word decimal numeral when set to 1. decimal notation correction is performed automatically at this time. this flag is set by the sed instruction and is cleared by the cld instruction. only the adc and sbc instructions are used for decimal arithmetic operations. note that the flags n, v and z are invalid when decimal arithmetic operations are per- formed by these instructions. [ break flag b ] ----------------------------------------------------- bit 4 this flag determines whether an interrupt was generated with the brk instruction. when a brk instruction interrupt occurs, the flag b is set to 1 and saved to the stack; for all other interrupts the flag is set to 0 and saved to the stack. c en tral proc essin g un it program counter (pc) processor status register (ps) 5 [ x modified operation mode flag t ] ----------------------- bit 5 this flag determines whether arithmetic operations are performed via the accumulator or directly on a memory location. when the flag is set to 0, arithmetic operations are performed between the accumulator and memory. when 1, arithmetic operations are performed directly on a memory location. this flag is set by the set instruction and is cleared by the clt instruction. (1) when the t flag = 0 a ? a * m2 * : indicates an arithmetic operation a: accumulator contents m2: contents of a memory location specified by the addressing mode of the arithmetic operation (2) when the t flag = 1 m1 ? m1 * m2 * : indicates arithmetic operation m1: contents of a memory location, designated by the contents of index register x. m2: contents of a memory location specified by the addressing mode of arithmetic operation. [ overflow flag v ] ------------------------------------------------- bit 6 this flag is set to 1 when an overflow occurs as a result of a signed arithmetic operation. an overflow occurs when the result of an addition or subtraction exceeds +127 (7f 16 ) or C128 (80 16 ) respectively. the clv instruction clears the overflow flag. there is no set instruction. the overflow flag is also set during the bit instruction when bit 6 of the value being tested is 1. + overflows do not occur when the result of an addition or subtraction is equal to or smaller than the above numerical values, or for additions involving values with different signs. [ negative flag n ] ------------------------------------------------- bit 7 this flag is set to match the sign bit (bit 7) of the result of a data or arithmetic operation. this flag can be used to determine whether the results of arithmetic operations are positive or negative, and also to perform a simple bit test. table 2.5.1 instructions to set/clear each flag of processor status register c en tral proc essin g un it processor status register (ps) flag n set instruction clear instruction flag c sec clc flag z flag i sei cli flag d sed cld flag b flag t set clt flag v clv 6 fig.3.1.1 byte structure of instructions in struc tion s addressing mode 3. instructions 3.1 addressing mode the 740 family has 19 addressing modes and a powerful memory access capability. when extracting data required for arithmetic and logic operations from memory or when storing the results of such operations in memory, a memory address must be specified. the specification of the memory address is called addressing. the data required for addressing and the registers involved are described below. the 740 family instructions can be classified into three kinds, by the number of bytes required in program memory for the instruction: 1-byte, 2-byte and 3-byte instructions. in each case, the first byte is known as the op-code (operation code) which forms the basis of the instruction. the second or third byte is called the oper- and which affects the addressing. the contents of index registers x and y can also effect the addressing. although there are many addressing modes, there is always a particular memory location specified. what differs is whether the operand, or the index register contents, or a combination of both should be used to specify the memory or jump destination. based on these 3 types of instructions, the range of variation is increased and operation is enhanced by combinations of the bit operation instructions, jump instruction, and arithmetic instructions. as for 1-byte instruction, an accumulator or a register is specified, so that the instruction does not have operand, which specify memory. aaaaa aaaaa op-code operand i operand ii 3-byte instruction index register aaaaa aaaaa op-code 1-byte instruction aaaaa aaaaa op-code operand i 2-byte instruction x y y 7 in struc tion s immediate ad d ressin g m od e : function : in stru ction s : ex a m p le : immediate specifies the operand as the data for the instruction. adc, and, cmp, cpx, cpy, eor, lda, ldx, ldy, ora, sbc mnemonic machine code d adc d #$a5 69 16 a5 16 addressing mode this symbol(#) indicates the immediate addressing mode. aaaaaa aaaaaa op-code (69 16 ) operand (a5 16 ) memory (a) ? (a) + (c) + a5 16 8 in struc tion s ac c u m u la t o r ad d ressin g m od e : function : in stru ction s : ex a m p le : accumulator specifies the contents of the accumulator as the data for the instruction. asl, dec, inc, lsr, rol, ror mnemonic machine code d rol d a2a 16 addressing mode accumulator c carry flag bit 7 bit 0 9 ze r o pa g e in struc tion s ad d ressin g m od e : function : in stru ction s : ex a m p le : zero page specifies the contents in a zero page memory location as the data for the instruction. the address in the zero page memory location is determined by using operand as the low-order byte of the address and 00 16 as the high-order byte. adc, and, asl, bit, cmp, com, cpx, cpy, dec, eor, inc, lda, ldm, ldx, ldy, lsr, ora, rol, ror, rrf, sbc, sta, stx, sty, tst mnemonic machine code d adc d $40 65 16 40 16 addressing mode 40 16 00 16 aaaaaa a aaaa a a aaaa a a aaaa a a aaaa a aaaaaa aaaaaa aaaaaa aaaaaa a aaaa a aaaaaa ff 16 (a) ? (a) + (c) + xx 16 zero page designation data(xx 16 ) op-code(65 16 ) operand (40 16 ) zero page memory 10 in struc tion s zero page x ad d ressin g m od e : function : in stru ction s : ex a m p le : zero page x specified the contents in a zero page memory location as the data for the instruction. the address in the zero page memory location is determined by the following: (a) operand and the index register x are added. (if as a result of this addition a carry occurs, it is ignored.) (b) the result of the addition is used as the low-order byte of the address and 00 16 as the high-order byte. adc, and, asl, cmp, dec, div, eor, inc, lda, ldy, lsr, mul, ora, rol, ror, sbc, sta, sty mnemonic machine code d adc d $5e,x 75 16 5e 16 addressing mode 44 16 00 16 aaaaaa a aaaa a a aaaa a a aaaa a aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa zero page data(xx 16 ) ff 16 op-code (75 16 ) operand (5e 16 ) (a) ? (a) + (c) + xx 16 + e6 16 = 1 44 16 ignored zero page x designation memory contents of index register x 11 zero page y ad d ressin g m od e : function : in stru ction s : ex a m p le : in struc tion s zero page y specifies the contents in a zero page memory location as the data for the instruction. the address in the zero page memory location is determined by the following: (a) operand and the index register y are added (if as a result of this addition a carry occurs, it is ig- nored). (b) the result of the addition is used as the low-order byte of the address and 00 16 as the high-order byte. ldx, stx mnemonic machine code d ldx d $62,y b6 16 62 16 addressing mode 68 16 00 16 aaaaaa a aaaa a a aaaa a a aaaa a aaaaaa aaaaaa aaaaaa aaaaaa aaaaaa zero page data(xx 16 ) ff 16 op-code (b6 16 ) operand (62 16 ) (x) ? xx 16 + 06 16 = 68 16 zero page y designation memory contents of index register y 12 in struc tion s ab s o lu t e ad d ressin g m od e : function : in stru ction s : ex a m p le : absolute specifies the contents in a memory location as the data for the instruction. the address in the memory location is determined by using operand i as the low- order byte of the address and operand ii as the high- order byte. adc, and, asl, bit, cmp, cpx, cpy, dec, eor, inc, jmp, jsr, lda, ldx, ldy, lsr, ora, rol, ror, sbc, sta, stx, sty mnemonic machine code d adc d $ad12 6d 16 12 16 ad 16 addressing mode aaaaaa aaaaaa op-code (6d 16 ) operand i (12 16 ) operand ii (ad 16 ) (a) ? (a) + (c) + xx 16 data (xx 16 ) memory ad12 16 absolute designation 13 in struc tion s ab s o lu t e x ad d ressin g m od e : function : in stru ction s : ex a m p le : absolute x specifies the contents in a memory location as the data for the instruction. the address in the memory location is determined by the following: (a) operand i is used as the low-order byte of an address, operand ii as the high-order byte. (b) index register x is added to the address above. the result is the address in the memory location. adc, and, asl, cmp, dec, eor, inc, lda, ldy, lsr, ora, rol, ror, sbc, sta mnemonic machine code d adc d $ad12, x 7d 16 12 16 ad 16 addressing mode + ee 16 = ae00 16 aaaaa aaaaa op-code (7d 16 ) operand i (12 16 ) operand ii (ad 16 ) (a) ? (a) + (c) + xx 16 data(xx 16 ) memory ae00 16 absolute x designation contetns of index register x 14 in struc tion s ab s o lu t e y ad d ressin g m od e : function : in stru ction s : ex a m p le : absolute y specifies the contents in a memory location as the data for the instruction. the address in the memory location is determined by the following: (a) operand i is used as the low-order byte of an address, operand ii as the high-order byte. (b) index register y is added to the address above. the result is the address in the memory location. adc, and, cmp, eor, lda, ldx, ora, sbc, sta mnemonics machine code d adc d $ad12, y 79 16 12 16 ad 16 addressing mode + ee 16 = ae00 16 aaaaaa aaaaaa op-code (79 16 ) operand i (12 16 ) operand ii (ad 16 ) (a) ? (a) + (c) + xx 16 data(xx 16 ) memory ae00 16 absolute y designation contents of index register y 15 im p lie d ad d ressin g m od e : function : in stru ction s : ex a m p le : implied operates on a given register or the accumulator, but the address is always inherent in the instruction. brk, clc, cld, cli, clt, clv, dex, dey, inx, iny, nop, pha, php, pla, plp, rti, rts, sec, sed, sei, set, stp, tax, tay, tsx, txa, txs, tya, wit mnemonic machine code d clc 18 16 in struc tion s addressing mode processor status register ? 0 carry flag bit 7 bit 0 carry flag is cleared to ?.? 16 in struc tion s re la t iv e ad d ressin g m od e : function : in stru ction s : ex a m p le : addressing mode relative specifies the address in a memory location where the next op-code is located. when the branch condition is satisfied, operand and the program counter are added. the result of this addition is the address in the memory location. when the branch condition is not satisfied, the next instruction is executed. bcc, bcs, beq, bmi, bne, bpl, bra, bvc, bvs mnemonic machine code d bcc d * C12 90 16 f2 16 decimal aaaaaa a aaaa a aaaaaa * * +2 aa aa a a a a aa aa aa aa address to be executed next op-code (90 16 ) operand (f2 16 ) jump memory aaaaaa a aaaa a aaaaaa * * +2 op-code (90 16 ) operand (f2 16 ) memory address to be executed next ?2 * when the carry flag is cleared, jumps to address ?2. when the carry flag is set, goes to address +2. * * 17 in struc tion s in direct x ad d ressin g m od e : function : in stru ction s : ex a m p le : indirect x specifies the contents in a memory location as the data for the instruction. the address in the memory location is determined by the following: (a) a zero page memory location is determined by the adding the operand and index register x (if as a result of this addition a carry occurs, it is ignored). (b) the result of the addition is used as the low-order byte of an address in the zero page memory location and 00 16 as the high-order byte. (c) the contents of the address in the zero page memory location is used as the low-order byte of the address in the memory location. (d) the next zero page memory location is used as the high-order byte of the address in the memory location. adc, and, cmp, eor, lda, ora, sbc, sta mnemonic machine code d adc d ($1e,x) 61 16 1e 16 addressing mode aaaaa aaaa a aaaa a aaaa a aaaa a aaaaa aaaaa aaaaa (a) ? (a) + (c) + xx 16 data(xx 16 ) 1400 16 op-code (61 16 ) operand (1e 16 ) 04 16 00 16 ff 16 + e6 16 = 1 04 16 ignored data ii (14 16 ) data i (00 16 ) zero page memory absolute designation zero page x designation 05 16 assuming that ?0 16 ?for data i, and ?4 16 ?for data ll are stored in advance. contents of index register x 18 in struc tion s in direct y ad d ressin g m od e : function : in stru ction s : ex a m p le : indirect y specifies the contents in a memory location as the data for the instruction. the address in the memory location is determined by the following: (a) the operand is used the low-order byte of an address in the zero page memory location and 00 16 of the high-order byte. (b) the contents of the address in the zero page memory location is used as the low-order byte of an address. the next zero page memory location is used as the high-order byte. (c) the index register y is added to the address in step b. the result of this addition is the address in the memory location. adc, and, cmp, eor, lda, ora, sbc, sta mnemonic machine code d adc d ($1e),y 71 16 1e 16 addressing mode aaaaaa a aaaa a a aaaa a a aaaa a a aaaa a aaaaaa aaaaaa aaaaaa (a) ? (a) + (c) + xx 16 data (xx 16 ) 12e7 16 op-code (71 16 ) operand (1e 16 ) 1e 16 00 16 ff 16 1201 16 + e6 16 = 12e7 16 data ii (12 16 ) data i (01 16 ) zero page memory 1f 16 absolute y designation zero page indirect designation contents of index register y assuming that ?1 16 ?for data i, and ?2 16 ?for data ll are stored in advance. 19 in struc tion s in d ir e c t ab s o lu t e ad d ressin g m od e : function : in stru ction s : ex a m p le : indirect absolute specifies the address in a memory location as the jump destination address. the address in the memory location is determined by the following: (a) operand i is used as the low-order byte of an address and operand ii as the high-order byte. (b) the contents of the address above is used as the low-order byte and the contents of the next address as the high-order byte. (c) the high-order and low-order bytes in step b together form the address in the memory location. jmp mnemonic machine code d jmp d ($1400) 6c 16 00 16 14 16 addressing mode aaaaa aaaaa op-code (6c 16 ) operand i (00 16 ) operand ii (14 16 ) aaaa a a a a a a a aa aa aa aa aa aa 1400 16 1eff 16 jump data ii (1e 16 ) data i (ff 16 ) address to be executed next indirect designation memory absolute designation ] assuming that ?f 16 ?for data i, and ?e 16 ?for data ll are stored in advance. note: the page? last address (address xxff 16 ) can not be specified for the indirect designation address; in other words, jmp ($xxff) can not be executed. 20 in struc tion s ad d ressin g m od e : function : in stru ction s : ex a m p le : zero page indirect absolute specifies the address in a memory location as the jump destination address. the address in the memory location is determined by the following: (a) operand is used as the low-order byte of an address in the zero page memory location and 00 16 as the high-order byte. (b) the contents of the address in the zero page memory location is used as the low-order byte and the contents of the next zero page memory location as high-order byte. (c) the high-order and low-order bytes in step b together form the address of the memory location. jmp, jsr mnemonic machine code d jmp d ($45) b2 16 45 16 addressing mode zero page in direct aaaaaa a aaaa a a aaaa a a aaaa a a aaaa a aaaaaa data ii (1e 16 ) data i (ff 16 ) aaaaaa aaaaaa op-code (b2 16 ) operand (45 16 ) 1eff 16 address to be executed next aaa a a a a aa aa aa jump 45 16 00 16 ff 16 46 16 absolute designation zero page zero page indirect designation * memory assuming that ?f 16 ?for data i, and ?e 16 ?for data ll are stored in advance. 21 in struc tion s special page ad d ressin g m od e : function : in stru ction s : ex a m p le : addressing mode special page specifies the address in a special page memory location as the jump destination address. the address in the special page memory location is determined by using operand as the low-order byte of the address and ff 16 as the high-order byte. jsr mnemonic machine code d jsr d \$ffc0 22 16 c0 16 this symbol indicates the special page mode. aaaaa a aaa a aaaaa op-code (22 16 ) operand (c0 16 ) aaaaa a aaa a a aaa a a aaa a a aaa a a aaa a aaaaa aaaaa aaaaa ff00 16 ffff 16 ffc0 16 special page * aaa aaa aa aa a a a a jump special page designation address to be executed next memory 22 in struc tion s zero page bit ad d ressin g m od e : function : in stru ction s : ex a m p le : zero page bit specifies one bit of the contents in a zero page memory location as the data for the instruction. operand is used as the low-order byte of the address in the zero page memory location and 00 16 as the high-order byte. the bit position is designated by the high-order three bits of the op-code. clb, seb mnemonic machine code d clb d 5,$44 bf 16 44 16 addressing mode memory zero page ff 16 00 16 44 16 op-code(bf 16 ) 0 1 1 1 1 1 1 1 ? bit 5 bit designation bit 5 44 16 zero page designation zero page operand (44 16 ) 0 23 in struc tion s ac c u m u la t o r bit ad d ressin g m od e : function : in stru ction : ex a m p le : accumulator bit specifies one bit of the accumulator as the data for the instruction. the bit position is designated by the high-order three bits of the op-code. clb, seb mnemonic machine code d clb d 5,a bb 16 addressing mode 1 1 1 1 1 1 0 accumulator ? bit 5 memory accumulator 0 bit 5 0 op-code(bb 16 ) bit designation 24 in struc tion s ad d ressin g m od e : function : in stru ction s : ex a m p le : addressing mode ac c u m u la t o r bit re la t iv e accumulator bit relative specifies the address in a memory location where the next op-code is located. the bit position is designated by the high-order three bits of the op-code. if the branch condition is satisfied, operand and the program counter are added. the result of this addition is the address in the memory location. when the branch condition is not satisfied, the next instruction is executed. bbc, bbs mnemonic machine code d bbc d 5,a, * C12 b3 16 f2 16 decimal 0 1 1 1 1 1 0 accumulator bit 5 memory 0 operand (f2 16 ) * * * address to be executed next C12 +2 jump 0 1 1 1 1 1 1 0 accumulator bit 5 memory 0 operand (f2 16 ) * * address to be executed next +2 0 when the bit 5 of the accumulator is set when the bit 5 of the accumulator is cleared op-code(b3 16 ) bit designation op-code(b3 16 ) bit designation 25 in struc tion s zero page bit relative specifies the address of a memory location where the next op-code is located. the bit position is designated by the high-order three bits of the op-code. the address in the zero page memory location is determined by using operand i as low-order byte of the address and 00 16 as the high- order byte. if the branch condition is satisfied, oper- and il and the program counter are added. the result of this addition is the address in the memory location. when the branch condition is not satisfied, the next instruction is executed. bbc, bbs mnemonic machine language d bbc d 5,$04, * C12 b7 16 04 16 f1 16 addressing mode zero page bit relative ad d ressin g m od e : function : in stru ction s : ex a m p le : decimal zero page designation 0 1 1 1 1 1 0 bit 5 memory 1 operand i (04 16 ) * address to be executed next *C12 0 1 1 1 1 1 0 1 operand i (04 16 ) * *+3 address to be executed next 0 1 bit 5 memory operand ii (f1 16 ) operand ii (f1 16 ) *+3 jump 04 16 00 16 ff 16 zero page 04 16 00 16 ff 16 zero page zero page designation when the bit 5 at address 04 16 is cleared, jumps to address * C12. when the bit 5 at address 04 16 is set, goes to address * +3. op-code(b7 16 ) bit designation op-code(b7 16 ) bit designation 26 3.2 instruction set the 740 family has 71 types of instructions. the detailed explanation of the instructions is presented in 3.3. note that some instructions cannot be used for any products. 3.2.1 data transfer instructions these instructions transfer the data between registers, register and memory, and memories. the following are data transfer instructions. in struc tion s instruction set function load memory value into accumulator, or memory where is indicated by index register x load immediate value into memory load memory contents into index register x load memory contents into index register y store accumulator into memory store index register x into memory store index register y into memory transfer accumulator to the index register x transfer index register x into the accumulator transfer accumulator into the index register y transfer index register y into the accumulator transfer stack pointer into the index register x transfer index register x into the stack pointer push accumulator onto the stack push processor status onto the stack pull accumulator from the stack pull processor status from the stack instruction lda ldm ldx ldy sta stx sty tax txa tay tya tsx txs pha php pla plp load store transfer stack operation 27 3.2.2 operating instruction the operating instructions include the operations of addition and subtraction, logic, comparison, rotation, and shift. the operating instructions are as follows: in struc tion s instruction set contents add memory contents and c flag to accumulator or memory where is indicated by index register x subtracts memory contents and c flags complement from accumulator or memory where is indicated by index register x increment accumulator or memory contents by 1 decrement accumulator or memory contents by 1 increment index register x by 1 decrement index register x by 1 increment index register y by 1 decrement index register y by 1 multiply accumulator with memory specified by zero page x addressing mode and store high-order byte of result on stack and low-order byte in accumulator quotient is stored in accumulator and ones complement of remainder is pushed onto stack and memory with accumulator or memory where is indicated by index register x or memory with accumulator or memory where is indicated by index register x exclusive-or memory with accumulator or memory where is indicated by index register x store ones complement of memory contents to memory and memory with accumulator (the result is not stored into anywhere.) test whether memory content is 0 or not compare memory contents and accumulator or memory where is indicated by index register x compare memory contents and index register x compare memory contents and index register y shift left one bit (memory contents or accumulator) shift right one bit (memory contents or accumulator) rotate one bit left with carry (memory contents or accumulator) rotate one bit right with carry (memory contents or accumulator) rotate four bits right witout carry (memory) note: for some products, multiplication and division instructions cannot be used. instructions adc sbc inc dec inx dex iny dey mul (note) div (note) and ora eor com bit tst cmp cpx cpy asl lsr rol ror rrf addition & subtraction multiplication & division logical operation comparison shift & rotate 28 in struc tion s instruction set contents clear c flag set c flag clear d flag set d flag clear i flag set i flag clear t flag set t flag clear v flag c flag : carry flag d flag : decimal mode flag i flag : interrupt disable flag t flag : x modified operation mode flag v flag : overflow flag flag setting 3.2.4 flag setting instructions the flag setting instructions clear 0 or set 1 c, d, i, t and v flags. instructions clc sec cld sed cli sei clt set clv 3.2.5 jump, branch and return instructions the jump, branch and return instructions as following are used to change program flow. jump branch return 3.2.3 bit managing instructions the bit managing instructions clear 0 or set 1 designated bits of the accumulator or memory. instructions clb seb contents clear designated bit in the accumulator or memory set designated bit in the accumulator or memory bit managing c flag : carry flag z flag : zero flag n flag : negative flag v flag : overflow flag instructions jmp bra jsr bbc bbs bcc bcs bne beq bpl bmi bvc bvs rti rts contents jump to new location jump to new location jump to new location saving the current address branch when the designated bit in the accumulator or memory is 0 branch when the designated bit in the accumulator or memory is 1 branch when the c flag is 0 branch when the c flag is 1 branch when the z flag is 0 branch when the z flag is 1 branch when the n flag is 0 branch when the n flag is 1 branch when the v flag is 0 branch when the v flag is 1 return from interrupt return from subroutine 29 instructions wit stp instruction brk contents executes a software interrupt. in struc tion s interrupt instruction set 3.2.6 interrupt instruction (break instruction) this instruction causes a software interrupt. 3.2.7 special instructions these special instructions control the oscillation and the internal clock. 3.2.8 other instruction special contents only advances the program counter. instruction nop other contents stops the internal clock. stops the oscillation of oscillator. 30 in struc tion s 3.3 description of instructions this section presents in detail the 740 family instructions by arranging mnemonics of instruc- tions alphabetically and dividing each instruction essentially into one page. the heading of each page is a mnemonic. operation, explanation and changes of status flags are indicated for each instruction. in addition, assembler coding format, machine code, byte number, and list of cycle numbers for each addressing mode are indicated. the following are symbols used in this manual: description address high-order byte data in 0 to 255 address low-order byte data in 0 to 255 zero page address data in 0 to 255 data in 0 to 255 data in 0 to 7 contents of the program counter tab or space immediate mode special page mode hexadecimal symbol addition subtraction multiplication division logical and logical or logical exclusive or contents of register, memory, etc. direction of data transfer description accumulator bit i of accumulator program counter low-order byte of program counter high-order byte of program counter processor status register stack pointer index register x index register y memory bit i of memory carry flag zero flag interrupt disable flag decimal operation mode flag break flag x modified operations mode flag overflow flag negative flag relative address break address symbol a ai pc pc l pc h ps s x y m mi c z i d b t v n rel badrs symbol hh ll zz nn i ] d # \ $ + C 5 / " ( ) ? instruction set 31 ad c ad c ad d with c arry when (t) = 0, (a) ? (a) + (m) + (c) (t) = 1, (m(x)) ? (m(x)) + (m) + (c) when t = 0, this instruction adds the contents m, c, and a; and stores the results in a and c. when t = 1, this instruction adds the contents of m(x), m and c; and stores the results in m(x) and c. when t=1, the contents of a remain unchanged, but the contents of status flags are changed. m(x) represents the contents of memory where is indicated by x. n is 1 when bit 7 is 1 after the operation; otherwise it is 0. v is 1 when the operation result exceeds +127 or C128; otherwise it is 0. no change no change no change no change z is 1 when the operation result is 0; otherwise it is 0. c is 1 when the result of a binary addition exceeds 255 or when the result of a decimal addition exceeds 99; otherwise it is 0. operation : function : status flag: n : v : t : b : i : d : z : c : byte number 2 2 2 3 3 3 2 2 statement d adc d #$nn d adc d $zz d adc d $zz,x d adc d $hhll d adc d $hhll,x d adc d $hhll,y d adc d ($zz,x) d adc d ($zz),y machine codes 69 16 , nn 16 65 16 , zz 16 75 16 , zz 16 6d 16 , ll 16 , hh 16 7d 16 , ll 16 , hh 16 79 16 , ll 16 , hh 16 61 16 , zz 16 71 16 , zz 16 cycle number 2 3 4 4 5 5 6 6 addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) notes 1: when t=1, add 3 to the cycle number. 2: when adc instruction is executed in the decimal operation mode (d = 1), decision of c is delayed. accordingly, do not execute the instruction which operates c such as sec, clc, etc. 32 an d an d logical and when (t) = 0, (a) ? (a) (m) (t) = 1, (m(x)) ? (m(x)) (m) when t = 0, this instruction transfers the contents of a and m to the alu which performs a bit-wise and operation and stores the result back in a. when t = 1, this instruction transfers the contents m(x) and m to the alu which performs a bit-wise and operation and stores the results back in m(x). when t = 1 the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. n is 1 when bit 7 is 1 after the operation; otherwise it is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise it is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) statement d and d #$nn d and d $zz d and d $zz,x d and d $hhll d and d $hhll,x d and d $hhll,y d and d ($zz,x) d and d ($zz),y machine codes 29 16 , nn 16 25 16 , zz 16 35 16 , zz 16 2d 16 , ll 16 , hh 16 3d 16 , ll 16 , hh 16 39 16 , ll 16 , hh 16 21 16 , zz 16 31 16 , zz 16 byte number 2 2 2 3 3 3 2 2 cycle number 2 3 4 4 5 5 6 6 note: when t = 1, add 3 to a cycle number. 33 asl asl a rithmetic s hift l eft operation : function : status flag : c ? b7 b0 ? 0 n : v : t : b : i : d : z : c : this instruction shifts the content of a or m by one bit to the left, with bit 0 always being set to 0 and bit 7 of a or m always being contained in c. n is 1 when bit 7 of a or m is 1 after the operation; otherwise it is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise it is 0. c is 1 when bit 7 of a or m is 1, before this operation; otherwise it is 0. cycle number 2 5 6 6 7 byte number 1 2 2 3 3 machine codes 0a 16 06 16 , zz 16 16 16 , zz 16 0e 16 , ll 16 , hh 16 1e 16 , ll 16 , hh 16 addressing mode accumulator zero page zero page x absolute absolute x statement d asl d a d asl d $zz d asl d $zz,x d asl d $hhll d asl d $hhll,x 34 bbc bbc b ranch on b it c lear when (mi) or (ai) = 0, (pc) ? (pc) + n + rel (mi) or (ai) = 1, (pc) ? (pc) + n n: if addressing mode is zero page bit relative, n=3. and if addressing mode is accumulator bit relative, n=2. this instruction tests the designated bit i of m or a and takes a branch if the bit is 0. the branch address is specified by a relative address. if the bit is 1, next instruction is executed. no change operation : function : status flag : cycle number 4 5 byte number 2 3 addressing mode accumulator bit relative zero page bit relative statement d bbc d i,a,$hhll d bbc d i,$zz,$hhll notes 1: rr 16 =$hhllC( ] +n). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 3: when executing the bbc instruction after the contents of the interrupt request bit is changed, one instruction or more must be passed before the bbc instruction is executed. machine codes (20i+13) 16 , rr 16 (20i+17) 16 , zz 16 , rr 16 35 bbs bbs b ranch on b it s et when (mi) or (ai) = 1, (pc) ? (pc) + n + rel (mi) or (ai) = 0, (pc) ? (pc) + n n : if addressing mode is zero page bit relative, n=3. and if addressing mode is accumulator bit relative, n=2. this instruction tests the designated bit i of the m or a and takes a branch if the bit is 1. the branch address is specified by a relative address. if the bit is 0, next instruction is exe- cuted. no change operation : function : status flag : machine codes (20i+3) 16 , rr 16 (20i+7) 16 , zz 16 , rr 16 cycle number 4 5 byte number 2 3 addressing mode accumulator bit relative zero page bit relative statement d bbs d i,a,$hhll d bbs d i,$zz,$hhll notes 1: rr 16 =$hhllC( ] +n). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 3: when executing the bbs instruction after the contents of the interrupt request bit is changed, one instruction or more must be passed before the bbs instruction is executed. 36 bc c bc c b ranch on c arry c lear when (c) = 0, (pc) ? (pc) + 2 + rel (c) = 1, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address if c is 0. the branch address is specified by a relative address. if c is 1, the next instruction is executed. no change operation : function : status flag : cycle number 2 byte number 2 addressing mode relative machine codes 90 16 , rr 16 statement d bcc d $hhll notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 37 bc s bc s b ranch on c arry s et when (c) = 1, (pc) ? (pc) + 2 + rel (c) = 0, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address if c is 1. the branch address is specified by a relative address. if c is 0, the next instruction is executed. no change operation : function : status flag : addressing mode relative statement d bcs d $hhll machine codes b0 16 , rr 16 byte number 2 cycle number 2 notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 38 beq beq b ranch on e qual when (z) = 1, (pc) ? (pc) + 2 + rel (z) = 0, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address when z is 1. the branch address is specified by a relative address. if z is 0, the next instruction is executed. no change operation : function : status flag : addressing mode relative statement d beq d $hhll machine codes f0 16 ,rr 16 byte number 2 cycle number 2 notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 39 bit bit test bit in memory with accumulator (a) (m) this instruction takes a bit-wise logical and of a and m contents; however, the contents of a and m are not modified. the contents of n, v, z are changed, but the contents of a, m remain unchanged. n is 1 when bit 7 of m is 1; otherwise it is 0. v is 1 when bit 6 of m is 1; otherwise it is 0. no change no change no change no change z is 1 when the result of the operation is 0; otherwise z is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : cycle number 3 4 machine codes 24 16 , zz 16 2c 16 , ll 16 , hh 16 statement d bit d $zz d bit d $hhll byte number 2 3 addressing mode zero page absolute 40 bm i bm i b ranch on result mi nus when (n) = 1, (pc) ? (pc) + 2 + rel (n) = 0, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address when n is 1. the branch address is specified by a relative address. if n is 0, the next instruction is executed. no change operation : function : status flag : statement d bmi d $hhll addressing mode relative machine codes 30 16 , rr 16 byte number 2 cycle number 2 notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 41 bn e bn e b ranch on n ot e qual when (z) = 0, (pc) ? (pc) + 2 + rel (z) = 1, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address if z is 0. the branch address is specified by a relative address. if z is 1, the next instruction is executed. no change operation : function : status flag : cycle number 2 byte number 2 machine codes d0 16 , rr 16 statement d bne d $hhll addressing mode relative notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 42 bpl bpl b ranch on result pl us when (n) = 0, (pc) ? (pc) + 2 + rel (n) = 1, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address if n is 0. the branch address is specified by a relative address. if n is 1, the next instruction is executed. no change operation : function : status flag : addressing mode relative statement d bpl d $hhll machine codes 10 16 , rr 16 byte number 2 cycle number 2 notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 43 bra bra br anch a lways (pc) ? (pc) + 2 + rel this instruction branches to the appointed address. the branch address is specified by a relative address. no change operation : function : status flag : cycle number 4 byte number 2 machine codes 80 16 , rr 16 statement d bra d $hhll addressing mode relative note: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 44 brk brk force br ea k (b) ? 1 (pc) ? (pc) + 2 (m(s)) ? (pc h ) (s) ? (s) C 1 (m(s)) ? (pc l ) (s) ? (s) C 1 (m(s)) ? (ps) (s) ? (s) C 1 (i) ? 1 (pc) ? badrs (note 1) when the brk instruction is executed, the cpu pushes the current pc contents onto the stack. the badrs designated in the interrupt vector table is stored into the pc. no change no change no change 1 1 no change no change no change operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode implied statement d brk d machine codes 00 16 byte number 1 cycle number 7 notes 1: badrs means a break address. 2: the value of the pc pushed onto the stack by the execution of the brk instruction is the brk instruction address plus two. therefore, the byte following the brk will not be executed when the value of the pc is returned from the brk routine. 3: both after the brk instruction is executed and after int is input, the program is branched to the address where is specified by the inter- rupt vector table. by testing the value of the b flag in the ps (pushed on the stack) in the interrupt service routine, the user can determine if the interrupt was caused by the brk instruction. 45 bv c bv c b ranch on o v erflow c lear when (v) = 0, (pc) ? (pc) + 2 + rel (v) = 1, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address if v is 0. the branch address is specified by a relative address. if v is 1, the next instruction is executed. no change operation : function : status flag : machine codes 50 16 , rr 16 cycle number 2 byte number 2 addressing mode relative statement d bvc d $hhll notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 46 bv s bv s b ranch on o v erflow s et when (v) = 1, (pc) ? (pc) + 2 + rel (v) = 0, (pc) ? (pc) + 2 this instruction takes a branch to the appointed address when v is 1. the branch address is specified by a relative address. when v is 0, the next instruction is executed. no change operation : function : status flag : cycle number 2 byte number 2 machine codes 70 16 , rr 16 statement d bvs d $hhll addressing mode relative notes 1: rr 16 =$hhllC( ] +2). the rr 16 is a value in a range of C128 to +127. 2: when a branch is executed, add 2 to the cycle number. 47 clb clb cl ear b it (ai) ? 0, or (mi) ? 0 this instruction clears the designated bit i of a or m. no change operation : function : status flag : machine codes (20i+1b) 16 (20i+1f) 16 , zz 16 byte number 1 2 cycle number 2 5 statement d clb d i,a d clb d i,$zz addressing mode accumulator bit zero page bit 48 clc clc cl ear c arry flag (c) ? 0 this instruction clears c. no change no change no change no change no change no change no change 0 operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode implied statement d clc machine codes 18 16 byte number 1 cycle number 2 49 cld cld cl ear d ecimal mode (d) ? 0 this instruction clears d. no change no change no change no change no change 0 no change no change operation : function : status flag: statement d cld machine codes d8 16 byte number 1 n : v : t : b : i : d : z : c : addressing mode implied cycle number 2 50 cli cli cl ear i nterrupt disable status addressing mode implied statement d cli machine codes 58 16 byte number 1 cycle number 2 operation : function : status flag: n : v : t : b : i : d : z : c : (i) ? 0 this instruction clears i. no change no change no change no change 0 no change no change no change 51 clt clt cl ear t ransfer flag (t) ? 0 this instruction clears t. no change no change 0 no change no change no change no change no change operation : function : status flag: addressing mode implied machine codes 12 16 byte number 1 cycle number 2 statement d clt n : v : t : b : i : d : z : c : 52 clv clv cl ear o v erflow flag (v) ? 0 this instruction clears v. no change 0 no change no change no change no change no change no change operation : function : status flag addressing mode implied byte number 1 machine codes b8 16 statement d clv n : v : t : b : i : d : z : c : cycle number 2 53 cm p cm p c o mp are when (t) = 0, (a) C (m) (t) = 1, (m(x)) C (m) when t = 0, this instruction subtracts the contents of m from the contents of a. the result is not stored and the contents of a or m are not modified. when t = 1, the cmp subtracts the contents of m from the contents of m(x). the result is not stored and the contents of x, m, and a are not modified. m(x) represents the contents of memory where is indicated by x. n is 1 when bit 7 of the operation result is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when the subtracted result is equal to or greater than 0; otherwise c is 0. operation : function : status flag: cycle number 2 3 4 4 5 5 6 6 addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) statement d cmp d #$nn d cmp d $zz d cmp d $zz,x d cmp d $hhll d cmp d $hhll,x d cmp d $hhll,y d cmp d ($zz,x) d cmp d ($zz),y machine codes c9 16 , nn 16 c5 16 , zz 16 d5 16 , zz 16 cd 16 , ll 16 , hh 16 dd 16, ll 16 , hh 16 d9 16 , ll 16 , hh 16 c1 16 , zz 16 d1 16 , zz 16 byte number 2 2 2 3 3 3 2 2 note: when t=1, add 1 to the cycle number. n : v : t : b : i : d : z : c : 54 com com com plement (m) ? (m) this instruction takes the ones complement of the contents of m and stores the result in m. n is 1 when bit 7 of the m is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag : addressing mode zero page statement d com d $zz machine codes 44 16 , zz 16 cycle number 5 byte number 2 n : v : t : b : i : d : z : c : 55 cpx cpx c om p are memory and index register x (x) C (m) this instruction subtracts the contents of m from the contents of x. the result is not stored and the contents of x and m are not modified. n is 1 when bit 7 of the operation result is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when the subtracted result is equal to or greater than 0; otherwise c is 0. operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode immediate zero page absolute statement d cpx d #$nn d cpx d $zz d cpx d $hhll machine codes e0 16 , nn 16 e4 16 , zz 16 ec 16 , ll 16 , hh 16 cycle number 2 3 4 byte number 2 2 3 56 cpy cpy c om p are memory and index register y (y) C (m) this instruction subtracts the contents of m from the contents of y. the result is not stored and the contents of y and m are not modified. n is 1 when bit 7 of the operation result is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when the subtracted result is equal to or greater than 0; otherwise c is 0. operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode immediate zero page absolute machine codes c0 16 , nn 16 c4 16 , zz 16 cc 16 , ll 16 , hh 16 cycle number 2 3 4 byte number 2 2 3 statement d cpy d #$nn d cpy d $zz d cpy d $hhll 57 dec dec dec rement by one (a) ? (a) C 1, or (m) ? (m) C 1 this instruction subtracts 1 from the contents of a or m. n is 1 when bit 7 is 1 after the addition; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: addressing mode accumulator zero page zero page x absolute absolute x machine codes 1a 16 c6 16 , zz 16 d6 16 , zz 16 ce 16 , ll 16 , hh 16 de 16 , ll 16 , hh 16 cycle number 2 5 6 6 7 byte number 1 2 2 3 3 statement d dec d a d dec d $zz d dec d $zz,x d dec d $hhll d dec d $hhll,x n : v : t : b : i : d : z : c : 58 dex dex de crement index register x by one (x) ? (x) C 1 this instruction subtracts one from the current contents of x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode implied machine codes ca 16 byte number 1 cycle number 2 statement d dex 59 dey dey de crement index register y by one (y) ? (y) C 1 this instruction subtracts one from the current contents of y. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode implied statement d dey machine codes 88 16 cycle number 2 byte number 1 60 (a) ? (m(zz+(x)+1),m(zz+(x)) / (a) m(s) ? ones complement of remainder (s) ? (s) C 1 divides the 16-bit data in m(zz+(x)) (low-order byte) and m(zz+(x)+1) (high-order byte) by the contents of a. the quotient is stored in a and the ones complement of the remainder is pushed onto the stack. no change div div div ide memory by accumulator addressing mode zero page x statement d div d $zz,x machine codes e2 16 , zz 16 byte number 2 cycle number 16 notes 1: the quotients overflow and zero division can not be detected. check the quotients overflow and zero division by software before div instruction is executed. this instruction changes the stack pointer and the contents of the accumulator. 2: the div instruction can not be used for any products. operation : function : status flag : m (zz+(x)) m (zz+(x)+1) m(s) zero page dividend low-order dividend high-order one's complement of remainder divisior quotient (a) (a) 61 eor eor e xclusive or memory with accumulator operation : function : status flag: when (t) = 0, (a) ? (a) " (m) (t) = 1, (m(x)) ? (m(x)) " (m) when t = 0, this instruction transfers the contents of the m and a to the alu which performs a bit-wise exclusive or, and stores the result in a. when t = 1, the contents of m(x) and m are transferred to the alu, which performs a bit-wise exclusive or and stores the results in m(x). the contents of a remain unchanged, but sta- tus flags are changed. m(x) represents the contents of memory where is indicated by x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change n : v : t : b : i : d : z : c : addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) machine codes 49 16 , nn 16 45 16 , zz 16 55 16 , zz 16 4d 16 , ll 16 , hh 16 5d 16 , ll 16 , hh 16 59 16 , ll 16 , hh 16 41 16 , zz 16 51 16 , zz 16 cycle number 2 3 4 4 5 5 6 6 byte number 2 2 2 3 3 3 2 2 note: when t=1, add 3 to the cycle number. statement d eor d #$nn d eor d $zz d eor d $zz,x d eor d $hhll d eor d $hhll,x d eor d $hhll,y d eor d ($zz,x) d eor d ($zz),y 62 in c in c inc rement by one operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode accumulator zero page zero page x absolute absolute x statement d inc d a d inc d $zz d inc d $zz,x d inc d $hhll d inc d $hhll,x machine codes 3a 16 e6 16 , zz 16 f6 16 , zz 16 ee 16 , ll 16 , hh 16 fe 16 , ll 16 , hh 16 cycle number 2 5 6 6 7 byte number 1 2 2 3 3 (a) ? (a) + 1, or (m) ? (m) + 1 this instruction adds one to the contents of a or m. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change 63 in x in x in crement index register x by one operation : function : status flag: (x) ? (x) + 1 this instruction adds one to the contents of x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change n : v : t : b : i : d : z : c : statement d inx machine codes e8 16 cycle number 2 byte number 1 addressing mode implied 64 in y in y in crement index register y by one (y) ? (y) + 1 this instruction adds one to the contents of y. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change cycle number operation : function : status flag: addressing mode implied statement d iny machine codes c8 16 byte number 1 2 n : v : t : b : i : d : z : c : 65 jm p jm p j ump operation : function : status flag: when addressing mode is (a) absolute, then (pc) ? hhll (b) indirect absolute, then (pc l ) ? (hhll) (pc h ) ? (hhll+1) (c) zero page indirect absolute, then (pc l ) ? (zz) (pc h ) ? (zz+1) this instruction jumps to the address designated by the following three addressing modes: absolute indirect absolute zero page indirect absolute no change cycle number 3 5 4 byte number 3 3 2 machine codes 4c 16 ,ll 16 ,hh 16 6c 16 ,ll 16 ,hh 16 b2 16 ,zz 16 statement d jmp d $hhll d jmp d ($hhll) d jmp d ($zz) addressing mode absolute indirect absolute zero page indirect 66 jsr jsr j ump to s ub r outine (m(s)) ? (pc h ) (s) ? (s) C 1 (m(s)) ? (pc l ) (s) ? (s) C 1 after the above operations, if the addressing mode is (a) absolute, then (pc) ? hhll (b) special page, then (pc l ) ? ll (pc h ) ? ff 16 (c) zero page indirect, then (pc l ) ? (zz) (pc h ) ? (zz+1) this instruction stores the contents of the pc in the stack, then jumps to the address designated by the following addressing modes: absolute special page zero page indirect absolute no change operation : function : status flag: cycle number 6 5 7 (note) \ (5c 16 of the ascii code) denotes special page. hh 16 must be ff 16 in the special page addressing mode. byte number 3 2 2 machine codes 20 16 , ll 16 , hh 16 22 16 , ll 16 02 16 , zz 16 statement d jsr d $hhll d jsr d \$hhll (note) d jsr d ($zz) addressing mode absolute special page zero page indirect 67 ld a ld a l oa d a ccumulator with memory operation : function : status flag: when (t) = 0, (a) ? (m) (t) = 1, (m(x)) ? (m) when t = 0, this instruction transfers the contents of m to a. when t = 1, this instruction transfers the contents of m to (m(x)). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change n : v : t : b : i : d : z : c : cycle number 2 3 4 4 5 5 6 6 byte number 2 2 2 3 3 3 2 2 machine codes a9 16 , nn 16 a5 16 , zz 16 b5 16 , zz 16 ad 16 , ll 16 , hh 16 bd 16 , ll 16 , hh 16 b9 16 , ll 16 , hh 16 a1 16 , zz 16 b1 16 , zz 16 statement d lda d #$nn d lda d $zz d lda d $zz,x d lda d $hhll d lda d $hhll,x d lda d $hhll,y d lda d ($zz,x) d lda d ($zz),y addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) note: when t = 1, add 2 to the cycle number. 68 ld m ld m l oad immediate d ata to m emory (m) ? nn this instruction loads the immediate value in m. no change cycle number 4 byte number 3 machine codes 3c 16 , nn 16 , zz 16 statement d ldm d #$nn,$zz addressing mode zero page operation : function : status flag : 69 ld x ld x l oa d index register x from memory (x) ? (m) this instruction loads the contents of m in x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : cycle number 2 3 4 4 5 byte number 2 2 2 3 3 machine codes a2 16 , nn 16 a6 16 , zz 16 b6 16 , zz 16 ae 16 , ll 16 , hh 16 be 16 , ll 16 , hh 16 statement d ldx d #$nn d ldx d $zz d ldx d $zz,y d ldx d $hhll d ldx d $hhll,y addressing mode immediate zero page zero page y absolute absolute y 70 ld y ld y l oa d index register y from memory (y) ? (m) this instruction loads the contents of m in y. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change addressing mode immediate zero page zero page x absolute absolute x statement d ldy d #$nn d ldy d $zz d ldy d $zz,x d ldy d $hhll d ldy d $hhll,x machine codes a0 16 , nn 16 a4 16 , zz 16 b4 16 , zz 16 ac 16 , ll 16 , hh 16 bc 16 , ll 16 , hh 16 cycle number 2 3 4 4 5 byte number 2 2 2 3 3 operation : function : status flag: n : v : t : b : i : d : z : c : 71 lsr lsr l ogical s hift r ight this instruction shifts either a or m one bit to the right such that bit 7 of the result always is set to 0, and the bit 0 is stored in c. 0 no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when the bit 0 of either the a or the m before the operation is 1; otherwise c is 0. operation : function : status flag: 0 ? b7 b0 ? c n : v : t : b : i : d : z : c : cycle number 2 5 6 6 7 byte number 1 2 2 3 3 machine codes 4a 16 46 16 , zz 16 56 16 , zz 16 4e 16 , ll 16 , hh 16 5e 16 , ll 16 , hh 16 statement d lsr d a d lsr d $zz d lsr d $zz,x d lsr d $hhll d lsr d $hhll,x addressing mode accumulator zero page zero page x absolute absolute x 72 m(s) ? (a) ? (a) 5 m(zz+(x)) (s) ? (s) C 1 multiplies accumulator with the memory specified by the zero page x addressing mode and stores the high-order byte of the result on the stack and the low-order byte in a. no change mul mul mul tiply accumulator and memory operation : function : status flag : m(zz+(x)) m(s) zero page multiplicant product multiplier (a) (a) statement d mul d $zz,x machine codes 62 16 , zz 16 cycle number 15 byte number 2 addressing mode zero page x notes 1: this instruction changes the contents of s and a. 2: the mul instruction can not be used for some products. high-order low-order 73 nop nop n o op eration addressing mode implied statement d nop (pc) ? (pc) + 1 this instruction adds one to the pc but does no other operation. no change operation : function : status flag : cycle number 2 byte number 1 machine codes ea 16 74 ora ora or memory with a ccumulator operation : function : status flag: when (t) = 0, (a) ? (a) (m) (t) = 1, (m(x)) ? (m(x)) (m) when t = 0, this instruction transfers the contents of a and m to the alu which performs a bit-wise or, and stores the result in a. when t = 1, this instruction transfers the contents of m(x) and the m to the alu which performs a bit-wise or, and stores the result in m(x). the contents of a remain unchanged, but status flags are changed. m(x) represents the contents of memory where is indicated by x. n is when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the execution result is 0; otherwise z is 0. no change n : v : t : b : i : d : z : c : cycle number 2 3 4 4 5 5 6 6 byte number 2 2 2 3 3 3 2 2 statement d ora d #$nn d ora d $zz d ora d $zz,x d ora d $hhll d ora d $hhll,x d ora d $hhll,y d ora d ($zz,x) d ora d ($zz),y addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) machine codes 09 16 , nn 16 05 16 , zz 16 15 16 , zz 16 0d 16 , ll 16 , hh 16 1d 16 , ll 16 , hh 16 19 16 , ll 16 , hh 16 01 16 , zz 16 11 16 , zz 16 note: when t=1, add 3 to the cycle number. 75 ph a ph a p us h a ccumulator on stack operation : function : status flag : (m(s)) ? (a) (s) ? (s) C 1 this instruction pushes the contents of a to the memory location designated by s, and decrements the contents of s by one. no change machine codes 48 16 statement d pha cycle number 3 byte number 1 addressing mode implied 76 ph p ph p p us h p rocessor status on stack (m(s)) ? (ps) (s) ? (s) C 1 this instruction pushes the contents of ps to the memory loca- tion designated by s and decrements the contents of s by one. no change operation : function : status flag: cycle number 3 byte number 1 machine codes 08 16 statement d php addressing mode implied 77 pla pla p u l l a ccumulator from stack operation : function : status flag: (s) ? (s) + 1 (a) ? (m(s)) this instruction increments s by one and stores the contents of the memory designated by s in a. n is 1 when bit 7 is 1 after the operation ; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change n : v : t : b : i : d : z : c : cycle number 4 byte number 1 machine codes 68 16 statement d pla addressing mode implied 78 plp plp p u l l p rocessor status from stack (s) ? (s) + 1 (ps) ? (m(s)) this instruction increments s by one and stores the contents of the memory location designated by s in ps. value returns to the original one that was pushed in the stack. operation : function : status flag : cycle number 4 byte number 1 machine codes 28 16 statement d plp addressing mode implied 79 rol rol r otate o ne bit l eft operation : function : status flag: this instruction shifts either a or m one bit left through c. c is stored in bit 0 and bit 7 is stored in c. n is 1 when bit 6 is 1 before the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when bit 7 is 1 before the operation; otherwise c is 0. b7 b0 c cycle number 2 5 6 6 7 byte number 1 2 2 3 3 machine codes 2a 16 26 16 , zz 16 36 16 , zz 16 2e 16 , ll 16 , hh 16 3e 16 , ll 16 , hh 16 statement d rol d a d rol d $zz d rol d $zz,x d rol d $hhll d rol d $hhll,x addressing mode accumulator zero page zero page x absolute absolute x n : v: t: b: i: d: z: c: 80 ror ror r otate o ne bit r ight this instruction shifts either a or m one bit right through c. c is stored in bit 7 and bit 0 is stored in c. n is 1 when c is 1 before the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when bit 0 is 1 before the operation; otherwise c is 0. operation : function : status flag: c b7 b0 cycle number 2 5 6 6 7 byte number 1 2 2 3 3 machine codes 6a 16 66 16 , zz 16 76 16 , zz 16 6e 16 , ll 16 , hh 16 7e 16 , ll 16 , hh 16 statement d ror d a d ror d $zz d ror d $zz,x d ror d $hhll d ror d $hhll,x addressing mode accumulator zero page zero page x absolute absolute x n : v: t: b: i: d: z: c: 81 rrf rrf r otate r ight of f our bits operation : function : status flag : b7 b4 b3 b0 this instruction rotates 4 bits of the m content to the right. no change cycle number 8 byte number 2 machine codes 82 16 , zz 16 statement d rrf d $zz addressing mode zero page 82 rti rti r e t urn from i nterrupt (s) ? (s) + 1 (ps) ? (m(s)) (s) ? (s) + 1 (pc l ) ? (m(s)) (s) ? (s) + 1 (pc h ) ? (m(s)) this instruction increments s by one, and stores the contents of the memory location designated by s in ps. s is again incremented by one and stores the contents of the memory location designated by s in pc l . s is again incremented by one and stores the contents of memory location designated by s in pc h . value returns to the original one that was pushed in the stack. (s) ? (s) + 1 operation : function : status flag : cycle number 6 byte number 1 statement d rti addressing mode implied machine codes 40 16 83 rts rts r e t urn from s ubroutine operation : function : status flag: (pc l ) ? (m(s)) (s) ? (s) + 1 (pc h ) ? (m(s)) (pc) ? (pc) + 1 this instruction increments s by one and stores the contents of the memory location designated by s in pc l . s is again incremented by one and the contents of the memory location is stored in pc h . pc is incremented by 1. no change addressing mode implied statement d rts machine codes 60 16 cycle number 6 byte number 1 84 sbc sbc s u b tract with c arry when (t) = 0, (a) ? (a) C (m) C (c) (t) = 1, (m(x)) ? (m(x)) C (m) C (c) when t = 0, this instruction subtracts the value of m and the complement of c from a, and stores the results in a and c. when t = 1, the instruction subtracts the contents of m and the complement of c from the contents of m(x), and stores the results in m(x) and c. a remain unchanged, but status flag are changed. m(x) represents the contents of memory where is indicated by x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. v is 1 when the operation result exceeds +127 or C128; otherwise v is 0. no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. c is 1 when the subtracted result is equal to or greater than 0; otherwise c is 0. operation : function : status flag: n : v : t : b : i : d : z : c : cycle number 2 3 4 4 5 5 6 6 byte number 2 2 2 3 3 3 2 2 machine codes e9 16 , nn 16 e5 16 , zz 16 f5 16 , zz 16 ed 16 , ll 16 , hh 16 fd 16 , ll 16 , hh 16 f9 16 , ll 16 , hh 16 e1 16 , zz 16 f1 16 , zz 16 statement d sbc d #$nn d sbc d $zz d sbc d $zz,x d sbc d $hhll d sbc d $hhll,x d sbc d $hhll,y d sbc d ($zz,x) d sbc d ($zz),y addressing mode immediate zero page zero page x absolute absolute x absolute y (indirect x) (indirect y) notes 1: when t=1, add 3 to the cycle number. 2: when sbc instruction is executed in the decimal operation mode (d = 1), decision of c is delayed. accordingly, do not execute the instruction which operates c such as sec, clc, etc. 85 seb seb se t b it (ai) ? 1, or (mi) ? 1 this instruction sets the designated bit i of a or m. no change operation : function : status flag: cycle number 2 5 byte number 1 2 machine codes (20i+b) 16 (20i+f) 16 , zz 16 statement d seb d i,a d seb d i,$zz addressing mode accumulator bit zero page bit 86 sec sec se t c arry flag (c) ? 1 this instruction sets c. no change no change no change no change no change no change no change 1 operation : function : status flag: cycle number 2 byte number 1 machine code 38 16 statement d sec addressing mode implied n : v : t : b : i : d : z : c : 87 sed sed se t d ecimal mode (d) ? 1 this instruction set d. no change no change no change no change no change 1 no change no change operation : function : status flag: n : v : t : b : i : d : z : c : machine codes f8 16 byte number 1 cycle number 2 statement d sed addressing mode implied 88 (i) ? 1 this instruction sets i. no change no change no change no change 1 no change no change no change sei sei se t i nterrupt disable flag operation : function : status flag : n : v : t : b : i : d : z : c : cycle number 2 byte number 1 machine codes 78 16 statement d sei addressing mode implied 89 set set se t t ransfer flag (t) ? 1 this instruction sets t. no change no change 1 no change no change no change no change no change operation : function : status flag: n : v : t : b : i : d : z : c : cycle number 2 byte number 1 machine codes 32 16 statement d set addressing mode implied 90 sta sta st ore a ccumulator in memory (m) ? (a) this instruction stores the contents of a in m. the contents of a does not change. no change operation : function : status flag: cycle number 4 5 5 6 6 7 7 byte number 2 2 3 3 3 2 2 statement d sta d $zz d sta d $zz,x d sta d $hhll d sta d $hhll,x d sta d $hhll,y d sta d ($zz,x) d sta d ($zz),y addressing mode zero page zero page x absolute absolute x absolute y (indirect x ) (indirect y) machine codes 85 16 , zz 16 95 16 , zz 16 8d 16 , ll 16 , hh 16 9d 16 , ll 16 , hh 16 99 16 , ll 16 , hh 16 81 16 , zz 16 91 16 , zz 16 91 stp stp st o p cpu ? stand-by state (oscillation stopped) this instruction resets the oscillation control f/f and the oscil- lation stops. reset or interrupt input is needed to wake up from this mode. no change operation : function : status flag: cycle number 2 byte number 1 machine codes 42 16 statement d stp addressing mode implied note: if the stp instruction is disabled the cycle number will be 2 (same in operation as nop). however, disabling this instruction is an optional feature; therefore, consult the specifications for the particular chip in question. 92 stx stx st ore index register x in memory (m) ? (x) this instruction stores the contents of x in m. the contents of x does not change. no change operation : function : status flag: byte number 2 2 3 cycle number 4 5 5 machine codes 86 16 , zz 16 96 16 , zz 16 8e 16 , ll 16 , hh 16 statement d stx d $zz d stx d $zz,y d stx d $hhll addressing mode zero page zero page y absolute 93 sty sty st ore index register y in memory (m) ? (y) this instruction stores the contents of y in m. the contents of y does not change. no change operation : function : status flag: cycle number 4 5 5 byte number 2 2 3 machine codes 84 16 , zz 16 94 16 , zz 16 8c 16 , ll 16 , hh 16 statement d sty d $zz d sty d $zz,x d sty d $hhll addressing mode zero page zero page x absolute 94 tax tax t ransfer a ccumulator to index register x (x) ? (a) this instruction stores the contents of a in x. the contents of a does not change. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : cycle number 2 byte number 1 machine codes aa 16 statement d tax addressing mode implied 95 tay tay t ransfer a ccumulator to index register y (y) ? (a) this instruction stores the contents of a in y. the contents of a does not change. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change cycle number 2 byte number 1 machine codes a8 16 statement d tay addressing mode implied n : v : t : b : i : d : z : c : operation : function : status flag: 96 tst tst t e st for negative or zero (m) = 0 ? this instruction tests whether the contents of m are 0 or not and modifies the n and z. n is 1 when bit 7 of m is 1; otherwise n is 0. no change no change no change no change no change z is 1 when the m content is 0; otherwise z is 0. no change operation : function : status flag: n : v : t : b : i : d : z : c : addressing mode zero page statement d tst d $zz machine codes 64 16 , zz 16 byte number 2 cycle number 3 97 tsx tsx t ransfer s tack pointer to index register x (x) ? (s) this instruction transfers the contents of s in x. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change cycle number 2 byte number 1 machine codes ba 16 statement d tsx addressing mode implied operation : function : status flag: n : v : t : b : i : d : z : c : 98 txa txa t ransfer index register x to a ccumulator (a) ? (x) this instruction stores the contents of x in a. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: cycle number 2 byte number 1 machine codes 8a 16 statement d txa addressing mode implied n : v: t: b: i: d: z: c: 99 txs txs t ransfer index register x to s tack pointer (s) ? (x) this instruction stores the contents of x in s. no change operation : function : status flag cycle number 2 byte number 1 machine codes 9a 16 statement d txs addressing mode implied 100 ty a ty a t ransfer index register y to a ccumulator (a) ? (y) this instruction stores the contents of y in a. n is 1 when bit 7 is 1 after the operation; otherwise n is 0. no change no change no change no change no change z is 1 when the operation result is 0; otherwise z is 0. no change operation : function : status flag: cycle number 2 byte number 1 machine codes 98 16 statement d tya addressing mode implied n : v: t: b: i: d: z: c: 101 wit wit w a it operation : function : status flag : cpu ? wait state the wit instruction stops the internal clock but not the oscillation of the oscillation circuit is not stopped. cpu starts its function after the timer x over flows (comes to the terminal count). all registers or internal memory contents except timer x will not change during this mode. (of course needs v dd ). no change cycle number 2 byte number 1 machine codes c2 16 addressing mode implied statement d wit 102 n otes on use 4. notes on use 4.1 notes on interrupts 4.1.1 setting for interrupt request bit and interrupt enable bit to set an interrupt request bit and an interrupt enable bit for interrupts, execute as the following sequence: clear an interrupt request bit to 0 (no interrupt request issued). set an interrupt enable bit to 1 (interrupts enabled). l reason if the above setting are performed simultaneously with one instruction, an unnecessary interrupt processing routine is executed. because an interrupt enable bit is set to 1 (interrupts enabled) before an interrupt request bit is cleared to 0. 4.1.2 switching of detection edge for the products able to switch the external interrupt detection edge, switch it as the following sequence. fig. 4.1.1 switching sequence of detection edge l reason the interrupt circuit recognizes the switching of the detection edge as the change of external input signals. this may cause to execute an unnecessary interrupt processing routine. clear an interrupt enable bit to ??(interrupt disabled) switch the detection edge clear an interrupt request bit to ??(no interrupt request issued) set the interrupt enable bit to ??(interrupt enabled) 103 n otes on use 4.1.3 distinction of interrupt request bit when executing the bbc or bbs instruction to an interrupt request (request distinguish) bit of an interrupt request register (interrupt request distinguish register) immediately after this bit is set to 0 by using a data transfer instruction ] , execute one or more instructions before executing the bbc or bbs instruction. fig. 4.1.2 distinction sequence of interrupt request bit ] data transfer instruction : ldm, lda, sta, stx, sty l reason if the bbc or bbs instruction is executed immediately after an interrupt request (request distinguish) bit of an interrupt request register (interrupt request distinguish register) is cleared to 0, the value of the interrupt request (request distinguish) bit before being cleared to 0 is read. clear an interrupt request (request distinguish) bit to ?? (no interrupt request issued) nop instruction (one or more instructions) execute the bbc or bbs instruction 104 n otes on use 4.2 notes on programming 4.2.1 processor status register (1) initialization of processor status register flags which affect program execution must be initialized after a reset. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. l reason after a reset, the contents of processor status register (ps) are undefined except for the i flag which is 1. fig. 4.2.1 initialization of flags in processor status register (2) how to reference processor status register to reference the contents of the processor status register (ps), execute the php instruction once then read the contents of (s + 1). if necessary, execute the plp instruction to return the ps to its original status. a nop instruction should be executed after every plp instruction. reset flags initializing main program fig. 4.2.2 plp instruction execution sequence plp instruction nop instruction fig. 4.2.3 stack memory contents after php instruction execution (s) (s) + 1 saved ps 105 n otes on use 4.2.2 brk instruction (1) method detecting interrupt source it can be detected that the brk instruction interrupt event or the least priority interrupt event by referring the stored b flag state. refer the stored b flag state in the interrupt routine, in this case. fig. 4.2.4 contents of stack memory in interrupt processing routine (2) interrupt priority level at the following status, the interrupt request bit has set to 1. the interrupt enable bit has set to 1. a the interrupt disable flag (i) has set to 1. if the brk instruction is executed, the interrupt disable state is cancelled and it becomes in the interrupt enable state. so that the requested interrupts (the interrupts that corresponding to their request bits have set to 1) are accepted. 4.2.3 decimal calculations (1) execution of decimal calculations the adc and sbc are the only instructions which will yield proper decimal results in decimal mode. to calculate in decimal notation, set the decimal mode flag (d) to 1 with the sed instruction. after executing the adc or sbc instruction, execute another instruction before executing the sec, clc, or cld instruction. pc l (program counter low-order) 1 = b flag ps 7 4 0 (s) pc h (program counter high-order) (s) + 1 106 n otes on use (2) status flags in decimal mode when decimal mode is selected (d = 1), the values of three of the flags in the status register (the flags n, v, and z) are invalid after a adc or sbc instruction is executed. the carry flag (c) is set to 1 if a carry is generated as a result of the calculation, or is cleared to 0 if a borrow is generated. to determine whether a calculation has generated a carry, the c flag must be initialized to 0 before each calculation. to check for a borrow, the c flag must be initialized to 1 before each calculation. fig. 4.2.5 status flags in decimal mode 4.2.4 jmp instruction when using the jmp instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. nop instruction adc or sbc instruction sec, clc, or cld instruction set d flag to ?? 107 appendix 1. instruction cycles in each addressing mode clock f controls the system timing of 740 family. the sync signal and the value of pc (program counter) are output in every instruction fetch cycle. the op-code is fetched during the next half-period of f . the instruction decoder of cpu decodes this op-code and determines the following how to execute the instruction. the instruction timings of all address- ing modes are described on the following pages. in these figures, f , sync, r/w (rd, wr), addr (addr l , addr h ), and data are internal signals of the single-chip microcomputer; therefore, these signals can be investigated only in the microprocessor mode. the combination of these signals differs according to the microcomputers type. the following table lists the valid signal for each product. valid signal for each product appendix 1 instruction cycles in each addressing mode type m507xx m509xx m374xx (except m37451) m38xxx m375xx m37451 m50734 f sync r/w r w addr data addr h addr l /data im plied 108 instructions : byte length : cycle number : timing : d clc d cld d cli d clt d clv d dex d dey d inx d iny d nop d sec d sed d sei d set d tax d tay d tsx d txa d txs d tya 1 2 f pc h pc l +1 op-code pc pc +1 pc h pc l pc l +1 sync r/w rd addr data addr h addr l /data wr invalid in- valid op- code im plied 109 instruction : byte length : cycle number : timing : d brk 1 7 pc h pc h pc l pc l +1 pc pc +1 s,00 (note 1) s-1,00 (note 1) s-2,00 (note 1) fff4 (note 2) fff5 (note 2) ad l ad h aa aa ps ad l ad h 01 pc h pc h pc l spc h s-1 pc l s-2 aa aa ps f4 a d l f5 a d h ad l sync r/w rd addr data addr h addr l /data wr ff f op- code invalid op- code notes 1 : some products are 01 or content of sps flag. 2 : some products differ the address. in- valid im plied 110 d stp d wit instructions : byte length : timing : 1 pc l pc l +1 pc l +1 pc h pc pc +1 pc h sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code return from standb y state is excuted by ex- ternal interrup t. return from wait state is excuted by internal or ex ternal interrup t. im plied 111 d rti instruction : byte length : cycle number : timing : 1 6 pc pc +1 pc h pc h pc l pc l +1 s,00 (note) s+1,00 (note) s+2,00 (note) s+3,00 (note) pc l pc h 00 (note) s s+1 s+2 pc l s+3 pc h pc l ps pc h pc l (stack) ps (stack) pc h (stack) sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code note: some products are 01 or content of sps flag. in- valid invalid im plied 112 instruction : byte length : cycle number : timing : d rts 1 6 pc l pc l +1 s s+1 s+2 pc l pc h pc h pc h 00 (note) pc h pc h pc l (stack) pc h (stack) pc pc +1 s,00 (note) s+1,00 (note) s+2,00 (note) pc l pc h pc l+ 1 pc h pc l +1 pc l sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code invalid invalid note: some products are 01 or content of sps flag. im plied 113 d pha d php instructions : byte length : cycle number : timing : 1 3 pc pc +1 pc h pc h pc l pc l +1 s aor ps 00 (note) a or ps s,00 (note) sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code note: some products are 01 or content of sps flag. im plied 114 instructions : byte length : cycle number : timing : d pla d plp 1 4 pc l pc l +1 pc h pc h 00 (note) pc pc +1 s+1,00 (note) data 00 (pc +1) l ,00 (pc+1) l s+1 sync r/w rd addr data addr h addr l /data wr data f op-code invalid in- valid op- code invalid note: some products are 01 or content of sps flag. 115 [t=0] [t=0] immediate instructions : byte length : cycle number : timing : d adc d #$nn (t=0) d and d #$nn (t=0) d cmp d #$nn (t=0) d cpx d #$nn d cpy d #$nn d eor d #$nn (t=0) d lda d #$nn (t=0) d ldx d #$nn d ldy d #$nn d ora d #$nn (t=0) d sbc d #$nn (t=0) 2 2 pc l pc l +1 pc h pc h pc pc +1 sync r/w rd addr data addr h addr l /data wr data data f op-code op- code 116 ac c um ulator instructions : byte length : cycle number : timing : d asl d a d dec d a d inc d a d lsr d a d rol d a d ror d a 1 2 pc pc +1 pc h pc h pc l pc l +1 pc l +1 pc h sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code in- valid 117 ac c um ulator bit relativ e instructions : byte length : (1) with no branch cycle number : timing : d bbc d i,a,$hhll d bbs d i,a,$hhll 2 4 pc pc +1 pc h pc h pc l pc l +1 pc l +1 pc l +1 sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code in- valid in- valid 118 ac c um ulator bit relativ e instructions : byte length : (2) with branch cycle number : timing : 2 6 d bbc d i,a,$hhll d bbs d i,a,$hhll ((pc+2) rr) l (pc+2) h pc pc h pc h pc l pc l +1 pc l +1 pc l +1 (pc +2) h (pc +2) h rr *2 *2 *1 rr pc +1 (pc +2) l (pc +1) h (pc +2) rr ((pc+2) rr )h sync r/w rd addr data addr h addr l /data wr rr :offset address * 1 : (pc +1) l * 2 : ((pc +2) rr) l f op-code invalid in- valid op- code in- valid invalid invalid 119 ac c um ulator bit instructions : byte length : cycle number : timing : d clb d i,a d seb d i,a 1 2 pc pc +1 pc h pc h pc l pc l +1 sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code 120 bit relativ e instructions : byte length : (1) with no branch cycle number : timing : d bbc d i,$zz,$hhll d bbs d i,$zz,$hhll 3 5 pc pc +1 pc h pc h pc l pc l +1 pc l +2 ad l ad l pc l +2 ad l pc h 00 ad l, 00 pc+2 sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code in- valid data data 121 bit relativ e instructions : byte length : (2) with branch cycle number : timing : d bbc d i,$zz,$hhll d bbs d i,$zz,$hhll 3 7 pc pc h pc h pc l pc l +1 pc l +2 (pc +2) h (pc +3) h rr *2 *2 *1 rr pc +1 (pc +3) l (pc +2) h ((pc+3) rr) l (pc+3) h (pc+3) rr ((pc+3) rr) h ad l ad l pc l +2 00 pc h ad l, 00 pc+2 ad l sync r/w rd addr data addr h addr l /data wr rr :offset address * 1 : (pc +3) l * 2 : ((pc +3) rr) l f op-code invalid in- valid op- code invalid invalid data data 122 zero page bit instructions : byte length : cycle number : timing : d clb d i,$zz d seb d i,$zz 2 5 pc pc l pc l +1 pc +1 ad l ad l 00 ad l, 00 ad l ad l ad l pc h pc h sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data new data new da t a 123 zero page [t=0] [t=0] instructions : byte length : cycle number : timing : d adc d $zz (t=0) d and d $zz (t=0) d bit d $zz d cmp d $zz (t=0) d cpx d $zz d cpy d $zz d eor d $zz (t=0) d lda d $zz (t=0) d ldx d $zz d ldy d $zz d ora d $zz (t=0) d sbc d $zz (t=0) d tst d $zz 2 3 pc pc +1 pc h pc h pc l pc l +1 00 ad l ad l, 00 ad l ad l sync r/w rd addr data addr h addr l /data wr data data f op-code op - code 124 zero page instructions : byte length : cycle number : timing : 2 5 d asl d $zz d com d $zz d dec d $zz d inc d $zz d lsr d $zz d rol d $zz d ror d $zz pc pc +1 pc h pc h pc l pc l +1 00 ad l ad l, 00 ad l ad l ad l ad l sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data new data new da t a 125 zero page instruction : byte length : cycle number : timing : d rrf d $zz 2 8 pc pc +1 pc h pc h pc l pc l +1 00 ad l ad l, 00 ad l ad l ad l ad l ad l ad l ad l sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data new data new da t a 126 zero page instruction : byte length : cycle number : timing : d ldm d #$nn,$zz 3 4 pc pc +1 pc h pc h pc l pc l +1 00 ad l ad l, 00 ad l ad l pc +2 pc h pc l +2 sync r/w rd addr data addr h addr l /data wr f op-code op- code data data data data 127 zero page instructions : byte length : cycle number : timing : 2 4 d sta d $zz d stx d $zz d sty d $zz pc pc +1 pc h pc l pc l +1 00 ad l ad l, 00 ad l ad l pc h ad l sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data 128 zero page x d mul d $zz,x (note) instruction : byte length : cycle number : timing : 2 15 pc pc +1 ad l ad l +x,00 s,sps sync r/w rd addr data wr f invalid op- code data new da t a in- valid in- valid sps: a selected page by stack page selection bit of the cpu mode register. note: this instruction cannot b e used for any p roducts. 129 zero page x instruction : byte length : cycle number : timing : d div d $zz,x (note) 2 16 pc pc +1 ad l ad l +x+1,00 s,sps ad l +x,00 sync r/w rd addr data wr sps: a selected page by stack page selection bit of the cpu mode register. note: this instruction cannot b e used for any p roducts. f invalid op- code low-order da ta new da t a in- valid in- valid high-order da ta 130 zero page x instructions : byte length : cycle number : timing : d asl d $zz,x d dec d $zz,x d inc d $zz,x d lsr d $zz,x d rol d $zz,x d ror d $zz,x 2 6 pc pc +1 pc h pc l pc l +1 pc h ad l (pc +1) l ,00 ad l (pc+1) l 00 ad l +x ad l +x ad l +x,00 sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data new data new da t a invalid ad l +x 131 zero page x, zero page y [t=0] d adc d $zz,x (t=0) d and d $zz,x (t=0) d cmp d $zz,x (t=0) d eor d $zz,x (t=0) d lda d $zz,x (t=0) d ldx d $zz,y d ldy d $zz,x d ora d $zz,x (t=0) d sbc d $zz,x (t=0) 2 4 instructions : byte length : cycle number : timing : pc pc +1 pc h pc l pc l +1 pc h ad l +x (ory ) ,00 ad l +x (or y) ad l (pc +1) l ,00 ad l (pc +1) l 00 sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data 132 zero page x, zero page y instructions : byte length : cycle number : timing : d sta d $zz,x d stx d $zz,y d sty d $zz,x 2 5 pc pc +1 pc h pc l pc l +1 pc h ad l +x(or y ) ,00 ad l +x (or y) ad l (pc +1) l ,00 ad l (pc +1) l 00 ad l +x (or y) sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data invalid 133 absolute [t=0] [t=0] instructions : byte length : cycle number : timing : d adc d $hhll (t=0) d and d $hhll (t=0) d bit d $hhll d cmp d $hhll (t=0) d cpx d $hhll d cpy d $hhll d eor d $hhll (t=0) d lda d $hhll (t=0) d ldx d $hhll d ldy d $hhll d ora d $hhll (t=0) d sbc d $hhll (t=0) 3 4 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h ad l ad h pc l +2 ad l ad h sync r/w rd addr data addr h addr l /data wr f op-code data op- code data 134 absolute d asl d $hhll d dec d $hhll d inc d $hhll d lsr d $hhll d rol d $hhll d ror d $hhll instructions : byte length : cycle number : timing : 3 6 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h ad l ad l pc l +2 ad l ad h ad l ,a d h sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code data data new data new da t a 135 absolute instruction : byte length : cycle number : timing : d jmp d $hhll 3 3 pc h pc l +1 pc pc +1 pc h pc l pc +2 pc h pc l +2 pc l pc l pc h pc h pc h pc l pc l, pc h sync r/w rd addr data addr h addr l /data wr f op-code op- code 136 absolute instruction : byte length : cycle number : timing : d jsr d $hhll 3 6 pc pc +1 pc h pc h pc l pc l +1 s,00 (note) s-1,00 (note) 00 (note) ss-1 s pc +2 pc h ad h ad h ad l pc l +2 (pc +2) h ad l ad l (pc +2) h (pc +2) l ad h ad l ad h (pc +2) l sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code note: some products are 01 or content of sps flag. 137 absolute instructions : byte length : cycle number : timing : d sta d $hhll d stx d $hhll d sty d $hhll 3 5 pc pc +1 pc h pc h pc l pc l +1 pc h ad h ad h ad l pc l +2 ad l ad l ad l ad h pc +2 ad h ad l sync r/w rd addr data addr h addr l /data wr data data f op-code invalid op- code 138 absolute x, absolute y [t=0] d adc d $hhll,x or y (t=0) d and d $hhll,x or y (t=0) d cmp d $hhll,x or y (t=0) d eor d $hhll,x or y (t=0) d lda d $hhll,x or y (t=0) d ldx d $hhll,y d ldy d $hhll,x d ora d $hhll,x or y (t=0) d sbc d $hhll,x or y (t=0) instructions : byte length : cycle number : timing : 3 5 pc pc +1 pc h pc l pc l +1 pc h ad l +x(or y ) ad h ad l +x (or y) ad l ad l pc l +2 ad h ad l +x (or y) pc h ad h ad h +c ad h pc +2 ad l +x(or y ) ad h +c c : carry of ad l +x or y sync r/w rd addr data addr h addr l /data wr data data f op-code invalid op- code 139 absolute x instructions : byte length : cycle number : timing : d asl d $hhll,x d dec d $hhll,x d inc d $hhll,x d lsr d $hhll,x d rol d $hhll,x d ror d $hhll,x 3 7 pc pc +1 pc h pc h pc l pc l +1 pc h ad h ad h pc l +2 ad l pc +2 ad h +c ad l ad h ad l +x ad h +c ad l +x ad h ad l +x ad l +x ad l +x ad l +x sync r/w rd addr data addr h addr l /data wr c : carry of ad l +x data data f op-code invalid op- code invalid new data new da t a 140 absolute x, absolute y instruction : byte length : cycle number : timing : 3 6 d sta d $hhll,x or y pc pc +1 pc h pc l pc l +1 pc h ad l +x(or y ) ad h ad l +x (or y) ad l ad l pc l +2 ad h ad l +x (or y) pc h ad h ad h +c ad h pc +2 ad l +x(or y ) ad h +c ad l +x (or y) sync r/w rd addr data addr h addr l /data wr c : carry of ad l +x or y data data f op-code invalid op- code invalid 141 in d irec t instruction : byte length : cycle number : timing : 3 5 d jmp d ($hhll) pc pc +1 pc h pc h pc l pc l +1 pc h ba h ad h pc l +2 ba l pc +2 ad l ad h ba l +1 ba h ba l +1 ba l ad l ad h ba l ba h ba l ba h ad l ba h ba h ad h ad l sync r/w rd addr data addr h addr l /data wr op-code op- code f ba : basic address 142 zero page in d irec t instruction : byte length : cycle number : timing : 2 4 d jmp d ($zz) pc pc +1 pc h pc l pc l +1 pc h ba l ad l ad h ba l ,00 ad l ad h ba l ad h ad l ad l ad h ba l +1,00 00 ba l +1 ba l sync r/w rd addr data addr h addr l /data wr op-code op- code f ba : basic address 143 zero page in d irec t instruction : byte length : cycle number : timing : d jsr d ($zz) 2 7 pc pc +1 pc h pc l pc l +1 ba l ad l ad h ba l ,00 ad l ad h ba l ad h ad l ad l ad h ba l +1 ,00 ba l +1 ba l s ss-1 (pc +1) l pc h 00 01 (pc +1) h (pc +1) l s,00 (note) s-1,00 (note) (pc +1) h sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code note: s ome kind ty p es are 01 or content of s ps flag. ba : basic address 144 in d irec t x [t=0] 2 6 instructions : byte length : cycle number : timing : d adc d ($zz,x) (t=0) d and d ($zz,x) (t=0) d cmp d ($zz,x) (t=0) d eor d ($zz,x) (t=0) d lda d ($zz,x) (t=0) d ora d ($zz,x) (t=0) d sbc d ($zz,x) (t=0) pc pc +1 pc h pc l pc l +1 ba l ad l ba l+x ,00 ad h ba l +x+1 ,00 ba l (pc +1) l pc h 00 ad h ad l ad h ad l ba l +x ba l +x+1 (pc +1) l ,00 ad l ad h sync r/w rd addr data addr h addr l /data wr data f op-code invalid op- code data ba : basic address 145 in d irec t x instruction : byte length : cycle number : timing : 2 7 d sta d ($zz,x) pc +1 pc h pc l pc l +1 ba l ad l ad l ad h ad h ad l ad l ad h ba l +x+1 ,00 ba l ba l +x+1 (pc +1) l pc h 00 pc ba l +x ,00 (pc +1) l ,00 ad h ad l ba l +x sync r/w rd addr data addr h addr l /data wr data f op-code invalid op- code data ba : basic address invalid 146 in d irec t y [t=0] [t=0] d adc d ($zz),y (t=0) d and d ($zz),y (t=0) d cmp d ($zz),y (t=0) d eor d ($zz),y (t=0) d lda d ($zz),y (t=0) d ora d ($zz),y (t=0) d sbc d ($zz),y (t=0) instructions : byte length : cycle number : timing : 2 6 pc pc +1 pc h pc l pc l +1 pc h ad h ad h ad l ad h +c ad l ad h ad l +y ad h +c ad l +y ad h ba l +1 ad l +y ba l ba l 00 ba l ba l ,00 ba l +1 ,00 ad l +y sync r/w rd addr data addr h addr l /data wr c : carry of ad l +y data data f op-code invalid op- code ba : basic address 147 in d irec t y instruction : byte length : cycle number : timing : 2 7 d sta d ($zz),y pc pc +1 pc h pc l pc l +1 pc h ad h ad h ad l ad h +c ad l ad h ad l +y ad h +c ad l +y ad h ba l +1 ad l +y ba l ba l 00 ba l ba l ,00 ba l +1 ,00 ad l +y ad l +y sync r/w rd addr data addr h addr l /data wr c : carry of ad l +y data data f op-code invalid op- code ba : basic address invalid 148 relativ e d bcc d $hhll d bcs d $hhll d beq d $hhll d bmi d $hhll d bne d $hhll d bpl d $hhll d bvc d $hhll d bvs d $hhll instructions : byte length : (1)with no branch cycle number : timing : 2 2 pc pc +1 pc h pc h pc l pc l +1 sync r/w rd addr data addr h addr l /data wr f op-code invalid in- valid op- code 149 relativ e d bcc d $hhll d bcs d $hhll d beq d $hhll d bmi d $hhll d bne d $hhll d bpl d $hhll d bvc d $hhll d bvs d $hhll instructions : byte length : (2)with branch cycle number : timing : 2 4 pc pc h pc h pc l +1 (pc +1) h (pc +2) h rr rr pc +1 (pc +2) l (pc +1) h ((pc+2) rr) l (pc+2) h (pc+2) rr pc h (pc+2) l ((pc+2) rr) h rr : offset v alue ((pc+2) rr) l ((pc+2) rr) l sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code invalid 150 relativ e instruction : byte length : cycle number : timing : 2 4 d bra d $hhll f pc pc l pc h pc l +1 (pc +1) h (pc +2) h rr rr pc +1 (pc +2) l (pc +1) h ((pc+2) rr) l (pc+2) h (pc+2 ) rr ((pc+2) rr) h pc h (pc +2) l ((pc+2) rr) l ((pc+2) rr) l sync r/w rd addr data addr h addr l /data wr rr : offset v alue op-code invalid op- code invalid 151 spec ial page instruction : byte length : cycle number : timing : d jsr d \$hhll 2 5 pc pc +1 pc h pc l pc l +1 s,00 (note) s-1,00 (note) 00 (note) s s-1 s pc h (pc +1) l (pc +1) h ba l ba l ,ff (pc +1) h (pc +1) l ba l ba l ff sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code note : some products are 01 or content of sps flag. ba : basic address 152 immediate [t=1] [t=1] instructions : byte length : cycle number : timing : 2 5 d adc d #$nn (t=1) d and d #$nn (t=1) d eor d #$nn (t=1) d ora d #$nn (t=1) d sbc d #$nn (t=1) pc l pc l +1 pc h pc h pc pc +1 da t a 2 00 da t a 1 x xx x,00 data 1 data 2 sync r/w rd addr data addr h addr l /data wr f op-code invalid op- code new da t a new data 153 immediate [t=1] [t=1] d cmp d #$nn (t=1) instruction : byte length : cycle number : timing : 2 3 pc pc +1 pc h pc h pc l pc l +1 x,00 00 x sync r/w rd addr data addr h addr l /data wr da t a 2 da t a 1 data 1 data 2 f op-code op- code 154 immediate [t=1] [t=1] instruction : byte length : cycle number : timing : d lda d #$nn (t=1) 2 4 pc pc +1 pc h pc h pc l pc l +1 00 x x x,00 sync r/w rd addr data addr h addr l /data wr data data f op-code op- code invalid data data 155 zero page [t=1] [t=1] instructions : byte length : cycle number : timing : 2 6 d adc d $zz (t=1) d and d $zz (t=1) d eor d $zz (t=1) d ora d $zz (t=1) d sbc d $zz (t=1) pc pc +1 pc h pc h pc l pc l +1 x,00 00 x x x ad l ad l ad l ,00 ad l sync r/w rd addr data addr h addr l /data wr da t a 2 da t a 1 data 1 f op-code invalid op- code new da t a new data da t a 2 156 d cmp d $zz (t=1) zero page [t=1] [t=1] instruction : byte length : cycle number : timing : 2 4 pc pc +1 pc h pc h pc l pc l +1 x,00 00 x ad l ad l ad l ,00 ad l sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code op- code da t a 2 157 zero page [t=1] [t=1] instruction : byte length : cycle number : timing : 2 5 d lda d $zz (t=1) pc pc +1 pc h pc h pc l pc l +1 x,00 00 x ad l ad l ad l ,00 ad l x sync r/w rd addr data addr h addr l /data wr data data f op-code invalid op- code data data 158 zero page x [t=1] [t=1] instructions : byte length : cycle number : timing : d adc d $zz,x (t=1) d and d $zz,x (t=1) d eor d $zz,x (t=1) d ora d $zz,x (t=1) d sbc d $zz,x (t=1) 2 7 pc pc +1 pc h pc h pc l pc l +1 x,00 00 x ad l ad l +x ad l +x ,00 ad l x x (pc +1) l ,00 (pc +1) l sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code invalid op- code new da t a new data da t a 2 invalid 159 zero page x [t=1] [t=1] instruction : byte length : cycle number : timing : d cmp d $zz,x (t=1) 2 5 pc +1 pc h pc h pc l pc l +1 x,00 00 x ad l ad l +x ad l +x ,00 ad l (pc +1) l ,00 (pc +1) l pc sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code invalid op- code da t a 2 160 d lda d $zz,x (t=1) zero page x [t=1] [t=1] instruction : byte length : cycle number : timing : 2 6 pc +1 pc h pc h pc l pc l +1 x,00 00 x ad l ad l +x ad l +x ,00 ad l (pc +1) l ,00 (pc +1) l pc x sync r/w rd addr data addr h addr l /data wr data data f op-code invalid op- code invalid data data 161 absolute [t=1] [t=1] instructions : byte length : cycle number : timing : d adc d $hhll (t=1) d and d $hhll (t=1) d eor d $hhll (t=1) d ora d $hhll (t=1) d sbc d $hhll (t=1) 3 7 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h ad l pc l +2 ad l ad h x xx ad h x,00 00 sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code op- code new da t a new data da t a 2 invalid 162 absolute [t=1] [t=1] instruction : byte length : cycle number : timing : d cmp d $hhll (t=1) 3 5 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h ad l pc l +2 ad l ad h x ad h x,00 00 sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code op- code da t a 2 163 absolute [t=1] [t=1] instruction : byte length : cycle number : timing : d lda d $hhll (t=1) 3 6 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h ad l pc l +2 ad l ad h x ad h x,00 00 x sync r/w rd addr data addr h addr l /data wr data data f op-code invalid op- code data data 164 d adc d $hhll,x or y (t=1) d and d $hhll,x or y (t=1) d eor d $hhll,x or y (t=1) d ora d $hhll,x or y (t=1) d sbc d $hhll,x or y (t=1) absolute x, absolute y [t=1] [t=1] instructions : byte length : cycle number : timing : 3 8 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h pc l +2 x ad h x,00 00 x ad h +c x ad l +x(or y ) ad h ad l +x (or y) ad l +x (or y) ad l +x(or y ) ad h +c sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code op- code new da t a new data da t a 2 invalid invalid c : carry of ad l +x or y 165 absolute x, absolute y [t=1] [t=1] instruction : byte length : cycle number : timing : d cmp d $hhll,x or y (t=1) 3 6 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h pc l +2 x ad h x,00 00 ad h +c ad l +x(or y ) ad h ad l +x (or y) ad l +x (or y) ad l +x(or y ) ad h +c sync r/w rd addr data addr h addr l /data wr data 2 da t a 1 data 1 f op-code op- code da t a 2 invalid c : carry of ad l +x or y 166 absolute x, absolute y [t=1] [t=1] instruction : byte length : cycle number : timing : d lda d $hhll,x or y (t=1) 3 7 pc h pc l +1 pc pc +1 ad l pc h pc l ad l pc +2 ad h pc h ad h pc l +2 x ad h x,00 00 ad h +c ad l +x(or y ) ad h ad l + x(ory ) ad l +x(or y ) ad h +c x ad l + x(ory ) sync r/w rd addr data addr h addr l /data wr data data f op-code op- code invalid c : carry of ad l +x or y invalid data data 167 in d irec t x [t=1] instructions : byte length : cycle number : timing : d adc d ($zz,x) (t=1) d and d ($zz,x) (t=1) d eor d ($zz,x) (t=1) d ora d ($zz,x) (t=1) d sbc d ($zz,x) (t=1) 2 9 pc h pc l +1 pc pc +1 ba l pc h pc l ad l ad h ad h x ad l x,00 00 ba l +x 00 (pc +1) l ad h ad l x x ba l ba l + x+1 (pc+1) l ,00 ba l +x ,00 ba l +x +1,00 ad l ad h sync r/w rd addr data addr h addr l /data wr data 1 f op- code op- code data 1 ba : basic address invalid data 2 invalid new data data 2 new data 168 in d irec t x [t=1] instruction : byte length : cycle number : timing : 2 7 d cmp d ($zz,x) (t=1) pc h pc l +1 pc pc +1 ba l pc h pc l ad h ad h x ad l x,00 00 ba l +x 00 (pc +1) l ba l (pc+1) l ,00 ba l +x ,00 ba l + x+1 ad l ad h ad l ad h ad l ba l +x+1 ,00 sync r/w rd addr data addr h addr l /data wr data 1 f op-code op- code data 1 ba : basic address invalid data 2 data 2 169 d lda d ($zz,x) (t=1) in d irec t x [t=1] instruction : byte length : cycle number : timing : 2 8 pc h pc l +1 pc pc +1 ba l pc h pc l ad l ad h ad h x ad l x,00 00 ba l +x 00 (pc +1) l ad h ad l x ba l ba l + x+1 (pc+1) l ,00 ba l +x ,00 ba l +x +1 ,00 ad l ad h sync r/w rd addr data addr h addr l /data wr data f op- code op- code data ba : basic address invalid data invalid data 170 in d irec t y [t=1] [t=1] instructions : byte length : cycle number : timing : d adc d ($zz),y (t=1) d and d ($zz),y (t=1) d eor d ($zz),y (t=1) d ora d ($zz),y (t=1) d sbc d ($zz),y (t=1) 2 9 pc h pc l +1 pc pc +1 ba l pc h pc l ad l ad h ad h +c x ad l 00 00 ad h x ba l ad l +y ad h +c ba l ba l +1 ad l +y ad l +y x ad h ba l ,00 ba l +1 ,00 x,00 ad l +y ad h sync r/w rd addr data addr h addr l /data wr data 2 data 1 data 1 data 2 f op-code invalid op - code new data new data invalid c : carry of ad l +y ba : basic address 171 in d irec t y [t=1] [t=1] instruction : byte length : cycle number : timing : d cmp d ($zz),y (t=1) 2 7 pc h pc l +1 pc pc +1 ba l pc h pc l ad l ad h ad h +c ad l 00 00 ad h x ba l ad l +y ad h +c ba l ba l +1 ad l +y ad l +y ad h ba l ,00 ba l +1 ,00 x,00 ad l +y ad h sync r/w rd addr data addr h addr l /data wr da t a 2 da t a 1 data 1 data 2 f op-code invalid op- code c : carry of ad l +y ba : basic address 172 in d irec t y [t=1] [t=1] d lda d ($zz),y (t=1) instruction : byte length : cycle number : timing : 2 8 pc h pc l +1 pc pc +1 ba l pc h pc l ad l ad h ad h +c ad l 00 00 ad h x ba l ad l +y ad h +c ba l ba l +1 ad l +y ad l +y ad h ba l ,00 ba l +1 ,00 x,00 ad l +y ad h x sync r/w rd addr data addr h addr l /data wr data data data f op - code invalid op - code c : carry of ad l +y ba : basic address data invalid 173 appendix 2 740 f amily mac hine langua g e instruction t ab le appendix 2. 740 f amil y machine langua g e instruction t ab le 2 3 4 4 5 5 6 6 2 3 4 4 5 2 3 4 4 5 4 4 5 5 6 6 7 7 4 5 5 4 5 6 2 2 2 2 2 2 3 3 4 4 2 2 2 3 3 3 2 2 2 2 2 3 3 2 2 2 3 3 3 2 2 3 3 3 2 2 2 2 3 2 2 3 1 1 1 1 1 1 1 1 1 1 a9 a5 b5 ad bd b9 a1 b1 a2 a6 b6 ae be a0 a4 b4 ac bc 3c 85 95 8d 9d 99 81 91 86 96 8e 84 94 8c aa 8a a8 98 ba 9a 48 08 68 28 2 2 2 2 2 2 2 2 hex instruction code flag n v tb d i zc (a) ? nn (a) ? (m) where m=(zz) (a) ? (m) where m=(zz+(x)) (a) ? (m) where m=(hhii) (a) ? (m) where m=(hhii+(x)) (a) ? (m) where m=(hhii+(y)) (a) ? (m) where m=((zz+(x)+1)(zz+(x))) (a) ? (m) where m=((zz+1)(zz)+(y)) (x) ? nn (x) ? (m) where m=(zz) (x) ? (m) where m=(zz+(y)) (x) ? (m) where m=(hhii) (x) ? (m) where m=(hhii+(y)) (y) ? nn (y) ? (m) where m=(zz) (y) ? (m) where m=(zz+(x)) (y) ? (m) where m=(hhii) (y) ? (m) where m=(hhii+(x)) (m) ? nn where m=(zz) (m) ? (a) where m=(zz) (m) ? (a) where m=(zz+(x)) (m) ? (a) where m=(hhll) (m) ? (a) where m=(hhii+(x)) (m) ? (a) where m=(hhii+(y)) (m) ? (a) where m=((zz+(x)+1)(zz+(x))) (m) ? (a) where m=((zz+1)(zz)+(y)) (m) ? (x) where m=(zz) (m) ? (x) where m=(zz+(y)) (m) ? (x) where m=(hhii) (m) ? (y) where m=(zz) (m) ? (y) where m=(zz+(x)) (m) ? (y) where m=(hhii) (x) ? (a) (a) ? (x) (y) ? (a) (a) ? (y) (x) ? (s) (s) ? (x) (m(s)) ? (a), (s) ? (s) 1 (m(s)) ? (ps), (s) ? (s) 1 (s) ? (s)+1, (a) ? (m(s)) (s) ? (s)+1, (ps) ? (m(s)) lda # $ nn lda $ zz lda $ zz, x lda $ hhii lda $ hhii, x lda $ hhii, y lda ($ zz, x) lda ($ zz), y ldx # $ nn ldx $ zz ldx $ zz, y ldx $ hhii ldx $ hhii, y ldy # $ nn ldy $ zz ldy $ zz, x ldy $ hhii ldy $ hhii, x ldm # $ nn, $ zz sta $ zz sta $ zz, x sta $ hhii sta $ hhii, x sta $ hhii, y sta ($ zz, x) sta ($ zz), y stx $ zz stx $ zz, y stx $ hhii sty $ zz sty $ zz, x sty $ hhii tax txa tay tya tsx txs pha php pla plp parameter cycle number load store t r ansf er data t r ansf e r classification function symbol 1010 1001 174 2 2 2 3 3 3 2 2 2 2 2 3 3 3 2 2 1 2 2 3 3 1 2 2 3 3 1 1 1 1 2 2 69 65 75 6d 7d 79 61 71 e9 e5 f5 ed fd f9 e1 f1 3a e6 f6 ee fe 1a c6 d6 ce de e8 ca c8 88 62 e2 0110 1001 175 and # $ nn and $ zz and $ zz, x and $ hhii and $ hhii, x and $ hhii, y and ($ zz, x) and ($ zz), y o r a # $ nn o r a $ zz o r a $ zz, x ora $ hhii ora $ hhii, x ora $ hhii, y o r a ($ zz, x) o r a ($ zz), y e o r # $ nn e o r $ zz e o r $ zz, x eor $ hhii eor $ hhii, x eor $ hhii, y e o r ($ zz, x) e o r ($ zz), y com $ zz bit $ zz bit $ hhll tst $ zz cmp # $ nn cmp $ zz cmp $ zz, x cmp $ hhii cmp $ hhii, x cmp $ hhii, y cmp ($ zz, x) cmp ($ zz), y cpx # $ nn cpx $ zz cpx $ hhii cpy # $ nn cpy $ zz cpy $ hhii d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 flag nv t b di z c instruction code symbol classification parameter logic operation operation comparison 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 m7m6 5 5 5 5 5 m7m6 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 note 29 25 35 2d 3d 39 21 31 09 05 15 0d 1d 19 01 11 49 45 55 4d 5d 59 41 51 44 24 2c 64 c9 c5 d5 cd dd d9 c1 d1 e0 e4 ec c0 c4 cc hex 2 3 4 4 5 5 6 6 2 3 4 4 5 5 6 6 2 3 4 4 5 5 6 6 5 3 4 3 2 3 4 4 5 5 6 6 2 3 4 2 3 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 (a) ? (a) nn (a) ? (a) (m) where m=(zz) (a) ? (a) (m) where m=(zz+(x)) (a) ? (a) (m) where m=(hhii) (a) ? (a) (m) where m=(hhii+(x)) (a) ? (a) (m) where m=(hhii+(y)) (a) ? (a) (m) where m=((zz+(x)+1)(zz+(x))) (a) ? (a) (m) where m=((zz+1)(zz)+(y)) (a) ? (a) nn (a) ? (a) (m) where m=(zz) (a) ? (a) (m) where m=(zz+(x)) (a) ? (a) (m) where m=(hhii) (a) ? (a) (m) where m=(hhii+(x)) (a) ? (a) (m) where m=(hhii+(y)) (a) ? (a) (m) where m=((zz+(x)+1)(zz+(x))) (a) ? (a) (m) where m=((zz+1)(zz)+(y)) (a) ? (a) " nn (a) ? (a) " (m) where m=(zz) (a) ? (a) " (m) where m=(zz+(x)) (a) ? (a) " (m) where m=(hhii) (a) ? (a) " (m) where m=(hhii+(x)) (a) ? (a) " (m) where m=(hhii+(y)) (a) ? (a) " (m) where m=((zz+(x)+1)(zz+(x))) (a) ? (a) " (m) where m=((zz+1)(zz)+(y)) _ _ _ _ _ (m) ? (m) where m=(zz) (a) (m) where m=(zz) (a) (m) where m=(hhii) (m)=0? where m=(zz) (a)enn (a)e(m) where m=(zz) (a)e(m) where m=(zz+(x)) (a)e(m) where m=(hhii) (a)e(m) where m=(hhii+(x)) (a)e(m) where m=(hhii+(y)) (a)e(m) where m=((zz+(x)+1)(zz+(x))) (a)e(m) where m=((zz+1)(zz)+(y)) (x)enn (x)e(m) where m=(zz) (x)e(m) where m=(hhii) (y)enn (y)e(m) where m=(zz) (y)e(m) where m=(hhii) function 0010 1001 176 2 5 6 6 7 2 5 6 6 7 2 5 6 6 7 2 5 6 6 7 8 2 5 2 5 1 2 2 3 3 1 2 2 3 3 1 2 2 3 3 1 2 2 3 3 2 1 2 1 2 0a 06 16 0e 1e 4a 46 56 4e 5e 2a 26 36 2e 3e 6a 66 76 6e 7e 82 (1+2i) 5 10 +b (1+2i) 5 10 +f 2i 5 10 +b 2i 5 10 +f instruction code d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 flag nv t b d i z c ? ? y ? ? ? t ? ? y ? ? ? t cycle number byte number function hex symbol operation parameter rotate and shift 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 0000 1010 0000 0110 177 4 3 5 4 6 7 5 4 5 4 5 2 2 2 2 2 2 2 2 6 6 7 2 2 2 2 3 3 2 3 2 2 2 3 2 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 80 4c 6c b2 20 02 22 (1+2i)x10 +3 (1+2i)x10 +7 2ix10 +3 2ix10 +7 90 b0 d0 f0 10 30 50 70 40 60 00 ea c2 42 1000 0000 178 symbol a ai x y m mi ps s pc pc l pc h n v t b d i z c # $ means accumulator bit i of accumulator index register x index register y memory bit i of memory processor status register stack pointer program counter low-order byte of program counter high-order byte of program counter negative flag overflow flag x modified operation mode flag break flag decimal mode flag interrupt disable flag zero flag carry flag immediate mode hexadecimal special page mode symbol hh ii zz nn i iii 179 d 7 C d 4 d 3 C d 0 hexadecimal notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f 0000 0 brk bpl jsr abs bmi rti bvc rts bvs bra bcc ldy imm bcs cpy imm bne cpx imm beq 0001 1 ora ind, x ora ind, y and ind, x and ind, y eor ind, x eor ind, y adc ind, x adc ind, y sta ind, x sta ind, y lda ind, x lda ind, y cmp ind, x cmp ind, y sbc ind, x sbc ind, y 0010 2 jsr zp, ind clt jsr sp set stp (note) mul (note) rrf zp ldx imm jmp zp, ind wit div (note) 0101 5 ora zp ora zp, x and zp and zp, x eor zp eor zp, x adc zp adc zp, x sta zp sta zp, x lda zp lda zp, x cmp zp cmp zp, x sbc zp sbc zp, x 0110 6 asl zp asl zp, x rol zp rol zp, x lsr zp lsr zp, x ror zp ror zp, x stx zp stx zp, y ldx zp ldx zp, y dec zp dec zp, x inc zp inc zp, x 0111 7 bbs 0, zp bbc 0, zp bbs 1, zp bbc 1, zp bbs 2, zp bbc 2, zp bbs 3, zp bbc 3, zp bbs 4, zp bbc 4, zp bbs 5, zp bbc 5, zp bbs 6, zp bbc 6, zp bbs 7, zp bbc 7, zp 1000 8 php clc plp sec pha cli pla sei dey tya tay clv iny cld inx sed 1001 9 ora imm ora abs, y and imm and abs, y eor imm eor abs, y adc imm adc abs, y sta abs, y lda imm lda abs, y cmp imm cmp abs, y sbc imm sbc abs, y 1010 a asl a dec a rol a inc a lsr a ror a txa txs tax tsx dex nop 1011 b seb 0, a clb 0, a seb 1, a clb 1, a seb 2, a clb 2, a seb 3, a clb 3, a seb 4, a clb 4, a seb 5, a clb 5, a seb 6, a clb 6, a seb 7, a clb 7, a 1101 d ora abs ora abs, x and abs and abs, x eor abs eor abs, x adc abs adc abs, x sta abs sta abs, x lda abs lda abs, x cmp abs cmp abs, x sbc abs sbc abs, x 3-byte instruction 2-byte instruction 1-byte instruction note: some products unuse these instructions. 1110 e asl abs asl abs, x rol abs rol abs, x lsr abs lsr abs, x ror abs ror abs, x stx abs ldx abs ldx abs, y dec abs dec abs, x inc abs inc abs, x 1111 f seb 0, zp clb 0, zp seb 1, zp clb 1, zp seb 2, zp clb 2, zp seb 3, zp clb 3, zp seb 4, zp clb 4, zp seb 5, zp clb 5, zp seb 6, zp clb 6, zp seb 7, zp clb 7, zp 1100 c bit abs ldm zp jmp abs jmp ind sty abs ldy abs ldy abs, x cpy abs cpx abs refer to the related section because the clock control instruction and multiplication and division instruction depend on products. instruction stp mul div products which unuse these instructions m37424,m37524 m507xx,m509xx,M37408,M37409,m37410 m37412,m37413,m37414,m37415,m37416,m37417 m37418,m37420,m37421 appendix 3 740 family iist of instruction codes 0011 3 bbs 0, a bbc 0, a bbs 1, a bbc 1, a bbs 2, a bbc 2, a bbs 3, a bbc 3, a bbs 4, a bbc 4, a bbs 5, a bbc 5, a bbs 6, a bbc 6, a bbs 7, a bbc 7, a 0100 4 bit zp com zp tst zp sty zp sty zp, x ldy zp ldy zp, x cpy zp cpx zp appendix 3. 740 family iist of instruction codes 180 memorandum 740 family iist of instruction codes mitsubishi semiconductors software manual 740 family sep. first edition 1997 editioned by committee of editing of mitsubishi semiconductor users manual published by mitsubishi electric corp., semiconductor marketing division this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1997 mitsubishi electric corporation mitsubishi electric corporation head office: mitsubishi denki bldg., marunouchi, tokyo 100. telex: j24532 cable: melco tokyo software manual 740 family ? 1997 mitsubishi electric corporation. new publication, effective sep. 1997. specifications subject to change without notice. |
Price & Availability of M3740
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |