md1810 high speed quad mosfet driver 1 nr090105 initial release features 6ns rise and fall time with 1000pf load 2a peak output source/sink current 1.2v to 5v input cmos compatible 5v to 12v total supply voltage smart logic threshold low jitter design four matched channels outputs can swing below ground output is high impedence when disabled low inductance package high-performance thermally-enhanced applications medical ultrasound imaging piezoelectric transducer drivers nondestructive evaluation pin diode driver ccd clock driver/buffer high speed level translator general description the supertex md1810 is a high-speed quad mosfet driver. it is designed to drive high voltage p-and n-channel mosfets for medical ultrasound imaging applications. the md1810 can also be used for ultrasound metal ? aw detection, nondestructive evaluation test, piezoelectric transducer drive, clock drive, and pin diode drive. the md1810 has four inputs which individually control four outputs. it also has an output enable (oe) pin. when oe is low, all of the outputs will be in a high impedance state regardless of their logic input control. when oe is high, the md1810 sets the threshold logic transition to (v oe +v gnd )/2. this ensures the transition to always be at half the amplitude of the logic input signal. this allows the device to have inherent propagation delay matching regardless of the logic input amplitude. the output stage of the md1810 has separate power connections enabling the output signal l and h levels to be chosen independently from the v dd and v ss supply voltages. as an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5 and C5 volts, and the output l and h levels may be varied anywhere over the range of C5 to +5 volts. the output stage is capable of peak currents of up to 2 amps, depending on the supply voltages used and load capacitance present. typical application circuit supertex md1810 10nf supertex tc6320tg 10nf 1.0f +100v 1.0f -100v 10nf supertex tc6320tg 10nf 1.0f +10v 1.0f -10v v ss v dd v h v l oe ina gnd inb inc ind outa +12v 3.3v cmos logic inputs outb outc outd +12v 0.47f 0.47f
2 nr090105 md1810 v dd -v ss logic supply voltage 4.5 13 v v ss low side supply voltage -5.5 0 v v h output high supply voltage v ss +2 v dd v v l output low supply voltage v ss v dd -2 v i ddq v dd quiescent current 0.8 ma no input transitions, oe = 1 i hq v h quiescent current 10 a i dd v dd average current 7.0 ma one channel on at 5.0mhz, no load i h v h average current 18 ma v ih input logic voltage high v oe -0.3 5 v for logic inputs ina, inb, inc, and ind v il input logic voltage low 0 0.3 v i ih input logic current high 1.0 a i il input logic current low 1.0 a v ih oe input logic voltage high 1.2 5 v for logic input oe v il oe input logic voltage low 0 0.3 v r in input logic impedance to gnd 12 20 30 k ? c in logic input capacitance 5 10 pf r sink output sink resistance 12.5 ? i sink = 50ma r source output source resistance 12.5 ? i source = 50ma i sink peak output sink current 2.0 a i source peak output source current 2.0 a outputs (v h = v dd = 12v, v l = v ss = gnd = 0v, v oe = 3.3v, t j = 25c) sym. parameter min. typ. max. units conditions ordering information device package option 16-lead 4x4x0.9 qfn md1810 MD1810K6-G ja 45c/w (1oz. 4-layer 3x4inch pcb) dc electrical characteristics (v h = v dd = 12v, v l = v ss = gnd = 0v, v oe = 3.3v, t j = 25c) sym. parameter min. typ. max. units conditions product marking information 1 st line device number 1810 2 nd line year, week code, lot number ywll example: 5a88 means lot #88 of ? rst or second week in 2005 absolute maximum ratings* v dd -v ss , logic supply voltage -0.5v to +13.5v v h , output high supply voltage v l -0.5v to v dd +0.5v v l , output low supply voltage v ss -0.5v to v h +0.5v vss, low side supply voltage -7v to +0.5v logic input levels v ss -0.5v to v ss +7v maximum junction temperature +125c storage temperature -65c to 150c soldering temperature 235c package power dissipation 2.2w pin 1 1810 ywll top view -g indicates package is rohs compliant (green) *absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground.
3 nr090105 md1810 ac electrical characteristics (v h = v dd = 12v, v l = v ss = gnd = 0v, v oe = 3.3v, t j = 25c) sym. parameter min. typ. max. units conditions t irf input or oe rise & fall time 10 ns logic input edge speed requirement t plh propagation delay when output is from low to high 7ns c load = 1000pf, see timing diagram input signal rise/fall time 2ns t phl propagation delay when output is from high to low 7ns t poe propagation delay oe to output 9 ns t r output rise time 6 ns t f output fall time 6 ns l t r - t f l rise and fall time matching 1.0 ns for each channel l t plh -t phl l propagation low to high and high to low matching 1.0 ns ? t dm propagation delay matching 2.0 ns device to device delay match logic truth table logic inputs output oe in hlv l hhv h l x high z timing diagram and v th / v oe curve v oe v th 0 0.5 1.0 1.5 2.0 1.0 2.0 3.0 4.0 5.0 0 0.6v v oe/2 0 v 1. 8 v in t plh 1 0 % 9 0 % 5 0 % 0 v 1 2 v 5 0 % out t phl t r 9 0 % 1 0 % t f v th vs v oe
4 nr090105 md1810 simpli? ed block diagram detailed block diagram v dd v ss v dd v h v ss v l level shifter ina outa v dd v ss v dd v h v ss v l level shifter inb outb v dd v ss v dd v h v ss v l level shifter inc outc v dd v ss v dd v h v ss v l level shifter ind outd level shifter oe gnd sub
5 nr090105 md1810 typical applications 10nf supertex tc6320tg 10nf 0.1f +100v 0.1f -100v 10nf supertex tc6320tg 10nf 0.1f +100v 0.1f -100v to piezoelectric transducer to piezoelectric transducer supertex md1810 v ss v dd v h v l oe ina gnd inb inc ind outa +12v 3.3v cmos logic inputs outb outc outd +12v 0.47f 0.47f 2-channel +100v to -100v pulser single channel 100v to 0v pulser supertex tc6320 0.1f +100 v 0.1f -100v to piezoelectric transducer 10nf 10nf supertex tc2320 supertex md1810 v ss v dd v h v l oe ina gnd inb inc ind outa +12v 3.3v cmos logic inputs outb outc outd +12v 0.47f 0.47f
6 nr090105 md1810 application information for proper operation of the md1810, low inductance bypass capacitors should be used on the various supply pins. the gnd pin should be connected to the logic ground. the ina, inb inc, ind, and oe pins should be connected to a logic source with a swing of gnd to v ll , where v ll is 1.2 to 5.0 volts. good trace practices should be followed corresponding to the desired operating speed. the internal circuitry of the md1810 is capable of operating up to 100mhz, with the primary speed limitation being the loading effects of the load capacitance. because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. unless the load speci? cally requires bipolar drive, the v ss , and v l pins should have low inductance feed-through connections directly to a ground plane. if these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. the power connection v dd should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. the voltages of v h and v l decide the output signal levels. these two pins can draw fast transient currents of up to 2a, so they should be provided with an appropriate bypass capacitor located next to the chip pins. a ceramic capacitor of up to 1.0f may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. pay particular attention to minimizing trace lengths, current loop area and using suf? cient trace width to reduce inductance. surface mount components are highly recommended. since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. this will of course reduce the output voltage slew rate at the terminals of a capacitive load. pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. the parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. since the input operates with signals down to 1.2v even small coupled voltages may cause problems. use of a solid ground plane and good power and signal layout practices will prevent this problem. be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. v dd high side supply voltage. v ss low side supply voltage. v ss is also connected to the ic substrate. it is required to connect to the most negative potential of voltage supplies and powered-up ? rst. v h supply voltage for p-channel output stage. v l supply voltage for n-channel output stage. gnd logic input ground reference. oe output enable logic input. when oe is high, (v oe +v gnd )/2 sets the threshold transition between logic level high and low. when oe is low, all outputs are at high impedance. keep oe low until ic powered up. ina, inb,inc, ind logic input. input logic high will cause the output to swing to v h . input logic low will cause the output to swing to v l . keep all logic inputs low until ic powered up. outa, outb, outc, outd output drivers substrate the ic substrate is internally connected to the thermal pad. thermal pad and v ss must be connected externally. pin description
7 doc.# dsfp - md1810 nr090105 md1810 pin con? guration pin # function 1inb 2v l 3gnd 4v l 5inc 6ind 7v ss 8outd 9outc 10 v h 11 v h 12 outb 13 outa 14 v dd 15 ina 16 oe note thermal pad, and pin #7 (v ss ), must be connected externally qfn-16 4x4x0.9 1 9 16 (top view, mm) 13 0.325 0.65 2.64 2.64 0.28 4 12 58
|
