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? 1999 microchip technology inc. preliminary ds21191f-page 1 device selection table features ? low power cmos technology - maximum write current 3 ma at 5.5v - maximum read current 400 a at 5.5v - standby current 100 na typical at 5.5v ? 2-wire serial interface bus, i 2 c compatible ? cascadable for up to eight devices ? self-timed erase/write cycle ? 64-byte page-write mode available ? 5 ms max write-cycle time ? hardware write protect for entire array ? output slope control to eliminate ground bounce ? schmitt trigger inputs for noise suppression ? 100,000 erase/write cycles guaranteed ? electrostatic discharge protection > 4000v ? data retention > 200 years ? 8-pin pdip and soic (150 and 208 mil) packages ? 14-pin tssop package ? temperature ranges: description the microchip technology inc. 24aa128/24lc128/ 24fc128 (24xx128*) is a 16k x 8 (128k bit) serial electrically erasable prom, capable of operation across a broad voltage range (1.8v to 5.5v). it has been developed for advanced, low power applications such as personal communications or data acquisition. this device also has a page-write capability of up to 64 bytes of data. this device is capable of both random and sequential reads up to the 128k boundary. func- tional address lines allow up to eight devices on the same bus, for up to 1m bit address space. this device is available in the standard 8-pin plastic dip, 8-pin soic (150 and 208 mil), and 14-pin tssop packages. package type block diagram part number v cc range max clock frequency temp ranges 24aa128 1.8-5.5v 400 khz ? c 24lc128 2.5-5.5v 400 khz ? i, e 24fc128 2.5-5.5v 1 mhz i ? 100 khz for v cc < 2.5v. ? 100 khz for e temperature range. - commercial (c) 0 to +70c - industrial (i): -40 cto +85 c - automotive (e): -40 cto+125 c a0 a1 a2 vss vcc wp scl sda 1 2 3 4 8 7 6 5 24xx128 pdip tssop 24xx128 1 2 3 4 14 7 8 5 6 9 11 12 13 10 nc a0 a1 nc a2 vss nc nc vcc wp nc scl sda nc a0 a1 a2 v ss v cc wp scl sda 24xx128 1 2 3 4 8 7 6 5 soic hv generator eeprom array page latches ydec xdec sense amp r/w control memory control logic i/o control logic a0 a1 a2 sda scl v cc v ss wp i/o i 2 c is a trademark of philips corporation. *24xx128 is used in this document as a generic part number for the 24aa128/24lc128/24fc128 devices. 24aa128/24lc128/24fc128 128k i 2 c ? cmos serial eeprom
24aa128/24lc128/24fc128 ds21191f-page 2 preliminary ? 1999 microchip technology inc. 1.0 electrical characteristics 1.1 maximum ratings* v cc ........................................................................6.5v all inputs and outputs w.r.t. v ss .....-0.6v to v cc +1.0v storage temperature .......................... -65c to +150c ambient temp. with power applied......-65c to +125c soldering temperature of leads (10 seconds) .. +300c esd protection on all pins ..................................... 3 4 kv *notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended peri- ods may affect device reliability. table 1-1: pin function table figure 1-1: bus timing data name function a0, a1, a2 user configurable chip selects v ss ground sda serial data scl serial clock wp write protect input v cc +1.8 to 5.5v (24aa128) +2.5 to 5.5v (24lc128) table 1-2: dc characteristics all parameters apply across the specified operating ranges, unless otherwise noted. commercial (c): v cc = +1.8v to 5.5v tamb = 0c to +70c industrial (i): v cc = +2.5v to 5.5v tamb = -40c to +85c automotive (e): v cc = +4.5v to 5.5v tamb = -40c to 125c parameter symbol min max units conditions a0, a1, a2, scl, sda, and wp pins: high level input voltage v ih 0.7 v cc v low level input voltage v il 0.3 v cc 0.2 v cc v v v cc 3 2.5v v cc < 2.5v hysteresis of schmitt trigger inputs (sda, scl pins) v hys 0.05 v cc vv cc 3 2.5v (note) low level output voltage v ol 0.40 vi ol = 3.0 ma @ v cc = 4.5v i ol = 2.1 ma @ v cc = 2.5v input leakage current i li -10 10 m a v in = v ss or v cc , wp = v ss v in = v ss or v cc , wp = v cc output leakage current i lo -10 10 m av out = v ss or v cc pin capacitance (all inputs/outputs) c in , c out 10pfv cc = 5.0v (note) tamb = 25c, f c = 1 mhz operating current i cc read 400 a v cc = 5.5v, scl = 400 khz i cc write 3 ma v cc = 5.5v standby current i ccs 1 m a scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss note: this parameter is periodically sampled and not 100% tested. wp (unprotected) (protected) t su : wp t hd : wp scl sda in t su : sta sda out t hd : sta t low t high t r t buf t aa t hd : dat t su : dat t su : sto t sp t f v hys
? 1999 microchip technology inc. preliminary ds21191f-page 3 24aa128/24lc128/24fc128 table 1-3: ac characteristics all parameters apply across the spec- ified operating ranges unless other- wise noted. commercial (c): v cc = +1.8v to 5.5v tamb = 0c to +70c industrial (i): v cc = +2.5v to 5.5v tamb = -40c to +85c automotive (e): v cc = +4.5v to 5.5v tamb = -40c to 125c parameter symbol min max units conditions clock frequency f clk 100 100 400 1000 khz 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) clock high time t high 4000 4000 600 500 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) clock low time t low 4700 4700 1300 500 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) sda and scl rise time (note 1) t r 1000 1000 300 300 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) sda and scl fall time (note 1) t f 300 100 ns all except 24fc128 24fc128 (2.5 v vcc 5.5 v) start condition hold time t hd : sta 4000 4000 600 250 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) start condition setup time t su : sta 4700 4700 600 250 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) data input hold time t hd : dat 0 ns (note 2) data input setup time t su : dat 250 250 100 100 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) stop condition setup time t su : sto 4000 4000 600 250 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) wp setup time t su : wp 4000 4000 600 600 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) wp hold time t hd : wp 4700 4700 1300 1300 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific application, please consult the total endurance model which can be obtained on microchips bbs or website.
24aa128/24lc128/24fc128 ds21191f-page 4 preliminary ? 1999 microchip technology inc. 2.0 pin descriptions 2.1 a0, a1, a2 chip address inputs the a0, a1, a2 inputs are used by the 24xx128 for multiple device operations. the levels on these inputs are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. up to eight devices may be connected to the same bus by using different chip select bit combinations. if left uncon- nected, these inputs will be pulled down internally to v ss . 2.2 sda serial data this is a bi-directional pin used to transfer addresses and data into and data out of the device. it is an open- drain terminal, therefore, the sda bus requires a pullup resistor to v cc (typical 10 k w for 100 khz, 2 k w for 400 khz and 1 mhz). for normal data transfer sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 2.3 scl serial clock this input is used to synchronize the data transfer from and to the device. 2.4 wp this pin can be connected to either v ss , v cc or left floating. an internal pull-down resistor on this pin will keep the device in the unprotected state if left floating. if tied to v ss or left floating, normal memory operation is enabled (read/write the entire memory 0000-3fff). if tied to v cc , write operations are inhibited. read operations are not affected. 3.0 functional description the 24xx128 supports a bi-directional 2-wire bus and data transmission protocol. a device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. the bus must be con- trolled by a master device which generates the serial clock (scl), controls the bus access, and generates the start and stop conditions while the 24xx128 works as a slave. both master and slave can operate as a transmitter or receiver, but the master device deter- mines which mode is activated. output valid from clock (note 2) t aa 3500 3500 900 400 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) bus free time: time the bus must be free before a new transmission can start t buf 4700 4700 1300 500 ns 4.5v v cc 5.5v (e temp range) 1.8v v cc 2.5v 2.5v v cc 5.5v 24fc128 (2.5 v vcc 5.5 v) output fall time from v ih minimum to v il maximum c b 100 pf t of 10 + 0.1c b 250 250 ns all except 24fc128 (note 1) 24fc128 (note 1) input filter spike suppression (sda and scl pins) t sp 50 ns all except 24fc128 (notes 1 and 3) write cycle time (byte or page) t wc 5ms endurance 100k cycles 25c, v cc = 5.0v, block mode (note 4) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to new schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but guaranteed by characterization. for endurance estimates in a specific application, please consult the total endurance model which can be obtained on microchips bbs or website. table 1-3: ac characteristics (continued) all parameters apply across the spec- ified operating ranges unless other- wise noted. commercial (c): v cc = +1.8v to 5.5v tamb = 0c to +70c industrial (i): v cc = +2.5v to 5.5v tamb = -40c to +85c automotive (e): v cc = +4.5v to 5.5v tamb = -40c to 125c parameter symbol min max units conditions
? 1999 microchip technology inc. preliminary ds21191f-page 5 24aa128/24lc128/24fc128 4.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 4-1). 4.1 bus not busy (a) both data and clock lines remain high. 4.2 start data transfer (b) a high to low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 4.3 stop data transfer (c) a low to high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must end with a stop condition. 4.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one bit of data per clock pulse. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device. 4.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. dur- ing reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave (24xx128) will leave the data line high to enable the master to generate the stop condition. figure 4-1: data transfer sequence on the serial bus figure 4-2: acknowledge timing note: the 24xx128 does not generate any acknowledge bits if an internal program- ming cycle is in progress. address or acknowledge valid data allowed to change stop condition start condition scl sda (a) (b) (d) (d) (c) (a) scl 9 8 7 6 5 4 3 2 1 123 transmitter must release the sda line at this point allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter data from transmitter sda acknowledge bit
24aa128/24lc128/24fc128 ds21191f-page 6 preliminary ? 1999 microchip technology inc. 5.0 device addressing a control byte is the first byte received following the start condition from the master device (figure 5-1). the control byte consists of a 4-bit control code; for the 24xx128 this is set as 1010 binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1, a0). the chip select bits allow the use of up to eight 24xx128 devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must correspond to the logic levels on the corresponding a2, a1, and a0 pins for the device to respond. these bits are in effect the three most significant bits of the word address. the last bit of the control byte defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. the next two bytes received define the address of the first data byte (figure 5-2). because only a13a0 are used, the upper two address bits are dont care bits. the upper address bits are transferred first, followed by the less significant bits. following the start condition, the 24xx128 monitors the sda bus checking the device type identifier being transmitted. upon receiving a 1010 code and appropri- ate device select bits, the slave device outputs an acknowledge signal on the sda line. depending on the state of the r/w bit, the 24xx128 will select a read or write operation. figure 5-1: control byte format 5.1 contiguous addressing across multiple devices the chip select bits a2, a1, a0 can be used to expand the contiguous address space for up to 1 mbit by add- ing up to eight 24xx128's on the same bus. in this case, software can use a0 of the control byte as address bit a14; a1, as address bit a15; and a2, as address bit a16. it is not possible to sequentially read across device boundaries. figure 5-2: address sequence bit assignments 1 0 1 0 a2 a1 a0 sack r/w control code chip select bits slave address acknowledge bit start bit read/write bit 1010 a 2 a 1 a 0 r/w xx a 11 a 10 a 9 a 7 a 0 a 8 ?????? a 12 control byte address high byte address low byte control code chip select bits x = dont care bit a 13
? 1999 microchip technology inc. preliminary ds21191f-page 7 24aa128/24lc128/24fc128 6.0 write operations 6.1 byte write following the start condition from the master, the control code (four bits), the chip select (three bits), and the r/w bit (which is a logic low) are clocked onto the bus by the master transmitter. this indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24xx128. the next byte is the least sig- nificant address byte. after receiving another acknowl- edge signal from the 24xx128, the master device will transmit the data word to be written into the addressed memory location. the 24xx128 acknowledges again and the master generates a stop condition. this ini- tiates the internal write cycle, and, during this time, the 24xx128 will not generate acknowledge signals (figure 6-1). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. after a byte write command, the inter- nal address counter will point to the address location following the one that was just written. 6.2 page write the write control byte, word address, and the first data byte are transmitted to the 24xx128 in the same way as in a byte write. but instead of generating a stop con- dition, the master transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. after receipt of each word, the six lower address pointer bits are internally incremented by one. if the master should transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received, an inter- nal write cycle will begin (figure 6-2). if an attempt is made to write to the array with the wp pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written, and the device will immediately accept a new command. 6.3 write protection the wp pin allows the user to write-protect the entire array (0000-3fff) when the pin is tied to v cc . if tied to v ss or left floating, the write protection is disabled. the wp pin is sampled at the stop bit for every write command (figure 1-1) toggling the wp pin after the stop bit will have no effect on the execution of the write cycle. figure 6-1: byte write figure 6-2: page write note: page write operations are limited to writing bytes within a single physical page, regard- less of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or page size) and end at addresses that are integer multiples of [page size - 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore neces- sary for the application software to prevent page write operations that would attempt to cross a page boundary. xx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data s t o p a c k a c k a c k a c k x = dont care bit s1 01 0 0 a 2 a 1 a 0 p xx bus activity master sda line bus activity s t a r t control byte address high byte address low byte data byte 0 s t o p a c k a c k a c k a c k data byte 63 a c k x = dont care bit s10 1 0 0 a 2 a 1 a 0 p
24aa128/24lc128/24fc128 ds21191f-page 8 preliminary ? 1999 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput.) once the stop condition for a write com- mand has been issued from the master, the device ini- tiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition, followed by the control byte for a write command (r/w = 0). if the device is still busy with the write cycle, then no ack will be returned. if no ack is returned, then the start bit and control byte must be resent. if the cycle is complete, then the device will return the ack, and the master can then proceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0)? next operation no yes
? 1999 microchip technology inc. preliminary ds21191f-page 9 24aa128/24lc128/24fc128 8.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the control byte is set to one. there are three basic types of read operations: current address read, random read, and sequential read. 8.1 current address read the 24xx128 contains an address counter that main- tains the address of the last word accessed, internally incremented by one. therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. upon receipt of the control byte with r/w bit set to one, the 24xx128 issues an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition and the 24xx128 discontinues transmission (figure 8-1). figure 8-1: current address read 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24xx128 as part of a write operation (r/w bit set to 0). after the word address is sent, the master generates a start condition following the acknowledge. this termi- nates the write operation, but not before the internal address pointer is set. then, the master issues the control byte again but with the r/w bit set to a one. the 24xx128 will then issue an acknowledge and transmit the 8-bit data word. the master will not acknowledge the transfer but does generate a stop condition which causes the 24xx128 to discontinue transmission (figure 8-2). after a random read command, the inter- nal address counter will point to the address location following the one that was just read. 8.3 sequential read sequential reads are initiated in the same way as a ran- dom read except that after the 24xx128 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. this acknowledge directs the 24xx128 to transmit the next sequentially addressed 8-bit word (figure 8-3). following the final byte transmitted to the master, the master will not generate an acknowledge but will gen- erate a stop condition. to provide sequential reads, the 24xx128 contains an internal address pointer which is incremented by one at the completion of each opera- tion. this address pointer allows the entire memory contents to be serially read during one operation. the internal address pointer will automatically roll over from address 3fff to address 0000 if the master acknowl- edges the byte received from the array address 3fff. figure 8-2: random read figure 8-3: sequential read bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k 11 00 aaa 1 byte 210 xx bus activity master sda line bus activity a c k n o a c k a c k a c k a c k s t o p s t a r t control byte address high byte address low byte control byte data byte s t a r t x = dont care bit s1010 aaa 0 210 s1 01 0 aaa 1 210 p bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x n o a c k a c k a c k a c k a c k s t o p p
24aa128/24lc128/24fc128 ds21191f-page 10 preliminary ? 1999 microchip technology inc. notes:
? 1999 microchip technology inc. preliminary ds21191f-page 11 24aa128/24lc128/24fc128 24xx128 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. sales and support package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body) st = tssop, 8-lead ot = sot-23, 5-lead temperature range: blank = 0 c to +70c i = C40c to +85c e = C40c to +125c device: 24aa128 128 bit 1.8v i 2 c serial eeprom 24aa128t 128 bit 1.8v k i 2 c serial eeprom (tape and reel) 24lc128 128 bit 2.5v i 2 c serial eeprom 24lc128t 128 bit 2.5v k i 2 c serial eeprom (tape and reel) 24fc128 128 bit 1mhz i 2 c serial eeprom 24fc128t 128 bit 1mhz i 2 c serial eeprom (tape and reel) 24xx128 /p data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (602) 786-7277. after september 1, 1999, (480) 786-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth er intellectual property rights arising from such use or otherwise. use of microchip?s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 631-273-5305 fax: 631-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yan?an road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc d?activite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the company?s quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchip ? s quality system for the design and manufacture of development systems is iso 9001 certified.

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