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rev. prd 5 march 03 preliminary technical data preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7453 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2003 pseudo differential, 555ksps, 12-bit adc in 8-lead sot-23 features specified for v dd of 2.7 v to 5.25 v low power at max throughput rate: 3.75 mw typ at 555ksps with v dd = 3 v 9 mw typ at 555ksps with v dd = 5 v pseudo differential analog input wide input bandwidth: 70db sinad at 100khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface - spi tm /qspi tm / microwire tm / dsp compatible power-down mode: 1a max 8 pin sot-23 and msop packages applications transducer interface battery powered systems data acquisition systems portable instrumentation motor control communications general description the AD7453 is a 12-bit, low power, successive-approxi- mation (sar) analog-to-digital converter that features a pseudo differential analog input. this part operates from a single 2.7 v to 5.25 v power supply and features through- put rates up to 555ksps. the part contains a low-noise, wide bandwidth, differen- tial track and hold amplifier (t/h) which can handle input frequencies in excess of 1mhz with the -3db point being 20mhz typically. the reference voltage for the AD7453 is applied externally to the v ref pin and can be varied from 100mv to 3.5 v. the conversion process and data acquisition are controlled using cs and the serial clock allowing the device to inter- face with microprocessors or dsps. the input signals are sampled on the falling edge of cs and the conversion is also initiated at this point. the sar architecture of this part ensures that there are no pipeline delays. functional block diagram the AD7453 use advanced design techniques to achieve very low power dissipation at high throughput rates. product highlights 1.operation with 2.7 v to 5.25 v power supplies. 2.low power consumption. with a 3v supply, the AD7453 offers 3.75mw typ power consumption for 555ksps throughput. 3.pseudo differential analog input. 4.variable voltage reference input 5.flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the power to be reduced as the conversion time is reduced through the serial clock speed increase. this part also features a shutdown mode to maximize power efficiency at lower throughput rates. 6.no pipeline delay. 7.accurate control of the sampling instant via a cs input and once off conversion control. 8. enob > 8 bits typically with 100mv reference. microwire is a trademark of national semiconductor corporation. spi and qspi are trademarks of motorola, inc. 12-bit successive approximation adc control logic AD7453 v in+ v in- v ref gnd sclk s data v dd t/h
rev. prd preliminary technical data ?2? parameter test conditions/comments b version 1 unit dynamic performance signal to (noise + distortion) (sinad) 2 70 db min total harmonic distortion (thd) 2 -80db typ -75 db max peak harmonic or spurious noise 2 -82db typ -75 db max intermodulation distortion (imd) 2 second order terms -85 db typ third order terms -85 db typ aperture delay 2 10 ns typ aperture jitter 2 50 ps typ full power bandwidth 2 @ -3 db 20 mhz typ @ -0.1 db 2.5 mhz typ dc accuracy resolution 12 bits integral nonlinearity (inl) 2 1 lsb max differential nonlinearity (dnl) 2 guaranteed no missed codes to 12 bits. 1 lsb max offset error 2 3 lsb max gain error 2 3 lsb max analog input full scale input span v in+ - v in- v ref v absolute input voltage v in+ v ref v v in- 3 100 mv dc leakage current 1 a max input capacitance when in track 20 pf typ when in hold 6 pf typ reference input v ref input voltage 1% tolerance for specified performance 2.5 4 v dc leakage current 1 a max v ref input capacitance 15 pf typ logic inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current, i in typically 10na, v in = 0vorv dd 1 a max input capacitance, c in 5 10 pf max logic outputs output high voltage, v oh v dd = 4.75v to5.25v i source = 200a 2.8 v min v dd = 2.7v to 3.6v i source = 200a 2.4 v min output low voltage, v ol i sink =200a 0.4 v max floating-state leakage current 1 a max floating-state output capacitance 5 10 pf max output coding straight (natural) binary conversion rate conversion time 1.6s with a 10mhz sclk 16 sclk cycles track/hold acquisition time 2 sine wave input 200 ns max step input t b d ns max throughput rate 6 555 ksps max AD7453 - specifications 1 ( v dd = 2.7v to 5.25v, f sclk = 10mhz, f s = 555ksps, v ref = 2.5 v; f in = 100khz; t a = t min to t max , unless otherwise noted.)
rev. prd preliminary technical data ?3? notes 1 temperature ranges as follows: b versions: ?40c to +85c. 2 see ?terminology? section. 3 a small dc input is applied to v in- to provide a pseudo ground for v in+ 4 the AD7453 is functional with a reference input in the range 100mv to 3.5 v. 5 sample tested @ +25c to ensure compliance. 6 see power versus throughput rate section. 7 measured with a midscale dc input. specifications subject to change without notice. AD7453 - specifications 1 parameter test conditions/comments b version 1 units power requirements v dd 2.7/5.25 vmin/max i dd 6,7 normal mode(static) sclk on or off 0.5 ma typ normal mode (operational) v dd = 4.75 v to 5.25 v 1.8 ma max v dd = 2.7 v to 3.6 v 1.25 ma max full power-down mode sclk on or off 1 a max power dissipation normal mode (operational) v dd =5 v. 9 mw max v dd =3 v. 3.75 mw max full power-down v dd =5 v. sclk on or off 5 w max v dd =3 v. sclk on or off 3 w max
rev. prd preliminary technical data ?4? limit at parameter t min , t max units description f sclk 3 10 khz min 10 mhz max t convert 16 x t sclk t sclk = 1/f sclk 1.6 s max t quiet 25 ns min minimum quiet time between the end of a serial read and the next falling edge of cs t 1 10 ns min minimum cs pulsewidth t 2 10 ns min cs falling edge to sclk falling edge setup time t 3 4 20 ns max delay from cs falling edge until sdata 3-state disabled t 4 4 40 ns max data access time after sclk falling edge t 5 0.4 t sclk ns min sclk high pulse width t 6 0.4 t sclk ns min sclk low pulse width t 7 10 ns min sclk edge to data valid hold time t 8 5 10 ns min sclk falling edge to sdata 3-state enabled 35 ns max sclk falling edge to sdata 3-state enabled t power-up 6 1 s max power-up time from full power-down notes 1 sample tested at +25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of v dd ) and timed from a voltage level of 1.6 volts. 2 see figure 1 and the ?serial interface? section. 3 mark/space ratio for the sclk input is 40/60 to 60/40. 4 measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.4 v with v dd = 5 v and time for an output to cross 0.4 v or 2.0 v for v dd = 3 v. 5 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2. the meas ured num- ber is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 6 see ?power-up time? section. specifications subject to change without notice. timing specifications 1,2 ( v dd = 2.7v to 5.25v, f sclk = 10mhz, f s = 555ksps, v ref = 2.5 v; f in = 100khz; t a = t min to t max , unless otherwise noted.) figure 1. serial interface timing diagram 1 2345 13 16 15 14 t 3 00 0 0 db11 db10 db2 db1 db0 t 2 4 leading zero?s 3-state t 4 t 6 t 5 t 7 t 8 t quiet convert t b sclk sdata t 1
rev. prd preliminary technical data ?5? AD7453 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7453 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 (t a = +25c unless otherwise noted) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3 v to +7 v v in+ to gnd . . . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v v in- to gnd . . . . . . . . . . . . . . . ?0.3 v to v dd + 0.3 v digital input voltage to gnd . . . . . . . . -0.3 v to +7 v digital output voltage to gnd . -0.3 v to v dd + 0.3 v v ref to gnd . . . . . . . . . . . . . . . . . -0.3 v to v dd +0.3 v input current to any pin except supplies 2 . . . . 10ma operating temperature range commercial (a, b version) . . . . . . . . . -40 o c to +85 o c storage temperature range . . . . . . . . . -65 o c to +150 o c junction temperature . . . . . . . . . . . . . . . . . . . . . . . +150 o c ja thermal impedance . . . . . . . . . . 205.9c/w (msop) 211.5c/w (sot-23) jc thermal impedance . . . . . . . . . 43.74c/w (msop) 91.99c/w (sot-23) lead temperature, soldering vapor phase (60 secs) . . . . . . . . . . . . . . . . . . . +215 o c infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . +220 o c e s d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv notes 1 stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch up. linearity package model range error (lsb) 1 option 4 branding information AD7453brt -40c to +85c 1 lsb rt-8 c09 AD7453brm -40c to +85c 1 lsb rm-8 c09 tbd 2 evaluation board eval-control brd2 3 controller board ordering guide notes 1 linearity error here refers to integral non-linearity error. 2 this can be used as a stand-alone evaluation board or in conjunction with the evaluation board controller for evaluation/demons tration purposes. 3 evaluation board controller. this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. to order a complete evaluation kit, you will need to order the adc evaluation b oard i.e. tbd, the eval-control brd2 and a 12v ac transformer. see the tbd technote for more information. 4 rt = sot-23; rm = msop figure 2. load circuit for digital output timing specifications

rev. prd preliminary technical data ?6? AD7453 pin configuration 8-lead msop pin function description pin mnemonic function v ref reference input for the AD7453. an external reference must be applied to this input. this pin should be decoupled to gnd with a capacitor of at least 0.1f. v in+ non-inverting input. v in- inverting input. this pin sets the ground reference point for the v in+ input. connect to ground or to a small dc offset to provide a pseudo ground. g n d analog ground. ground reference point for all circuitry on the AD7453. all analog input signals and any external reference signal should be referred to this gnd voltage. cs chip select. active low logic input. this input provides the dual function of initiating a conversion on the AD7453 and framing the serial data transfer. sdata serial data. logic output. the conversion result from the AD7453 is provided on this output as a serial data stream. the bits are clocked out on the falling edge of the sclk input. the data stream of the AD7453 consists of four leading zeros followed by the 12 bits of conversion data which are provided msb first. the output coding is straight (natural) binary. sclk serial clock. logic input. sclk provides the serial clock for accessing data from the part. this clock input is also used as the clock source for the conversion process. v dd power supply input. v dd is 2.7 v to 5.25 v. this supply should be decoupled to gnd with a 0.1f capacitor and a 10f tantalum capacitor. pin configuration 8-lead sot-23 AD7453 sot-23 (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in + v in - gnd sdata sclk v dd AD7453 msop (not to scale) top view 1 2 3 4 5 6 7 8 v ref v in + v in - gnd sdata sclk v dd
rev. prd preliminary technical data ?7? AD7453 terminology signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit con- verter with a sine wave input is given by: signal to ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7450, it is defined as: thd (db ) = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms in- clude (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). the AD7453 is tested using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual dis- tortion products to the rms amplitude of the sum of the fundamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample to sample variation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input fre- quency at which the amplitude of the reconstructed fundamental is reduced by 0.1db or 3db for a full scale input. integral nonlinearity (inl) this is the maximum deviation from a straight line pass- ing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. agnd + 1lsb) gain error this is the deviation of the last code transition (111...110 to 111...111) from the ideal (i.e., v ref - 1lsb), after the offset error has been adjusted out. track/hold acquisition time the track/hold amplifier returns into track mode on the 13th sclk rising edge (see the ?serial interface sec- tion?). the track/hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 120mv p-p sine wave applied to the adc v dd supply of frequency fs. the frequency of this input varies from 1khz to 1mhz. psrr (db) = 10 log (pf/pfs) pf is the power at frequency f in the adc output; pfs is the power at frequency fs in the adc output.
rev. prd preliminary technical data ?8? AD7453 tpc 1. sinad vs analog input frequency for various supply voltages tpc 2 and tpc 3 shows the power supply rejection ratio (see terminology) versus v dd supply ripple frequency for the AD7453 with and without power supply decoupling respectively. tpc 2. psrr vs. supply ripple frequency without supply decoupling performance curves (default conditions: ta = 25c, fs = 555ksps, fsclk = 10mhz, v dd = 2.7 v to 5.25 v, v ref = 2.5 v) tpc 3. psrr vs. supply ripple frequency with supply decoupling of tbd tpc 4. dynamic performance tpc 5. typical dnl
rev. prd preliminary technical data ?9? AD7453 tpc 6. typical inl tpc 7. histogram of 10000 conversions of a dc input circuit information the AD7453 is a 12-bit, fast, low power, single supply, successive approximation analog-to-digital converter (adc) with a pseudo differential analog input. it oper- ates with a single 2.7 v to 5.25 v power supply and is capable of throughput rates up to 555ksps when supplied with an 10mhz sclk. it requires an external reference to be applied to the v ref pin. the AD7453 has an on-chip differential track and hold amplifier, a successive approximation (sar) adc and a serial interface, housed in either an 8-lead sot-23 or msop package. the serial clock input accesses data from the part and also provides the clock source for the successive-approximation adc. the AD7453 features a power-down option for reduced power consumption be- tween conversions. the power-down feature is implemented across the standard serial interface as de- scribed in the ?modes of operation? section. converter operation the AD7453 is a successive approximation adc based around two capacitive dacs. figures 3 and 4 show sim- plified schematics of the adc in acquisition and conversion phase respectively. the adc comprises of control logic, a sar and two capacitive dacs. in fig- ure 3 (acquisition phase), sw3 is closed and sw1 and sw2 are in position a, the comparator is held in a bal- anced condition and the sampling capacitor arrays acquire the differential signal on the input. sw3 v in+ v in- sw1 c s c s a a b v ref sw2 control logic capacitive dac capacitive dac comparator b figure 3. adc acquisition phase when the adc starts a conversion (figure 4), sw3 will open and sw1 and sw2 will move to position b, causing the comparator to become unbalanced. both inputs are disconnected once the conversion begins. the control logic and the charge redistribution dacs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a bal- anced condition. when the comparator is rebalanced, the conversion is complete. the control logic generates the adc?s output code. the output impedances of the sources driving the v in+ and the v in- pins must be matched otherwise the two inputs will have different set- tling times, resulting in errors. sw3 v in+ v in- sw1 c s c s a b a b v ref sw2 control logic capacitive dac capacitive dac comparator figure 4. adc conversion phase adc transfer function the output coding for the AD7453 is straight (natural) binary. the designed code transitions occur at successive lsb values (i.e. 1lsb, 2lsbs, etc.). the lsb size is v ref /4096 and the ideal transfer characteristic is shown in figure 5.
rev. prd preliminary technical data ?10? AD7453 000...00 0v adc code analog input 111...11 1 000...00 000...01 0 111...11 111...00 011...11 1lsb v ref -1lsb 1lsb = v ref /4096 figure 5. ideal transfer characteristic typical connection diagram figure 6 shows a typical connection diagram for the AD7453. in this setup the gnd pin is connected to the analog ground plane of the system. the v ref pin is con- nected to the ad780, 2.5 v decoupled reference source to setup the analog input range of 2.5 v. the signal source is connected to the v in+ analog input via a unity gain buffer. a dc voltage in the range -100mv to +100mv is con- nected to the v in- pin to provide a pseudo ground for the v in+ input. the v dd pin should be decoupled to agnd with a 1f tantalum capacitor in parallel with a 0.1f ceramic capacitor. the reference pin should be decoupled to agnd with a capacitor of at least 0.1f. the conver- sion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit result. v in+ v in- v dd sclk sdata gnd v ref c/p serial interface +2.7 v to 5.25 v supply 2.5 v ad780 0.1f 0.1f 10f AD7453 v ref p-to-p dc input voltage range 100mv figure 6. typical connection diagram the analog input the AD7453 has a pseudo differential analog input. the v in+ input is coupled to the signal source and must have an amplitude of v ref peak-peak to make use of the full dynamic range of the part. a dc input input in the range -100mv to +100mv is applied to the v in- . the voltage applied to this input provides an offset from ground or a pseudo ground for the v in+ input. the main benefit of pseudo differential inputs is that they separate the analog input signal ground from the adc?s ground, allowing dc common-mode voltages to be cancelled. because the adc operates from a single supply, it will be necessary to level shift ground based bipolar signals to comply with the input requirements. when a conversion takes place, the pseudo ground corre- sponds to 0 and the maximum analog input corresponds to 4096. analog input structure figure 7 shows the equivalent circuit of the analog input structure of the AD7453. the four diodes provide esd protection for the analog inputs. care must be taken to ensure that the analog input signals never exceed the sup- ply rails by more than 300mv. this will cause these diodes to become forward biased and start conducting into the substrate. these diodes can conduct up to 10ma with- out causing irreversible damage to the part. the capacitors c1, in figure 12 are typically 4pf and can pri- marily be attributed to pin capacitance. the resistors are lumped components made up of the on-resistance of the switches. the value of these resistors is typically about 100 . the capacitors, c2, are the adc?s sampling ca- pacitors and have a capacitance of 16pf typically. for ac applications, removing high frequency components from the analog input signal is recommended by the use of an rc low-pass filter on the relevant analog input pins. in applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the opamp will be a function of the particu- lar application. v dd c1 d d v in+ r1 c2 v in- r1 c2 v dd d d c1 figure 7. equivalent analog input circuit. conversion phase - switches open track phase - switches closed when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will degrade. figure 8 shows a graph of
rev. prd preliminary technical data ?11? AD7453 the thd versus analog input signal frequency for differ- ent source impedances. figure 8.thd vs analog input frequency for various source impedances figure 9 shows a graph of thd versus analog input fre- quency for various supply voltages. in this case the source impedance is 10 . figure 9.thd vs analog input frequency for various supply voltages digital inputs the digital inputs applied to the AD7453 are not limited by the maximum ratings which limit the analog inputs. instead the digital inputs applied i.e cs and sclk, can go to 7 v and are not restricted by the v dd + 0.3 v limits as on the analog input. the main advantage of the inputs not being restricted to the v dd + 0.3 v limit is the fact that power supply se- quencing issues are avoided. if cs or sclk are applied before v dd , there is no risk of latch up as there would be on the analog inputs if a signal greater than 0.3 v were applied prior to v dd . reference section an external is required to supply the reference to the AD7453. this reference input can range from 100mv to 3.5 v. the specified reference is 2.5 v for the power supply range 2.7 v to 5.25 v. the reference input cho- sen for an application should never be greater than the power supply. errors in the reference source will result in gain errors in the AD7453 transfer function and will add to the specified full-scale errors of the part. a capacitor of at least 0.1 f should be placed on the v ref pin. suitable reference sources for the AD7453 include the ad780, the tbd and the tbd. figure 10 shows a typical connection diagram for the v ref pin. v ref AD7453* v dd 1 2 3 4 5 6 7 8 vin te m p gnd tr i m vout opsel 0.1f nc nc nc nc vdd 0.1f 0.1f 10nf *additional pins omitted for clarity ad780 2.5 v figure 10. typical v ref connection diagram for v dd = 5 v serial interface figures 1 shows a detailed timing diagram for the serial interface of the AD7453. the serial clock provides the conversion clock and also controls the transfer of data from the device during conversion. cs initiates the con- version process and frames the data transfer. the falling edge of cs puts the track and hold into hold mode and takes the bus out of three-state. the analog input is sampled and the conversion initiated at this point. the conversion will require 16 sclk cycles to complete. once 13 sclk falling edges have occurred, the track and hold will go back into track on the next sclk rising edge as shown at point b in figure 1. on the 16th sclk fall- ing edge the sdata line will go back into three-state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion will be terminated and the sdata line will go back into three-state on the 16th sclk falling edge. the conversion result from the AD7453 is provided on the sdata output as a serial data streatm. the bits are clocked out on the falling edge of the sclk input. the data stream consists of four leading zeros, followed by 12 bits of conver- sion data which is provided msb first. the output coding is straight (natural) binary. 16 serial clock cycles are required to perform a conversion and to access data from the AD7453. cs going low provides the first leading zero to be read in by the micro-controller or dsp. the remaining data is then clocked out on the subsequent sclk falling edges beginning with the second
rev. prd preliminary technical data ?12? AD7453 leading zero. thus the first falling clock edge on the serial clock provides the second leading zero. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. in applications with a slower sclk, it may be possible to read in data on each sclk rising edge i.e. the first rising edge of sclk after the cs falling edge would have the leading zero provided and the 15th sclk edge would have db0 provided. modes of operation the mode of operation of the AD7453 is selected by controlling the logic state of the cs signal during a conversion. there are two possible modes of operation, normal mode and power-down mode. the point at which cs is pulled high after the conversion has been initiated will determine whether or not the AD7453 will enter the power- down mode. similarly, if already in power-down, cs controls whether the devices will return to normal operation or remain in power-down. these modes of operation are designed to provide flexible power management options. these options can be chosen to optimize the power dissipa- tion/throughput rate ratio for differing application requirements. normal mode this mode is intended for fastest throughput rate perfor- mance. the user does not have to worry about any power-up times with the AD7453 remaining fully pow- ered up all the time. figure 11 shows the general diagram of the operation of the AD7453 in this mode. the conversion is initiated on the falling edge of cs as described in the ?serial interface section?. to ensure the part remains fully powered up, cs must remain low until at least 10 sclk falling edges have elapsed after the fall- ing edge of cs . if cs is brought high any time after the 10th sclk fall- ing edge, but before the 16th sclk falling edge, the part will remain powered up but the conversion will be termi- nated and sdata will go back into three-state. sixteen serial clock cycles are required to complete the conversion and access the complete conversion result. cs may idle high until the next conversion or may idle low until some- time prior to the next conversion. once a data transfer is complete, i.e. when sdata has returned to three-state, another conversion can be initiated after the quiet time, t quiet has elapsed by again bringing cs low. 4 leading zeros + conversion result sdata 10 16 sclk 1 figure 11. normal mode operation power down mode this mode is intended for use in applications where slower throughput rates are required; either the adc is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and the adc is then powered down for a relatively long duration between these bursts of several conversions. when the AD7453 is in the power down mode, all analog circuitry is powered down. to enter power down mode, the conversion process must be interrupted by bringing cs high anywhere after the second falling edge of sclk and before the tenth falling edge of sclk as shown in figure 12. once cs has been brought high in this window of sclks, the part will enter power down and the conver- sion that was initiated by the falling edge of cs will be terminated and sdata will go back into three-state. the time from the rising edge of cs to sdata three- state enabled will never be greater than t 8 (see the ?timing specifications?). if cs is brought high before the second sclk falling edge, the part will remain in normal mode and will not power-down. this will avoid accidental power-down due to glitches on the cs line. in order to exit this mode of operation and power the AD7453 up again, a dummy conversion is performed. on the falling edge of cs the device will begin to power up, and will continue to power up as long as cs is held low until after the falling edge of the 10th sclk. the device will be fully powered up after 1sec has elapsed and, as shown in figure 13, valid data will result from the next conversion. if cs is brought high before the 10th falling edge of sclk, the AD7453 will again go back into power-down. this avoids accidental power-up due to glitches on the cs line or an inadvertent burst of eight sclk cycles while cs is low. so although the device may begin to power up on the falling edge of cs , it will again power-down on the rising edge of cs as long as it occurs before the 10th sclk falling edge. three state sclk sdata 12 10 figure 12. entering power down mode power up time the power up time of the AD7453 is typically 1sec, which means that with any frequency of sclk up to 10mhz, one dummy cycle (1.6sec) will always be suffi- cient to allow the device to power-up. once the dummy cycle is complete, the adc will be fully powered up and the input signal will be acquired properly. the quiet time t quiet must still be allowed from the point at which the bus goes back into three-state after the dummy conversion, to the next falling edge of cs .
rev. prd preliminary technical data ?13? AD7453 when running at the maximum throughput rate of 555ksps, the AD7453 will power up and acquire a signal within 0.5lsb in one dummy cycle, i.e. 1.6sec. when powering up from the power-down mode with a dummy cycle, as in figure 13, the track and hold, which was in hold mode while the part was powered down, returns to track mode after the first sclk edge the part receives after the falling edge of cs . this is shown as point a in figure 13. although at any sclk frequency one dummy cycle is sufficient to power the device up and acquire v in , it does not necessarily mean that a full dummy cycle of 16 sclks must always elapse to power up the device and acquire v in fully; 1s will be sufficient to power the de- vice up and acquire the input signal. for example, if a 5mhz sclk frequency was applied to the adc, the cycle time would be 3.2s (i.e. 1/(5mhz) x 16). in one dummy cycle, 3.2s, the part would be pow- ered up and v in acquired fully. however after 1s with a 5mhz sclk only 5 sclk cycles would have elapsed. at this stage, the adc would be fully powered up and the signal acquired. so, in this case the cs can be brought high after the 10th sclk falling edge and brought low again after a time t quiet to initiate the conversion. when power supplies are first applied to the AD7453, the adc may either power up in the power-down mode or normal mode. because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up be- fore attempting a valid conversion. likewise, if the user wishes the part to power up in power-down mode, then the dummy cycle may be used to ensure the device is in power-down by executing a cycle such as that shown in figure 12. once supplies are applied to the AD7453, the power up time is the same as that when powering up from the power-down mode. it takes approximately 1s to power up fully if the part powers up in normal mode. it is not necessary to wait 1s before executing a dummy cycle to ensure the desired mode of operation. instead, the dummy cycle can occur directly after power is supplied to the adc. if the first valid conversion is then performed di- rectly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. as mentioned earlier, when powering up from the power- down mode, the part will return to track upon the first sclk edge applied after the falling edge of cs . how- ever, when the adc powers up initially after supplies are applied, the track and hold will already be in track. this means if (assuming one has the facility to monitor the adc supply current) the adc powers up in the desired mode of operation and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track and hold into track. microprocessor and dsp interfacing the serial interface on the AD7453 allows the part to be directly connected to a range of different microprocessors. this section explains how to interface the AD7453 with some of the more common microcontroller and dsp se- rial interface protocols. AD7453 to adsp21xx the adsp21xx family of dsps are interfaced directly to the AD7453 without any glue logic required. the sport control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16-bit data words isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0, itfs = 1. to implement the power-down mode slen should be set to 1001 to issue an 8-bit sclk burst. the connection diagram is shown in figure 14. the adsp21xx has the tfs and rfs of the sport tied together, with tfs set as an output and rfs set as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronisation signal generated on the tfs is tied to cs and as with all signal processing applications equidistant sampling is necessary. however, in this ex- ample, the timer interrupt is used to control the sampling rate of the adc and under certain conditions, equidistant sampling may not be acheived. figure 13. exiting power down mode sdata invalid data sclk 116 valid data 1 a the part begins to power up the part is fully powered up with vin fully acquired 10 10 16 t powerup
rev. prd preliminary technical data ?14? AD7453 AD7453* sclk sdata sclk dr rfs tfs adsp21xx* *additional pins omitted for clarity figure 14. interfacing to the adsp 21xx the timer registers etc., are loaded with a value which will provide an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to con- trol the rfs and hence the reading of data. the frequency of the serial clock is set in the sclkdiv register. when the instruction to transmit with tfs is given, (i.e. ax0=tx0), the state of the sclk is checked. the dsp will wait until the sclk has gone high, low and high before transmission will start. if the timer and sclk val- ues are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, then the data may be transmitted or it may wait until the next clock edge. for example, the adsp-2111 has a master clock fre- quency of 16mhz. if the sclkdiv register is loaded with the value 3 then a sclk of 2mhz is obtained, and 8 master clock periods will elapse for every 1 sclk period. if the timer registers are loaded with the value 803, then 100.5 sclks will occur between interrupts and subse- quently between transmit instructions. this situation will result in non-equidistant sampling as the transmit instruc- tion is occuring on a sclk edge. if the number of sclks between interrupts is a whole integer figure of n then equidistant sampling will be implemented by the dsp. AD7453 to tms320c5x/c54x the serial interface on the tms320c5x/c54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7453. the cs input allows easy inter- facing between the tms320c5x/c54x and the AD7453 without any glue logic required. the serial port of the tms320c5x/c54x is set up to operate in burst mode with internal clkx (tx serial clock) and fsx (tx frame sync). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1 and txm = 1. the format bit, fo, may be set to 1 to set the word length to 8-bits, in order to implement the power-down mode on the AD7453. the connection dia- gram is shown in figure 15. it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the tms320c5x/c54x will provide equidistant sampling. AD7453* sclk sdata clkx fsr tms320c5x/c54x* *additional pins omitted for clarity clkr dr fsx figure 15. interfacing to the tms320c5x/c54x AD7453 to mc68hc16 the serial peripheral interface (spi) on the mc68hc16 is configured for master mode (mstr = 1), clock polar- ity bit (cpol) = 1 and the clock phase bit (cpha) = 0. the spi is configured by writing to the spi control reg- ister (spcr) - see 68hc16 user manual. the serial transfer will take place as a 16-bit operation when the size bit in the spcr register is set to size = 1. to implement the power-down modes with an 8-bit transfer set size = 0. a connection diagram is shown in figure 16. AD7453* sdata * *additional pins omitted for clarity miso/pmc0 sclk/pmc2 sclk ss/pmc3 mc68hc16* figure 16. interfacing to the mc68hc16 AD7453 to dsp56xxx the connection diagram in figure 17 shows how the AD7453 can be connected to the ssi (synchronous serial interface) of the dsp56xxx family of dsps from motorola. the ssi is operated in synchronous mode (syn bit in crb =1) with internally generated 1-bit clock period frame sync for both tx and rx (bits fsl1 =1 and fsl0 =0 in crb). set the word length to 16 by setting bits wl1 =1 and wl0 = 0 in cra. to implement the power-down mode on the AD7453 then the word length can be changed to 8 bits by setting bits wl1 = 0 and wl0 = 0 in cra. it should be noted that for signal processing applications, it is imperative that the frame synchronisation signal from the dsp56xxx will provideequidistant sampling.
rev. prd preliminary technical data ?15? AD7453 AD7453* sdata * *additional pins omitted for clarity srd sclk sclk sr2 dsp56xxx* figure 17. interfacing to the dsp56xx application hints grounding and layout the printed circuit board that houses the AD7453 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily sepa- rated. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should be joined in only one place and the connection should be a star ground point estab- lished as close to the gnd pin on the AD7453 as possible. avoid running digital lines under the device as this will couple noise onto the die. the analog ground plane should be allowed to run under the AD7453 to avoid noise coupling. the power supply lines to the AD7453 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power sup- ply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and analog sig- nals. traces on opposite sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double- sided board. in this technique the component side of the board is dedi- cated to ground planes while signals are placed on the solder side. good decoupling is also important. all ana- log supplies should be decoupled with 10f tantalum capacitors in parallel with 0.1f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device.
rev. prd preliminary technical data ?16? AD7453 outline dimensions 8-lead sot-23 (rt-8) 8-lead msop (rm-8) dimensions shown in inches (millimeters) 1234 8765 0.122 (3.10) 0.110 (2.80) pin 1 0.077 (1.95) bsc 0.026 (0.65) bsc 0.071 (1.80) 0.059 (1.50) 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.015 (0.38) 0.009 (0.22) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90) 0.118 (3.0) 0.098 (2.50)

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