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final publication# 15451 rev: d amendment/ 0 issue date: june 1996 am79865/am79866a physical data transmitter/physical data receiver distinctive characteristics n fully compliant with ansi x3t9.5 fddi, tp-fddi, and 100base-tx/fx phy standards n provides data and clock recovery functions for fddi and fast ethernet applications n parallel input to the pdt is a 5-bit encoded nrz symbol clocked by lsclk n parallel output from the pdr is a 5-bit unframed nrz symbol clocked by rsclk n the on-chip phase-locked-loop (pll) only requires an external frequency reference n 125 mbaud (100 mbps) serial link data rate n interfaces to ?er or copper media n dedicated pins provide electrical loopback data path n 20-pin plastic leaded chip carrier (plcc) n single +5 v power supply operation general description the physical data transmitter (am79865) and the physical data receiver (am79866) devices provide clock recovery/generation functions meeting the re- quirements of fddi, tp-fddi, and 100base-tx phy standards. the pdt and pdr devices are part of the supernet 2 fddi physical layer protocol chip set which also in- cludes the physical layer controller with scrambler (plc-s). the plc-s (am79c864a), pdt and pdr de- vices are collectively known as the amphy. the plc-s performs the fddi physical layer functions which includes, among others, the 4b5b encoding and decoding. the pdt converts encoded symbols into a serial nrzi data stream. the on-chip pll generates a bit rate clock from the lsclk reference. the pdr uses a built-in clock recovery pll to extract clock information from the received data stream. the recovered clock is used for serial-to-parallel data conversion.
2 am79865/am79866a block diagram am79865 pdt tdat 4-0 input register shifter nrz nrzi output control output control test mode sync logic ? 5 clock multiplier (pll) lsclk lpbck ltx, lty test fo t off tx, ty 15451d-1 rdat 4-0 output register shifter nrz nrzi clock recovery pll ? 5 q d rsclk sdo lsclk am79866a pdr 15451d-2 test lsclk media interface lrx, lry rx, ry sdi
am79865/am79866a 3 connection diagrams top view tdat2 tdat3 tdat4 lpbck lty 1 3 2 20 19 vcc 1 gnd 1 nc 5 6 7 8 tdat1 lsclk 17 16 15 14 ltx 4 gnd 2 18 fotoff test nc ty 9 13 11 12 10 tdat0 tx vcc 2 vcc 1 am79865 pdt rdat2 gnd 1 rdat1 vcc 1 rdat0 1 3 2 20 19 gnd 1 vcc 2 sdo 5 6 7 8 rdat4 lpbck 17 16 15 14 rsclk 4 rdat3 18 lry lrx rx sdi 9 13 11 12 10 gnd 2 ry test lsclk am79866a pdr 20-pin plcc 20-pin plcc 15451d-3 15451d-4
4 am79865/am79866a logic symbols parallel data symbol forcing optical transmitter off loopback control lsclk test tdat 4? fo t off lpbck data loopback to local pdr ltx, lty tx, ty am79865 pdt am79c864a plc-s interface serial data transmitted in nrzi format fiber or copper interface 15451d-5 note: three v cc pins and two gnd pins. 25 mhz local symbol clock test mode select parallel data symbol recovered symbol clock loopback control lsclk test rdat 4? rsclk lpbck data loopback from local pdt lrx, lry rx, ry am79866a pdr am79c864a plc-s interface serial data received in nrzi format fiber or copper interface light level signal sdo sdi light level signal note: two v cc pins and three gnd pins. 15451d-6 25 mhz local symbol clock test mode select
am79865/am79866a 5 ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the elements below. valid combinations valid combinations list con?urations planned to be sup- ported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. temperature range c = commercial (0 c to +70 c) package type j = 20-pin plastic leaded chip carrier (pl 020) speed option not applicable am79865/ jc am79866a device number/description am79865 = physical data transmitter am79866a = physical data receiver valid combinations am79865 jc am79866a
6 am79865/am79866a am79865 pdt pin description tdat 4? transmit data (ttl inputs) these ve inputs accept data symbols from the am79c864 plc, latched by the rising edge of lsclk. lsclk local symbol clock (ttl input) this pin supplies the frequency and phase reference to the internal pll clock multiplier. it should be driven by an external 25 mhz crystal-controlled clock source. fo t off fiber optic transmitter off (ttl input, active low) when held low, the tx output is forced low and ty output is forced high so that the fiber optic transmit- ter will output logical 0. in test mode, fo t off is used as the test clock input and does not control tx/ty. lpbck loopback control (ttl input, active low) when asserted, the ltx/lty outputs transmit the nrzi serial bit stream to the pdr to establish the loopback data path. when deasserted, the ltx output is forced low and lty output is forced high. test test mode enable (ttl input) when asserted, the pdt is in test mode. for normal operation, test pin must be tied low. tx, ty** transmit data (pecl differential outputs) these transmit outputs carry differential nrzi data. they can be forced to logical 0 (tx low, ty high) by asserting the fo t off input. ltx, lty** loopback transmit data (pecl differential outputs) these differential outputs carry the same signal as tx/ ty when the lpbck input is asserted (low). ltx/lty should be connected to the lrx/lry pins of am79866a pdr to perform loopback function. when lpbck is deasserted (high), ltx is forced low and lty is forced high. **all differential pecl outputs carry data at ecl volt- age levels referenced to +5.0 v (pecl levels). the ex- ternal terminations required are shown in the interface connection diagram in the appendix. v cc1 , v cc2 power supply v cc1 ,v cc2 are +5.0 v nominal power supply pins. v cc1 powers all ttl and ecl i/o circuits. v cc2 powers all in- ternal logic gates and analog circuits. they must be connected to a common external supply. gnd1, gnd2 ground pins gnd1 is ttl and ecl i/o ground. gnd2 is the internal logic and analog ground. they must be connected to a common external ground reference.
am79865/am79866a 7 am79866a pdr pin description lsclk local symbol clock (ttl input) lsclk is driven by an external frequency source at the 25 mhz symbol rate. this signal is used as a frequency reference for the pdr clock-recovery pll. lpbck loopback (ttl input, active low) when active, lpbck selects the serial data stream at lrx/lry inputs as the received data. when high, rx/ ry are selected. this function is used during system loopback test to bypass the transmission medium. test test mode enable (ttl input) when asserted, the pdr is in test mode. for normal operation, test pin must be tied low. rdat 4? received data (ttl outputs) these 5-bit parallel outputs are clocked by the falling edge of rsclk and carry the nrz data symbols to the plc. rsclk recovered symbol clock (ttl output) rsclk is derived from the clock synchronization pll circuit. it is synchronous to the received serial data, and is the recovered bit clock divided-by-?e. this is a 25 mhz clock. sdi signal detect input (pecl single-ended input) sdi typically comes from the ?er optic receiver to indi- cate that the received optical signal is above the detec- tion threshold. when asserted (high), the data on rx/ ry are used for the input to the pdr. when deasserted (low), the rx/ry data stream is gated off and the pll locks onto the lsclk. sdo signal detect output (ttl output) sdo is the sdi input synchronized by lsclk. it has the same logical sense as sdi, i.e., high indicates the received optical signal is above the detection threshold. rx, ry* received data (pecl differential line receiver inputs) these pins receive nrzi data. lrx, lry* loopback received data (pecl differential line receiver inputs) this input pair should be connected to the pdt ltx/ lty outputs through properly terminated lines to estab- lish the loopback data path. when lpbck is asserted, lrx/lry carry the data to be used as the input to the pdr. in test mode, lrx/lry become the test clock input. *rx/ry and lrx/lry are differential line receivers which have high input sensitivity and wide common-mode range. they can also accept pecl voltage swings and shall be driven by properly termi- nated transmission lines. v cc1 , v cc2 power supply v cc1 ,v cc2 are +5.0 v nominal power supply pins. v cc1 powers all ttl and ecl i/o circuits. v cc2 powers all in- ternal logic gates and analog circuits. they must be connected to a common external supply. gnd 1 , gnd 2 ground pins gnd1 is ttl and ecl i/o ground. gnd2 is the internal logic and analog ground. they must be connected to a common external ground reference.
8 am79865/am79866a functional description normal operation mode the am79865 pdt accepts encoded data symbols at tdat 4? pins. the 5-bit symbol is latched into the pdt by the rising edge of lsclk, serialized, converted to nrzi format and shifted to the outputs (tdat4 bit is transmitted ?st). there are two pairs of serial data out- puts capable of driving either fiber optic interface hardware or wire transmission lines without external buffering. the tx/ty pair is connected to the serial link and the ltx/lty pair is used in the loopback connec- tion to the am79866a pdr. the pdt uses lsclk as the frequency reference to generate the serial link data rate. the external clock source must be crystal controlled and continuous. all of the internal logic of pdt runs on an internal clock that is pll-multiplied from the external reference source. the pdts internal pll is referenced to the rising edges of lsclk only. the input clock frequency required to achieve 125 mbaud on the serial link is 25 mhz at lsclk. in order to generate the serial output waveforms conform- ing to the fddi specication, the external reference clock (lsclk) must meet fddi frequency and stability requirements. the pdt serial output typically contains less than 0.4 ns peak-to-peak jitter at 125 mbaud. the latency from the lsclk to the serial output is typically 4 to 6 bits (8 ns/bit). the am79866a pdr accepts encoded nrzi serial data on the rx/ry inputs and converts them to nrz format. it then latches the unframed symbol (5 bits) to the rdat 4-0 outputs on the falling edge of rsclk. the heart of the am79866a pdr chip is its clock-recovery pll which extracts encoded clock infor- mation from the serial nrzi data stream and recovers the data. the pll examines every data transition in the received serial stream and aligns its internal bit clock with these data transitions. in order to guarantee the correct operation of the pll, the encoding scheme (such as the fddi 4b5b code) must insure adequate transition density of the encoded data stream. the pdr has input jitter tolerance characteristics that meet or exceed the recommendations of physical layer medium dependent (pmd) fddi document. typ- ically, at 125 mbaud (8 ns/bit), the peak-to-peak duty-cycle distortion (dcd) tolerance is 1.4 ns, the peak-to-peak data-dependent jitter (ddj) tolerance is 2.2 ns, and the peak-to-peak random jitter (rj) toler- ance is 2.27 ns. the total combined peak-to-peak jitter tolerance is typically 5 ns with bit error rate (ber) less than 2.5 x 10 ?0 . the pdrs pll typically has an acquisition time of 100 m s or less when ?aster symbols (one data transition within ten bits) are received. the acquisition time re- duces with increasing transition density in the data stream. the sdi input quali?s the data at rx/ry. when sdi is low, the pdr uses lsclk as the pll input and forces low at the output register. the lpbck input selects the data source between rx/ry and lrx/lry. when lpbck is low, the sdi input is ignored. when sdi is high and the rx/ry input stream con- tains no data transition for pll input, the pll operating frequency range is limited by the lsclk reference. the observed rsclk output frequency is generally within 0.5% of the lsclk frequency. under normal conditions, the frequency of lsclk mul- tiplied by ?e must be within 0.25% of the expected re- ceived data for the pll to operate correctly. (note, fddi speci?s the two frequencies to be within 50 ppm or 0.005% of each other.)
am79865/am79866a 9 am79865 pdt functional block description clock multiplier lsclk supplies the reference frequency which is mul- tiplied by ?e using an on-chip pll. the transmission rate and all serialization logic are controlled by the internally generated bit clock. input register tdat 4? are clocked into the input register by the ris- ing edge of lsclk. shifter parallel data are loaded from the input register into the shifter at the internally generated symbol boundary, and serially shifted at the bit clock rate. nrz-to-nrzi converter the nrz output of the shifter is converted into nrzi data patterns for transmission. output control the differential outputs carry the encoded serial nrzi bit stream. the tx/ty pair can be forced to logical 0 (tx low, ty high) by asserting fo t off input. the ltx/lty pair can be forced to logical 0 (ltx low, lty high) by deasserting the lpbck input. am79866a pdr functional block description clock-recovery pll the clock-recovery pll separates the input data stream into clock and data patterns. the pll operating frequency is established by the reference at lsclk. the pll is capable of tracking data correctly within + 0.25% of lsclk (exceeds the frequency range de?ed by the fddi speci?ation). media interface the rx/ry inputs are typically driven by differential pecl voltages, referenced to +5 v. these inputs accept the encoded nrzi serial data. lrx/lry are also differential line receiver inputs which accept the loopback data stream from the local pdt ltx/lty outputs. nrzi-to-nrz converter serial data are retimed and associated jitter is re- moved. retimed data are converted into nrz format prior to the shifter input. shifter the shifter is serially loaded from the nrzi_to_nrz converter, using the recovered bit clock. output register the output register is clocked by rsclk falling edges. rsclk is the recovered bit clock divided-by-?e and is synchronous to the received serial data. test mode asserting pdt test input pin forces pdt into its test mode. this allows testing of the internal logic without the pll clock multiplier. the internal clock source is re- placed by the test clock provided at the fo t off input. an automatic test system can clock the pdt through functional test patterns at any rate, typically less than 25 mhz, or any sequence to facilitate logic veri?ation. in pdt test mode, lsclk strobes data into the input register and provides initialization to the internal counter. the pdr test mode allows testing of the internal logic without the pll. when test is high, the internal clock source is replaced by the test clock provided at the lrx/lry inputs. note : the loopback data path in the am79866a pdr cannot be tested in test mode. an automatic test system can clock the pdr through functional test patterns at any rate, typically less than 25 mhz, or any sequence to facilitate logic veri?ation.
10 am79865/am79866a absolute maximum ratings storage temperature . . . . . . . . . . . . ?5 c to +150 c ambient temperature under bias . . . . . . 0 c to 70 c supply voltage (v cc ) to ground potential continuous . . . . . . . ?.5 v to +7.0 v dc voltage applied to outputs. . . . . .?.5 to v cc max dc input voltage . . . . . . . . . . . . . . . . ?.5 v to +5.5 v dc output current . . . . . . . . . . . . . . . . . . . . . . . 100 ma dc input current . . . . . . . . . . . . . ?0 ma to +5.0 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . .0 c to 70 c supply voltage (v cc ) . . . . . . . . . . +4.75 v to +5.25 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise speci?d am79865 pdt parameter symbol parameter description test description min max ttl inputs: tdat 4?, lsclk, fo t off , lpbck , test v ih input high voltage v cc = max (note 2) 2.0 v v il input low voltage v cc = max (note 2) 0.8 v v i input clamp voltage v cc = min, i in = ?8 ma ?.5 v i ih input high current v cc = max, v in = 2.7 v 50 m a i il input low current v cc = max, v in = 0.4 v ?00 m a i i input leakage current v cc = max, v in = 5.5 v 50 m a pecl outputs: tx, tx; ltx, lty v oh input high voltage pecl load (note 3) v cc ?1.025 v v cc ?0.88 v v ol input low voltage pecl load (note 3) v cc ?1.81 v 0.8v cc ?1.62 v power supplies i cc1 v cc1 supply current v cc1 = v cc2 = max (note 4) 20 i cc2 v cc2 supply current v cc1 = v cc2 = max 65
am79865/am79866a 11 dc characteristics over commercial operating ranges unless otherwise speci?d am79866 pdt parameter symbol parameter description test description min max ttl inputs: lsclk, lpbck , test v ih input high voltage v cc = max (note 2) 2.0 v v il input low voltage v cc = max (note 2) 0.8 v v i input clamp voltage v cc = min, i in = ?8 ma ?.5 v i ih input high current v cc = max, v in = 2.7 v 50 m a i il input low current v cc = max, v in = 0.4 v ?00 m a i i input leakage current v cc = max, v in = 5.5 v 50 m a ttl outputs: rdat 4?, sdo, rsclk v oh output high voltage v cc = min, i oh = ? ma 2.4 v v ol output low voltage v cc = min, i ol = 4 ma 0.45 v i sc output short circuit current v cc = max (note 5) ?5 ma v ?5 ma differential pecl inputs: rx, ry; lrx, lry v in input voltage (absolute high or low) v cc = max (note 2) 2.5 v v cc v dif input differential voltage v cc = max (note 2, 6) 50 mv 1.1 v i ih input high current v cc = max, v in = v cc ?0.88 v 220 m a i il input low current v cc = max, v in = v cc ?1.81 v 0.5 m a single-ended pecl input: sdi v ihs input single-ended high voltage v cc = max (note 2, 7) v cc ?1.165 v v cc ? 0.88 v v ils input single-ended low voltage v cc = max (note 2, 7) v cc ?1.81 v v cc ?1.475 v i ih input high current v cc = max, v in = v cc ?0.88 v 220 m a i il input low current v cc = max, v in = v cc ?1.81 v 0.5 m a power supplies i cc1 v cc1 supply current v cc1 = v cc2 = max 25 i cc2 v cc2 supply current v cc1 = v cc2 = max 145
12 am79865/am79866a switching characteristics over operating range unless otherwise speci?d am79865 pdt am79866a pdr notes: 1. for conditions shown as min or max, use the appropriate values speci?d under operating range. 2. typically measured with device in test mode while monitoring output logic states. 3. tested for v cc = min, shown limits are speci?d over entire v cc operating range. 4. pdt i cc1 is tested with all pecl outputs terminated to v cc (unloaded). the pecl outputs contribute 25 ma/pair nominally to i cc1 when they are loaded with pecl loads, 50 w to (v cc ?2). in calculating the chip power dissipation, the contribution by the output loads shall be multiplied by 1 v instead of by v cc . 5. not more than one output should be shorted at a time. duration of the short circuit test should not exceed one second. ? not included in the production test. no. parameter symbol parameter description test conditions (note 8) min max unit 1 t p lsclk period 40 40 ns 2 t pw lsclk pulse width high 15 ns 3 t pw lsclk pulse width low 15 ns 4 t s tdat 4? to lsclk rise setup time 12 ns 5 t h tdat 4? to lsclk rise hold time 2.5 ns 6 t r ? tx, ty, ltx, lty rise time pecl load 0.3 3 ns 7 t f ? tx, ty, ltx, lty hold time pecl load 0.3 3 ns 8 t sk ? tx/ty, ltx/lty skew pecl load 200 ps no. parameter symbol parameter description test conditions (note 8) min max unit 21 f os lsclk to received data frequency offset (note 9) 0.25 % 22 t pw lsclk pulse width high 15 ns 23 t pw lsclk pulse width low 16 ns 24 t pw rsclk pulse width high ttl load (note 10) 10 ns 25 t pw rsclk pulse width low ttl load (note 10) 20 ns 26 t pd rdat4? valid to rsclk rise ttl load (note 11) 13 ns 27 t pd rsclk rise to rdat4? invalid ttl load (note 11) 10 ns 28 t s sdi to lsclk rise setup time 5 ns 29 t h sdi to lsclk rise hold time 7 ns 30 t pd lsclk rise to sdo delay ttl load 30 ns
am79865/am79866a 13 notes (continued): 6. v dif is tested with each input voltage within the v in range. 7. device thresholds on the sdi pin are veri?d during production test by ensuring that the input threshold is less than v ihs (min) and greater than v ils (max). the ?ure below shows the acceptable range (shaded area) for the transition voltage. 8. all timing references are made with respect to + 1.5 v for ttl-level signals or to the 50% point between v oh and v ol for pecl signals. pecl input rise and fall times must be 2 ns + 0.2 ns between 20% and 80% points. ttl input rise and fall times must be 2 ns between 1 v and 2 v. 9. received data frequency is determined by serial data inputs. multiply lsclk frequency by 5 to convert the receive data bit rate. 10. tested for 125 mbaud received data rate (1 bit-time is 8 ns). t pw (high) is functionally 2 bit-time wide. t pw (low) is functionally 3 bit-time wide. 11. tested for 125 mbaud received data rate (1 bit-time 8 ns). (max) (min) (max) (min) v ils v ihs v v cc ?0.88 v v cc ?1.165 v input threshold transition voltage v cc ?1.475 v v cc ?1.81 v
14 am79865/am79866a switching waveforms am79865 pdt am79866a pdr lsclk tdat 4? tx, ty ltx, lty tx, ty ltx, lty 1 2 3 4 5 6 7 8 symbol k valid symbol k+1 bit 4 bit 3 bit 2 bit 1 bit 0 v ol 80% 20% tx ty 50% 50% 15451d-7 latency symbol k bit 4 corresponds to tdat4 v oh parallel 5-bit symbol valid parallel 5-bit symbol valid parallel 5-bit symbol valid rsclk rdat 4? lsclk sdi (pecl) sdo 24 24 27 26 27 22 23 28 29 30 15451d-8 25
am79865/am79866a 15 key to switching waveforms switching test circuits notes: 1. r 1 = 1 k w for the i ol = 4 ma 2. all diodes in916 or in3064, or equivalent. 3. c l = 30 pf includes scope probe, wiring and stray capacitances without device in text ?ture. 4. amd uses constant current (a.t.e.) load con?urations and forcing functions. this ?ure is for reference only. notes: 1. c l = 30 pf includes scope probe, wiring and stray capacitances without device in text ?ture. 2. amd uses automatic test equipment (a.t.e.) load con?urations and forcing functions. this ?ure is for ref- erence only. must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal r 1 v cc 2.4 k v out 30 pf ttl output load pecl output load 50 w 3 pf v cc ?2 v v out 15451d-9 15451d-10
16 am79865/am79866a switching test waveforms v cc ?0.9 v 80% 50% 20% v cc ?1.7 v 2 0.2 ns 2 0.2 ns 3.0 v 2.0 v 1.5 v 1.0 v 0.0v 2 0.2 ns ecl input waveform ttl input waveform 15451d-10 15451d-11 2 0.2 ns
am79865/am79866a 17 physical dimensions am79865/am79866a physical data transmitter/data receiver pl 020 20-pin plastic leaded chip carrier (measured in inches) trademarks copyright ?1996 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies. top view seating plane .385 .395 .350 .356 pin 1 i.d. .385 .395 .350 .356 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .290 .330 .200 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 020 df79 2-20-96 lv side view

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