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| september 2006 rev 6 1/53 53 STR73XF arm7tdmi? 32-bit mcu with flash, 3x can, 4 uarts, 20 timers, adc, 12 comm. interfaces core ? arm7tdmi 32-bit risc cpu ? 32 mips @ 36 mhz memories ? up to 256 kbytes flash program memory (10,000 cycles endurance, data retention 20 years @ 85 c) ? 16 kbytes ram clock, reset and supply management ? 4.5 - 5.5v application supply and i/os ? embedded 1.8v regulator for core supply ? embedded oscillator running from external 4-8mhz crystal or ceramic resonator ? up to 36 mhz cpu freq. with internal pll ? internal rc oscilla tor 32khz or 2mhz software configurable for fast startup and backup clock ? realtime clock for clock-calendar function ? wakeup timer driven by internal rc for wakeup from stop mode ? 5 power saving modes: slow, wfi, lpwfi, stop and halt modes nested interrupt controller ? fast interrupt handling with multiple vectors ? 64 maskable irqs with 64 vectors and 16 priority levels ? 2 maskable fiq sources ? 16 ext. interrupts, up to 32 wake-up lines up to 112 i/o ports ? 72/112 multifunctional bidirectional i/os dma ? 4 dma controllers with 4 channels each timers ? 16-bit watchdog timer (wdg) ? 6/10 16-bit timers (tim) each with: 2 input captures, 2 output compares, pwm and pulse counter modes ? 6 16-bit pwm modules (pwm) ? 3 16-bit timebase timers with 8-bit prescalers 12 communications interfaces ?2 i 2 c interfaces ? 4 uart asynchronous serial interfaces ? 3 bspi synchronous serial interfaces ?up to 3 can interfaces (2.0b active) 10-bit a/d converter ? 12/16 channels ? conversion time: min. 3 s, range: 0 to 5v development tools support ?jtag interface tqfp144 20 x 20 tqfp100 14 x 14 lfbga144 10 x 10 x 1.7 table 1. device summary features str730fzx str735fzx str731fvx str736fvx flash memory - bytes 128k 256k 128k 256k 64k 128k 256k 64k 128k 256k ram - bytes 16k 16k peripheral functions 10 tim timers, 112 i/os, 32 wake-up lines, 16 adc channels 6 tim timers, 72 i/os, 18 wake-up lines, 12 adc channels can peripherals 3 0 3 0 operating voltage 4.5 to 5.5v operating temperature -40 to +85c/-40 to +105c packages t =tqfp144 20 x 20 h =lfbga144 10 x10 t =tqfp100 14x14 www.st.com
contents STR73XF 2/53 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.1 str730f/str735f (tqfp144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 str730f/str735f (lfbga144) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.3 str731f/str736f (tqfp100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3.1 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3.2 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.3 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3.4 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.3.5 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.3.6 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STR73XF contents 3/53 6 known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1 low power wait for interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.2 pll free running mode at high temperature . . . . . . . . . . . . . . . . . . . . . . 51 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 introduction STR73XF 4/53 1 introduction this datasheet provides the str73x ordering information, mechanical and electrical device characteristics. for complete information on the STR73XF microcontroller memory, registers and peripherals. please refer to the str73x reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the str7 flash programming reference manual for information on the arm7tdmi core please refer to the arm7tdmi technical reference manual. 1.1 overview arm ? core with embedded flash & ram STR73XF family combines the high performance arm7tdmi ? cpu with an extensive range of peripheral functions and en hanced i/o capabilities. all devi ces have on-chip high-speed single voltage flash memory and high-speed ram. the STR73XF family has an embedded arm core and is therefore compatible with all arm tools and software. extensive tools support stmicroelectronics? 32-bit, arm core-based mi crocontrollers are supported by a complete range of high-end and low-cost development tools to meet the needs of application developers. this extensive line of hardware/software tools includes starter kits and complete development packages all tailored for st?s arm core-based mcus. the range of development packages includes third-party solutions that come complete with a graphical development environment and an in-circuit emulator/programmer featuring a jtag application interface. these support a range of embedded operating systems (os), while several royalty-free oss are also available. for more information, please refer to st mcu site http://www.st.com/mcu figure 1 shows the general block diagram of the device family. package choice: reduced pin-count tqfp10 0 or feature-rich 144-pin tqfp or lfbga the STR73XF family is available in 3 packages. the tqfp144 and lfbga144 versions have the full set of all features. the 100-pin version has fewer timers, i/os and adc channels. refer to the device summary on page 1 for a comparison of the i/os available on each package. the family includes versions with and without can. STR73XF introduction 5/53 high speed flash memory the flash program memory is organized in 32-bit wide memory cells which can be used for storing both code and data constants. it is accessed by cpu with zero wait states @ 36 mhz. the str7 embedded flash memory can be programmed using in-circuit programming or in-application programming. the flash memory endurance is 10k write/erase cycles and the data retention is 20 years @ 85 c. iap (in-application programming): the iap is the ability to re -program the flash memory of a microcontroller while the user program is running. icp (in-circuit programming): the icp is the ability to prog ram the flash memory of a microcontroller using jtag protocol while the device is mounted on the user application board. the flash memory can be protected against different types of unwanted access (read/write/erase). there are two types of protection: sector write protection flash debug protection (locks jtag access) flexible power management to minimize power consumption, you can program the STR73XF to switch to slow, wfi lpwfi, stop or halt modes depending on the current system activity in the application. flexible clock control two clock sources are used to drive the microcontroller, a main clock driven by an external crystal or ceramic resonator and an internal ba ckup rc oscillator that operates at 2mhz or 32 khz. the embedded pll can be configured to generate an internal system clock of up to 36 mhz. the pll output frequency can be programmed using a wide selection of multipliers and dividers. voltag e regulators the STR73XF requires an external 4.5 to 5.5v power supply. there are two internal voltage regulators for generating the 1.8v power supply needed by the core and peripherals. the main vr is switched off and the low power vr switched on when the application puts the STR73XF in low power wait for interrupt (lpwfi) mode. low voltage detectors the voltage regulator and flash modules each have an embedded lvd that monitors the internal 1.8v supply. if the voltage drops be low a certain threshold, the lvd will reset the STR73XF. note: an external power-on reset must be provided ensure the microcontroller starts-up correctly. introduction STR73XF 6/53 1.2 on-chip peripherals can interfaces the three can modules are compliant with the can specification v2.0 part b (active). the bit rate can be programmed up to 1 mbaud. these are not available in the str735 and str736. dma 4 dma controllers, each with 4 data streams manage memory to memory, peripheral to peripheral, peripheral to memory and memory to peripheral transfers. the dma requests are connected to tim timers, bspi0, bspi1, b spi2 and adc. one of the streams can be configured to be triggered by a software request, independently from any peripheral activity. 16-bit timers (tim) each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a pwm channel with selectable frequency. this provides a total of 16 independent pwms (12 in 100-pin devices) when added with the pwm modules (see next paragraph). pwm modules (pwm) the six 16-bit pwm modules ha ve independently programmab le periods and duty-cycles, with 5+3 bit prescaler factor. timebase timers (tb) the three 16-bit timebase timers with 8-bit prescaler for general purpose time triggering operations. realtime clock (rtc) the rtc provides a set of continuously running counters driven by separate clock signal derived from the main oscillator. the rtc can be used as a general timebase or clock/calendar/alarm function. when the STR73XF is in lpwfi mode the rtc keeps running, powered by the low power voltage regulator. uarts the 4 uarts allow full duplex, asynchronous, communications with external devices with independently programmable tx and rx baud rates up to 625k baud. buffered serial peripheral interfaces (bspi) each of the three bspis allow full duplex, synchronous communica tions with external devices, master or slave communication at up 6 mb/s (@36 mhz system clock). i 2 c interfaces the two i 2 c interfaces provide multi-master and slave functions, support normal and fast i 2 c mode (400 khz) and 7 or 10-bit addressing modes. a/d converter the 10-bit analog to digital converter, converts up to 16 channels in single-shot or continuous conversion modes (12 channels in 100-pin devices). the minimum conversion time is 3us. STR73XF introduction 7/53 watchdog the 16-bit watchdog timer protects the application against hardware or software failures and ensures recovery by generating a reset. i/o ports up to 112 i/o ports (72 in 100-pin devices) are programmable as general purpose input/output or alternate function. external interrupts and wake-up lines 16 external interrupts lines are available for application use. in addition, up to 32 external wakeup lines (18 in 100-pin devices) can be used as general purpose interrupts or to wake- up the application from stop mode. block diagram STR73XF 8/53 2 block diagram figure 1. str730f/str735f block diagram apb bus 122 ports gpio ports 0-6 watchdog i2c0-1 wakeup/int (wiu) uart0, 1, 2, 3 wakeup timer apb bus bspi 0-2 rtc can 0-2* interrupt ctl (eic) a/d converter (adc) 32 af 8 af 16 af 12 af xtal1 xtal2 osc timer (tim) 2-4 4 af af: alternate function on i/o port pin pwm 0-5 clock mgt (cmu) timer (tim) 0-1 8 af timer (tim) 5-9 20 af 6 af (wut) timebase timer (tb) 0-2 6 af 12 af * can peripherals not available on str735f. flash program memory 64/128/256k apb bridge 0 apb bridge 1 power supply prccu/pll ram 16k jtag arm7tdmi cpu jtdi jtck jtms jtrst jtdo rstin v18 vdd vss vreg vdda vssa arm7 native bus dma0-3 ahb bus ahb bridge m0 m1 test STR73XF block diagram 9/53 figure 2. str731f/str736 block diagram apb bus 72 ports gpio ports 0-6 flash program memory 64/128/256k watchdog i2c0-1 wakeup/int (wiu) uart0, 1, 2, 3 wakeup timer apb bridge 0 apb bridge 1 apb bus bspi 0-2 rtc can 0-2* interrupt ctl (eic) a/d converter (adc) power supply prccu/pll ram 16k jtag arm7tdmi cpu 18 af 8 af 12 af 12 af xtal1 xtal2 jtdi jtck jtms jtrst jtdo rstin v18 vdd vss osc vreg vdda vssa timer (tim) 2-4 arm7 native bus 4 af af: alternate function on i/o port pin pwm 0-5 clock mgt (cmu) dma0-3 timer (tim) 0-1 8 af timer (tim) 5 4 af 6 af (wut) timebase timer (tb) 0-2 ahb bus ahb bridge 6 af m0 m1 test 12 af * can peripherals not available on str736f. block diagram STR73XF 10/53 2.1 related documentation available from www.arm.com: arm7tdmi technical reference manual available from http://www.st.com: str73x reference manual str7 flash programming reference manual str73x software library user manual for a list of related app lication notes refer to http://www.st.com . STR73XF block diagram 11/53 2.2 pin description 2.2.1 str730f/str735f (tqfp144) figure 3. str730f/str735f pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 ocmpb2 / p0.0 ocmpa2 / p0.1 icapa2 / p0.2 icapb2 / p0.3 v ss v dd ocmpa5 / p0.4 ocmpb5 / p0.5 icapa5 / p0.6 icapb5 / p0.7 ocmpa6 / p0.8 ocmpb6 / p0.9 ocmpa7 / p0.10 ocmpb7 / p0.11 v dd v ss icapa3 / p0.12 icapb3 / p0.13 ocmpb3 / p0.14 ocmpa3 / p0.15 ocmpa4 / p1.0 ocmpb4 / p1.1 icapb4 / p1.2 icapa4 / p1.3 v ss v dd p1.4 p1.5 ocmpb1 / p1.6 ocmpa1 / p1.7 int0 / ocmpa0 / p1.8 int1 / ocmpb0 / p1.9 icapb0 / wup28 / p1.10 icapa0 / wup29 / p1.11 icapa1 / wup30 / p1.12 icapb1 / wup31 / p1.13 p4.14 / ss1 p4.13 / icapb9 p4.12 / icapa9 / wup21 p4.11 / ocmpb8 p4.10 / icapa6 / wup20 p4.9 / icapb6 p4.8 / ocmpa8 p4.7 / sda1 p4.6 / scl1 / wup19 p4.5 / can2rx / wup18 p4.4 / can2tx p4.3 / icapb8 / wup27 p4.2 / icapa8 / wup26 p4.1 / icapb7 / wup25 p4.0 / icapa7 / wup24 v dd v ss jtdo jtck jtms jtdi jtrst v ss v dd p3.15 / ain15 / int5 p3.14 / ain14 / int4 p3.13 / ain13 / int3 p3.12 / ain12 / int2 p3.11 / ain11 p3.10 / ain10 p3.9 / ain9 p3.8 / ain8 v dda v ssa p3.7 / ain7 p3.6 / ain6 wup12 / can0rx / p1.14 can0tx / p1.15 pwm0 / p2.0 wup13 / can1rx / p2.1 can1tx / p2.2 pwm1 / p2.3 pwm2 / p2.4 pwm3 / p2.5 pwm4 / p2.6 pwm5 / p2.7 m0 rstin m1 v dd v ss xtal1 xtal2 v ss tdo1 / p2.8 wup14 / rdi1 / p2.9 wup16 / p2.10 wup17 / p2.11 int14 / p2.12 int15 / p2.13 wup15 / scl0 / p2.14 sda0 / p2.15 test v bias v ss v dd ain0 / p3.0 ain1 / p3.1 ain2 / p3.2 ain3 / p3.3 ain4 / p3.4 ain5 / p3.5 p6.15 / wup9 p6.14 / ss0 p6.13 / sck0 / wup11 p6.12 / mosi0 p6.11 / miso0 p6.10 / wup8 p6.9 / tdo0 p6.8 / rdi0 / wup10 p6.7 / wup7 p6.6 / wup6 p6.5 / wup5 p6.4 / tdo3 / wup4 p6.3 / wup3 p6.2 / rdi3 / wup2 p6.1 / wup1 p6.0 / wup0 vdd vss v18 p5.15 / int13 p5.14 / int12 p5.13 / int11 p5.12 / int10 p5.11 / tdo2 / int9 p5.10 / rdi2 / int8 p5.9 / int7 p5.8 / int6 p5.7 / miso2 p5.6 / mosi2 p5.5 / sck2 / wup23 p5.4 / ss2 p5.3 / ocmpb9 p5.2 / ocmpa9 p5.1 / miso1 p5.0 / mosi1 p4.15 / sck1 / wup22 str730f/str735f note 1: can alternate functions not available on str735f. block diagram STR73XF 12/53 2.2.2 str730f/st r735f (lfbga144) note 1: can alternate functions not available on str735f. table 2. str730f/str735f lfbga ball connections ball name ball name ball name ball name a1 p0.0 / ocmpb2 b1 p0.4 / ocmpa5 c1 p0.5 / ocmpb5 d1 v ss a2 p6.10 / wup8 b2 p0.1 / ocmpa2 c2 p0.2 / icapa2 d2 v dd a3 p6.9 / tdo0 b3 p6.15 / wup9 c3 p0.3 / icapb2 d3 p0.6 / icapa5 a4 p6.12 / mosi0 b4 p6.13 / scko / wup11 c4 p6.14 / sso d4 p0.7 /icapb5 a5 p6.6 / wup6 b5 p6.7 / wup7 c5 p6.8 / rdi0 / wup10 d5 p6.11 / miso0 a6 v 18 b6 p6.2 / wup2 / rdi3 c6 p6.3 / wup3 d6 p6.4 / wup4 /tdo3 a7 p5.15 / int13 b7 p5.14 / int12 c7 v ss d7 vdd a8 p5.8 / int6 b8 p5.9 / int7 c8 p5.10 / int8 / rdi2 d8 p5.12 / int10 a9 p5.2 / ocmpa9 b9 p5.3 / ocmpb9 c9 p5.4 / ss2 d9 p5.5 / sck2 / wup23 a10 p5.7 / miso2 b10 p5.0 / mosi1 c10 p5.1 / miso1 d10 p4.13 / icapb9 a11 p5.6 / mosi2 b11 p4.15 / sck1 / wup22 c11 p4.14 / ss1 d11 p4.12 / icapa9 / wup21 a12 p5.11 / tdo2 / int9 b12 p4.8 / ocmpa8 c12 p4.7 / sda1 d12 p4.11 / ocmpb8 e1 p0.8 / ocmpa6 f1 v dd g1 v ss h1 v dd e2 p0.9 / ocmpb6 f2 p0.13 / icapb3 g2 p1.2 / icapb4 h2 p1.8 / ocmpa0 / int0 e3 p0.10 / ocmpa7 f3 p0.14 / ocmpb3 g3 p1.3 / icapa4 h3 p1.9 / ocmpb0 / int1 e4 p0.11 / ocmpb7 f4 p0.15 / ocmpa3 g4 v ss h4 p1.10 / icapb0 / wup28 e5 p0.12 / icapa3 f5 p1.0 / ocmpa4 g5 p1.5 h5 xtal2 e6 p6.5 / wup5 f6 p1.1 / ocmpb4 g6 p2.11 / wup17 h6 p2.10 / wup16 e7 p6.0 / wup0 f7 p6.1 / wup1 g7 p4.0 / icapa7 / wup24 h7 p2.15 / sda 0 e8 p5.13 / int11 f8 p4.4 / can2tx 1) g8 vdd h8 jtms e9 p4.10 / icapa6 / wup20 f9 p4.3 / icapb8 / wup27 g9 vss h9 vss e10 p4.9 / icapb6 f10 p4.2 / icapa8 / wup26 g10 jtdo h10 vdd e11 p4.6 / scl1 / wup19 f11 p4.1 / icapb7 / wup25 g11 jtck h11 p3.15 / ain15 / int5 e12 p4.5 / wup18 / can2rx 1) f12 jtdi g12 njtrst h12 p3.14 / ain14 / int4 j1 p1.4 k1 p1.6 / ocmpb1 l1 p1.7 / ocmpa1 m1 p1.14 / can0rx 1) / wup12 j2 p1.11 / icapa0 / wup29 k2 p1.13 / icapb1 / wup31 l2 p1.15 / can0tx 1) m2 p2.4 / pwm2 j3 p1.12 / icapa1 / wup30 k3 p2.1 / can1rx 1) / wup13 l3 p2.0 / pwm0 m3 p2.5 / pwm3 j4 p2.7 / pwm5 k4 p2.6 / pwm4 l4 p2.3 / pwm1 m4 p2.2 / can1tx 1) j5 v dd k5 m1 l5 rstin m5 m0 j6 p2.9 / rdi1 / wup14 k6 p2.8 / tdo1 l6 v ss m6 v ss j7 p2.14 / scl 0 / wup15 k7 p2.13 / int15 l7 p2.12 / int14 m7 xtal1 j8 p3.1 / ain1 k8 p3.0 / ain0 l8 vbias m8 tst j9 p3.13 / ain13 / int3 k9 p3.4 / ain4 l9 p3.3 / ain3 m9 p3.2 / ain2 j10 p3.12 / ain12 / int2 k10 v dda l10 p3.5 / ain5 m10 v ss j11 p3.9 / ain9 k11 v ssa l11 p3.7 / ain7 m11 v dd j12 p3.8 / ain8 k12 p3.11 / ain11 l12 p3.10 / ain10 m12 p3.6 / ain6 STR73XF block diagram 13/53 2.2.3 str731f/str736f (tqfp100) figure 4. str731f/str736f pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 ocmpb2 / p0.0 ocmpa2 / p0.1 icapa2 / p0.2 icapb2 / p0.3 ocmpa5 / p0.4 ocmpb5 / p0.5 icapa5 / p0.6 v dd v ss icapa3 / p0.12 icapb3 / p0.13 ocmpb3 / p0.14 ocmpa3 / p0.15 ocmpa4 / p1.0 ocmpb4 / p1.1 icapb4 / p1.2 icapa4 / p1.3 ocmpb1 / p1.6 ocmpa1 / p1.7 int0 / ocmpa0 / p1.8 int1 / ocmpb0 / p1.9 icapb0 / wup28 / p1.10 icapa0 / wup29 / p1.11 icapa1 / wup30 / p1.12 icapb1 / wup31 / p1.13 p4.14 / ss1 p4.10 / icapb5 / wup20 p4.7 / sda1 p4.6 / scl1 / wup19 v dd v ss jtdo jtck jtms jtdi jtrst v ss v dd p3.15 / ain11 / int5 p3.14 / ain10 / int4 p3.13 / ain9 / int3 p3.12 / ain8 / int2 p3.11 / ain7 p3.10 / ain6 p3.9 / ain5 p3.8 / ain4 v dda v ssa p3.7 / ain3 p3.6 / ain2 wup12 / can0rx / p1.14 can0tx / p1.15 pwm0 / p2.0 wup13 / can1rx / p2.1 can1tx / p2.2 pwm1 / p2.3 pwm2 / p2.4 m0 rstin m1 v dd v ss xtal1 xtal2 v ss can2rx / tdo1 / p2.8 wup14 / can2tx / rdi1 / p2.9 wup15 / scl0 / p2.14 sda0 / p2.15 test v bias v ss v dd ain0 / p3.4 ain1 / p3.5 p6.14 / ss0 p6.13 / sck0 / wup11 p6.12 / mosi0 p6.11 / miso0 p6.9 / tdo0 p6.8 / rdi0 / wup10 p6.6 / wup6 p6.4 / tdo3 / wup4 p6.2 / rdi3 / wup2 p6.0 / wup0 vdd vss v18 p5.12 / int10 p5.11 / tdo2 / int9 p5.10 / rdi2 / int8 p5.9 / pwm5 / int7 p5.8 / pwm4 / int6 p5.7 / miso2 p5.6 / mosi2 p5.5 / sck2 / wup23 p5.4 / ss2 /pwm3 p5.1 / miso1 p5.0 / mosi1 p4.15 / sck1 / wup22 str731f/str736f note 1: can alternate functions not available on str736f. block diagram STR73XF 14/53 legend / abbreviations for ta bl e 3 : type: i = input, o = output, s = supply, hiz= high impedance, in/output level: t t = ttl 0.8v / 2v with input trigger c t = cmos 0.3v dd /0.7v dd with input trigger port and control configuration: input: pu/pd = with internal 100k ? weak pull-up or pull down output: od = open drain (logic level) pp = push-pull interrupts: intx =external interrupt line wupx =wake-up interrupt line the reset state (during and just after the reset) of the i/o ports is input floating (input tristate ttl mode). to avoid excess power consumption, unused i/o ports must be tied to ground. table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp 1 a1 1 p0.0/ocmpb2 i/o t t 2ma x x port 0.0 tim2: output compare b output 2 b2 2 p0.1/ocmpa2 i/o t t 2ma x x port 0.1 tim2: output compare a output 3 c2 3 p0.2/icapa2 i/o t t 2ma x x port 0.2 tim2: input capture a input 4 c3 4 p0.3/icapb2 i/o t t 2ma x x port 0.3 tim2: input capture b input 5d1 v ss s ground 6d2 v dd s supply voltage (5v) 7 b1 5 p0.4/ocmpa5 i/o t t 2ma x x port 0.4 tim5: output compare a output 8 c1 6 p0.5/ocmpb5 i/o t t 2ma x x port 0.5 tim5: output compare b output 9 d3 7 p0.6/icapa5 i/o t t 2ma x x port 0.6 tim5: input capture a input 10 d4 p0.7/icapb5 i/o t t 2ma x x port 0.7 tim5: input capture b input 11 e1 p0.8/ocmpa6 i/o t t 2ma x x port 0.8 tim6: output compare a output 12 e2 p0.9/ocmpb6 i/o t t 2ma x x port 0.9 tim6: output compare b output 13 e3 p0.10/ocmpa7 i/o t t 2ma x x port 0.10 tim7: output compare a output 14 e4 p0.11/ocmpb 7 i/o t t 2ma x x port 0.11 tim7: output compare b output 15 f1 8 v dd s supply voltage (5v) 16 g1 9 v ss s ground 17 e5 10 p0.12/icapa3 i/o t t 2ma x x port 0.12 tim3: input capture a input STR73XF block diagram 15/53 18 f2 11 p0.13/icapb3 i/o t t 2ma x x port 0.13 tim3: input capture b input 19 f3 12 p0.14/ocmpb 3 i/o t t 2ma x x port 0.14 tim3: output compare b output 20 f4 13 p0.15/ocmpa3 i/o t t 2ma x x port 0.15 tim3: output compare a output 21 f5 14 p1.0/ocmpa4 i/o t t 2ma x x port 1.0 tim4: output compare a output 22 f6 15 p1.1/ocmpb4 i/o t t 2ma x x port 1.1 tim4: output compare b output 23 g2 16 p1.2/icapb4 i/o t t 2ma x x port 1.2 tim4: input capture b input 24 g3 17 p1.3/icapa4 i/o t t 2ma x x port 1.3 tim4: input capture a input 25 g4 v ss s ground 26 h1 v dd s supply voltage (5v) 27 j1 p1.4 i/o t t 2ma x x port 1.4 28 g5 p1.5 i/o t t 2ma x x port 1.5 29 k1 18 p1.6/ocmpb1 i/o t t 2ma x x port 1.6 tim1: output compare b output 30 l1 19 p1.7/ocmpa1 i/o t t 2ma x x port 1.7 tim1: output compare a output 31 h2 20 p1.8/ocmpa0 i/o t t int0 2ma x x port 1.8 tim0: output compare a output 32 h3 21 p1.9/ocmpb0 i/o t t int1 2ma x x port 1.9 tim0: output compare b output 33 h4 22 p1.10/icapb0 i/o t t wup28 2ma x x port 1.10 tim0: input capture b input 34 j2 23 p1.11/icapa0 i/o t t wup29 2ma x x port 1.11 tim0: input capture a input 35 j3 24 p1.12/icapa1 i/o t t wup30 2ma x x port 1.12 tim1: input capture a input 36 k2 25 p1.13/icapb1 i/o t t wup31 2ma x x port 1.13 tim1: input capture b input 37 m1 26 p1.14/can0rx i/o t t wup12 2ma x x port 1.14 can0: receive data input 38 l2 27 p1.15/can0tx i/o t t 2ma x x port 1.15 can0: transmit data output 39 l3 28 p2.0/pwm0 i/o t t 2ma x x port 2.0 pwm0: pwm output 40 k3 29 p2.1/can1rx i/o t t wup13 2ma x x port 2.1 can1: receive data input 41 m4 30 p2.2/can1tx i/o t t 2ma x x port 2.2 can1: transmit data output 42 l4 31 p2.3/pwm1 i/o t t 2ma x x port 2.3 pwm1: pwm output 43 m2 32 p2.4/pwm2 i/o t t 2ma x x port 2.4 pwm2: pwm output table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp block diagram STR73XF 16/53 44 m3 p2.5/pwm3 i/o t t 2ma x x port 2.5 pwm3: pwm output 45 k4 p2.6/pwm4 i/o t t 2ma x x port 2.6 pwm4: pwm output 46 j4 p2.7/pwm5 i/o t t 2ma x x port 2.7 pwm5: pwm output 47 m5 33 m0 i t t pd boot: mode selection 0 input 48 l5 34 rstin i c t pu reset input 49 k5 35 m1 i t t pd boot: mode selection 1 input 50 j5 36 v dd s supply voltage (5v) 51 m6 37 v ss s ground 52 m7 38 xtal1 i oscillator amplifier circuit input and internal clock generator input. 53 h5 39 xtal2 o oscillator amplifier circuit output. 54 l6 40 v ss s ground 55 k6 41 p2.8/tdo1/ca n2rx i/o t t 2ma x x port 2.8 uart1: transmit data output can2: receive data input (tqfp100 only) 56 j6 42 p2.9/rdi1/can 2tx i/o t t wup14 2ma x x port 2.9 uart1: receive data input can2: transmit data output (tqfp100 only) 57 h6 p2.10 i/o t t wup16 2ma x x port 2.10 58 g6 p2.11 i/o t t wup17 2ma x x port 2.11 59 l7 p2.12 i/o t t int14 2ma x x port 2.12 60 k7 p2.13 i/o t t int15 2ma x x port 2.13 61 j7 43 p2.14/scl0 i/o t t wup15 2ma x x port 2.14 i2c0:serial clock 62 h7 44 p2.15/sda0 i/o t t 2ma x x port 2.15 i2c0:serial data 63 m8 45 test i pd reserved pin. must be tied to ground table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp STR73XF block diagram 17/53 64 l8 46 v bias s internal rc oscillator bias. a 1.3m ? external resistor has to be connected to this pin when a 32khz rc oscillator frequency is used. 65 m10 47 v ss s ground 66 m11 48 v dd s supply voltage (5v) 67 k8 p3.0/ain0 i/o t t 2ma x x port 3.0 adc: analog input 0 68 j8 p3.1/ain1 i/o t t 2ma x x port 3.1 adc: analog input 1 69 m9 p3.2/ain2 i/o t t 2ma x x port 3.2 adc: analog input 2 70 l9 p3.3/ain3 i/o t t 2ma x x port 3.3 adc: analog input 3 71 k9 49 p3.4/ain4 i/o t t 2ma x x port 3.4 adc: analog input 4 (ain0 in tqfp100) 72 l10 50 p3.5/ain5 i/o t t 2ma x x port 3.5 adc: analog input 5 (ain1 in tqfp100) 73 m12 51 p3.6/ain6 i/o t t 2ma x x port 3.6 adc: analog input 6 (ain2 in tqfp100) 74 l11 52 p3.7/ain7 i/o t t 2ma x x port 3.7 adc: analog input 7 (ain3 in tqfp100) 75 k11 53 v ssa s reference ground for a/d converter 76 k10 54 v dda s reference voltage for a/d converter 77 j12 55 p3.8/ain8 i/o t t 2ma x x port 3.8 adc: analog input 8 (ain4 in tqfp100) 78 j11 56 p3.9/ain9 i/o t t 2ma x x port 3.9 adc: analog input 9 (ain5 in tqfp100) 79 l12 57 p3.10/ain10 i/o t t 2ma x x port 3.10 adc: analog input 10 (ain6 in tqfp100) 80 k12 58 p3.11/ain11 i/o t t 2ma x x port 3.11 adc: analog input 11 (ain7 in tqfp100) 81 j10 59 p3.12/ain12 i/o t t int2 2ma x x port 3.12 adc: analog input 12 (ain8 in tqfp100) 82 j9 60 p3.13/ain13 i/o t t int3 2ma x x port 3.13 adc: analog input 13 (ain9 in tqfp100) 83 h12 61 p3.14/ain14 i/o t t int4 2ma x x port 3.14 adc: analog input 14 (ain10 in tqfp100) 84 h11 62 p3.15/ain15 i/o t t int5 2ma x x port 3.15 adc: analog input 15 (ain11 in tqfp100) 85 h10 63 v dd s supply voltage (5v) table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp block diagram STR73XF 18/53 86 h9 64 v ss s ground 87 g12 65 jtrst i t t pu jtag reset input 88 f12 66 jtdi i t t pu jtag data input 89 h8 67 jtms i t t pu jtag mode selection input 90 g11 68 jtck i t t pd jtag clock input 91 g10 69 jtdo o 4ma jtag data output. note: reset state = hiz 92 g9 70 v ss s ground 93 g8 71 v dd s supply voltage (5v) 94 g7 p4.0/icapa7 i/o t t wup24 2ma x x port 4.0 tim7: input capture a input 95 f11 p4.1/icapb7 i/o t t wup25 2ma x x port 4.1 tim7: input capture b input 96 f10 p4.2/icapa8 i/o t t wup26 2ma x x port 4.2 tim8: input capture a input 97 f9 p4.3/icapb8 i/o t t wup27 2ma x x port 4.3 tim8: input capture b input 98 f8 p4.4/can2tx i/o t t 2ma x x port 4.4 can2: transmit data output 99 e12 p4.5/can2rx i/o t t wup18 2ma x x port 4.5 can2: receive data input 100 e11 72 p4.6/scl1 i/o t t wup19 2ma x x port 4.6 i2c1:serial clock 101 c12 73 p4.7/sda1 i/o t t 2ma x x port 4.7 i2c1:serial data 102 b12 p4.8/ocmpa8 i/o t t 2ma x x port 4.8 tim8: output compare a output 103 e10 p4.9/icapb6 i/o t t 2ma x x port 4.9 tim6: input capture b input 104 e9 74 p4.10/icapa6/i capb5 i/o t t wup20 2ma x x port 4.10 tim6: input capture a input (144-pin pkg only) tim5: input capture b input (tqfp100 only) 105 d12 p4.11/ocmpb 8 i/o t t 2ma x x port 4.11 tim8: output compare b output 106 d11 p4.12/icapa9 i/o t t wup21 2ma x x port 4.12 tim9: input capture a input 107 d10 p4.13/icapb9 i/o t t 2ma x x port 4.13 tim9: input capture b input 108 c11 75 p4.14/ss 1 i/o t t 2ma x x port 4.14 bspi1: slave select 109 b11 76 p4.15/sck1 i/o t t wup22 2ma x x port 4.15 bspi1: serial clock table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp STR73XF block diagram 19/53 110 b10 77 p5.0/mosi1 i/o t t 2ma x x port 5.0 bspi1: master output/slave input 111 c10 78 p5.1/miso1 i/o t t 2ma x x port 5.1 bspi1: master input/slave output 112 a9 p5.2/ocmpa9 i/o t t 2ma x x port 5.2 tim9: output compare a output 113 b9 p5.3/ocmpb9 i/o t t 2ma x x port 5.3 tim9: output compare b output 114 c9 79 p5.4/ss 2/pwm 3 i/o t t 2ma x x port 5.4 bspi2: slave select pwm3: pwm output (tqfp100 only) 115 d9 80 p5.5/sck2 i/o t t wup23 2ma x x port 5.5 bspi2: serial clock 116 a11 81 p5.6/mosi2 i/o t t 2ma x x port 5.6 bspi2: master output/slave input 117 a10 82 p5.7/miso2 i/o t t 2ma x x port 5.7 bspi2: master input/slave output 118 a8 83 p5.8/pwm4 i/o t t int6 2ma x x port 5.8 pwm4: pwm output (tqfp100 only) 119 b8 84 p5.9/pwm5 i/o t t int7 2ma x x port 5.9 pwm5: pwm output (tqfp100 only) 120 c8 85 p5.10/rdi2 i/o t t int8 2ma x x port 5.10 uart2: receive data input 121 a12 86 p5.11/tdo2 i/o t t int9 2ma x x port 5.11 uart2: transmit data output 122 d8 87 p5.12 i/o t t int10 2ma x x port 5.12 123 e8 p5.13 i/o t t int11 2ma x x port 5.13 124 b7 p5.14 i/o t t int12 2ma x x port 5.14 125 a7 p5.15 i/o t t int13 2ma x x port 5.15 126 a6 88 v 18 s 1.8v decoupling pin: a decoupling capacitor (recommended value: 100nf) must be connected between this pin and nearest v ss pin. 127 c7 89 v ss s ground 128 d7 90 v dd s supply voltage (5v) table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp block diagram STR73XF 20/53 129 e7 91 p6.0 i/o t t wup0 8ma x x port 6.0 130 f7 p6.1 i/o t t wup1 2ma x x port 6.1 131 b6 92 p6.2/rdi3 i/o t t wup2 2ma x x port 6.2 uart3: receive data input 132 c6 p6.3 i/o t t wup3 2ma x x port 6.3 133 d6 93 p6.4/tdo3 i/o t t wup4 2ma x x port 6.4 uart3: transmit data output 134 e6 p6.5 i/o t t wup5 2ma x x port 6.5 135 a5 94 p6.6 i/o t t wup6 2ma x x port 6.6 136 b5 p6.7 i/o t t wup7 2ma x x port 6.7 137 c5 95 p6.8/rdi0 i/o t t wup10 2ma x x port 6.8 uart0: receive data input 138 a3 96 p6.9/tdo0 i/o t t 2ma x x port 6.9 uart0: transmit data output 139 a2 p6.10 i/o t t wup8 2ma x x port 6.10 140 d5 97 p6.11/miso0 i/o t t 2ma x x port 6.11 bspi0: master input/slave output 141 a4 98 p6.12/mosi0 i/o t t 2ma x x port 6.12 bspi0: master output/slave input 142 b4 99 p6.13/sck0 i/o t t wup11 2ma x x port 6.13 bspi0: serial clock 143 c4 10 0 p6.14/ss 0 i/o t t 2ma x x port 6.14 bspi0: slave select 144 b3 p6.15 i/o t t wup9 2ma x x port 6.15 table 3. STR73XF pin description pin n pin name type input output main functio n (after reset) alternate function tqfp144 lfbga144 tqfp100 input level pu/pd interrupt capability od pp STR73XF block diagram 21/53 2.3 memory mapping figure 5 shows the various memory configurations of the STR73XF system. the system memory map (from 0x0000_0000 to 0xffff_ffff) is shown on the left part of the figure, the right part shows maps of the flash and apb areas. for flexibility the flash or ram addresses can be aliased to block 0 addresses using the remapping feature most reserved memory spaces (gray shaded areas in figure 5 ) are protected from access by the user code. when an access this memory space is attempted, an abort signal is generated. depending on the type of access , the arm processor will ent er ?prefetch abort? state (exception vector 0x0000_000c) or ?data abort? state (exception vector 0x0000_0010). it is up to the application software to manage these abort exceptions. figure 5. memory map flash memory space 64k/128/256 kbytes apb bridge 1 regs addressable memory space 0 1 2 3 4 1k 5 6 7 0x1fff ffff 0x2000 0000 0x3fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x8000 0000 0x9fff ffff 0xa000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 0xffff 8000 0xffff 83ff 0xffff 8400 0xffff 87ff 0xffff 8800 0xffff 8bff 0xffff 8c00 0xffff 8fff 0xffff 9000 0xffff 93ff 0xffff 9400 0xffff 97ff 0xffff 9800 0xffff 9bff 0xffff 9c00 0xffff 9fff 0xffff a000 0xffff a3ff 0xffff a800 0xffff abff 0xffff ac00 0xffff afff 0xffff b000 0xffff c3ff 0xffff c400 0xffff c7ff 0xffff c800 0xffff cbff 0xffff cc00 0xffff d000 0xffff ffff 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 0x0010 0017 0x6000 03ff 0x0000 0000 apb memory space 4 gbytes 32 kbytes flash (1) 64k/128k/256k prccu 1k apb to arm7 bridge 0xffff 8000 32k eic 0xffff fc00 1k apb bridge 0 regs 0xffff fbff 0xffff cfff config. regs 64b drawing not to scale 0x4000 003f flash 0x8010 0017 64k/128k/256k 0xffff c000 0xffff d400 0xffff d3ff 0xffff d800 0xffff d7ff 0xffff dc00 0xffff dbff 0xffff e000 0xffff dfff 0xffff e400 0xffff e3ff 0xffff e800 0xffff e7ff 0xffff ec00 0xffff ebff 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k 1k i 2 c 0 reserved reserved reserved tb 0-2 uart 0 uart 1 tim 0 tim 1 can 0 (4) can 1 (4) can 2 (4) pwm 0-5 gp i/o 0-6 bspi 0 bspi 1 bspi 2 dma 0-3 rtc adc 0xffff f800 0xffff f7ff 0xffff f400 0xffff f3ff 0xffff f000 0xffff efff 0xffff b3ff 0xffff b400 0xffff b7ff 0xffff b800 ram 16k 1k 0xffff bbff tim 2 tim 3 tim 4 tim 5-9 reserved wakeup reserved 1k 0xffff bfff 0xffff bc00 i 2 c 1 access to gray shaded area will return an abort b0f5 (3) 0x8000 1fff 0x8000 0000 0x8000 2000 0x8000 3fff 0x8000 4000 0x8000 5fff 0x8000 6000 0x8000 7fff 0x8000 8000 0x8000 ffff 0x8001 0000 0x8001 ffff 0x8010 0000 0x8010 0017 0x8010 c000 0x8010 dfff 8k 8k 8k 8k 32k 8k 20b 64k b0f4 flash registers native arbiter 16b b0f6 (2) 0x8002 0000 0x8002 ffff 64k b0f7 (2) 0x8003 0000 0x8003 ffff 64k uart 2 uart 3 0xffff 9e00 0xffff a200 cmu 0xffff f600 0x2000 000f system memory b0f3 b0f2 b0f1 b0tf 1k 1k 1k (1) flash aliased at 0x0000 0000h by system decoder for booting wi th valid instruction upon reset from block b0 (8 kbytes) 0xffff a400 0xffff a7ff 1k wdg wakeuptim 0xffff a600 0xa000 3fff (2) only available in str73xz2/v2 (3) only available in str73xz2/v2 and str73xz1/v1 (4) only available in str730/str731 electrical parameters STR73XF 22/53 3 electrical parameters 3.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 3.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a =25c and t a =t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 3.1.2 typical values unless otherwise specified, typical data are based on t a =25c and v dd =5v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 3.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 3.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 6 . 3.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 7 . figure 6. pin loading conditions figure 7. pin input voltage l =50pf str7 pin v in str7 pin STR73XF electrical parameters 23/53 3.2 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability 1. all 5v power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external 5v supply 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in STR73XF electrical parameters 25/53 3.3 operating conditions subject to general operating conditions for v dd , and t a . table 7. general operating conditions symbol parameter conditions min max unit f mclk internal cpu and system clock frequency accessing sram or flash (zero wait state flash access up to 36 mhz) 036mhz v dd standard operating voltage 4.5 5.5 v v dda operating analog refer- ence voltage with respect to ground 4.5 v dd +0.1 v t a ambient temperature range 6 partnumber suffix 7 partnumber suffix -40 -40 85 105 c table 8. operating conditions at power-up / power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate subject to general operating conditions for t a . -20-ms/v electrical parameters STR73XF 26/53 3.3.1 supply current characteristics the current consumption is measured as described in figure 6 and figure 7 . total current consumption the mcu is placed under the following conditions: all i/o pins in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except if explicitly mentioned. subject to general operating conditions for v dd , and t a . table 9. total current consumption notes: 1. typical data are based on t a =25c, v dd =5v 2. data based on characterization results, tested in production at v dd max. and t a = 25c. 3. i/o in static configuration (not toggling). run mode is almost independent of temperature . on the contrary run mode current is highly dependent on the application . the i ddrun value can be significantly reduced by the applic ation in the following ways: swit ch-off unused peripherals (default), reduce peripheral frequency through in ternal prescaler, fetch the most frequently-used functions from ram and use low power mode when possible. symbol parameter conditions typ 1) max 2) unit i dd run mode 3) formula, f mclk in mhz, ram execution 7 + 1.9 f mclk ma f mclk =36 mhz, ram execution 76 ma f mclk =36 mhz, flash execution 86 ma wfi mode f osc = 4 mhz, f mclk = f osc /16 = 250khz main voltage regulator on, lp voltage regulator = 2ma, rtc and wdg on, other modules off. 6.7 8 ma lpwfi mode f rc = high frequency (cmu_rcctl= 0x8), f mclk = f rc /16, lp voltage regulator = 2ma, other modules off. 220 350 a stop mode f osc = 4 mhz, rc oscillator on f rc = high frequency (cmu_rcctl= 0x0) lp voltage regulator = 6ma, rtc and wut on, other modules off. internal wake-up possible. 500 700 a f rc = high frequency (cmu_rcctl= 0xf), lp voltage regulator = 2ma. wut on. other modules off. internal wake-up possible. 150 220 lp voltage regulator = 2ma, wiu on, other modules off, external wake-up. 50 140 halt mode lp voltage regulator = 2ma. 50 140 a STR73XF electrical parameters 27/53 figure 8. stop i dd vs. vdd figure 9. halt i dd vs. v dd figure 10. wfi i dd vs. v dd figure 11. lpwfi i dd vs. v dd 0 50 100 150 200 250 300 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd stop (a) ta=-45c ta=25c ta=85c ta=105c 0 50 100 150 200 250 300 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd halt (a) ta=-45c ta=25c ta=85c ta=105c 5.5 6.0 6.5 7.0 7.5 8.0 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd wfi (ma) ta= -45c ta=25c ta=85c ta=105c 0 50 100 150 200 250 300 350 400 450 500 3.5 4 4.5 5 5.5 6 6.5 vdd (v) idd lpwfi (a) ta=-45c ta=25c ta=85c ta=105c electrical parameters STR73XF 28/53 typical application current consumption table 10. typical consumption in run mode at 25c and 85c conditions f mclk (mhz) f adc (mhz) typical i dd (ma) v dd = 5.5 v, rc oscillator off, pll on, rtc enabled, 1 timer (tim) running, and adc running in scan mode. code executing in ram 10 10 20 20 29 36 9 42 code executing in flash 10 10 22 20 32 36 9 48 table 11. typical consumption in run and low power modes at 25c mode conditions f mclk typical i dd run all peripherals on, ram execution 36mhz 76 ma 24mhz 56 ma wfi main voltage regulator on, flash on, eic on, wiu on, gpios on. 36mhz 33 ma 24mhz 31 ma slow pll off, main voltage regulator on 4mhz 11 ma clock2/16, main voltage regulator on, 250khz 8 ma clock2/16, main voltage regulator off, 250khz 3 ma rc oscillator running in low frequency, main crystal oscillator off, main voltage regulator off 29khz 2.5 ma lpwfi clock2/16, main voltage regulator off, lp voltage regulator = 2ma, flash in power down mode. 250khz 528 a stop main voltage regulator off, rtc on, rc oscillator off, lp voltage regulator = 6 ma - 378 a main voltage regulator off, rtc off, rc oscillator off, lp voltage regulator = 6 ma - 83 a main voltage regulator off, rtc off, rc oscillator off, lp voltage regulator = 4 ma - 64 a main voltage regulator off, rtc off, rc oscillator off, lp voltage regulator = 2 ma - 44 a halt rtc off, lp voltage regulator = 2 ma - 44 a STR73XF electrical parameters 29/53 on-chip peripherals notes : 1. data based on a differential i dd measurement between the on-chip peripheral when kept under reset, not clocked and the on-chip peripheral when clocked an d not kept under reset. this measurement does not include the pad toggling consumption. 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. table 12. peripheral current consumption at t a = 25c symbol parameter conditions typ unit i dd(rc) rc (backup oscillator) supply current high frequency 120 a low frequency 60 a i dd(tim) tim timer supply current 1) f mclk =36 mhz 350 a i dd(bspi) bspi supply current 1) 1.1 ma i dd(uart) uart supply current 1) 850 a i dd(i2c) i2c supply current 1) 430 a i dd(adc) adc supply current when converting 2) 5ma i dd(eic) eic supply current 2.88 ma i dd(can) can supply current 1) 2.95 ma i dd(gpio) gpio supply current 150 a i dd(tb) tb supply current 250 a i dd(pwm) pwm supply current 240 a i dd(rtc) rtc supply current 370 a i dd(dma) dma supply current 2.5 ma i dd(arb) native arbiter supply current 180 a i dd(ahb) ahb arbiter supply current 570 a i dd(wut) wut supply current 300 a i dd(wiu) wiu supply current 460 a electrical parameters STR73XF 30/53 3.3.2 clock and timi ng characteristics crystal / ceramic resonator oscillator the STR73XF can operate with a crystal o scillator or resonator clock source. figure 12 describes a simple model of the internal oscillator driver as well as example of connection for an oscillator or a resonator. figure 12. crystal oscillator and resonator notes 1) xtal2 must not be used to directly drive external circuits. 2) for test or boot purpose, xtal2 can be used as an high impedance input pin to provide an external clock to the device. xtal1 should be grounded, and xtal2 connected to a wave signal generator providing a 0 to vdd signal. direc tly driving xtal2 may results in deteriorated jitter and duty cycle. c l c l crystal xtal1 xtal2 r s resonator xtal1 xtal2 str73x str73x str73x xtal1 xtal2 i r f v dd STR73XF electrical parameters 31/53 v dd = 5v 10% , t a = -40c to t amax , unless otherwise specified. table 13. main oscillator characteristics symbol parameter conditions value unit min typ max f osc oscillator frequency 4 8 mhz g m oscillator transconductance 1.5 4.2 ma/v v osc 1) oscillation amplitude f osc = 4 mhz, t a = 25 o c-2.4- v f osc = 8 mhz, t a = 25 o c1.- v av 1) oscillator operating point sine wave middle, t a = 25 o c - 0.77 - v t stup 1) oscillator start-up time external crystal, v dd = 5.5v, f osc = 4 mhz, t a =-40 o c --12ms external crystal, v dd = 5.0v, f osc = 4 mhz, t a =25 o c -5.5 - ms external crystal, v dd = 5.5v, f osc = 6 mhz, t a =-40 o c --8ms external crystal, v dd = 5.0v, f osc = 6 mhz, t a =25 o c -3.3 - ms external crystal, v dd = 5.5v, f osc = 8 mhz, t a =-40 o c --7ms external crystal, v dd = 5.0v, f osc = 8 mhz, t a = 25 o c -2.7 - ms electrical parameters STR73XF 32/53 1. min and max values are guaranteed by char acterization, not tested in production. 2. c p represents the total capacitance between xtal1 and xtal2, including the shunt capacitance of the external quartz crystal as well as the total board parasitic cros s-capacitance between xtal1 track and xtal2 track. 3. c 1 represents the total capacitance between xtal1 and ground, including the exter nal capacitance tied to xtal1 pin (c l ) as well as the total parasitic capacitanc e between xtal1 track and ground (this includes application board track capacitance to ground and device pin capacitance). 4. c 2 represents the total capacitance between xtal2 and ground, including the exter nal capacitance tied to xtal1 pin (c l ) as well as the total parasitic capacitanc e between xtal2 track and ground (this includes application board track capacitance to ground and device pin capacitance). r f 1) feedback resistor f osc = 4 mhz cp 2) = 10pf c 1 3) = c 2 4) = 10pf 150 555 - ? c 1 = c 2 = 20pf 490 1035 - c 1 = c 2 = 30pf 490 1030 - c 1 = c 2 = 40pf 380 850 - f osc = 5 mhz cp = 10pf c 1 = c 2 = 10pf 160 470 - c 1 = c 2 = 20pf 415 800 - c 1 = c 2 = 30pf 340 735 - c 1 = c 2 = 40pf 260 580 - f osc = 6 mhz cp = 10pf c 1 = c 2 = 10pf 160 415 - c 1 = c 2 = 20pf 325 640 - c 1 = c 2 = 30pf 250 550 - c 1 = c 2 = 40pf 180 420 - f osc = 7 mhz cp = 10pf c 1 = c 2 = 10pf 160 375 - c 1 = c 2 = 20pf 260 525 - c 1 = c 2 = 30pf 185 420 - c 1 = c 2 = 40pf 135 315 - f osc = 8mhz cp = 10pf c 1 = c 2 = 10pf 155 340 - c 1 = c 2 = 20pf 210 435 - c 1 = c 2 = 30pf 145 335 - c 1 = c 2 = 40pf 100 245 - symbol parameter conditions value unit min typ max STR73XF electrical parameters 33/53 rc/backup oscillator characteristics v dd = 5v 10% , t a = -40c to t amax , unless otherwise specified. table 14. rc oscillator characteristics 1) cmu_rcctl = 0x8 2) rc frequency shift ve rsus average value (%) pll electrical characteristics v dd = 5v 10% , t a = -40c to t amax , unless otherwise specified table 15. pll characteristics. symbol parameter conditions value unit min typ max f rc rc frequency high frequency mode 1) 2.35 mhz low frequency mode 1) 29 khz f rchf rc high frequency cmu_rcctl = 0x0 3 mhz cmu_rcctl = 0xf 2.3 mhz f rclf rc low frequency cmu_rcctl = 0x0 35 khz cmu_rcctl = 0xf 30 khz f rchfs 2) rc high frequency stability fixed cmu_rcctl 10 % f rclfs 2) rc low frequency stability fixed cmu_rcctl 23 % t rcstup rc start-up time stable v dd , f rc = 2.35 mhz, t a = 25 o c 2.35 s symbol parameter conditions value unit min typ max f pllin (1) 1. f pllin is obtained from f osc directly or through an optional divider by 2. 2. typical data are based on t a =25c, v dd =5v 3. max value is guaranteed by characteri zation, not tested in production. pll reference clock fref_range = ?0? fref_range = ?1? 1.5 3.0 3.0 5.0 mhz f pllout pll output clock mx = ?00? mx = ?01? mx = ?10? mx = ?11? 20 x f pllin 12 x f pllin 28 x f pllin 16 x f pllin mhz f mclk system clock dx = 1..7 f pllout /dx 36 mhz f free (2) pll free running frequency fref_range = ?0?, mx0 = ?1? fref_range = ?0?, mx0 = ?0? fref_range = ?1?, mx0 = ?1? fref_range = ?1?, mx0 = ?0? 120 240 240 480 khz t lock (3) pll lock time stable oscillator (f pllin = 4 mhz), stable v dd 100 300 s ? t pkjit pll jitter (pk to pk) f pllin = 4 mhz (pulse generator) 1.5 ns electrical parameters STR73XF 34/53 1) flash memory has been programmed to enter power down mode during lpwfi. table 16. low-power mode wake-up timing symbol parameter conditions typ unit t wuhalt wake-up from halt mode 200 s t wustop wake-up from stop mode rc high frequency in stop mode 180 s rc low frequency in stop mode 234 s t wulpwfi 1) wake-up from lpwfi mode main voltage regulator on rc oscillator off f osc = 4 mhz, f mclk = f osc /16 ram or flash execution 27 s main voltage regulator on rc oscillator = high frequency flash execution 46 s main voltage regulator on rc oscillator = low frequency flash execution 3.6 ms STR73XF electrical parameters 35/53 3.3.3 memory characteristics flash memory 1. t a =-45c after 0 cycles, guaranteed by char acterization, not tested in production 2. all bits programmed to 0. 3. guaranteed by design, not tested in production. table 17. flash memory characteristics symbol parameter test conditions value unit min typ max 1) t wp word program (32-bit) 35 80 s t dwp double word program(64-bit) 64 150 s t bp64 bank program (64k) double word program 0.5 1.25 s t bp128 bank program (128k) double word program 1 2.5 s t bp256 bank program (256k) double word program 2 4.9 s t se8 sector erase (8k) not preprogrammed preprogrammed 2) 0.6 0.5 0.9 0.8 s t se32 sector erase (32k) not preprogrammed preprogrammed 2) 1.1 0.8 2 1.8 s t se64 sector erase (64k) not preprogrammed preprogrammed 2) 1.7 1.3 3.7 3.3 s t rpd 3) recovery from power-down 20 s t psl 3) program suspend latency 10 s t esl 3) erase suspend latency 30 s t esr 3) erase suspend rate min time from erase resume to next erase suspend 20 20 ms t sp 3) set protection 40 170 s t fpw 3) first word program 1 ms n end endurance 10 kcycles t ret data retention t a =85 20 ye a r s electrical parameters STR73XF 36/53 3.3.4 emc characteristics susceptibility tests ar e performed on a sample basis du ring product characterization. functional ems (electro magnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electro magnetic ev ents until a failure occurs (indicated by the leds). esd : electro-static discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 1000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100pf capacitor, until a functional disturbance occurs. this test conforms with the iec 1000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations: the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials: most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 18. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 5v, t a = +25c, f mclk = 36mhz conforms to iec 1000-4-2 4a v eftb fast transient voltage burst limits to be applied through 100pf on v dd and v ss pins to induce a functional disturbance v dd = 5v, t a = +25c, f mclk = 36mhz conforms to iec 1000-4-4 4a STR73XF electrical parameters 37/53 electro magnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of emi ssion. this emission test is in line with the norm sae j 1752/3 which sp ecifies the boar d and the loading of each pin. absolute maximum ratings (electrical sensitivity) based on three different tests (esd, lu and dlu) using specific measurement methods, the product is stressed in order to determine its per formance in terms of electrical sensitivity. for more details, refer to the application note an1181. electro-static discharge (esd) electro-static discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and machine model. this test conforms to the jesd22-a114a/a115a standard. notes: 1. data based on characterization results, not tested in production. static and dynamic latch-up lu : 3 complementary static tests are required on 10 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each table 19. emi data symbol parameter conditions monitored frequency band max vs. [f osc4m /f mclk ] unit 6/36mhz 8/8mhz s emi peak level v dd = 5.0v, t a = +25c, all packages 0.1mhz to 30mhz 23 30 dbv 30mhz to 130mhz 37 34 130mhz to 1ghz 20 7 sae emi level 4 3.5 - table 20. esd absolute maximum ratings symbol ratings conditions maximum value 1) unit v esd(hbm) electro-static discharge voltage (human body model) t a = +25c 2000 v v esd(mm) electro-static discharge voltage (machine model) 200 v esd(cdm) electro-static discharge voltage (charge device model) 750 on corner pins, 500 on others electrical parameters STR73XF 38/53 sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. dlu : electro-static discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the mi cro and the component is put in reset mode. this test conforms to the iec1000-4-2 and saej1752/3 standards. for more details, refer to the application note an1181. electrical sensitivities notes: 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). symbol parameter conditions class 1) lu static latch-up class t a = +25c t a = +85c t a = +105c a a a dlu dynamic latch-up class v dd = 5.5v, f osc4m = 4mhz, f mclk = 32mhz, t a = +25c a STR73XF electrical parameters 39/53 3.3.5 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. notes : 1. data based on characterization results, not tested in production. 2. when the current limitation is not possible, the v in absolute maximum rating must be respected, otherwise refer to i inj(pin) specification. a positive injection is induced by v in >v 33 while a negative injection is induced by v in STR73XF electrical parameters 41/53 figure 15. v oh jtdo pin vs i ol @ vdd 5v figure 16. v ol jtdo pin vs i ol @ vdd 5v 4.50 4.60 4.70 4.80 4.90 5.00 5.10 0123456 ioh (ma) voh(v) at vdd= 5 v ta -45c ta 25c ta 90c ta 110c 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0 1.2 2.4 3.6 4.8 6 iol (ma) vol(v) at vdd= 5 v ta -45c ta 25c ta 90c ta 110c figure 17. v oh p6.0 pin vs i ol @ vdd 5v figure 18. v ol p6.0 pin vs i ol @ v dd 5v 4.50 4.60 4.70 4.80 4.90 5.00 5.10 012345678 ioh (ma) voh(v) at vdd= 5 v ta -45c ta 25c ta 90c ta 110c 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 012345678 iol (ma) vol(v) at vdd= 5 v ta -45c ta 25c ta 90c ta 110c electrical parameters STR73XF 42/53 nrstin pin nrstin pin input driver is cmos. a permanent pull-up is present which is the same as r pu (see : general characteristics on page 39 ) subject to general operating conditions for v dd and t a unless otherwise specified. notes: 1. data based on characterization results, not tested in production. 2. hysteresis voltage between schm itt trigger switching levels. 3. data guaranteed by design, not tested in production. figure 19. recommended nrstin pin protection 1) notes: 1. the r pu pull-up equivalent resistor is based on a resistive transistor. 2. the reset network protects t he device against par asitic resets. 3. the user must ensure that the level on the nrstin pin can go below the v il(nrstin) max. level specified in table 23 . otherwise the reset will not be taken into account internally. table 23. reset pin characteristics symbol parameter conditions min typ 1) max unit v il(nrstin) rstin input low level voltage 1) 0.3 v dd v v ih(nrstin) rstin input high level voltage 1) 0.7 v dd v hys(nrstin) rstin schmitt trigger voltage hysteresis 2) 800 mv v f(rstinn) rstin input filtered pulse 3) 500 ns v nf(rstinn) rstin input not filtered pulse 3) 2s v rp(rstinn) rstin removal after power-up 3) 100 s 0.01 f external reset circuit required str7x filter r pu v dd internal reset STR73XF electrical parameters 43/53 figure 20. nrstin r pu vs. v dd 0 50 100 150 200 250 3 3.5 4 4.5 5 5.5 vdd (v) rpu (kohm) 25c -45c 110c electrical parameters STR73XF 44/53 3.3.6 10-bit adc characteristics subject to general operating conditions for v dda , f mclk , and t a unless otherwise specified. notes: 1. unless otherwise specified, typical data are based on t a =25c and v dda -v ss =5.0v. they are given only as design guidelines and are not tested. 2. calibration is recommended once after each power-up. 3. during the sample time the input capacitance c ain (6.8 max) can be charged/di scharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s. after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. 1. adc accuracy vs. negative injection current: in jecting negative current on any of the standard (non- robust) analog input pins should be av oided as this significantly reduce s the accuracy of the conversion being performed on another analog input. it is recommend ed to add a schottky diode (pin to ground) to standard analog pins which may potentia lly inject negative current. the effect of negative injection current table 24. adc characteristics symbol parameter conditions min typ 1) max unit f adc 0.4 10 mhz v ain conversion voltage range 2) v ssa v dda v i lkg negative input leakage current on analog pins v in < v ss, | i in |< 400a on adjacent analog pin 56 a c adc internal sample and hold capacitor 3.5 pf t cal 2) calibration time f adc = 10mhz 580.2 s 5802 1/f adc t s 3) sampling time f adc = 10mhz 114s t conv total conversion time (including sampling time) f adc = 10mhz 3s 30 (10 for sampling +20 for successive approximation) 1/f adc i adc running mode normal mode 5 ma power-down mode 1 a table 25. adc accuracy with f mclk = 20mhz, f adc =10mhz, r ain < 10k ? rain, v dda =5v. this assumes that the adc is calibrated 2) symbol parameter conditions typ max unit |e t | total unadjusted error 1) 1.0 2.0 lsb |e o | offset error 1) 0.15 1.0 |e g | gain error 1) 0.97 1.1 |e d | differential linearity error 1) 0.7 1.0 |e l | integral linearity error 1) 0.76 1.5 STR73XF electrical parameters 45/53 on robust pins is specified in section 3.3.5 . any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 3.3.5 does not affect the adc accuracy. 2. calibration is needed once after each power-up. figure 21. adc accuracy characteristics figure 22. typical application with adc e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = v (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021 1022 1023 1024 (1) (2) e t e d e l (3) v dda v ssa ainx str73x v dd i l 1 a v t 0.6v v t 0.6v c adc 3.5pf v ain r ain 10-bit a/d conversion 2.3k ?( max ) c ain electrical parameters STR73XF 46/53 analog power supply and reference pins the v dda and v ssa pins are the analog power supply of the a/d converter cell. they act as the high and low reference voltages for the conversion. separation of the digital and analog power pins allow board designers to improve a/d performance. conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see : general pcb design guidelines ). general pcb design guidelines to obtain best results, some general design and layout rules should be followed when designing the application pcb to shield the noise-sensitive, analog physical interface from noise-generating cmos logic signals. use separate digital and analog planes. the analog ground plane should be connected to the digital ground plane via a single point on the pcb. filter power to the analog power planes. it is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing 0.1f and optionally, if needed 10pf capacitors as close as possible to the str7 power supply pins and a 1 to 10f capacitor close to the power source (see figure 23 ). the analog and digital power supplies should be connected in a star network. do not use a resistor, as v dda is used as a reference voltage by the a/d converter and any resistance would cause a voltage drop and a loss of accuracy. properly place components and route the signal traces on the pcb to shield the analog inputs. analog signals paths should run over the analog ground plane and be as short as possible. isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the a/d converter. do not toggle digital outputs near the a/d input being converted. software filtering of spurious conversion results for emc performance reasons, it is recommended to filter a/d conversion outliers using software filtering techniques. figure 23. power supply filtering v ss v dd 0.1 f 5v str73x v dda v ssa power supply source str7 digital noise filtering external noise filtering 1 to 10 f 0.1 f STR73XF package characteristics 47/53 4 package characteristics 4.1 package mechanical data figure 24. 100-pin thin quad flat package figure 25. 144-pin thin quad flat package dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 d 16.00 0.630 d1 14.00 0.551 e 16.00 0.630 e1 14.00 0.551 e 0.50 0.020 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 100 h c l l 1 e b a a 2 a1 d d1 e e 1 dim. mm inches min typ max min typ max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.057 b 0.17 0.22 0.27 0.007 0.011 c 0.09 0.20 0.004 0.008 d 21.80 22.00 22.20 0.858 0.867 0.874 d1 19.80 20.00 20.20 0.780 0.787 0.795 d3 17.50 0.699 e 21.80 22.00 22.20 0.858 0.867 0.874 e1 19.80 20.00 20.20 0.780 0.787 0.795 e3 17.50 0.699 e 0.50 0.020 k 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 number of pins n 144 a a2 a1 b c 36 37 72 73 108 109 144 e1 e d1 d 1 h b l l1 seating plane 0.10mm .004 in. e e3 d3 package characteristics STR73XF 48/53 figure 26. 144-ball low profile fine pitch ball grid array package figure 27. recommended pcb design rules (0.80/0.75mm pitch bga) dim. mm inches min typ max min typ max a 1.21 1.70 0.048 0.067 a1 0.21 0.008 a2 1.085 0.043 b 0.35 0.40 0.45 0.014 0.016 0.018 d 9.85 10.00 10.15 0.388 0.394 0.400 d1 8.80 0.346 e 9.85 10.00 10.15 0.388 0.394 0.400 e1 8.80 0.346 e 0.80 0.031 f 0.60 0.024 ddd 0.10 0.004 eee 0.15 0.006 fff 0.08 0.003 number of pins n 144 dpad dsm dpad 0.37 mm dsm 0.52 mm typ. (depends on solder mask registration tolerance solder paste 0.37 mm aperture diameter ? non solder mask defined pads are recommended ? 4 to 6 mils screen print STR73XF package characteristics 49/53 4.2 thermal characteristics the average chip-junction temperature, t j , in degrees celsius, may be calculated using the following equation: t j = t a + (p d x ja )(1) where: ?t a is the ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ?p d is the sum of p int and p i/o (p d = p int + p i/o ), ?p int is the product of i dd and v dd , expressed in watt. this is the chip internal power, ?p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications p i/o < p int and may be neglected. on the other hand, p i/o may be significant if the device is config ured to drive continuously external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273c) (2) therefore (solving equations 1 and 2): k = p d x (t a + 273c) + ja x p d 2 (3) where: ? k is a constant for the particular part, which may be determined from equation (3) by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations (1) and (2) iteratively for any value of t a table 26. thermal characteristics symbol description package value (typical) unit ja thermal resistance junction-ambient lfbga144 50 c/w tqfp144 40 tqfp100 40 order codes STR73XF 50/53 5 order codes table 27. order codes partnumber flash kbytes package ram kbytes tim timers 6x pwm module can periph a/d chan. wake-up lines i/o ports temp. range str730fz1t6 128 tqfp144 20x20 16 10 1 3 16 32 112 -40 to +85c str730fz2t6 256 str730fz1h6 128 lfbga144 10x10 str730fz2h6 256 str735fz1t6 128 tqfp144 20x20 0 str735fz2t6 256 str735fz1h6 128 lfbga144 10x10 str735fz2h6 256 str731fv0t6 64 tqfp100 14x14 6 3 12 18 72 str731fv1t6 128 str731fv2t6 256 str736fv0t6 64 tqfp100 14x14 0 str736fv1t6 128 str736fv2t6 256 str730fz1t7 128 tqfp144 20x20 16 10 1 3 16 32 112 -40 to +105c str730fz2t7 256 str730fz1h7 128 lfbga144 10x10 str730fz2h7 256 str735fz1t7 128 tqfp144 20x20 0 str735fz2t7 256 str735fz1h7 128 lfbga144 10x10 str735fz2h7 256 str731fv0t7 64 tqfp100 14x14 6 3 12 18 72 str731fv1t7 128 str731fv2t7 256 str736fv0t7 64 tqfp100 14x14 0 str736fv1t7 128 str736fv2t7 256 STR73XF known limitations 51/53 6 known limitations 6.1 low power wait for interrupt mode when the str73x device is put in low power wait for interrupt mode (lpwfi), the flash goes into low power mode or power down mode, depending on the setting of the pwd bit in the flash control register 0 (default is ?0?, low power mode). this default mode can create excessive voltage conditions on the transistor gates and may affect the long term behavior of the low power mode circuitry. workaround there is no workaround. if low power wait for interrupt mode is used, it is strongly suggested to configure the flash to enter power down mode (bit pwd = ?1?). 6.2 pll free running mode at high temperature when the str73x device is operated and an ambient temperature (t a ) of more than 55c and the main system clock (f mclk ) is sourced by the pll in free running mode, the device may not work properly. workaround at high temperatur e (more than 55c), it is recommended to use the internal rc oscillator as a backup clock source rather than the pll free running mode. revision history STR73XF 52/53 7 revision history table 28. revision history date revision description of changes 19-sep-2005 1 first release 2-nov-2005 2 removed table 8 power consumption in lp modes updated pll frequency in section 1.1 and ta b l e 1 2 8-mar-2006 3 section 3.4: preliminary power consumption data updated section 3.5: dc electr ical characteristics updated section 6: known limitations added. 4-jun-2006 4 section 3: electrical parameters updated section 6: known limitations updated added temperature range -40c to 85c in section 5: order codes 19-jun-2006 5 changed flash data retention to 20 years at 85c in table 17 on page 35 . 08-sep-2006 6 changed table 22: output driving current on page 40 added figure 14: vol standard ports vs iol @ vdd 5v thru figure 18: vol p6.0 pin vs iol @ vdd 5v on page 41 . added figure 20: nrstin rpu vs. vdd STR73XF 53/53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an 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